1 /* Driver for Realtek RTS5139 USB card reader
2 *
3 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, see <http://www.gnu.org/licenses/>.
16 *
17 * Author:
18 * Roger Tseng <rogerable@realtek.com>
19 */
20
21 #ifndef __RTSX_USB_H
22 #define __RTSX_USB_H
23
24 #include <linux/usb.h>
25
26 /* related module names */
27 #define RTSX_USB_SD_CARD 0
28 #define RTSX_USB_MS_CARD 1
29
30 /* endpoint numbers */
31 #define EP_BULK_OUT 1
32 #define EP_BULK_IN 2
33 #define EP_INTR_IN 3
34
35 /* USB vendor requests */
36 #define RTSX_USB_REQ_REG_OP 0x00
37 #define RTSX_USB_REQ_POLL 0x02
38
39 /* miscellaneous parameters */
40 #define MIN_DIV_N 60
41 #define MAX_DIV_N 120
42
43 #define MAX_PHASE 15
44 #define RX_TUNING_CNT 3
45
46 #define QFN24 0
47 #define LQFP48 1
48 #define CHECK_PKG(ucr, pkg) ((ucr)->package == (pkg))
49
50 /* data structures */
51 struct rtsx_ucr {
52 u16 vendor_id;
53 u16 product_id;
54
55 int package;
56 u8 ic_version;
57 bool is_rts5179;
58
59 unsigned int cur_clk;
60
61 u8 *cmd_buf;
62 unsigned int cmd_idx;
63 u8 *rsp_buf;
64
65 struct usb_device *pusb_dev;
66 struct usb_interface *pusb_intf;
67 struct usb_sg_request current_sg;
68 unsigned char *iobuf;
69 dma_addr_t iobuf_dma;
70
71 struct timer_list sg_timer;
72 struct mutex dev_mutex;
73 };
74
75 /* buffer size */
76 #define IOBUF_SIZE 1024
77
78 /* prototypes of exported functions */
79 extern int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status);
80
81 extern int rtsx_usb_read_register(struct rtsx_ucr *ucr, u16 addr, u8 *data);
82 extern int rtsx_usb_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
83 u8 data);
84
85 extern int rtsx_usb_ep0_write_register(struct rtsx_ucr *ucr, u16 addr, u8 mask,
86 u8 data);
87 extern int rtsx_usb_ep0_read_register(struct rtsx_ucr *ucr, u16 addr,
88 u8 *data);
89
90 extern void rtsx_usb_add_cmd(struct rtsx_ucr *ucr, u8 cmd_type,
91 u16 reg_addr, u8 mask, u8 data);
92 extern int rtsx_usb_send_cmd(struct rtsx_ucr *ucr, u8 flag, int timeout);
93 extern int rtsx_usb_get_rsp(struct rtsx_ucr *ucr, int rsp_len, int timeout);
94 extern int rtsx_usb_transfer_data(struct rtsx_ucr *ucr, unsigned int pipe,
95 void *buf, unsigned int len, int use_sg,
96 unsigned int *act_len, int timeout);
97
98 extern int rtsx_usb_read_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
99 extern int rtsx_usb_write_ppbuf(struct rtsx_ucr *ucr, u8 *buf, int buf_len);
100 extern int rtsx_usb_switch_clock(struct rtsx_ucr *ucr, unsigned int card_clock,
101 u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk);
102 extern int rtsx_usb_card_exclusive_check(struct rtsx_ucr *ucr, int card);
103
104 /* card status */
105 #define SD_CD 0x01
106 #define MS_CD 0x02
107 #define XD_CD 0x04
108 #define CD_MASK (SD_CD | MS_CD | XD_CD)
109 #define SD_WP 0x08
110
111 /* reader command field offset & parameters */
112 #define READ_REG_CMD 0
113 #define WRITE_REG_CMD 1
114 #define CHECK_REG_CMD 2
115
116 #define PACKET_TYPE 4
117 #define CNT_H 5
118 #define CNT_L 6
119 #define STAGE_FLAG 7
120 #define CMD_OFFSET 8
121 #define SEQ_WRITE_DATA_OFFSET 12
122
123 #define BATCH_CMD 0
124 #define SEQ_READ 1
125 #define SEQ_WRITE 2
126
127 #define STAGE_R 0x01
128 #define STAGE_DI 0x02
129 #define STAGE_DO 0x04
130 #define STAGE_MS_STATUS 0x08
131 #define STAGE_XD_STATUS 0x10
132 #define MODE_C 0x00
133 #define MODE_CR (STAGE_R)
134 #define MODE_CDIR (STAGE_R | STAGE_DI)
135 #define MODE_CDOR (STAGE_R | STAGE_DO)
136
137 #define EP0_OP_SHIFT 14
138 #define EP0_READ_REG_CMD 2
139 #define EP0_WRITE_REG_CMD 3
140
141 #define rtsx_usb_cmd_hdr_tag(ucr) \
142 do { \
143 ucr->cmd_buf[0] = 'R'; \
144 ucr->cmd_buf[1] = 'T'; \
145 ucr->cmd_buf[2] = 'C'; \
146 ucr->cmd_buf[3] = 'R'; \
147 } while (0)
148
rtsx_usb_init_cmd(struct rtsx_ucr * ucr)149 static inline void rtsx_usb_init_cmd(struct rtsx_ucr *ucr)
150 {
151 rtsx_usb_cmd_hdr_tag(ucr);
152 ucr->cmd_idx = 0;
153 ucr->cmd_buf[PACKET_TYPE] = BATCH_CMD;
154 }
155
156 /* internal register address */
157 #define FPDCTL 0xFC00
158 #define SSC_DIV_N_0 0xFC07
159 #define SSC_CTL1 0xFC09
160 #define SSC_CTL2 0xFC0A
161 #define CFG_MODE 0xFC0E
162 #define CFG_MODE_1 0xFC0F
163 #define RCCTL 0xFC14
164 #define SOF_WDOG 0xFC28
165 #define SYS_DUMMY0 0xFC30
166
167 #define MS_BLKEND 0xFD30
168 #define MS_READ_START 0xFD31
169 #define MS_READ_COUNT 0xFD32
170 #define MS_WRITE_START 0xFD33
171 #define MS_WRITE_COUNT 0xFD34
172 #define MS_COMMAND 0xFD35
173 #define MS_OLD_BLOCK_0 0xFD36
174 #define MS_OLD_BLOCK_1 0xFD37
175 #define MS_NEW_BLOCK_0 0xFD38
176 #define MS_NEW_BLOCK_1 0xFD39
177 #define MS_LOG_BLOCK_0 0xFD3A
178 #define MS_LOG_BLOCK_1 0xFD3B
179 #define MS_BUS_WIDTH 0xFD3C
180 #define MS_PAGE_START 0xFD3D
181 #define MS_PAGE_LENGTH 0xFD3E
182 #define MS_CFG 0xFD40
183 #define MS_TPC 0xFD41
184 #define MS_TRANS_CFG 0xFD42
185 #define MS_TRANSFER 0xFD43
186 #define MS_INT_REG 0xFD44
187 #define MS_BYTE_CNT 0xFD45
188 #define MS_SECTOR_CNT_L 0xFD46
189 #define MS_SECTOR_CNT_H 0xFD47
190 #define MS_DBUS_H 0xFD48
191
192 #define CARD_DMA1_CTL 0xFD5C
193 #define CARD_PULL_CTL1 0xFD60
194 #define CARD_PULL_CTL2 0xFD61
195 #define CARD_PULL_CTL3 0xFD62
196 #define CARD_PULL_CTL4 0xFD63
197 #define CARD_PULL_CTL5 0xFD64
198 #define CARD_PULL_CTL6 0xFD65
199 #define CARD_EXIST 0xFD6F
200 #define CARD_INT_PEND 0xFD71
201
202 #define LDO_POWER_CFG 0xFD7B
203
204 #define SD_CFG1 0xFDA0
205 #define SD_CFG2 0xFDA1
206 #define SD_CFG3 0xFDA2
207 #define SD_STAT1 0xFDA3
208 #define SD_STAT2 0xFDA4
209 #define SD_BUS_STAT 0xFDA5
210 #define SD_PAD_CTL 0xFDA6
211 #define SD_SAMPLE_POINT_CTL 0xFDA7
212 #define SD_PUSH_POINT_CTL 0xFDA8
213 #define SD_CMD0 0xFDA9
214 #define SD_CMD1 0xFDAA
215 #define SD_CMD2 0xFDAB
216 #define SD_CMD3 0xFDAC
217 #define SD_CMD4 0xFDAD
218 #define SD_CMD5 0xFDAE
219 #define SD_BYTE_CNT_L 0xFDAF
220 #define SD_BYTE_CNT_H 0xFDB0
221 #define SD_BLOCK_CNT_L 0xFDB1
222 #define SD_BLOCK_CNT_H 0xFDB2
223 #define SD_TRANSFER 0xFDB3
224 #define SD_CMD_STATE 0xFDB5
225 #define SD_DATA_STATE 0xFDB6
226 #define SD_VPCLK0_CTL 0xFC2A
227 #define SD_VPCLK1_CTL 0xFC2B
228 #define SD_DCMPS0_CTL 0xFC2C
229 #define SD_DCMPS1_CTL 0xFC2D
230
231 #define CARD_DMA1_CTL 0xFD5C
232
233 #define HW_VERSION 0xFC01
234
235 #define SSC_CLK_FPGA_SEL 0xFC02
236 #define CLK_DIV 0xFC03
237 #define SFSM_ED 0xFC04
238
239 #define CD_DEGLITCH_WIDTH 0xFC20
240 #define CD_DEGLITCH_EN 0xFC21
241 #define AUTO_DELINK_EN 0xFC23
242
243 #define FPGA_PULL_CTL 0xFC1D
244 #define CARD_CLK_SOURCE 0xFC2E
245
246 #define CARD_SHARE_MODE 0xFD51
247 #define CARD_DRIVE_SEL 0xFD52
248 #define CARD_STOP 0xFD53
249 #define CARD_OE 0xFD54
250 #define CARD_AUTO_BLINK 0xFD55
251 #define CARD_GPIO 0xFD56
252 #define SD30_DRIVE_SEL 0xFD57
253
254 #define CARD_DATA_SOURCE 0xFD5D
255 #define CARD_SELECT 0xFD5E
256
257 #define CARD_CLK_EN 0xFD79
258 #define CARD_PWR_CTL 0xFD7A
259
260 #define OCPCTL 0xFD80
261 #define OCPPARA1 0xFD81
262 #define OCPPARA2 0xFD82
263 #define OCPSTAT 0xFD83
264
265 #define HS_USB_STAT 0xFE01
266 #define HS_VCONTROL 0xFE26
267 #define HS_VSTAIN 0xFE27
268 #define HS_VLOADM 0xFE28
269 #define HS_VSTAOUT 0xFE29
270
271 #define MC_IRQ 0xFF00
272 #define MC_IRQEN 0xFF01
273 #define MC_FIFO_CTL 0xFF02
274 #define MC_FIFO_BC0 0xFF03
275 #define MC_FIFO_BC1 0xFF04
276 #define MC_FIFO_STAT 0xFF05
277 #define MC_FIFO_MODE 0xFF06
278 #define MC_FIFO_RD_PTR0 0xFF07
279 #define MC_FIFO_RD_PTR1 0xFF08
280 #define MC_DMA_CTL 0xFF10
281 #define MC_DMA_TC0 0xFF11
282 #define MC_DMA_TC1 0xFF12
283 #define MC_DMA_TC2 0xFF13
284 #define MC_DMA_TC3 0xFF14
285 #define MC_DMA_RST 0xFF15
286
287 #define RBUF_SIZE_MASK 0xFBFF
288 #define RBUF_BASE 0xF000
289 #define PPBUF_BASE1 0xF800
290 #define PPBUF_BASE2 0xFA00
291
292 /* internal register value macros */
293 #define POWER_OFF 0x03
294 #define PARTIAL_POWER_ON 0x02
295 #define POWER_ON 0x00
296 #define POWER_MASK 0x03
297 #define LDO3318_PWR_MASK 0x0C
298 #define LDO_ON 0x00
299 #define LDO_SUSPEND 0x08
300 #define LDO_OFF 0x0C
301 #define DV3318_AUTO_PWR_OFF 0x10
302 #define FORCE_LDO_POWERB 0x60
303
304 /* LDO_POWER_CFG */
305 #define TUNE_SD18_MASK 0x1C
306 #define TUNE_SD18_1V7 0x00
307 #define TUNE_SD18_1V8 (0x01 << 2)
308 #define TUNE_SD18_1V9 (0x02 << 2)
309 #define TUNE_SD18_2V0 (0x03 << 2)
310 #define TUNE_SD18_2V7 (0x04 << 2)
311 #define TUNE_SD18_2V8 (0x05 << 2)
312 #define TUNE_SD18_2V9 (0x06 << 2)
313 #define TUNE_SD18_3V3 (0x07 << 2)
314
315 /* CLK_DIV */
316 #define CLK_CHANGE 0x80
317 #define CLK_DIV_1 0x00
318 #define CLK_DIV_2 0x01
319 #define CLK_DIV_4 0x02
320 #define CLK_DIV_8 0x03
321
322 #define SSC_POWER_MASK 0x01
323 #define SSC_POWER_DOWN 0x01
324 #define SSC_POWER_ON 0x00
325
326 #define FPGA_VER 0x80
327 #define HW_VER_MASK 0x0F
328
329 #define EXTEND_DMA1_ASYNC_SIGNAL 0x02
330
331 /* CFG_MODE*/
332 #define XTAL_FREE 0x80
333 #define CLK_MODE_MASK 0x03
334 #define CLK_MODE_12M_XTAL 0x00
335 #define CLK_MODE_NON_XTAL 0x01
336 #define CLK_MODE_24M_OSC 0x02
337 #define CLK_MODE_48M_OSC 0x03
338
339 /* CFG_MODE_1*/
340 #define RTS5179 0x02
341
342 #define NYET_EN 0x01
343 #define NYET_MSAK 0x01
344
345 #define SD30_DRIVE_MASK 0x07
346 #define SD20_DRIVE_MASK 0x03
347
348 #define DISABLE_SD_CD 0x08
349 #define DISABLE_MS_CD 0x10
350 #define DISABLE_XD_CD 0x20
351 #define SD_CD_DEGLITCH_EN 0x01
352 #define MS_CD_DEGLITCH_EN 0x02
353 #define XD_CD_DEGLITCH_EN 0x04
354
355 #define CARD_SHARE_LQFP48 0x04
356 #define CARD_SHARE_QFN24 0x00
357 #define CARD_SHARE_LQFP_SEL 0x04
358 #define CARD_SHARE_XD 0x00
359 #define CARD_SHARE_SD 0x01
360 #define CARD_SHARE_MS 0x02
361 #define CARD_SHARE_MASK 0x03
362
363
364 /* SD30_DRIVE_SEL */
365 #define DRIVER_TYPE_A 0x05
366 #define DRIVER_TYPE_B 0x03
367 #define DRIVER_TYPE_C 0x02
368 #define DRIVER_TYPE_D 0x01
369
370 /* SD_BUS_STAT */
371 #define SD_CLK_TOGGLE_EN 0x80
372 #define SD_CLK_FORCE_STOP 0x40
373 #define SD_DAT3_STATUS 0x10
374 #define SD_DAT2_STATUS 0x08
375 #define SD_DAT1_STATUS 0x04
376 #define SD_DAT0_STATUS 0x02
377 #define SD_CMD_STATUS 0x01
378
379 /* SD_PAD_CTL */
380 #define SD_IO_USING_1V8 0x80
381 #define SD_IO_USING_3V3 0x7F
382 #define TYPE_A_DRIVING 0x00
383 #define TYPE_B_DRIVING 0x01
384 #define TYPE_C_DRIVING 0x02
385 #define TYPE_D_DRIVING 0x03
386
387 /* CARD_CLK_EN */
388 #define SD_CLK_EN 0x04
389 #define MS_CLK_EN 0x08
390
391 /* CARD_SELECT */
392 #define SD_MOD_SEL 2
393 #define MS_MOD_SEL 3
394
395 /* CARD_SHARE_MODE */
396 #define CARD_SHARE_LQFP48 0x04
397 #define CARD_SHARE_QFN24 0x00
398 #define CARD_SHARE_LQFP_SEL 0x04
399 #define CARD_SHARE_XD 0x00
400 #define CARD_SHARE_SD 0x01
401 #define CARD_SHARE_MS 0x02
402 #define CARD_SHARE_MASK 0x03
403
404 /* SSC_CTL1 */
405 #define SSC_RSTB 0x80
406 #define SSC_8X_EN 0x40
407 #define SSC_FIX_FRAC 0x20
408 #define SSC_SEL_1M 0x00
409 #define SSC_SEL_2M 0x08
410 #define SSC_SEL_4M 0x10
411 #define SSC_SEL_8M 0x18
412
413 /* SSC_CTL2 */
414 #define SSC_DEPTH_MASK 0x03
415 #define SSC_DEPTH_DISALBE 0x00
416 #define SSC_DEPTH_2M 0x01
417 #define SSC_DEPTH_1M 0x02
418 #define SSC_DEPTH_512K 0x03
419
420 /* SD_VPCLK0_CTL */
421 #define PHASE_CHANGE 0x80
422 #define PHASE_NOT_RESET 0x40
423
424 /* SD_TRANSFER */
425 #define SD_TRANSFER_START 0x80
426 #define SD_TRANSFER_END 0x40
427 #define SD_STAT_IDLE 0x20
428 #define SD_TRANSFER_ERR 0x10
429 #define SD_TM_NORMAL_WRITE 0x00
430 #define SD_TM_AUTO_WRITE_3 0x01
431 #define SD_TM_AUTO_WRITE_4 0x02
432 #define SD_TM_AUTO_READ_3 0x05
433 #define SD_TM_AUTO_READ_4 0x06
434 #define SD_TM_CMD_RSP 0x08
435 #define SD_TM_AUTO_WRITE_1 0x09
436 #define SD_TM_AUTO_WRITE_2 0x0A
437 #define SD_TM_NORMAL_READ 0x0C
438 #define SD_TM_AUTO_READ_1 0x0D
439 #define SD_TM_AUTO_READ_2 0x0E
440 #define SD_TM_AUTO_TUNING 0x0F
441
442 /* SD_CFG1 */
443 #define SD_CLK_DIVIDE_0 0x00
444 #define SD_CLK_DIVIDE_256 0xC0
445 #define SD_CLK_DIVIDE_128 0x80
446 #define SD_CLK_DIVIDE_MASK 0xC0
447 #define SD_BUS_WIDTH_1BIT 0x00
448 #define SD_BUS_WIDTH_4BIT 0x01
449 #define SD_BUS_WIDTH_8BIT 0x02
450 #define SD_ASYNC_FIFO_RST 0x10
451 #define SD_20_MODE 0x00
452 #define SD_DDR_MODE 0x04
453 #define SD_30_MODE 0x08
454
455 /* SD_CFG2 */
456 #define SD_CALCULATE_CRC7 0x00
457 #define SD_NO_CALCULATE_CRC7 0x80
458 #define SD_CHECK_CRC16 0x00
459 #define SD_NO_CHECK_CRC16 0x40
460 #define SD_WAIT_CRC_TO_EN 0x20
461 #define SD_WAIT_BUSY_END 0x08
462 #define SD_NO_WAIT_BUSY_END 0x00
463 #define SD_CHECK_CRC7 0x00
464 #define SD_NO_CHECK_CRC7 0x04
465 #define SD_RSP_LEN_0 0x00
466 #define SD_RSP_LEN_6 0x01
467 #define SD_RSP_LEN_17 0x02
468 #define SD_RSP_TYPE_R0 0x04
469 #define SD_RSP_TYPE_R1 0x01
470 #define SD_RSP_TYPE_R1b 0x09
471 #define SD_RSP_TYPE_R2 0x02
472 #define SD_RSP_TYPE_R3 0x05
473 #define SD_RSP_TYPE_R4 0x05
474 #define SD_RSP_TYPE_R5 0x01
475 #define SD_RSP_TYPE_R6 0x01
476 #define SD_RSP_TYPE_R7 0x01
477
478 /* SD_STAT1 */
479 #define SD_CRC7_ERR 0x80
480 #define SD_CRC16_ERR 0x40
481 #define SD_CRC_WRITE_ERR 0x20
482 #define SD_CRC_WRITE_ERR_MASK 0x1C
483 #define GET_CRC_TIME_OUT 0x02
484 #define SD_TUNING_COMPARE_ERR 0x01
485
486 /* SD_DATA_STATE */
487 #define SD_DATA_IDLE 0x80
488
489 /* CARD_DATA_SOURCE */
490 #define PINGPONG_BUFFER 0x01
491 #define RING_BUFFER 0x00
492
493 /* CARD_OE */
494 #define SD_OUTPUT_EN 0x04
495 #define MS_OUTPUT_EN 0x08
496
497 /* CARD_STOP */
498 #define SD_STOP 0x04
499 #define MS_STOP 0x08
500 #define SD_CLR_ERR 0x40
501 #define MS_CLR_ERR 0x80
502
503 /* CARD_CLK_SOURCE */
504 #define CRC_FIX_CLK (0x00 << 0)
505 #define CRC_VAR_CLK0 (0x01 << 0)
506 #define CRC_VAR_CLK1 (0x02 << 0)
507 #define SD30_FIX_CLK (0x00 << 2)
508 #define SD30_VAR_CLK0 (0x01 << 2)
509 #define SD30_VAR_CLK1 (0x02 << 2)
510 #define SAMPLE_FIX_CLK (0x00 << 4)
511 #define SAMPLE_VAR_CLK0 (0x01 << 4)
512 #define SAMPLE_VAR_CLK1 (0x02 << 4)
513
514 /* SD_SAMPLE_POINT_CTL */
515 #define DDR_FIX_RX_DAT 0x00
516 #define DDR_VAR_RX_DAT 0x80
517 #define DDR_FIX_RX_DAT_EDGE 0x00
518 #define DDR_FIX_RX_DAT_14_DELAY 0x40
519 #define DDR_FIX_RX_CMD 0x00
520 #define DDR_VAR_RX_CMD 0x20
521 #define DDR_FIX_RX_CMD_POS_EDGE 0x00
522 #define DDR_FIX_RX_CMD_14_DELAY 0x10
523 #define SD20_RX_POS_EDGE 0x00
524 #define SD20_RX_14_DELAY 0x08
525 #define SD20_RX_SEL_MASK 0x08
526
527 /* SD_PUSH_POINT_CTL */
528 #define DDR_FIX_TX_CMD_DAT 0x00
529 #define DDR_VAR_TX_CMD_DAT 0x80
530 #define DDR_FIX_TX_DAT_14_TSU 0x00
531 #define DDR_FIX_TX_DAT_12_TSU 0x40
532 #define DDR_FIX_TX_CMD_NEG_EDGE 0x00
533 #define DDR_FIX_TX_CMD_14_AHEAD 0x20
534 #define SD20_TX_NEG_EDGE 0x00
535 #define SD20_TX_14_AHEAD 0x10
536 #define SD20_TX_SEL_MASK 0x10
537 #define DDR_VAR_SDCLK_POL_SWAP 0x01
538
539 /* MS_CFG */
540 #define SAMPLE_TIME_RISING 0x00
541 #define SAMPLE_TIME_FALLING 0x80
542 #define PUSH_TIME_DEFAULT 0x00
543 #define PUSH_TIME_ODD 0x40
544 #define NO_EXTEND_TOGGLE 0x00
545 #define EXTEND_TOGGLE_CHK 0x20
546 #define MS_BUS_WIDTH_1 0x00
547 #define MS_BUS_WIDTH_4 0x10
548 #define MS_BUS_WIDTH_8 0x18
549 #define MS_2K_SECTOR_MODE 0x04
550 #define MS_512_SECTOR_MODE 0x00
551 #define MS_TOGGLE_TIMEOUT_EN 0x00
552 #define MS_TOGGLE_TIMEOUT_DISEN 0x01
553 #define MS_NO_CHECK_INT 0x02
554
555 /* MS_TRANS_CFG */
556 #define WAIT_INT 0x80
557 #define NO_WAIT_INT 0x00
558 #define NO_AUTO_READ_INT_REG 0x00
559 #define AUTO_READ_INT_REG 0x40
560 #define MS_CRC16_ERR 0x20
561 #define MS_RDY_TIMEOUT 0x10
562 #define MS_INT_CMDNK 0x08
563 #define MS_INT_BREQ 0x04
564 #define MS_INT_ERR 0x02
565 #define MS_INT_CED 0x01
566
567 /* MS_TRANSFER */
568 #define MS_TRANSFER_START 0x80
569 #define MS_TRANSFER_END 0x40
570 #define MS_TRANSFER_ERR 0x20
571 #define MS_BS_STATE 0x10
572 #define MS_TM_READ_BYTES 0x00
573 #define MS_TM_NORMAL_READ 0x01
574 #define MS_TM_WRITE_BYTES 0x04
575 #define MS_TM_NORMAL_WRITE 0x05
576 #define MS_TM_AUTO_READ 0x08
577 #define MS_TM_AUTO_WRITE 0x0C
578 #define MS_TM_SET_CMD 0x06
579 #define MS_TM_COPY_PAGE 0x07
580 #define MS_TM_MULTI_READ 0x02
581 #define MS_TM_MULTI_WRITE 0x03
582
583 /* MC_FIFO_CTL */
584 #define FIFO_FLUSH 0x01
585
586 /* MC_DMA_RST */
587 #define DMA_RESET 0x01
588
589 /* MC_DMA_CTL */
590 #define DMA_TC_EQ_0 0x80
591 #define DMA_DIR_TO_CARD 0x00
592 #define DMA_DIR_FROM_CARD 0x02
593 #define DMA_EN 0x01
594 #define DMA_128 (0 << 2)
595 #define DMA_256 (1 << 2)
596 #define DMA_512 (2 << 2)
597 #define DMA_1024 (3 << 2)
598 #define DMA_PACK_SIZE_MASK 0x0C
599
600 /* CARD_INT_PEND */
601 #define XD_INT 0x10
602 #define MS_INT 0x08
603 #define SD_INT 0x04
604
605 /* LED operations*/
rtsx_usb_turn_on_led(struct rtsx_ucr * ucr)606 static inline int rtsx_usb_turn_on_led(struct rtsx_ucr *ucr)
607 {
608 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x02);
609 }
610
rtsx_usb_turn_off_led(struct rtsx_ucr * ucr)611 static inline int rtsx_usb_turn_off_led(struct rtsx_ucr *ucr)
612 {
613 return rtsx_usb_ep0_write_register(ucr, CARD_GPIO, 0x03, 0x03);
614 }
615
616 /* HW error clearing */
rtsx_usb_clear_fsm_err(struct rtsx_ucr * ucr)617 static inline void rtsx_usb_clear_fsm_err(struct rtsx_ucr *ucr)
618 {
619 rtsx_usb_ep0_write_register(ucr, SFSM_ED, 0xf8, 0xf8);
620 }
621
rtsx_usb_clear_dma_err(struct rtsx_ucr * ucr)622 static inline void rtsx_usb_clear_dma_err(struct rtsx_ucr *ucr)
623 {
624 rtsx_usb_ep0_write_register(ucr, MC_FIFO_CTL,
625 FIFO_FLUSH, FIFO_FLUSH);
626 rtsx_usb_ep0_write_register(ucr, MC_DMA_RST, DMA_RESET, DMA_RESET);
627 }
628 #endif /* __RTS51139_H */
629
