1 /* 2 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 3 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License, version 2, as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __ARM_KVM_ARM_H__ 20 #define __ARM_KVM_ARM_H__ 21 22 #include <linux/const.h> 23 #include <linux/types.h> 24 25 /* Hyp Configuration Register (HCR) bits */ 26 #define HCR_TGE (1 << 27) 27 #define HCR_TVM (1 << 26) 28 #define HCR_TTLB (1 << 25) 29 #define HCR_TPU (1 << 24) 30 #define HCR_TPC (1 << 23) 31 #define HCR_TSW (1 << 22) 32 #define HCR_TAC (1 << 21) 33 #define HCR_TIDCP (1 << 20) 34 #define HCR_TSC (1 << 19) 35 #define HCR_TID3 (1 << 18) 36 #define HCR_TID2 (1 << 17) 37 #define HCR_TID1 (1 << 16) 38 #define HCR_TID0 (1 << 15) 39 #define HCR_TWE (1 << 14) 40 #define HCR_TWI (1 << 13) 41 #define HCR_DC (1 << 12) 42 #define HCR_BSU (3 << 10) 43 #define HCR_BSU_IS (1 << 10) 44 #define HCR_FB (1 << 9) 45 #define HCR_VA (1 << 8) 46 #define HCR_VI (1 << 7) 47 #define HCR_VF (1 << 6) 48 #define HCR_AMO (1 << 5) 49 #define HCR_IMO (1 << 4) 50 #define HCR_FMO (1 << 3) 51 #define HCR_PTW (1 << 2) 52 #define HCR_SWIO (1 << 1) 53 #define HCR_VM 1 54 55 /* 56 * The bits we set in HCR: 57 * TAC: Trap ACTLR 58 * TSC: Trap SMC 59 * TVM: Trap VM ops (until MMU and caches are on) 60 * TSW: Trap cache operations by set/way 61 * TWI: Trap WFI 62 * TWE: Trap WFE 63 * TIDCP: Trap L2CTLR/L2ECTLR 64 * BSU_IS: Upgrade barriers to the inner shareable domain 65 * FB: Force broadcast of all maintainance operations 66 * AMO: Override CPSR.A and enable signaling with VA 67 * IMO: Override CPSR.I and enable signaling with VI 68 * FMO: Override CPSR.F and enable signaling with VF 69 * SWIO: Turn set/way invalidates into set/way clean+invalidate 70 */ 71 #define HCR_GUEST_MASK (HCR_TSC | HCR_TSW | HCR_TWI | HCR_VM | HCR_BSU_IS | \ 72 HCR_FB | HCR_TAC | HCR_AMO | HCR_IMO | HCR_FMO | \ 73 HCR_TVM | HCR_TWE | HCR_SWIO | HCR_TIDCP) 74 75 /* System Control Register (SCTLR) bits */ 76 #define SCTLR_TE (1 << 30) 77 #define SCTLR_EE (1 << 25) 78 #define SCTLR_V (1 << 13) 79 80 /* Hyp System Control Register (HSCTLR) bits */ 81 #define HSCTLR_TE (1 << 30) 82 #define HSCTLR_EE (1 << 25) 83 #define HSCTLR_FI (1 << 21) 84 #define HSCTLR_WXN (1 << 19) 85 #define HSCTLR_I (1 << 12) 86 #define HSCTLR_C (1 << 2) 87 #define HSCTLR_A (1 << 1) 88 #define HSCTLR_M 1 89 #define HSCTLR_MASK (HSCTLR_M | HSCTLR_A | HSCTLR_C | HSCTLR_I | \ 90 HSCTLR_WXN | HSCTLR_FI | HSCTLR_EE | HSCTLR_TE) 91 92 /* TTBCR and HTCR Registers bits */ 93 #define TTBCR_EAE (1 << 31) 94 #define TTBCR_IMP (1 << 30) 95 #define TTBCR_SH1 (3 << 28) 96 #define TTBCR_ORGN1 (3 << 26) 97 #define TTBCR_IRGN1 (3 << 24) 98 #define TTBCR_EPD1 (1 << 23) 99 #define TTBCR_A1 (1 << 22) 100 #define TTBCR_T1SZ (7 << 16) 101 #define TTBCR_SH0 (3 << 12) 102 #define TTBCR_ORGN0 (3 << 10) 103 #define TTBCR_IRGN0 (3 << 8) 104 #define TTBCR_EPD0 (1 << 7) 105 #define TTBCR_T0SZ (7 << 0) 106 #define HTCR_MASK (TTBCR_T0SZ | TTBCR_IRGN0 | TTBCR_ORGN0 | TTBCR_SH0) 107 108 /* Hyp System Trap Register */ 109 #define HSTR_T(x) (1 << x) 110 #define HSTR_TTEE (1 << 16) 111 #define HSTR_TJDBX (1 << 17) 112 113 /* Hyp Coprocessor Trap Register */ 114 #define HCPTR_TCP(x) (1 << x) 115 #define HCPTR_TCP_MASK (0x3fff) 116 #define HCPTR_TASE (1 << 15) 117 #define HCPTR_TTA (1 << 20) 118 #define HCPTR_TCPAC (1 << 31) 119 120 /* Hyp Debug Configuration Register bits */ 121 #define HDCR_TDRA (1 << 11) 122 #define HDCR_TDOSA (1 << 10) 123 #define HDCR_TDA (1 << 9) 124 #define HDCR_TDE (1 << 8) 125 #define HDCR_HPME (1 << 7) 126 #define HDCR_TPM (1 << 6) 127 #define HDCR_TPMCR (1 << 5) 128 #define HDCR_HPMN_MASK (0x1F) 129 130 /* 131 * The architecture supports 40-bit IPA as input to the 2nd stage translations 132 * and PTRS_PER_S2_PGD becomes 1024, because each entry covers 1GB of address 133 * space. 134 */ 135 #define KVM_PHYS_SHIFT (40) 136 #define KVM_PHYS_SIZE (_AC(1, ULL) << KVM_PHYS_SHIFT) 137 #define KVM_PHYS_MASK (KVM_PHYS_SIZE - _AC(1, ULL)) 138 #define PTRS_PER_S2_PGD (_AC(1, ULL) << (KVM_PHYS_SHIFT - 30)) 139 140 /* Virtualization Translation Control Register (VTCR) bits */ 141 #define VTCR_SH0 (3 << 12) 142 #define VTCR_ORGN0 (3 << 10) 143 #define VTCR_IRGN0 (3 << 8) 144 #define VTCR_SL0 (3 << 6) 145 #define VTCR_S (1 << 4) 146 #define VTCR_T0SZ (0xf) 147 #define VTCR_MASK (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0 | VTCR_SL0 | \ 148 VTCR_S | VTCR_T0SZ) 149 #define VTCR_HTCR_SH (VTCR_SH0 | VTCR_ORGN0 | VTCR_IRGN0) 150 #define VTCR_SL_L2 (0 << 6) /* Starting-level: 2 */ 151 #define VTCR_SL_L1 (1 << 6) /* Starting-level: 1 */ 152 #define KVM_VTCR_SL0 VTCR_SL_L1 153 /* stage-2 input address range defined as 2^(32-T0SZ) */ 154 #define KVM_T0SZ (32 - KVM_PHYS_SHIFT) 155 #define KVM_VTCR_T0SZ (KVM_T0SZ & VTCR_T0SZ) 156 #define KVM_VTCR_S ((KVM_VTCR_T0SZ << 1) & VTCR_S) 157 158 /* Virtualization Translation Table Base Register (VTTBR) bits */ 159 #if KVM_VTCR_SL0 == VTCR_SL_L2 /* see ARM DDI 0406C: B4-1720 */ 160 #define VTTBR_X (14 - KVM_T0SZ) 161 #else 162 #define VTTBR_X (5 - KVM_T0SZ) 163 #endif 164 #define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X) 165 #define VTTBR_VMID_SHIFT _AC(48, ULL) 166 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 167 168 /* Hyp Syndrome Register (HSR) bits */ 169 #define HSR_EC_SHIFT (26) 170 #define HSR_EC (_AC(0x3f, UL) << HSR_EC_SHIFT) 171 #define HSR_IL (_AC(1, UL) << 25) 172 #define HSR_ISS (HSR_IL - 1) 173 #define HSR_ISV_SHIFT (24) 174 #define HSR_ISV (_AC(1, UL) << HSR_ISV_SHIFT) 175 #define HSR_SRT_SHIFT (16) 176 #define HSR_SRT_MASK (0xf << HSR_SRT_SHIFT) 177 #define HSR_FSC (0x3f) 178 #define HSR_FSC_TYPE (0x3c) 179 #define HSR_SSE (1 << 21) 180 #define HSR_WNR (1 << 6) 181 #define HSR_CV_SHIFT (24) 182 #define HSR_CV (_AC(1, UL) << HSR_CV_SHIFT) 183 #define HSR_COND_SHIFT (20) 184 #define HSR_COND (_AC(0xf, UL) << HSR_COND_SHIFT) 185 186 #define FSC_FAULT (0x04) 187 #define FSC_ACCESS (0x08) 188 #define FSC_PERM (0x0c) 189 #define FSC_SEA (0x10) 190 #define FSC_SEA_TTW0 (0x14) 191 #define FSC_SEA_TTW1 (0x15) 192 #define FSC_SEA_TTW2 (0x16) 193 #define FSC_SEA_TTW3 (0x17) 194 #define FSC_SECC (0x18) 195 #define FSC_SECC_TTW0 (0x1c) 196 #define FSC_SECC_TTW1 (0x1d) 197 #define FSC_SECC_TTW2 (0x1e) 198 #define FSC_SECC_TTW3 (0x1f) 199 200 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 201 #define HPFAR_MASK (~0xf) 202 203 #define HSR_EC_UNKNOWN (0x00) 204 #define HSR_EC_WFI (0x01) 205 #define HSR_EC_CP15_32 (0x03) 206 #define HSR_EC_CP15_64 (0x04) 207 #define HSR_EC_CP14_MR (0x05) 208 #define HSR_EC_CP14_LS (0x06) 209 #define HSR_EC_CP_0_13 (0x07) 210 #define HSR_EC_CP10_ID (0x08) 211 #define HSR_EC_JAZELLE (0x09) 212 #define HSR_EC_BXJ (0x0A) 213 #define HSR_EC_CP14_64 (0x0C) 214 #define HSR_EC_SVC_HYP (0x11) 215 #define HSR_EC_HVC (0x12) 216 #define HSR_EC_SMC (0x13) 217 #define HSR_EC_IABT (0x20) 218 #define HSR_EC_IABT_HYP (0x21) 219 #define HSR_EC_DABT (0x24) 220 #define HSR_EC_DABT_HYP (0x25) 221 #define HSR_EC_MAX (0x3f) 222 223 #define HSR_WFI_IS_WFE (_AC(1, UL) << 0) 224 225 #define HSR_HVC_IMM_MASK ((_AC(1, UL) << 16) - 1) 226 227 #define HSR_DABT_S1PTW (_AC(1, UL) << 7) 228 #define HSR_DABT_CM (_AC(1, UL) << 8) 229 230 #define kvm_arm_exception_type \ 231 {0, "RESET" }, \ 232 {1, "UNDEFINED" }, \ 233 {2, "SOFTWARE" }, \ 234 {3, "PREF_ABORT" }, \ 235 {4, "DATA_ABORT" }, \ 236 {5, "IRQ" }, \ 237 {6, "FIQ" }, \ 238 {7, "HVC" } 239 240 #define HSRECN(x) { HSR_EC_##x, #x } 241 242 #define kvm_arm_exception_class \ 243 HSRECN(UNKNOWN), HSRECN(WFI), HSRECN(CP15_32), HSRECN(CP15_64), \ 244 HSRECN(CP14_MR), HSRECN(CP14_LS), HSRECN(CP_0_13), HSRECN(CP10_ID), \ 245 HSRECN(JAZELLE), HSRECN(BXJ), HSRECN(CP14_64), HSRECN(SVC_HYP), \ 246 HSRECN(HVC), HSRECN(SMC), HSRECN(IABT), HSRECN(IABT_HYP), \ 247 HSRECN(DABT), HSRECN(DABT_HYP) 248 249 250 #endif /* __ARM_KVM_ARM_H__ */ 251
