1 /* 2 * SH7734 processor support - PFC hardware block 3 * 4 * Copyright (C) 2012 Renesas Solutions Corp. 5 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 6 * 7 * This file is subject to the terms and conditions of the GNU General Public 8 * License. See the file "COPYING" in the main directory of this archive 9 * for more details. 10 */ 11 #include <linux/init.h> 12 #include <linux/kernel.h> 13 #include <cpu/sh7734.h> 14 15 #include "sh_pfc.h" 16 17 #define CPU_ALL_PORT(fn, sfx) \ 18 PORT_GP_32(0, fn, sfx), \ 19 PORT_GP_32(1, fn, sfx), \ 20 PORT_GP_32(2, fn, sfx), \ 21 PORT_GP_32(3, fn, sfx), \ 22 PORT_GP_32(4, fn, sfx), \ 23 PORT_GP_12(5, fn, sfx) 24 25 #undef _GP_DATA 26 #define _GP_DATA(bank, pin, name, sfx, cfg) \ 27 PINMUX_DATA(name##_DATA, name##_FN, name##_IN, name##_OUT) 28 29 #define _GP_INOUTSEL(bank, pin, name, sfx, cfg) name##_IN, name##_OUT 30 #define _GP_INDT(bank, pin, name, sfx, cfg) name##_DATA 31 #define GP_INOUTSEL(bank) PORT_GP_32_REV(bank, _GP_INOUTSEL, unused) 32 #define GP_INDT(bank) PORT_GP_32_REV(bank, _GP_INDT, unused) 33 34 enum { 35 PINMUX_RESERVED = 0, 36 37 PINMUX_DATA_BEGIN, 38 GP_ALL(DATA), /* GP_0_0_DATA -> GP_5_11_DATA */ 39 PINMUX_DATA_END, 40 41 PINMUX_INPUT_BEGIN, 42 GP_ALL(IN), /* GP_0_0_IN -> GP_5_11_IN */ 43 PINMUX_INPUT_END, 44 45 PINMUX_OUTPUT_BEGIN, 46 GP_ALL(OUT), /* GP_0_0_OUT -> GP_5_11_OUT */ 47 PINMUX_OUTPUT_END, 48 49 PINMUX_FUNCTION_BEGIN, 50 GP_ALL(FN), /* GP_0_0_FN -> GP_5_11_FN */ 51 52 /* GPSR0 */ 53 FN_IP1_9_8, FN_IP1_11_10, FN_IP1_13_12, FN_IP1_15_14, 54 FN_IP0_7_6, FN_IP0_9_8, FN_IP0_11_10, FN_IP0_13_12, 55 FN_IP0_15_14, FN_IP0_17_16, FN_IP0_19_18, FN_IP0_21_20, 56 FN_IP0_23_22, FN_IP0_25_24, FN_IP0_27_26, FN_IP0_29_28, 57 FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, 58 FN_IP1_7_6, FN_IP11_28, FN_IP0_1_0, FN_IP0_3_2, 59 FN_IP0_5_4, FN_IP1_17_16, FN_IP1_19_18, FN_IP1_22_20, 60 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, 61 62 /* GPSR1 */ 63 FN_IP3_20, FN_IP3_29_27, FN_IP11_20_19, FN_IP11_22_21, 64 FN_IP2_16_14, FN_IP2_19_17, FN_IP2_22_20, FN_IP2_24_23, 65 FN_IP2_27_25, FN_IP2_30_28, FN_IP3_1_0, FN_CLKOUT, 66 FN_BS, FN_CS0, FN_IP3_2, FN_EX_CS0, 67 FN_IP3_5_3, FN_IP3_8_6, FN_IP3_11_9, FN_IP3_14_12, 68 FN_IP3_17_15, FN_RD, FN_IP3_19_18, FN_WE0, 69 FN_WE1, FN_IP2_4_3, FN_IP3_23_21, FN_IP3_26_24, 70 FN_IP2_7_5, FN_IP2_10_8, FN_IP2_13_11, FN_IP11_25_23, 71 72 /* GPSR2 */ 73 FN_IP11_6_4, FN_IP11_9_7, FN_IP11_11_10, FN_IP4_2_0, 74 FN_IP8_29_28, FN_IP11_27_26, FN_IP8_22_20, FN_IP8_25_23, 75 FN_IP11_12, FN_IP8_27_26, FN_IP4_5_3, FN_IP4_8_6, 76 FN_IP4_11_9, FN_IP4_14_12, FN_IP4_17_15, FN_IP4_19_18, 77 FN_IP4_21_20, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26, 78 FN_IP4_29_28, FN_IP4_31_30, FN_IP5_2_0, FN_IP5_5_3, 79 FN_IP5_8_6, FN_IP5_11_9, FN_IP5_14_12, FN_IP5_17_15, 80 FN_IP5_20_18, FN_IP5_22_21, FN_IP5_24_23, FN_IP5_26_25, 81 82 /* GPSR3 */ 83 FN_IP6_2_0, FN_IP6_5_3, FN_IP6_7_6, FN_IP6_9_8, 84 FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14, FN_IP6_17_16, 85 FN_IP6_20_18, FN_IP6_23_21, FN_IP7_2_0, FN_IP7_5_3, 86 FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, 87 FN_IP7_20_18, FN_IP7_23_21, FN_IP7_26_24, FN_IP7_28_27, 88 FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4, 89 FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, 90 FN_IP8_15_14, FN_IP8_17_16, FN_IP8_19_18, FN_IP9_1_0, 91 92 /* GPSR4 */ 93 FN_IP9_19_18, FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, 94 FN_IP9_11_10, FN_IP9_13_12, FN_IP9_15_14, FN_IP9_17_16, 95 FN_IP9_3_2, FN_IP9_5_4, FN_IP9_7_6, FN_IP9_9_8, 96 FN_IP9_27_26, FN_IP9_29_28, FN_IP10_2_0, FN_IP10_5_3, 97 FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_15, 98 FN_IP10_18_16, FN_IP10_21_19, FN_IP11_0, FN_IP11_1, 99 FN_SCL0, FN_IP11_2, FN_PENC0, FN_IP11_15_13, /* Need check*/ 100 FN_USB_OVC0, FN_IP11_18_16, 101 FN_IP10_22, FN_IP10_24_23, 102 103 /* GPSR5 */ 104 FN_IP10_25, FN_IP11_3, FN_IRQ2_B, FN_IRQ3_B, 105 FN_IP10_27_26, /* 10 */ 106 FN_IP10_29_28, /* 11 */ 107 108 /* IPSR0 */ 109 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, FN_TIOC3D_C, 110 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 111 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 112 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 113 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C, 114 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C, 115 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C, 116 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C, 117 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C, 118 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C, 119 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C, 120 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C, 121 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C, 122 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C, 123 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C, 124 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C, 125 126 /* IPSR1 */ 127 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, FN_FD3_A, 128 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, FN_FD2_A, 129 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, FN_FD1_A, 130 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, FN_FD0_A, 131 FN_A25, FN_TX2_D, FN_ST1_D2, 132 FN_A24, FN_RX2_D, FN_ST1_D1, 133 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 134 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 135 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 136 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 137 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C, 138 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C, 139 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C, 140 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C, 141 142 /* IPSR2 */ 143 FN_D14, FN_TX2_B, FN_FSE_A, FN_ET0_TX_CLK_B, 144 FN_D13, FN_RX2_B, FN_FRB_A, FN_ET0_ETXD6_B, 145 FN_D12, FN_FWE_A, FN_ET0_ETXD5_B, 146 FN_D11, FN_RSPI_MISO_A, FN_QMI_QIO1_A, FN_FRE_A, 147 FN_ET0_ETXD3_B, 148 FN_D10, FN_RSPI_MOSI_A, FN_QMO_QIO0_A, FN_FALE_A, 149 FN_ET0_ETXD2_B, 150 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, FN_FCLE_A, 151 FN_ET0_ETXD1_B, 152 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, FN_FCE_A, 153 FN_ET0_GTX_CLK_B, 154 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, FN_FD7_A, 155 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, FN_FD6_A, 156 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A, 157 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, FN_FD4_A, 158 159 /* IPSR3 */ 160 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, FN_ET0_ETXD7, 161 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C, 162 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 163 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C, 164 FN_ET0_LINK_C, FN_ET0_ETXD5_A, 165 FN_EX_WAIT0, FN_TCLK1_B, 166 FN_RD_WR, FN_TCLK0, FN_CAN_CLK_B, FN_ET0_ETXD4, 167 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, FN_ET0_ETXD3_A, 168 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, FN_ET0_ETXD2_A, 169 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, FN_ET0_ETXD1_A, 170 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, FN_ET0_GTX_CLK_A, 171 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, FN_ET0_ETXD0, 172 FN_CS1_A26, FN_QIO3_B, 173 FN_D15, FN_SCK2_B, 174 175 /* IPSR4 */ 176 FN_SCK2_A, FN_VI0_G3, 177 FN_RTS1_B, FN_VI0_G2, 178 FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 179 FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A, 180 FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A, 181 FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A, 182 FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A, 183 FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, FN_ET0_MDC, 184 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, FN_ET0_COL, 185 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, FN_ET0_CRS, 186 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, FN_ET0_RX_ER, 187 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, FN_ET0_RX_DV, 188 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, FN_ET0_ERXD7, 189 190 /* IPSR5 */ 191 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, FN_ET0_RX_CLK_B, 192 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, FN_ET0_ERXD2_B, 193 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, FN_ET0_ERXD3_B, 194 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, FN_ET0_MDIO_B, 195 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, FN_ET0_LINK_B, 196 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, FN_ET0_MAGIC_B, 197 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, FN_ET0_PHY_INT_B, 198 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 199 FN_REF125CK, FN_ADTRG, FN_RX5_C, 200 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 201 202 /* IPSR6 */ 203 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, FN_TCLKA_A, FN_HIFD00, 204 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, FN_TCLKB_A, FN_HIFD01, 205 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02, 206 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03, 207 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04, 208 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05, 209 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06, 210 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07, 211 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, FN_TIOC1A_A, FN_HIFD08, 212 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, FN_HIFD09, 213 214 /* IPSR7 */ 215 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, FN_HIFD10, 216 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, FN_HIFD11, 217 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, FN_HIFD12, 218 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, FN_HIFD13, 219 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, FN_HIFD14, 220 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, FN_HIFD15, 221 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, FN_HIFCS, 222 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, FN_HIFRS, 223 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, FN_HIFWR, 224 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD, 225 FN_DU0_DB4, FN_HIFINT, 226 227 /* IPSR8 */ 228 FN_DU0_DB5, FN_HIFDREQ, 229 FN_DU0_DB6, FN_HIFRDY, 230 FN_DU0_DB7, FN_SSI_SCK0_B, FN_HIFEBL_B, 231 FN_DU0_DOTCLKIN, FN_HSPI_CS0_C, FN_SSI_WS0_B, 232 FN_DU0_DOTCLKOUT, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B, 233 FN_DU0_EXHSYNC_DU0_HSYNC, FN_HSPI_TX0_C, FN_SSI_SCK1_B, 234 FN_DU0_EXVSYNC_DU0_VSYNC, FN_HSPI_RX0_C, FN_SSI_WS1_B, 235 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, FN_SSI_SDATA1_B, 236 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B, 237 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B, 238 FN_IRQ0_A, FN_HSPI_TX_B, FN_RX3_E, FN_ET0_ERXD0, 239 FN_IRQ1_A, FN_HSPI_RX_B, FN_TX3_E, FN_ET0_ERXD1, 240 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A, 241 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A, 242 243 /* IPSR9 */ 244 FN_VI1_CLK_A, FN_FD0_B, FN_LCD_DATA0_B, 245 FN_VI1_0_A, FN_FD1_B, FN_LCD_DATA1_B, 246 FN_VI1_1_A, FN_FD2_B, FN_LCD_DATA2_B, 247 FN_VI1_2_A, FN_FD3_B, FN_LCD_DATA3_B, 248 FN_VI1_3_A, FN_FD4_B, FN_LCD_DATA4_B, 249 FN_VI1_4_A, FN_FD5_B, FN_LCD_DATA5_B, 250 FN_VI1_5_A, FN_FD6_B, FN_LCD_DATA6_B, 251 FN_VI1_6_A, FN_FD7_B, FN_LCD_DATA7_B, 252 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 253 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 254 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 255 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B, 256 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B, 257 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 258 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 259 260 /* IPSR10 */ 261 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, FN_LCD_DATA15_B, 262 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, FN_LCD_DON_B, 263 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, FN_LCD_CL1_B, 264 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, FN_LCD_CL2_B, 265 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, FN_LCD_FLM_B, 266 FN_AUDIO_CLKB_A, FN_LCD_CLK_B, 267 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, FN_LCD_VEPWC_B, 268 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, FN_LCD_M_DISP_B, 269 FN_CAN_CLK_A, FN_RX4_D, 270 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 271 FN_CAN1_RX_A, FN_IRQ1_B, 272 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 273 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 274 275 /* IPSR11 */ 276 FN_SCL1, FN_SCIF_CLK_C, 277 FN_SDA1, FN_RX1_E, 278 FN_SDA0, FN_HIFEBL_A, 279 FN_SDSELF, FN_RTS1_E, 280 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, FN_ET0_ERXD4, 281 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, FN_ET0_ERXD5, 282 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6, 283 FN_TX0_A, FN_HSPI_TX_A, 284 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, FN_IETX_B, 285 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, FN_IERX_B, 286 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 287 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 288 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, FN_ET0_TX_CLK_A, 289 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A, 290 FN_PRESETOUT, FN_ST_CLKOUT, 291 292 /* MOD_SEL1 */ 293 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, 294 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1, 295 FN_SEL_VIN1_0, FN_SEL_VIN1_1, 296 FN_SEL_HIF_0, FN_SEL_HIF_1, 297 FN_SEL_RSPI_0, FN_SEL_RSPI_1, 298 FN_SEL_LCDC_0, FN_SEL_LCDC_1, 299 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 300 FN_SEL_ET0_0, FN_SEL_ET0_1, 301 FN_SEL_RMII_0, FN_SEL_RMII_1, 302 FN_SEL_TMU_0, FN_SEL_TMU_1, 303 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 304 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3, 305 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1, 306 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 307 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1, 308 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, 309 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1, 310 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1, 311 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 312 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 313 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1, 314 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1, 315 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1, 316 FN_SEL_MMC_0, FN_SEL_MMC_1, 317 FN_SEL_INTC_0, FN_SEL_INTC_1, 318 319 /* MOD_SEL2 */ 320 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1, 321 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1, 322 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1, 323 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 324 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 325 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1, 326 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, 327 FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 328 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, 329 FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 330 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, 331 FN_SEL_SCIF3_3, FN_SEL_SCIF3_4, 332 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 333 FN_SEL_SCIF2_3, 334 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 335 FN_SEL_SCIF1_3, FN_SEL_SCIF1_4, 336 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 337 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 338 339 PINMUX_FUNCTION_END, 340 341 PINMUX_MARK_BEGIN, 342 343 CLKOUT_MARK, BS_MARK, CS0_MARK, EX_CS0_MARK, RD_MARK, 344 WE0_MARK, WE1_MARK, 345 346 SCL0_MARK, PENC0_MARK, USB_OVC0_MARK, 347 348 IRQ2_B_MARK, IRQ3_B_MARK, 349 350 /* IPSR0 */ 351 A15_MARK, ST0_VCO_CLKIN_MARK, LCD_DATA15_A_MARK, TIOC3D_C_MARK, 352 A14_MARK, LCD_DATA14_A_MARK, TIOC3C_C_MARK, 353 A13_MARK, LCD_DATA13_A_MARK, TIOC3B_C_MARK, 354 A12_MARK, LCD_DATA12_A_MARK, TIOC3A_C_MARK, 355 A11_MARK, ST0_D7_MARK, LCD_DATA11_A_MARK, TIOC2B_C_MARK, 356 A10_MARK, ST0_D6_MARK, LCD_DATA10_A_MARK, TIOC2A_C_MARK, 357 A9_MARK, ST0_D5_MARK, LCD_DATA9_A_MARK, TIOC1B_C_MARK, 358 A8_MARK, ST0_D4_MARK, LCD_DATA8_A_MARK, TIOC1A_C_MARK, 359 A7_MARK, ST0_D3_MARK, LCD_DATA7_A_MARK, TIOC0D_C_MARK, 360 A6_MARK, ST0_D2_MARK, LCD_DATA6_A_MARK, TIOC0C_C_MARK, 361 A5_MARK, ST0_D1_MARK, LCD_DATA5_A_MARK, TIOC0B_C_MARK, 362 A4_MARK, ST0_D0_MARK, LCD_DATA4_A_MARK, TIOC0A_C_MARK, 363 A3_MARK, ST0_VLD_MARK, LCD_DATA3_A_MARK, TCLKD_C_MARK, 364 A2_MARK, ST0_SYC_MARK, LCD_DATA2_A_MARK, TCLKC_C_MARK, 365 A1_MARK, ST0_REQ_MARK, LCD_DATA1_A_MARK, TCLKB_C_MARK, 366 A0_MARK, ST0_CLKIN_MARK, LCD_DATA0_A_MARK, TCLKA_C_MARK, 367 368 /* IPSR1 */ 369 D3_MARK, SD0_DAT3_A_MARK, MMC_D3_A_MARK, ST1_D6_MARK, FD3_A_MARK, 370 D2_MARK, SD0_DAT2_A_MARK, MMC_D2_A_MARK, ST1_D5_MARK, FD2_A_MARK, 371 D1_MARK, SD0_DAT1_A_MARK, MMC_D1_A_MARK, ST1_D4_MARK, FD1_A_MARK, 372 D0_MARK, SD0_DAT0_A_MARK, MMC_D0_A_MARK, ST1_D3_MARK, FD0_A_MARK, 373 A25_MARK, TX2_D_MARK, ST1_D2_MARK, 374 A24_MARK, RX2_D_MARK, ST1_D1_MARK, 375 A23_MARK, ST1_D0_MARK, LCD_M_DISP_A_MARK, 376 A22_MARK, ST1_VLD_MARK, LCD_VEPWC_A_MARK, 377 A21_MARK, ST1_SYC_MARK, LCD_VCPWC_A_MARK, 378 A20_MARK, ST1_REQ_MARK, LCD_FLM_A_MARK, 379 A19_MARK, ST1_CLKIN_MARK, LCD_CLK_A_MARK, TIOC4D_C_MARK, 380 A18_MARK, ST1_PWM_MARK, LCD_CL2_A_MARK, TIOC4C_C_MARK, 381 A17_MARK, ST1_VCO_CLKIN_MARK, LCD_CL1_A_MARK, TIOC4B_C_MARK, 382 A16_MARK, ST0_PWM_MARK, LCD_DON_A_MARK, TIOC4A_C_MARK, 383 384 /* IPSR2 */ 385 D14_MARK, TX2_B_MARK, FSE_A_MARK, ET0_TX_CLK_B_MARK, 386 D13_MARK, RX2_B_MARK, FRB_A_MARK, ET0_ETXD6_B_MARK, 387 D12_MARK, FWE_A_MARK, ET0_ETXD5_B_MARK, 388 D11_MARK, RSPI_MISO_A_MARK, QMI_QIO1_A_MARK, FRE_A_MARK, 389 ET0_ETXD3_B_MARK, 390 D10_MARK, RSPI_MOSI_A_MARK, QMO_QIO0_A_MARK, FALE_A_MARK, 391 ET0_ETXD2_B_MARK, 392 D9_MARK, SD0_CMD_A_MARK, MMC_CMD_A_MARK, QIO3_A_MARK, 393 FCLE_A_MARK, ET0_ETXD1_B_MARK, 394 D8_MARK, SD0_CLK_A_MARK, MMC_CLK_A_MARK, QIO2_A_MARK, 395 FCE_A_MARK, ET0_GTX_CLK_B_MARK, 396 D7_MARK, RSPI_SSL_A_MARK, MMC_D7_A_MARK, QSSL_A_MARK, 397 FD7_A_MARK, 398 D6_MARK, RSPI_RSPCK_A_MARK, MMC_D6_A_MARK, QSPCLK_A_MARK, 399 FD6_A_MARK, 400 D5_MARK, SD0_WP_A_MARK, MMC_D5_A_MARK, FD5_A_MARK, 401 D4_MARK, SD0_CD_A_MARK, MMC_D4_A_MARK, ST1_D7_MARK, 402 FD4_A_MARK, 403 404 /* IPSR3 */ 405 DRACK0_MARK, SD1_DAT2_A_MARK, ATAG_MARK, TCLK1_A_MARK, ET0_ETXD7_MARK, 406 EX_WAIT2_MARK, SD1_DAT1_A_MARK, DACK2_MARK, CAN1_RX_C_MARK, 407 ET0_MAGIC_C_MARK, ET0_ETXD6_A_MARK, 408 EX_WAIT1_MARK, SD1_DAT0_A_MARK, DREQ2_MARK, CAN1_TX_C_MARK, 409 ET0_LINK_C_MARK, ET0_ETXD5_A_MARK, 410 EX_WAIT0_MARK, TCLK1_B_MARK, 411 RD_WR_MARK, TCLK0_MARK, CAN_CLK_B_MARK, ET0_ETXD4_MARK, 412 EX_CS5_MARK, SD1_CMD_A_MARK, ATADIR_MARK, QSSL_B_MARK, 413 ET0_ETXD3_A_MARK, 414 EX_CS4_MARK, SD1_WP_A_MARK, ATAWR_MARK, QMI_QIO1_B_MARK, 415 ET0_ETXD2_A_MARK, 416 EX_CS3_MARK, SD1_CD_A_MARK, ATARD_MARK, QMO_QIO0_B_MARK, 417 ET0_ETXD1_A_MARK, 418 EX_CS2_MARK, TX3_B_MARK, ATACS1_MARK, QSPCLK_B_MARK, 419 ET0_GTX_CLK_A_MARK, 420 EX_CS1_MARK, RX3_B_MARK, ATACS0_MARK, QIO2_B_MARK, 421 ET0_ETXD0_MARK, 422 CS1_A26_MARK, QIO3_B_MARK, 423 D15_MARK, SCK2_B_MARK, 424 425 /* IPSR4 */ 426 SCK2_A_MARK, VI0_G3_MARK, 427 RTS1_B_MARK, VI0_G2_MARK, 428 CTS1_B_MARK, VI0_DATA7_VI0_G1_MARK, 429 TX1_B_MARK, VI0_DATA6_VI0_G0_MARK, ET0_PHY_INT_A_MARK, 430 RX1_B_MARK, VI0_DATA5_VI0_B5_MARK, ET0_MAGIC_A_MARK, 431 SCK1_B_MARK, VI0_DATA4_VI0_B4_MARK, ET0_LINK_A_MARK, 432 RTS0_B_MARK, VI0_DATA3_VI0_B3_MARK, ET0_MDIO_A_MARK, 433 CTS0_B_MARK, VI0_DATA2_VI0_B2_MARK, RMII0_MDIO_A_MARK, 434 ET0_MDC_MARK, 435 HTX0_A_MARK, TX1_A_MARK, VI0_DATA1_VI0_B1_MARK, 436 RMII0_MDC_A_MARK, ET0_COL_MARK, 437 HRX0_A_MARK, RX1_A_MARK, VI0_DATA0_VI0_B0_MARK, 438 RMII0_CRS_DV_A_MARK, ET0_CRS_MARK, 439 HSCK0_A_MARK, SCK1_A_MARK, VI0_VSYNC_MARK, 440 RMII0_RX_ER_A_MARK, ET0_RX_ER_MARK, 441 HRTS0_A_MARK, RTS1_A_MARK, VI0_HSYNC_MARK, 442 RMII0_TXD_EN_A_MARK, ET0_RX_DV_MARK, 443 HCTS0_A_MARK, CTS1_A_MARK, VI0_FIELD_MARK, 444 RMII0_RXD1_A_MARK, ET0_ERXD7_MARK, 445 446 /* IPSR5 */ 447 SD2_CLK_A_MARK, RX2_A_MARK, VI0_G4_MARK, ET0_RX_CLK_B_MARK, 448 SD2_CMD_A_MARK, TX2_A_MARK, VI0_G5_MARK, ET0_ERXD2_B_MARK, 449 SD2_DAT0_A_MARK, RX3_A_MARK, VI0_R0_MARK, ET0_ERXD3_B_MARK, 450 SD2_DAT1_A_MARK, TX3_A_MARK, VI0_R1_MARK, ET0_MDIO_B_MARK, 451 SD2_DAT2_A_MARK, RX4_A_MARK, VI0_R2_MARK, ET0_LINK_B_MARK, 452 SD2_DAT3_A_MARK, TX4_A_MARK, VI0_R3_MARK, ET0_MAGIC_B_MARK, 453 SD2_CD_A_MARK, RX5_A_MARK, VI0_R4_MARK, ET0_PHY_INT_B_MARK, 454 SD2_WP_A_MARK, TX5_A_MARK, VI0_R5_MARK, 455 REF125CK_MARK, ADTRG_MARK, RX5_C_MARK, 456 REF50CK_MARK, CTS1_E_MARK, HCTS0_D_MARK, 457 458 /* IPSR6 */ 459 DU0_DR0_MARK, SCIF_CLK_B_MARK, HRX0_D_MARK, IETX_A_MARK, 460 TCLKA_A_MARK, HIFD00_MARK, 461 DU0_DR1_MARK, SCK0_B_MARK, HTX0_D_MARK, IERX_A_MARK, 462 TCLKB_A_MARK, HIFD01_MARK, 463 DU0_DR2_MARK, RX0_B_MARK, TCLKC_A_MARK, HIFD02_MARK, 464 DU0_DR3_MARK, TX0_B_MARK, TCLKD_A_MARK, HIFD03_MARK, 465 DU0_DR4_MARK, CTS0_C_MARK, TIOC0A_A_MARK, HIFD04_MARK, 466 DU0_DR5_MARK, RTS0_C_MARK, TIOC0B_A_MARK, HIFD05_MARK, 467 DU0_DR6_MARK, SCK1_C_MARK, TIOC0C_A_MARK, HIFD06_MARK, 468 DU0_DR7_MARK, RX1_C_MARK, TIOC0D_A_MARK, HIFD07_MARK, 469 DU0_DG0_MARK, TX1_C_MARK, HSCK0_D_MARK, IECLK_A_MARK, 470 TIOC1A_A_MARK, HIFD08_MARK, 471 DU0_DG1_MARK, CTS1_C_MARK, HRTS0_D_MARK, TIOC1B_A_MARK, 472 HIFD09_MARK, 473 474 /* IPSR7 */ 475 DU0_DG2_MARK, RTS1_C_MARK, RMII0_MDC_B_MARK, TIOC2A_A_MARK, 476 HIFD10_MARK, 477 DU0_DG3_MARK, SCK2_C_MARK, RMII0_MDIO_B_MARK, TIOC2B_A_MARK, 478 HIFD11_MARK, 479 DU0_DG4_MARK, RX2_C_MARK, RMII0_CRS_DV_B_MARK, TIOC3A_A_MARK, 480 HIFD12_MARK, 481 DU0_DG5_MARK, TX2_C_MARK, RMII0_RX_ER_B_MARK, TIOC3B_A_MARK, 482 HIFD13_MARK, 483 DU0_DG6_MARK, RX3_C_MARK, RMII0_RXD0_B_MARK, TIOC3C_A_MARK, 484 HIFD14_MARK, 485 DU0_DG7_MARK, TX3_C_MARK, RMII0_RXD1_B_MARK, TIOC3D_A_MARK, 486 HIFD15_MARK, 487 DU0_DB0_MARK, RX4_C_MARK, RMII0_TXD_EN_B_MARK, TIOC4A_A_MARK, 488 HIFCS_MARK, 489 DU0_DB1_MARK, TX4_C_MARK, RMII0_TXD0_B_MARK, TIOC4B_A_MARK, 490 HIFRS_MARK, 491 DU0_DB2_MARK, RX5_B_MARK, RMII0_TXD1_B_MARK, TIOC4C_A_MARK, 492 HIFWR_MARK, 493 DU0_DB3_MARK, TX5_B_MARK, TIOC4D_A_MARK, HIFRD_MARK, 494 DU0_DB4_MARK, HIFINT_MARK, 495 496 /* IPSR8 */ 497 DU0_DB5_MARK, HIFDREQ_MARK, 498 DU0_DB6_MARK, HIFRDY_MARK, 499 DU0_DB7_MARK, SSI_SCK0_B_MARK, HIFEBL_B_MARK, 500 DU0_DOTCLKIN_MARK, HSPI_CS0_C_MARK, SSI_WS0_B_MARK, 501 DU0_DOTCLKOUT_MARK, HSPI_CLK0_C_MARK, SSI_SDATA0_B_MARK, 502 DU0_EXHSYNC_DU0_HSYNC_MARK, HSPI_TX0_C_MARK, SSI_SCK1_B_MARK, 503 DU0_EXVSYNC_DU0_VSYNC_MARK, HSPI_RX0_C_MARK, SSI_WS1_B_MARK, 504 DU0_EXODDF_DU0_ODDF_MARK, CAN0_RX_B_MARK, HSCK0_B_MARK, 505 SSI_SDATA1_B_MARK, 506 DU0_DISP_MARK, CAN0_TX_B_MARK, HRX0_B_MARK, AUDIO_CLKA_B_MARK, 507 DU0_CDE_MARK, HTX0_B_MARK, AUDIO_CLKB_B_MARK, LCD_VCPWC_B_MARK, 508 IRQ0_A_MARK, HSPI_TX_B_MARK, RX3_E_MARK, ET0_ERXD0_MARK, 509 IRQ1_A_MARK, HSPI_RX_B_MARK, TX3_E_MARK, ET0_ERXD1_MARK, 510 IRQ2_A_MARK, CTS0_A_MARK, HCTS0_B_MARK, ET0_ERXD2_A_MARK, 511 IRQ3_A_MARK, RTS0_A_MARK, HRTS0_B_MARK, ET0_ERXD3_A_MARK, 512 513 /* IPSR9 */ 514 VI1_CLK_A_MARK, FD0_B_MARK, LCD_DATA0_B_MARK, 515 VI1_0_A_MARK, FD1_B_MARK, LCD_DATA1_B_MARK, 516 VI1_1_A_MARK, FD2_B_MARK, LCD_DATA2_B_MARK, 517 VI1_2_A_MARK, FD3_B_MARK, LCD_DATA3_B_MARK, 518 VI1_3_A_MARK, FD4_B_MARK, LCD_DATA4_B_MARK, 519 VI1_4_A_MARK, FD5_B_MARK, LCD_DATA5_B_MARK, 520 VI1_5_A_MARK, FD6_B_MARK, LCD_DATA6_B_MARK, 521 VI1_6_A_MARK, FD7_B_MARK, LCD_DATA7_B_MARK, 522 VI1_7_A_MARK, FCE_B_MARK, LCD_DATA8_B_MARK, 523 SSI_SCK0_A_MARK, TIOC1A_B_MARK, LCD_DATA9_B_MARK, 524 SSI_WS0_A_MARK, TIOC1B_B_MARK, LCD_DATA10_B_MARK, 525 SSI_SDATA0_A_MARK, VI1_0_B_MARK, TIOC2A_B_MARK, LCD_DATA11_B_MARK, 526 SSI_SCK1_A_MARK, VI1_1_B_MARK, TIOC2B_B_MARK, LCD_DATA12_B_MARK, 527 SSI_WS1_A_MARK, VI1_2_B_MARK, LCD_DATA13_B_MARK, 528 SSI_SDATA1_A_MARK, VI1_3_B_MARK, LCD_DATA14_B_MARK, 529 530 /* IPSR10 */ 531 SSI_SCK23_MARK, VI1_4_B_MARK, RX1_D_MARK, FCLE_B_MARK, 532 LCD_DATA15_B_MARK, 533 SSI_WS23_MARK, VI1_5_B_MARK, TX1_D_MARK, HSCK0_C_MARK, 534 FALE_B_MARK, LCD_DON_B_MARK, 535 SSI_SDATA2_MARK, VI1_6_B_MARK, HRX0_C_MARK, FRE_B_MARK, 536 LCD_CL1_B_MARK, 537 SSI_SDATA3_MARK, VI1_7_B_MARK, HTX0_C_MARK, FWE_B_MARK, 538 LCD_CL2_B_MARK, 539 AUDIO_CLKA_A_MARK, VI1_CLK_B_MARK, SCK1_D_MARK, IECLK_B_MARK, 540 LCD_FLM_B_MARK, 541 AUDIO_CLKB_A_MARK, LCD_CLK_B_MARK, 542 AUDIO_CLKC_MARK, SCK1_E_MARK, HCTS0_C_MARK, FRB_B_MARK, 543 LCD_VEPWC_B_MARK, 544 AUDIO_CLKOUT_MARK, TX1_E_MARK, HRTS0_C_MARK, FSE_B_MARK, 545 LCD_M_DISP_B_MARK, 546 CAN_CLK_A_MARK, RX4_D_MARK, 547 CAN0_TX_A_MARK, TX4_D_MARK, MLB_CLK_MARK, 548 CAN1_RX_A_MARK, IRQ1_B_MARK, 549 CAN0_RX_A_MARK, IRQ0_B_MARK, MLB_SIG_MARK, 550 CAN1_TX_A_MARK, TX5_C_MARK, MLB_DAT_MARK, 551 552 /* IPSR11 */ 553 SCL1_MARK, SCIF_CLK_C_MARK, 554 SDA1_MARK, RX1_E_MARK, 555 SDA0_MARK, HIFEBL_A_MARK, 556 SDSELF_MARK, RTS1_E_MARK, 557 SCIF_CLK_A_MARK, HSPI_CLK_A_MARK, VI0_CLK_MARK, RMII0_TXD0_A_MARK, 558 ET0_ERXD4_MARK, 559 SCK0_A_MARK, HSPI_CS_A_MARK, VI0_CLKENB_MARK, RMII0_TXD1_A_MARK, 560 ET0_ERXD5_MARK, 561 RX0_A_MARK, HSPI_RX_A_MARK, RMII0_RXD0_A_MARK, ET0_ERXD6_MARK, 562 TX0_A_MARK, HSPI_TX_A_MARK, 563 PENC1_MARK, TX3_D_MARK, CAN1_TX_B_MARK, TX5_D_MARK, 564 IETX_B_MARK, 565 USB_OVC1_MARK, RX3_D_MARK, CAN1_RX_B_MARK, RX5_D_MARK, 566 IERX_B_MARK, 567 DREQ0_MARK, SD1_CLK_A_MARK, ET0_TX_EN_MARK, 568 DACK0_MARK, SD1_DAT3_A_MARK, ET0_TX_ER_MARK, 569 DREQ1_MARK, HSPI_CLK_B_MARK, RX4_B_MARK, ET0_PHY_INT_C_MARK, 570 ET0_TX_CLK_A_MARK, 571 DACK1_MARK, HSPI_CS_B_MARK, TX4_B_MARK, ET0_RX_CLK_A_MARK, 572 PRESETOUT_MARK, ST_CLKOUT_MARK, 573 574 PINMUX_MARK_END, 575 }; 576 577 static const u16 pinmux_data[] = { 578 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ 579 580 PINMUX_SINGLE(CLKOUT), 581 PINMUX_SINGLE(BS), 582 PINMUX_SINGLE(CS0), 583 PINMUX_SINGLE(EX_CS0), 584 PINMUX_SINGLE(RD), 585 PINMUX_SINGLE(WE0), 586 PINMUX_SINGLE(WE1), 587 PINMUX_SINGLE(SCL0), 588 PINMUX_SINGLE(PENC0), 589 PINMUX_SINGLE(USB_OVC0), 590 PINMUX_SINGLE(IRQ2_B), 591 PINMUX_SINGLE(IRQ3_B), 592 593 /* IPSR0 */ 594 PINMUX_IPSR_GPSR(IP0_1_0, A0), 595 PINMUX_IPSR_GPSR(IP0_1_0, ST0_CLKIN), 596 PINMUX_IPSR_MSEL(IP0_1_0, LCD_DATA0_A, SEL_LCDC_0), 597 PINMUX_IPSR_MSEL(IP0_1_0, TCLKA_C, SEL_MTU2_CLK_1), 598 599 PINMUX_IPSR_GPSR(IP0_3_2, A1), 600 PINMUX_IPSR_GPSR(IP0_3_2, ST0_REQ), 601 PINMUX_IPSR_MSEL(IP0_3_2, LCD_DATA1_A, SEL_LCDC_0), 602 PINMUX_IPSR_MSEL(IP0_3_2, TCLKB_C, SEL_MTU2_CLK_1), 603 604 PINMUX_IPSR_GPSR(IP0_5_4, A2), 605 PINMUX_IPSR_GPSR(IP0_5_4, ST0_SYC), 606 PINMUX_IPSR_MSEL(IP0_5_4, LCD_DATA2_A, SEL_LCDC_0), 607 PINMUX_IPSR_MSEL(IP0_5_4, TCLKC_C, SEL_MTU2_CLK_1), 608 609 PINMUX_IPSR_GPSR(IP0_7_6, A3), 610 PINMUX_IPSR_GPSR(IP0_7_6, ST0_VLD), 611 PINMUX_IPSR_MSEL(IP0_7_6, LCD_DATA3_A, SEL_LCDC_0), 612 PINMUX_IPSR_MSEL(IP0_7_6, TCLKD_C, SEL_MTU2_CLK_1), 613 614 PINMUX_IPSR_GPSR(IP0_9_8, A4), 615 PINMUX_IPSR_GPSR(IP0_9_8, ST0_D0), 616 PINMUX_IPSR_MSEL(IP0_9_8, LCD_DATA4_A, SEL_LCDC_0), 617 PINMUX_IPSR_MSEL(IP0_9_8, TIOC0A_C, SEL_MTU2_CH0_1), 618 619 PINMUX_IPSR_GPSR(IP0_11_10, A5), 620 PINMUX_IPSR_GPSR(IP0_11_10, ST0_D1), 621 PINMUX_IPSR_MSEL(IP0_11_10, LCD_DATA5_A, SEL_LCDC_0), 622 PINMUX_IPSR_MSEL(IP0_11_10, TIOC0B_C, SEL_MTU2_CH0_1), 623 624 PINMUX_IPSR_GPSR(IP0_13_12, A6), 625 PINMUX_IPSR_GPSR(IP0_13_12, ST0_D2), 626 PINMUX_IPSR_MSEL(IP0_13_12, LCD_DATA6_A, SEL_LCDC_0), 627 PINMUX_IPSR_MSEL(IP0_13_12, TIOC0C_C, SEL_MTU2_CH0_1), 628 629 PINMUX_IPSR_GPSR(IP0_15_14, A7), 630 PINMUX_IPSR_GPSR(IP0_15_14, ST0_D3), 631 PINMUX_IPSR_MSEL(IP0_15_14, LCD_DATA7_A, SEL_LCDC_0), 632 PINMUX_IPSR_MSEL(IP0_15_14, TIOC0D_C, SEL_MTU2_CH0_1), 633 634 PINMUX_IPSR_GPSR(IP0_17_16, A8), 635 PINMUX_IPSR_GPSR(IP0_17_16, ST0_D4), 636 PINMUX_IPSR_MSEL(IP0_17_16, LCD_DATA8_A, SEL_LCDC_0), 637 PINMUX_IPSR_MSEL(IP0_17_16, TIOC1A_C, SEL_MTU2_CH1_2), 638 639 PINMUX_IPSR_GPSR(IP0_19_18, A9), 640 PINMUX_IPSR_GPSR(IP0_19_18, ST0_D5), 641 PINMUX_IPSR_MSEL(IP0_19_18, LCD_DATA9_A, SEL_LCDC_0), 642 PINMUX_IPSR_MSEL(IP0_19_18, TIOC1B_C, SEL_MTU2_CH1_2), 643 644 PINMUX_IPSR_GPSR(IP0_21_20, A10), 645 PINMUX_IPSR_GPSR(IP0_21_20, ST0_D6), 646 PINMUX_IPSR_MSEL(IP0_21_20, LCD_DATA10_A, SEL_LCDC_0), 647 PINMUX_IPSR_MSEL(IP0_21_20, TIOC2A_C, SEL_MTU2_CH2_2), 648 649 PINMUX_IPSR_GPSR(IP0_23_22, A11), 650 PINMUX_IPSR_GPSR(IP0_23_22, ST0_D7), 651 PINMUX_IPSR_MSEL(IP0_23_22, LCD_DATA11_A, SEL_LCDC_0), 652 PINMUX_IPSR_MSEL(IP0_23_22, TIOC2B_C, SEL_MTU2_CH2_2), 653 654 PINMUX_IPSR_GPSR(IP0_25_24, A12), 655 PINMUX_IPSR_MSEL(IP0_25_24, LCD_DATA12_A, SEL_LCDC_0), 656 PINMUX_IPSR_MSEL(IP0_25_24, TIOC3A_C, SEL_MTU2_CH3_1), 657 658 PINMUX_IPSR_GPSR(IP0_27_26, A13), 659 PINMUX_IPSR_MSEL(IP0_27_26, LCD_DATA13_A, SEL_LCDC_0), 660 PINMUX_IPSR_MSEL(IP0_27_26, TIOC3B_C, SEL_MTU2_CH3_1), 661 662 PINMUX_IPSR_GPSR(IP0_29_28, A14), 663 PINMUX_IPSR_MSEL(IP0_29_28, LCD_DATA14_A, SEL_LCDC_0), 664 PINMUX_IPSR_MSEL(IP0_29_28, TIOC3C_C, SEL_MTU2_CH3_1), 665 666 PINMUX_IPSR_GPSR(IP0_31_30, A15), 667 PINMUX_IPSR_GPSR(IP0_31_30, ST0_VCO_CLKIN), 668 PINMUX_IPSR_MSEL(IP0_31_30, LCD_DATA15_A, SEL_LCDC_0), 669 PINMUX_IPSR_MSEL(IP0_31_30, TIOC3D_C, SEL_MTU2_CH3_1), 670 671 672 /* IPSR1 */ 673 PINMUX_IPSR_GPSR(IP1_1_0, A16), 674 PINMUX_IPSR_GPSR(IP1_1_0, ST0_PWM), 675 PINMUX_IPSR_MSEL(IP1_1_0, LCD_DON_A, SEL_LCDC_0), 676 PINMUX_IPSR_MSEL(IP1_1_0, TIOC4A_C, SEL_MTU2_CH4_1), 677 678 PINMUX_IPSR_GPSR(IP1_3_2, A17), 679 PINMUX_IPSR_GPSR(IP1_3_2, ST1_VCO_CLKIN), 680 PINMUX_IPSR_MSEL(IP1_3_2, LCD_CL1_A, SEL_LCDC_0), 681 PINMUX_IPSR_MSEL(IP1_3_2, TIOC4B_C, SEL_MTU2_CH4_1), 682 683 PINMUX_IPSR_GPSR(IP1_5_4, A18), 684 PINMUX_IPSR_GPSR(IP1_5_4, ST1_PWM), 685 PINMUX_IPSR_MSEL(IP1_5_4, LCD_CL2_A, SEL_LCDC_0), 686 PINMUX_IPSR_MSEL(IP1_5_4, TIOC4C_C, SEL_MTU2_CH4_1), 687 688 PINMUX_IPSR_GPSR(IP1_7_6, A19), 689 PINMUX_IPSR_GPSR(IP1_7_6, ST1_CLKIN), 690 PINMUX_IPSR_MSEL(IP1_7_6, LCD_CLK_A, SEL_LCDC_0), 691 PINMUX_IPSR_MSEL(IP1_7_6, TIOC4D_C, SEL_MTU2_CH4_1), 692 693 PINMUX_IPSR_GPSR(IP1_9_8, A20), 694 PINMUX_IPSR_GPSR(IP1_9_8, ST1_REQ), 695 PINMUX_IPSR_MSEL(IP1_9_8, LCD_FLM_A, SEL_LCDC_0), 696 697 PINMUX_IPSR_GPSR(IP1_11_10, A21), 698 PINMUX_IPSR_GPSR(IP1_11_10, ST1_SYC), 699 PINMUX_IPSR_MSEL(IP1_11_10, LCD_VCPWC_A, SEL_LCDC_0), 700 701 PINMUX_IPSR_GPSR(IP1_13_12, A22), 702 PINMUX_IPSR_GPSR(IP1_13_12, ST1_VLD), 703 PINMUX_IPSR_MSEL(IP1_13_12, LCD_VEPWC_A, SEL_LCDC_0), 704 705 PINMUX_IPSR_GPSR(IP1_15_14, A23), 706 PINMUX_IPSR_GPSR(IP1_15_14, ST1_D0), 707 PINMUX_IPSR_MSEL(IP1_15_14, LCD_M_DISP_A, SEL_LCDC_0), 708 709 PINMUX_IPSR_GPSR(IP1_17_16, A24), 710 PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3), 711 PINMUX_IPSR_GPSR(IP1_17_16, ST1_D1), 712 713 PINMUX_IPSR_GPSR(IP1_19_18, A25), 714 PINMUX_IPSR_MSEL(IP1_17_16, RX2_D, SEL_SCIF2_3), 715 PINMUX_IPSR_GPSR(IP1_17_16, ST1_D2), 716 717 PINMUX_IPSR_GPSR(IP1_22_20, D0), 718 PINMUX_IPSR_MSEL(IP1_22_20, SD0_DAT0_A, SEL_SDHI0_0), 719 PINMUX_IPSR_MSEL(IP1_22_20, MMC_D0_A, SEL_MMC_0), 720 PINMUX_IPSR_GPSR(IP1_22_20, ST1_D3), 721 PINMUX_IPSR_MSEL(IP1_22_20, FD0_A, SEL_FLCTL_0), 722 723 PINMUX_IPSR_GPSR(IP1_25_23, D1), 724 PINMUX_IPSR_MSEL(IP1_25_23, SD0_DAT0_A, SEL_SDHI0_0), 725 PINMUX_IPSR_MSEL(IP1_25_23, MMC_D1_A, SEL_MMC_0), 726 PINMUX_IPSR_GPSR(IP1_25_23, ST1_D4), 727 PINMUX_IPSR_MSEL(IP1_25_23, FD1_A, SEL_FLCTL_0), 728 729 PINMUX_IPSR_GPSR(IP1_28_26, D2), 730 PINMUX_IPSR_MSEL(IP1_28_26, SD0_DAT0_A, SEL_SDHI0_0), 731 PINMUX_IPSR_MSEL(IP1_28_26, MMC_D2_A, SEL_MMC_0), 732 PINMUX_IPSR_GPSR(IP1_28_26, ST1_D5), 733 PINMUX_IPSR_MSEL(IP1_28_26, FD2_A, SEL_FLCTL_0), 734 735 PINMUX_IPSR_GPSR(IP1_31_29, D3), 736 PINMUX_IPSR_MSEL(IP1_31_29, SD0_DAT0_A, SEL_SDHI0_0), 737 PINMUX_IPSR_MSEL(IP1_31_29, MMC_D3_A, SEL_MMC_0), 738 PINMUX_IPSR_GPSR(IP1_31_29, ST1_D6), 739 PINMUX_IPSR_MSEL(IP1_31_29, FD3_A, SEL_FLCTL_0), 740 741 /* IPSR2 */ 742 PINMUX_IPSR_GPSR(IP2_2_0, D4), 743 PINMUX_IPSR_MSEL(IP2_2_0, SD0_CD_A, SEL_SDHI0_0), 744 PINMUX_IPSR_MSEL(IP2_2_0, MMC_D4_A, SEL_MMC_0), 745 PINMUX_IPSR_GPSR(IP2_2_0, ST1_D7), 746 PINMUX_IPSR_MSEL(IP2_2_0, FD4_A, SEL_FLCTL_0), 747 748 PINMUX_IPSR_GPSR(IP2_4_3, D5), 749 PINMUX_IPSR_MSEL(IP2_4_3, SD0_WP_A, SEL_SDHI0_0), 750 PINMUX_IPSR_MSEL(IP2_4_3, MMC_D5_A, SEL_MMC_0), 751 PINMUX_IPSR_MSEL(IP2_4_3, FD5_A, SEL_FLCTL_0), 752 753 PINMUX_IPSR_GPSR(IP2_7_5, D6), 754 PINMUX_IPSR_MSEL(IP2_7_5, RSPI_RSPCK_A, SEL_RSPI_0), 755 PINMUX_IPSR_MSEL(IP2_7_5, MMC_D6_A, SEL_MMC_0), 756 PINMUX_IPSR_MSEL(IP2_7_5, QSPCLK_A, SEL_RQSPI_0), 757 PINMUX_IPSR_MSEL(IP2_7_5, FD6_A, SEL_FLCTL_0), 758 759 PINMUX_IPSR_GPSR(IP2_10_8, D7), 760 PINMUX_IPSR_MSEL(IP2_10_8, RSPI_SSL_A, SEL_RSPI_0), 761 PINMUX_IPSR_MSEL(IP2_10_8, MMC_D7_A, SEL_MMC_0), 762 PINMUX_IPSR_MSEL(IP2_10_8, QSSL_A, SEL_RQSPI_0), 763 PINMUX_IPSR_MSEL(IP2_10_8, FD7_A, SEL_FLCTL_0), 764 765 PINMUX_IPSR_GPSR(IP2_13_11, D8), 766 PINMUX_IPSR_MSEL(IP2_13_11, SD0_CLK_A, SEL_SDHI0_0), 767 PINMUX_IPSR_MSEL(IP2_13_11, MMC_CLK_A, SEL_MMC_0), 768 PINMUX_IPSR_MSEL(IP2_13_11, QIO2_A, SEL_RQSPI_0), 769 PINMUX_IPSR_MSEL(IP2_13_11, FCE_A, SEL_FLCTL_0), 770 PINMUX_IPSR_MSEL(IP2_13_11, ET0_GTX_CLK_B, SEL_ET0_1), 771 772 PINMUX_IPSR_GPSR(IP2_16_14, D9), 773 PINMUX_IPSR_MSEL(IP2_16_14, SD0_CMD_A, SEL_SDHI0_0), 774 PINMUX_IPSR_MSEL(IP2_16_14, MMC_CMD_A, SEL_MMC_0), 775 PINMUX_IPSR_MSEL(IP2_16_14, QIO3_A, SEL_RQSPI_0), 776 PINMUX_IPSR_MSEL(IP2_16_14, FCLE_A, SEL_FLCTL_0), 777 PINMUX_IPSR_MSEL(IP2_16_14, ET0_ETXD1_B, SEL_ET0_1), 778 779 PINMUX_IPSR_GPSR(IP2_19_17, D10), 780 PINMUX_IPSR_MSEL(IP2_19_17, RSPI_MOSI_A, SEL_RSPI_0), 781 PINMUX_IPSR_MSEL(IP2_19_17, QMO_QIO0_A, SEL_RQSPI_0), 782 PINMUX_IPSR_MSEL(IP2_19_17, FALE_A, SEL_FLCTL_0), 783 PINMUX_IPSR_MSEL(IP2_19_17, ET0_ETXD2_B, SEL_ET0_1), 784 785 PINMUX_IPSR_GPSR(IP2_22_20, D11), 786 PINMUX_IPSR_MSEL(IP2_22_20, RSPI_MISO_A, SEL_RSPI_0), 787 PINMUX_IPSR_MSEL(IP2_22_20, QMI_QIO1_A, SEL_RQSPI_0), 788 PINMUX_IPSR_MSEL(IP2_22_20, FRE_A, SEL_FLCTL_0), 789 790 PINMUX_IPSR_GPSR(IP2_24_23, D12), 791 PINMUX_IPSR_MSEL(IP2_24_23, FWE_A, SEL_FLCTL_0), 792 PINMUX_IPSR_MSEL(IP2_24_23, ET0_ETXD5_B, SEL_ET0_1), 793 794 PINMUX_IPSR_GPSR(IP2_27_25, D13), 795 PINMUX_IPSR_MSEL(IP2_27_25, RX2_B, SEL_SCIF2_1), 796 PINMUX_IPSR_MSEL(IP2_27_25, FRB_A, SEL_FLCTL_0), 797 PINMUX_IPSR_MSEL(IP2_27_25, ET0_ETXD6_B, SEL_ET0_1), 798 799 PINMUX_IPSR_GPSR(IP2_30_28, D14), 800 PINMUX_IPSR_MSEL(IP2_30_28, TX2_B, SEL_SCIF2_1), 801 PINMUX_IPSR_MSEL(IP2_30_28, FSE_A, SEL_FLCTL_0), 802 PINMUX_IPSR_MSEL(IP2_30_28, ET0_TX_CLK_B, SEL_ET0_1), 803 804 /* IPSR3 */ 805 PINMUX_IPSR_GPSR(IP3_1_0, D15), 806 PINMUX_IPSR_MSEL(IP3_1_0, SCK2_B, SEL_SCIF2_1), 807 808 PINMUX_IPSR_GPSR(IP3_2, CS1_A26), 809 PINMUX_IPSR_MSEL(IP3_2, QIO3_B, SEL_RQSPI_1), 810 811 PINMUX_IPSR_GPSR(IP3_5_3, EX_CS1), 812 PINMUX_IPSR_MSEL(IP3_5_3, RX3_B, SEL_SCIF2_1), 813 PINMUX_IPSR_GPSR(IP3_5_3, ATACS0), 814 PINMUX_IPSR_MSEL(IP3_5_3, QIO2_B, SEL_RQSPI_1), 815 PINMUX_IPSR_GPSR(IP3_5_3, ET0_ETXD0), 816 817 PINMUX_IPSR_GPSR(IP3_8_6, EX_CS2), 818 PINMUX_IPSR_MSEL(IP3_8_6, TX3_B, SEL_SCIF3_1), 819 PINMUX_IPSR_GPSR(IP3_8_6, ATACS1), 820 PINMUX_IPSR_MSEL(IP3_8_6, QSPCLK_B, SEL_RQSPI_1), 821 PINMUX_IPSR_MSEL(IP3_8_6, ET0_GTX_CLK_A, SEL_ET0_0), 822 823 PINMUX_IPSR_GPSR(IP3_11_9, EX_CS3), 824 PINMUX_IPSR_MSEL(IP3_11_9, SD1_CD_A, SEL_SDHI1_0), 825 PINMUX_IPSR_GPSR(IP3_11_9, ATARD), 826 PINMUX_IPSR_MSEL(IP3_11_9, QMO_QIO0_B, SEL_RQSPI_1), 827 PINMUX_IPSR_MSEL(IP3_11_9, ET0_ETXD1_A, SEL_ET0_0), 828 829 PINMUX_IPSR_GPSR(IP3_14_12, EX_CS4), 830 PINMUX_IPSR_MSEL(IP3_14_12, SD1_WP_A, SEL_SDHI1_0), 831 PINMUX_IPSR_GPSR(IP3_14_12, ATAWR), 832 PINMUX_IPSR_MSEL(IP3_14_12, QMI_QIO1_B, SEL_RQSPI_1), 833 PINMUX_IPSR_MSEL(IP3_14_12, ET0_ETXD2_A, SEL_ET0_0), 834 835 PINMUX_IPSR_GPSR(IP3_17_15, EX_CS5), 836 PINMUX_IPSR_MSEL(IP3_17_15, SD1_CMD_A, SEL_SDHI1_0), 837 PINMUX_IPSR_GPSR(IP3_17_15, ATADIR), 838 PINMUX_IPSR_MSEL(IP3_17_15, QSSL_B, SEL_RQSPI_1), 839 PINMUX_IPSR_MSEL(IP3_17_15, ET0_ETXD3_A, SEL_ET0_0), 840 841 PINMUX_IPSR_GPSR(IP3_19_18, RD_WR), 842 PINMUX_IPSR_GPSR(IP3_19_18, TCLK0), 843 PINMUX_IPSR_MSEL(IP3_19_18, CAN_CLK_B, SEL_RCAN_CLK_1), 844 PINMUX_IPSR_GPSR(IP3_19_18, ET0_ETXD4), 845 846 PINMUX_IPSR_GPSR(IP3_20, EX_WAIT0), 847 PINMUX_IPSR_MSEL(IP3_20, TCLK1_B, SEL_TMU_1), 848 849 PINMUX_IPSR_GPSR(IP3_23_21, EX_WAIT1), 850 PINMUX_IPSR_MSEL(IP3_23_21, SD1_DAT0_A, SEL_SDHI1_0), 851 PINMUX_IPSR_GPSR(IP3_23_21, DREQ2), 852 PINMUX_IPSR_MSEL(IP3_23_21, CAN1_TX_C, SEL_RCAN1_2), 853 PINMUX_IPSR_MSEL(IP3_23_21, ET0_LINK_C, SEL_ET0_CTL_2), 854 PINMUX_IPSR_MSEL(IP3_23_21, ET0_ETXD5_A, SEL_ET0_0), 855 856 PINMUX_IPSR_GPSR(IP3_26_24, EX_WAIT2), 857 PINMUX_IPSR_MSEL(IP3_26_24, SD1_DAT1_A, SEL_SDHI1_0), 858 PINMUX_IPSR_GPSR(IP3_26_24, DACK2), 859 PINMUX_IPSR_MSEL(IP3_26_24, CAN1_RX_C, SEL_RCAN1_2), 860 PINMUX_IPSR_MSEL(IP3_26_24, ET0_MAGIC_C, SEL_ET0_CTL_2), 861 PINMUX_IPSR_MSEL(IP3_26_24, ET0_ETXD6_A, SEL_ET0_0), 862 863 PINMUX_IPSR_GPSR(IP3_29_27, DRACK0), 864 PINMUX_IPSR_MSEL(IP3_29_27, SD1_DAT2_A, SEL_SDHI1_0), 865 PINMUX_IPSR_GPSR(IP3_29_27, ATAG), 866 PINMUX_IPSR_MSEL(IP3_29_27, TCLK1_A, SEL_TMU_0), 867 PINMUX_IPSR_GPSR(IP3_29_27, ET0_ETXD7), 868 869 /* IPSR4 */ 870 PINMUX_IPSR_MSEL(IP4_2_0, HCTS0_A, SEL_HSCIF_0), 871 PINMUX_IPSR_MSEL(IP4_2_0, CTS1_A, SEL_SCIF1_0), 872 PINMUX_IPSR_GPSR(IP4_2_0, VI0_FIELD), 873 PINMUX_IPSR_MSEL(IP4_2_0, RMII0_RXD1_A, SEL_RMII_0), 874 PINMUX_IPSR_GPSR(IP4_2_0, ET0_ERXD7), 875 876 PINMUX_IPSR_MSEL(IP4_5_3, HRTS0_A, SEL_HSCIF_0), 877 PINMUX_IPSR_MSEL(IP4_5_3, RTS1_A, SEL_SCIF1_0), 878 PINMUX_IPSR_GPSR(IP4_5_3, VI0_HSYNC), 879 PINMUX_IPSR_MSEL(IP4_5_3, RMII0_TXD_EN_A, SEL_RMII_0), 880 PINMUX_IPSR_GPSR(IP4_5_3, ET0_RX_DV), 881 882 PINMUX_IPSR_MSEL(IP4_8_6, HSCK0_A, SEL_HSCIF_0), 883 PINMUX_IPSR_MSEL(IP4_8_6, SCK1_A, SEL_SCIF1_0), 884 PINMUX_IPSR_GPSR(IP4_8_6, VI0_VSYNC), 885 PINMUX_IPSR_MSEL(IP4_8_6, RMII0_RX_ER_A, SEL_RMII_0), 886 PINMUX_IPSR_GPSR(IP4_8_6, ET0_RX_ER), 887 888 PINMUX_IPSR_MSEL(IP4_11_9, HRX0_A, SEL_HSCIF_0), 889 PINMUX_IPSR_MSEL(IP4_11_9, RX1_A, SEL_SCIF1_0), 890 PINMUX_IPSR_GPSR(IP4_11_9, VI0_DATA0_VI0_B0), 891 PINMUX_IPSR_MSEL(IP4_11_9, RMII0_CRS_DV_A, SEL_RMII_0), 892 PINMUX_IPSR_GPSR(IP4_11_9, ET0_CRS), 893 894 PINMUX_IPSR_MSEL(IP4_14_12, HTX0_A, SEL_HSCIF_0), 895 PINMUX_IPSR_MSEL(IP4_14_12, TX1_A, SEL_SCIF1_0), 896 PINMUX_IPSR_GPSR(IP4_14_12, VI0_DATA1_VI0_B1), 897 PINMUX_IPSR_MSEL(IP4_14_12, RMII0_MDC_A, SEL_RMII_0), 898 PINMUX_IPSR_GPSR(IP4_14_12, ET0_COL), 899 900 PINMUX_IPSR_MSEL(IP4_17_15, CTS0_B, SEL_SCIF0_1), 901 PINMUX_IPSR_GPSR(IP4_17_15, VI0_DATA2_VI0_B2), 902 PINMUX_IPSR_MSEL(IP4_17_15, RMII0_MDIO_A, SEL_RMII_0), 903 PINMUX_IPSR_GPSR(IP4_17_15, ET0_MDC), 904 905 PINMUX_IPSR_MSEL(IP4_19_18, RTS0_B, SEL_SCIF0_1), 906 PINMUX_IPSR_GPSR(IP4_19_18, VI0_DATA3_VI0_B3), 907 PINMUX_IPSR_MSEL(IP4_19_18, ET0_MDIO_A, SEL_ET0_0), 908 909 PINMUX_IPSR_MSEL(IP4_21_20, SCK1_B, SEL_SCIF1_1), 910 PINMUX_IPSR_GPSR(IP4_21_20, VI0_DATA4_VI0_B4), 911 PINMUX_IPSR_MSEL(IP4_21_20, ET0_LINK_A, SEL_ET0_CTL_0), 912 913 PINMUX_IPSR_MSEL(IP4_23_22, RX1_B, SEL_SCIF1_1), 914 PINMUX_IPSR_GPSR(IP4_23_22, VI0_DATA5_VI0_B5), 915 PINMUX_IPSR_MSEL(IP4_23_22, ET0_MAGIC_A, SEL_ET0_CTL_0), 916 917 PINMUX_IPSR_MSEL(IP4_25_24, TX1_B, SEL_SCIF1_1), 918 PINMUX_IPSR_GPSR(IP4_25_24, VI0_DATA6_VI0_G0), 919 PINMUX_IPSR_MSEL(IP4_25_24, ET0_PHY_INT_A, SEL_ET0_CTL_0), 920 921 PINMUX_IPSR_MSEL(IP4_27_26, CTS1_B, SEL_SCIF1_1), 922 PINMUX_IPSR_GPSR(IP4_27_26, VI0_DATA7_VI0_G1), 923 924 PINMUX_IPSR_MSEL(IP4_29_28, RTS1_B, SEL_SCIF1_1), 925 PINMUX_IPSR_GPSR(IP4_29_28, VI0_G2), 926 927 PINMUX_IPSR_MSEL(IP4_31_30, SCK2_A, SEL_SCIF2_0), 928 PINMUX_IPSR_GPSR(IP4_31_30, VI0_G3), 929 930 /* IPSR5 */ 931 PINMUX_IPSR_MSEL(IP5_2_0, SD2_CLK_A, SEL_SDHI2_0), 932 PINMUX_IPSR_MSEL(IP5_2_0, RX2_A, SEL_SCIF2_0), 933 PINMUX_IPSR_GPSR(IP5_2_0, VI0_G4), 934 PINMUX_IPSR_MSEL(IP5_2_0, ET0_RX_CLK_B, SEL_ET0_1), 935 936 PINMUX_IPSR_MSEL(IP5_5_3, SD2_CMD_A, SEL_SDHI2_0), 937 PINMUX_IPSR_MSEL(IP5_5_3, TX2_A, SEL_SCIF2_0), 938 PINMUX_IPSR_GPSR(IP5_5_3, VI0_G5), 939 PINMUX_IPSR_MSEL(IP5_5_3, ET0_ERXD2_B, SEL_ET0_1), 940 941 PINMUX_IPSR_MSEL(IP5_8_6, SD2_DAT0_A, SEL_SDHI2_0), 942 PINMUX_IPSR_MSEL(IP5_8_6, RX3_A, SEL_SCIF3_0), 943 PINMUX_IPSR_GPSR(IP4_8_6, VI0_R0), 944 PINMUX_IPSR_MSEL(IP4_8_6, ET0_ERXD2_B, SEL_ET0_1), 945 946 PINMUX_IPSR_MSEL(IP5_11_9, SD2_DAT1_A, SEL_SDHI2_0), 947 PINMUX_IPSR_MSEL(IP5_11_9, TX3_A, SEL_SCIF3_0), 948 PINMUX_IPSR_GPSR(IP5_11_9, VI0_R1), 949 PINMUX_IPSR_MSEL(IP5_11_9, ET0_MDIO_B, SEL_ET0_1), 950 951 PINMUX_IPSR_MSEL(IP5_14_12, SD2_DAT2_A, SEL_SDHI2_0), 952 PINMUX_IPSR_MSEL(IP5_14_12, RX4_A, SEL_SCIF4_0), 953 PINMUX_IPSR_GPSR(IP5_14_12, VI0_R2), 954 PINMUX_IPSR_MSEL(IP5_14_12, ET0_LINK_B, SEL_ET0_CTL_1), 955 956 PINMUX_IPSR_MSEL(IP5_17_15, SD2_DAT3_A, SEL_SDHI2_0), 957 PINMUX_IPSR_MSEL(IP5_17_15, TX4_A, SEL_SCIF4_0), 958 PINMUX_IPSR_GPSR(IP5_17_15, VI0_R3), 959 PINMUX_IPSR_MSEL(IP5_17_15, ET0_MAGIC_B, SEL_ET0_CTL_1), 960 961 PINMUX_IPSR_MSEL(IP5_20_18, SD2_CD_A, SEL_SDHI2_0), 962 PINMUX_IPSR_MSEL(IP5_20_18, RX5_A, SEL_SCIF5_0), 963 PINMUX_IPSR_GPSR(IP5_20_18, VI0_R4), 964 PINMUX_IPSR_MSEL(IP5_20_18, ET0_PHY_INT_B, SEL_ET0_CTL_1), 965 966 PINMUX_IPSR_MSEL(IP5_22_21, SD2_WP_A, SEL_SDHI2_0), 967 PINMUX_IPSR_MSEL(IP5_22_21, TX5_A, SEL_SCIF5_0), 968 PINMUX_IPSR_GPSR(IP5_22_21, VI0_R5), 969 970 PINMUX_IPSR_GPSR(IP5_24_23, REF125CK), 971 PINMUX_IPSR_GPSR(IP5_24_23, ADTRG), 972 PINMUX_IPSR_MSEL(IP5_24_23, RX5_C, SEL_SCIF5_2), 973 PINMUX_IPSR_GPSR(IP5_26_25, REF50CK), 974 PINMUX_IPSR_MSEL(IP5_26_25, CTS1_E, SEL_SCIF1_3), 975 PINMUX_IPSR_MSEL(IP5_26_25, HCTS0_D, SEL_HSCIF_3), 976 977 /* IPSR6 */ 978 PINMUX_IPSR_GPSR(IP6_2_0, DU0_DR0), 979 PINMUX_IPSR_MSEL(IP6_2_0, SCIF_CLK_B, SEL_SCIF_CLK_1), 980 PINMUX_IPSR_MSEL(IP6_2_0, HRX0_D, SEL_HSCIF_3), 981 PINMUX_IPSR_MSEL(IP6_2_0, IETX_A, SEL_IEBUS_0), 982 PINMUX_IPSR_MSEL(IP6_2_0, TCLKA_A, SEL_MTU2_CLK_0), 983 PINMUX_IPSR_GPSR(IP6_2_0, HIFD00), 984 985 PINMUX_IPSR_GPSR(IP6_5_3, DU0_DR1), 986 PINMUX_IPSR_MSEL(IP6_5_3, SCK0_B, SEL_SCIF0_1), 987 PINMUX_IPSR_MSEL(IP6_5_3, HTX0_D, SEL_HSCIF_3), 988 PINMUX_IPSR_MSEL(IP6_5_3, IERX_A, SEL_IEBUS_0), 989 PINMUX_IPSR_MSEL(IP6_5_3, TCLKB_A, SEL_MTU2_CLK_0), 990 PINMUX_IPSR_GPSR(IP6_5_3, HIFD01), 991 992 PINMUX_IPSR_GPSR(IP6_7_6, DU0_DR2), 993 PINMUX_IPSR_MSEL(IP6_7_6, RX0_B, SEL_SCIF0_1), 994 PINMUX_IPSR_MSEL(IP6_7_6, TCLKC_A, SEL_MTU2_CLK_0), 995 PINMUX_IPSR_GPSR(IP6_7_6, HIFD02), 996 997 PINMUX_IPSR_GPSR(IP6_9_8, DU0_DR3), 998 PINMUX_IPSR_MSEL(IP6_9_8, TX0_B, SEL_SCIF0_1), 999 PINMUX_IPSR_MSEL(IP6_9_8, TCLKD_A, SEL_MTU2_CLK_0), 1000 PINMUX_IPSR_GPSR(IP6_9_8, HIFD03), 1001 1002 PINMUX_IPSR_GPSR(IP6_11_10, DU0_DR4), 1003 PINMUX_IPSR_MSEL(IP6_11_10, CTS0_C, SEL_SCIF0_2), 1004 PINMUX_IPSR_MSEL(IP6_11_10, TIOC0A_A, SEL_MTU2_CH0_0), 1005 PINMUX_IPSR_GPSR(IP6_11_10, HIFD04), 1006 1007 PINMUX_IPSR_GPSR(IP6_13_12, DU0_DR5), 1008 PINMUX_IPSR_MSEL(IP6_13_12, RTS0_C, SEL_SCIF0_1), 1009 PINMUX_IPSR_MSEL(IP6_13_12, TIOC0B_A, SEL_MTU2_CH0_0), 1010 PINMUX_IPSR_GPSR(IP6_13_12, HIFD05), 1011 1012 PINMUX_IPSR_GPSR(IP6_15_14, DU0_DR6), 1013 PINMUX_IPSR_MSEL(IP6_15_14, SCK1_C, SEL_SCIF1_2), 1014 PINMUX_IPSR_MSEL(IP6_15_14, TIOC0C_A, SEL_MTU2_CH0_0), 1015 PINMUX_IPSR_GPSR(IP6_15_14, HIFD06), 1016 1017 PINMUX_IPSR_GPSR(IP6_17_16, DU0_DR7), 1018 PINMUX_IPSR_MSEL(IP6_17_16, RX1_C, SEL_SCIF1_2), 1019 PINMUX_IPSR_MSEL(IP6_17_16, TIOC0D_A, SEL_MTU2_CH0_0), 1020 PINMUX_IPSR_GPSR(IP6_17_16, HIFD07), 1021 1022 PINMUX_IPSR_GPSR(IP6_20_18, DU0_DG0), 1023 PINMUX_IPSR_MSEL(IP6_20_18, TX1_C, SEL_SCIF1_2), 1024 PINMUX_IPSR_MSEL(IP6_20_18, HSCK0_D, SEL_HSCIF_3), 1025 PINMUX_IPSR_MSEL(IP6_20_18, IECLK_A, SEL_IEBUS_0), 1026 PINMUX_IPSR_MSEL(IP6_20_18, TIOC1A_A, SEL_MTU2_CH1_0), 1027 PINMUX_IPSR_GPSR(IP6_20_18, HIFD08), 1028 1029 PINMUX_IPSR_GPSR(IP6_23_21, DU0_DG1), 1030 PINMUX_IPSR_MSEL(IP6_23_21, CTS1_C, SEL_SCIF1_2), 1031 PINMUX_IPSR_MSEL(IP6_23_21, HRTS0_D, SEL_HSCIF_3), 1032 PINMUX_IPSR_MSEL(IP6_23_21, TIOC1B_A, SEL_MTU2_CH1_0), 1033 PINMUX_IPSR_GPSR(IP6_23_21, HIFD09), 1034 1035 /* IPSR7 */ 1036 PINMUX_IPSR_GPSR(IP7_2_0, DU0_DG2), 1037 PINMUX_IPSR_MSEL(IP7_2_0, RTS1_C, SEL_SCIF1_2), 1038 PINMUX_IPSR_MSEL(IP7_2_0, RMII0_MDC_B, SEL_RMII_1), 1039 PINMUX_IPSR_MSEL(IP7_2_0, TIOC2A_A, SEL_MTU2_CH2_0), 1040 PINMUX_IPSR_GPSR(IP7_2_0, HIFD10), 1041 1042 PINMUX_IPSR_GPSR(IP7_5_3, DU0_DG3), 1043 PINMUX_IPSR_MSEL(IP7_5_3, SCK2_C, SEL_SCIF2_2), 1044 PINMUX_IPSR_MSEL(IP7_5_3, RMII0_MDIO_B, SEL_RMII_1), 1045 PINMUX_IPSR_MSEL(IP7_5_3, TIOC2B_A, SEL_MTU2_CH2_0), 1046 PINMUX_IPSR_GPSR(IP7_5_3, HIFD11), 1047 1048 PINMUX_IPSR_GPSR(IP7_8_6, DU0_DG4), 1049 PINMUX_IPSR_MSEL(IP7_8_6, RX2_C, SEL_SCIF2_2), 1050 PINMUX_IPSR_MSEL(IP7_8_6, RMII0_CRS_DV_B, SEL_RMII_1), 1051 PINMUX_IPSR_MSEL(IP7_8_6, TIOC3A_A, SEL_MTU2_CH3_0), 1052 PINMUX_IPSR_GPSR(IP7_8_6, HIFD12), 1053 1054 PINMUX_IPSR_GPSR(IP7_11_9, DU0_DG5), 1055 PINMUX_IPSR_MSEL(IP7_11_9, TX2_C, SEL_SCIF2_2), 1056 PINMUX_IPSR_MSEL(IP7_11_9, RMII0_RX_ER_B, SEL_RMII_1), 1057 PINMUX_IPSR_MSEL(IP7_11_9, TIOC3B_A, SEL_MTU2_CH3_0), 1058 PINMUX_IPSR_GPSR(IP7_11_9, HIFD13), 1059 1060 PINMUX_IPSR_GPSR(IP7_14_12, DU0_DG6), 1061 PINMUX_IPSR_MSEL(IP7_14_12, RX3_C, SEL_SCIF3_2), 1062 PINMUX_IPSR_MSEL(IP7_14_12, RMII0_RXD0_B, SEL_RMII_1), 1063 PINMUX_IPSR_MSEL(IP7_14_12, TIOC3C_A, SEL_MTU2_CH3_0), 1064 PINMUX_IPSR_GPSR(IP7_14_12, HIFD14), 1065 1066 PINMUX_IPSR_GPSR(IP7_17_15, DU0_DG7), 1067 PINMUX_IPSR_MSEL(IP7_17_15, TX3_C, SEL_SCIF3_2), 1068 PINMUX_IPSR_MSEL(IP7_17_15, RMII0_RXD1_B, SEL_RMII_1), 1069 PINMUX_IPSR_MSEL(IP7_17_15, TIOC3D_A, SEL_MTU2_CH3_0), 1070 PINMUX_IPSR_GPSR(IP7_17_15, HIFD15), 1071 1072 PINMUX_IPSR_GPSR(IP7_20_18, DU0_DB0), 1073 PINMUX_IPSR_MSEL(IP7_20_18, RX4_C, SEL_SCIF4_2), 1074 PINMUX_IPSR_MSEL(IP7_20_18, RMII0_TXD_EN_B, SEL_RMII_1), 1075 PINMUX_IPSR_MSEL(IP7_20_18, TIOC4A_A, SEL_MTU2_CH4_0), 1076 PINMUX_IPSR_GPSR(IP7_20_18, HIFCS), 1077 1078 PINMUX_IPSR_GPSR(IP7_23_21, DU0_DB1), 1079 PINMUX_IPSR_MSEL(IP7_23_21, TX4_C, SEL_SCIF4_2), 1080 PINMUX_IPSR_MSEL(IP7_23_21, RMII0_TXD0_B, SEL_RMII_1), 1081 PINMUX_IPSR_MSEL(IP7_23_21, TIOC4B_A, SEL_MTU2_CH4_0), 1082 PINMUX_IPSR_GPSR(IP7_23_21, HIFWR), 1083 1084 PINMUX_IPSR_GPSR(IP7_26_24, DU0_DB2), 1085 PINMUX_IPSR_MSEL(IP7_26_24, RX5_B, SEL_SCIF5_1), 1086 PINMUX_IPSR_MSEL(IP7_26_24, RMII0_TXD1_B, SEL_RMII_1), 1087 PINMUX_IPSR_MSEL(IP7_26_24, TIOC4C_A, SEL_MTU2_CH4_0), 1088 1089 PINMUX_IPSR_GPSR(IP7_28_27, DU0_DB3), 1090 PINMUX_IPSR_MSEL(IP7_28_27, TX5_B, SEL_SCIF5_1), 1091 PINMUX_IPSR_MSEL(IP7_28_27, TIOC4D_A, SEL_MTU2_CH4_0), 1092 PINMUX_IPSR_GPSR(IP7_28_27, HIFRD), 1093 1094 PINMUX_IPSR_GPSR(IP7_30_29, DU0_DB4), 1095 PINMUX_IPSR_GPSR(IP7_30_29, HIFINT), 1096 1097 /* IPSR8 */ 1098 PINMUX_IPSR_GPSR(IP8_1_0, DU0_DB5), 1099 PINMUX_IPSR_GPSR(IP8_1_0, HIFDREQ), 1100 1101 PINMUX_IPSR_GPSR(IP8_3_2, DU0_DB6), 1102 PINMUX_IPSR_GPSR(IP8_3_2, HIFRDY), 1103 1104 PINMUX_IPSR_GPSR(IP8_5_4, DU0_DB7), 1105 PINMUX_IPSR_MSEL(IP8_5_4, SSI_SCK0_B, SEL_SSI0_1), 1106 PINMUX_IPSR_MSEL(IP8_5_4, HIFEBL_B, SEL_HIF_1), 1107 1108 PINMUX_IPSR_GPSR(IP8_7_6, DU0_DOTCLKIN), 1109 PINMUX_IPSR_MSEL(IP8_7_6, HSPI_CS0_C, SEL_HSPI_2), 1110 PINMUX_IPSR_MSEL(IP8_7_6, SSI_WS0_B, SEL_SSI0_1), 1111 1112 PINMUX_IPSR_GPSR(IP8_9_8, DU0_DOTCLKOUT), 1113 PINMUX_IPSR_MSEL(IP8_9_8, HSPI_CLK0_C, SEL_HSPI_2), 1114 PINMUX_IPSR_MSEL(IP8_9_8, SSI_SDATA0_B, SEL_SSI0_1), 1115 1116 PINMUX_IPSR_GPSR(IP8_11_10, DU0_EXHSYNC_DU0_HSYNC), 1117 PINMUX_IPSR_MSEL(IP8_11_10, HSPI_TX0_C, SEL_HSPI_2), 1118 PINMUX_IPSR_MSEL(IP8_11_10, SSI_SCK1_B, SEL_SSI1_1), 1119 1120 PINMUX_IPSR_GPSR(IP8_13_12, DU0_EXVSYNC_DU0_VSYNC), 1121 PINMUX_IPSR_MSEL(IP8_13_12, HSPI_RX0_C, SEL_HSPI_2), 1122 PINMUX_IPSR_MSEL(IP8_13_12, SSI_WS1_B, SEL_SSI1_1), 1123 1124 PINMUX_IPSR_GPSR(IP8_15_14, DU0_EXODDF_DU0_ODDF), 1125 PINMUX_IPSR_MSEL(IP8_15_14, CAN0_RX_B, SEL_RCAN0_1), 1126 PINMUX_IPSR_MSEL(IP8_15_14, HSCK0_B, SEL_HSCIF_1), 1127 PINMUX_IPSR_MSEL(IP8_15_14, SSI_SDATA1_B, SEL_SSI1_1), 1128 1129 PINMUX_IPSR_GPSR(IP8_17_16, DU0_DISP), 1130 PINMUX_IPSR_MSEL(IP8_17_16, CAN0_TX_B, SEL_RCAN0_1), 1131 PINMUX_IPSR_MSEL(IP8_17_16, HRX0_B, SEL_HSCIF_1), 1132 PINMUX_IPSR_MSEL(IP8_17_16, AUDIO_CLKA_B, SEL_AUDIO_CLKA_1), 1133 1134 PINMUX_IPSR_GPSR(IP8_19_18, DU0_CDE), 1135 PINMUX_IPSR_MSEL(IP8_19_18, HTX0_B, SEL_HSCIF_1), 1136 PINMUX_IPSR_MSEL(IP8_19_18, AUDIO_CLKB_B, SEL_AUDIO_CLKB_1), 1137 PINMUX_IPSR_MSEL(IP8_19_18, LCD_VCPWC_B, SEL_LCDC_1), 1138 1139 PINMUX_IPSR_MSEL(IP8_22_20, IRQ0_A, SEL_INTC_0), 1140 PINMUX_IPSR_MSEL(IP8_22_20, HSPI_TX_B, SEL_HSPI_1), 1141 PINMUX_IPSR_MSEL(IP8_22_20, RX3_E, SEL_SCIF3_4), 1142 PINMUX_IPSR_GPSR(IP8_22_20, ET0_ERXD0), 1143 1144 PINMUX_IPSR_MSEL(IP8_25_23, IRQ1_A, SEL_INTC_0), 1145 PINMUX_IPSR_MSEL(IP8_25_23, HSPI_RX_B, SEL_HSPI_1), 1146 PINMUX_IPSR_MSEL(IP8_25_23, TX3_E, SEL_SCIF3_4), 1147 PINMUX_IPSR_GPSR(IP8_25_23, ET0_ERXD1), 1148 1149 PINMUX_IPSR_MSEL(IP8_27_26, IRQ2_A, SEL_INTC_0), 1150 PINMUX_IPSR_MSEL(IP8_27_26, CTS0_A, SEL_SCIF0_0), 1151 PINMUX_IPSR_MSEL(IP8_27_26, HCTS0_B, SEL_HSCIF_1), 1152 PINMUX_IPSR_MSEL(IP8_27_26, ET0_ERXD2_A, SEL_ET0_0), 1153 1154 PINMUX_IPSR_MSEL(IP8_29_28, IRQ3_A, SEL_INTC_0), 1155 PINMUX_IPSR_MSEL(IP8_29_28, RTS0_A, SEL_SCIF0_0), 1156 PINMUX_IPSR_MSEL(IP8_29_28, HRTS0_B, SEL_HSCIF_1), 1157 PINMUX_IPSR_MSEL(IP8_29_28, ET0_ERXD3_A, SEL_ET0_0), 1158 1159 /* IPSR9 */ 1160 PINMUX_IPSR_MSEL(IP9_1_0, VI1_CLK_A, SEL_VIN1_0), 1161 PINMUX_IPSR_MSEL(IP9_1_0, FD0_B, SEL_FLCTL_1), 1162 PINMUX_IPSR_MSEL(IP9_1_0, LCD_DATA0_B, SEL_LCDC_1), 1163 1164 PINMUX_IPSR_MSEL(IP9_3_2, VI1_0_A, SEL_VIN1_0), 1165 PINMUX_IPSR_MSEL(IP9_3_2, FD1_B, SEL_FLCTL_1), 1166 PINMUX_IPSR_MSEL(IP9_3_2, LCD_DATA1_B, SEL_LCDC_1), 1167 1168 PINMUX_IPSR_MSEL(IP9_5_4, VI1_1_A, SEL_VIN1_0), 1169 PINMUX_IPSR_MSEL(IP9_5_4, FD2_B, SEL_FLCTL_1), 1170 PINMUX_IPSR_MSEL(IP9_5_4, LCD_DATA2_B, SEL_LCDC_1), 1171 1172 PINMUX_IPSR_MSEL(IP9_7_6, VI1_2_A, SEL_VIN1_0), 1173 PINMUX_IPSR_MSEL(IP9_7_6, FD3_B, SEL_FLCTL_1), 1174 PINMUX_IPSR_MSEL(IP9_7_6, LCD_DATA3_B, SEL_LCDC_1), 1175 1176 PINMUX_IPSR_MSEL(IP9_9_8, VI1_3_A, SEL_VIN1_0), 1177 PINMUX_IPSR_MSEL(IP9_9_8, FD4_B, SEL_FLCTL_1), 1178 PINMUX_IPSR_MSEL(IP9_9_8, LCD_DATA4_B, SEL_LCDC_1), 1179 1180 PINMUX_IPSR_MSEL(IP9_11_10, VI1_4_A, SEL_VIN1_0), 1181 PINMUX_IPSR_MSEL(IP9_11_10, FD5_B, SEL_FLCTL_1), 1182 PINMUX_IPSR_MSEL(IP9_11_10, LCD_DATA5_B, SEL_LCDC_1), 1183 1184 PINMUX_IPSR_MSEL(IP9_13_12, VI1_5_A, SEL_VIN1_0), 1185 PINMUX_IPSR_MSEL(IP9_13_12, FD6_B, SEL_FLCTL_1), 1186 PINMUX_IPSR_MSEL(IP9_13_12, LCD_DATA6_B, SEL_LCDC_1), 1187 1188 PINMUX_IPSR_MSEL(IP9_15_14, VI1_6_A, SEL_VIN1_0), 1189 PINMUX_IPSR_MSEL(IP9_15_14, FD7_B, SEL_FLCTL_1), 1190 PINMUX_IPSR_MSEL(IP9_15_14, LCD_DATA7_B, SEL_LCDC_1), 1191 1192 PINMUX_IPSR_MSEL(IP9_17_16, VI1_7_A, SEL_VIN1_0), 1193 PINMUX_IPSR_MSEL(IP9_17_16, FCE_B, SEL_FLCTL_1), 1194 PINMUX_IPSR_MSEL(IP9_17_16, LCD_DATA8_B, SEL_LCDC_1), 1195 1196 PINMUX_IPSR_MSEL(IP9_19_18, SSI_SCK0_A, SEL_SSI0_0), 1197 PINMUX_IPSR_MSEL(IP9_19_18, TIOC1A_B, SEL_MTU2_CH1_1), 1198 PINMUX_IPSR_MSEL(IP9_19_18, LCD_DATA9_B, SEL_LCDC_1), 1199 1200 PINMUX_IPSR_MSEL(IP9_21_20, SSI_WS0_A, SEL_SSI0_0), 1201 PINMUX_IPSR_MSEL(IP9_21_20, TIOC1B_B, SEL_MTU2_CH1_1), 1202 PINMUX_IPSR_MSEL(IP9_21_20, LCD_DATA10_B, SEL_LCDC_1), 1203 1204 PINMUX_IPSR_MSEL(IP9_23_22, SSI_SDATA0_A, SEL_SSI0_0), 1205 PINMUX_IPSR_MSEL(IP9_23_22, VI1_0_B, SEL_VIN1_1), 1206 PINMUX_IPSR_MSEL(IP9_23_22, TIOC2A_B, SEL_MTU2_CH2_1), 1207 PINMUX_IPSR_MSEL(IP9_23_22, LCD_DATA11_B, SEL_LCDC_1), 1208 1209 PINMUX_IPSR_MSEL(IP9_25_24, SSI_SCK1_A, SEL_SSI1_0), 1210 PINMUX_IPSR_MSEL(IP9_25_24, VI1_1_B, SEL_VIN1_1), 1211 PINMUX_IPSR_MSEL(IP9_25_24, TIOC2B_B, SEL_MTU2_CH2_1), 1212 PINMUX_IPSR_MSEL(IP9_25_24, LCD_DATA12_B, SEL_LCDC_1), 1213 1214 PINMUX_IPSR_MSEL(IP9_27_26, SSI_WS1_A, SEL_SSI1_0), 1215 PINMUX_IPSR_MSEL(IP9_27_26, VI1_2_B, SEL_VIN1_1), 1216 PINMUX_IPSR_MSEL(IP9_27_26, LCD_DATA13_B, SEL_LCDC_1), 1217 1218 PINMUX_IPSR_MSEL(IP9_29_28, SSI_SDATA1_A, SEL_SSI1_0), 1219 PINMUX_IPSR_MSEL(IP9_29_28, VI1_3_B, SEL_VIN1_1), 1220 PINMUX_IPSR_MSEL(IP9_29_28, LCD_DATA14_B, SEL_LCDC_1), 1221 1222 /* IPSE10 */ 1223 PINMUX_IPSR_GPSR(IP10_2_0, SSI_SCK23), 1224 PINMUX_IPSR_MSEL(IP10_2_0, VI1_4_B, SEL_VIN1_1), 1225 PINMUX_IPSR_MSEL(IP10_2_0, RX1_D, SEL_SCIF1_3), 1226 PINMUX_IPSR_MSEL(IP10_2_0, FCLE_B, SEL_FLCTL_1), 1227 PINMUX_IPSR_MSEL(IP10_2_0, LCD_DATA15_B, SEL_LCDC_1), 1228 1229 PINMUX_IPSR_GPSR(IP10_5_3, SSI_WS23), 1230 PINMUX_IPSR_MSEL(IP10_5_3, VI1_5_B, SEL_VIN1_1), 1231 PINMUX_IPSR_MSEL(IP10_5_3, TX1_D, SEL_SCIF1_3), 1232 PINMUX_IPSR_MSEL(IP10_5_3, HSCK0_C, SEL_HSCIF_2), 1233 PINMUX_IPSR_MSEL(IP10_5_3, FALE_B, SEL_FLCTL_1), 1234 PINMUX_IPSR_MSEL(IP10_5_3, LCD_DON_B, SEL_LCDC_1), 1235 1236 PINMUX_IPSR_GPSR(IP10_8_6, SSI_SDATA2), 1237 PINMUX_IPSR_MSEL(IP10_8_6, VI1_6_B, SEL_VIN1_1), 1238 PINMUX_IPSR_MSEL(IP10_8_6, HRX0_C, SEL_HSCIF_2), 1239 PINMUX_IPSR_MSEL(IP10_8_6, FRE_B, SEL_FLCTL_1), 1240 PINMUX_IPSR_MSEL(IP10_8_6, LCD_CL1_B, SEL_LCDC_1), 1241 1242 PINMUX_IPSR_GPSR(IP10_11_9, SSI_SDATA3), 1243 PINMUX_IPSR_MSEL(IP10_11_9, VI1_7_B, SEL_VIN1_1), 1244 PINMUX_IPSR_MSEL(IP10_11_9, HTX0_C, SEL_HSCIF_2), 1245 PINMUX_IPSR_MSEL(IP10_11_9, FWE_B, SEL_FLCTL_1), 1246 PINMUX_IPSR_MSEL(IP10_11_9, LCD_CL2_B, SEL_LCDC_1), 1247 1248 PINMUX_IPSR_MSEL(IP10_14_12, AUDIO_CLKA_A, SEL_AUDIO_CLKA_0), 1249 PINMUX_IPSR_MSEL(IP10_14_12, VI1_CLK_B, SEL_VIN1_1), 1250 PINMUX_IPSR_MSEL(IP10_14_12, SCK1_D, SEL_SCIF1_3), 1251 PINMUX_IPSR_MSEL(IP10_14_12, IECLK_B, SEL_IEBUS_1), 1252 PINMUX_IPSR_MSEL(IP10_14_12, LCD_FLM_B, SEL_LCDC_1), 1253 1254 PINMUX_IPSR_MSEL(IP10_15, AUDIO_CLKB_A, SEL_AUDIO_CLKB_0), 1255 PINMUX_IPSR_MSEL(IP10_15, LCD_CLK_B, SEL_LCDC_1), 1256 1257 PINMUX_IPSR_GPSR(IP10_18_16, AUDIO_CLKC), 1258 PINMUX_IPSR_MSEL(IP10_18_16, SCK1_E, SEL_SCIF1_4), 1259 PINMUX_IPSR_MSEL(IP10_18_16, HCTS0_C, SEL_HSCIF_2), 1260 PINMUX_IPSR_MSEL(IP10_18_16, FRB_B, SEL_FLCTL_1), 1261 PINMUX_IPSR_MSEL(IP10_18_16, LCD_VEPWC_B, SEL_LCDC_1), 1262 1263 PINMUX_IPSR_GPSR(IP10_21_19, AUDIO_CLKOUT), 1264 PINMUX_IPSR_MSEL(IP10_21_19, TX1_E, SEL_SCIF1_4), 1265 PINMUX_IPSR_MSEL(IP10_21_19, HRTS0_C, SEL_HSCIF_2), 1266 PINMUX_IPSR_MSEL(IP10_21_19, FSE_B, SEL_FLCTL_1), 1267 PINMUX_IPSR_MSEL(IP10_21_19, LCD_M_DISP_B, SEL_LCDC_1), 1268 1269 PINMUX_IPSR_MSEL(IP10_22, CAN_CLK_A, SEL_RCAN_CLK_0), 1270 PINMUX_IPSR_MSEL(IP10_22, RX4_D, SEL_SCIF4_3), 1271 1272 PINMUX_IPSR_MSEL(IP10_24_23, CAN0_TX_A, SEL_RCAN0_0), 1273 PINMUX_IPSR_MSEL(IP10_24_23, TX4_D, SEL_SCIF4_3), 1274 PINMUX_IPSR_GPSR(IP10_24_23, MLB_CLK), 1275 1276 PINMUX_IPSR_MSEL(IP10_25, CAN1_RX_A, SEL_RCAN1_0), 1277 PINMUX_IPSR_MSEL(IP10_25, IRQ1_B, SEL_INTC_1), 1278 1279 PINMUX_IPSR_MSEL(IP10_27_26, CAN0_RX_A, SEL_RCAN0_0), 1280 PINMUX_IPSR_MSEL(IP10_27_26, IRQ0_B, SEL_INTC_1), 1281 PINMUX_IPSR_GPSR(IP10_27_26, MLB_SIG), 1282 1283 PINMUX_IPSR_MSEL(IP10_29_28, CAN1_TX_A, SEL_RCAN1_0), 1284 PINMUX_IPSR_MSEL(IP10_29_28, TX5_C, SEL_SCIF1_2), 1285 PINMUX_IPSR_GPSR(IP10_29_28, MLB_DAT), 1286 1287 /* IPSR11 */ 1288 PINMUX_IPSR_GPSR(IP11_0, SCL1), 1289 PINMUX_IPSR_MSEL(IP11_0, SCIF_CLK_C, SEL_SCIF_CLK_2), 1290 1291 PINMUX_IPSR_GPSR(IP11_1, SDA1), 1292 PINMUX_IPSR_MSEL(IP11_0, RX1_E, SEL_SCIF1_4), 1293 1294 PINMUX_IPSR_GPSR(IP11_2, SDA0), 1295 PINMUX_IPSR_MSEL(IP11_2, HIFEBL_A, SEL_HIF_0), 1296 1297 PINMUX_IPSR_GPSR(IP11_3, SDSELF), 1298 PINMUX_IPSR_MSEL(IP11_3, RTS1_E, SEL_SCIF1_3), 1299 1300 PINMUX_IPSR_MSEL(IP11_6_4, SCIF_CLK_A, SEL_SCIF_CLK_0), 1301 PINMUX_IPSR_MSEL(IP11_6_4, HSPI_CLK_A, SEL_HSPI_0), 1302 PINMUX_IPSR_GPSR(IP11_6_4, VI0_CLK), 1303 PINMUX_IPSR_MSEL(IP11_6_4, RMII0_TXD0_A, SEL_RMII_0), 1304 PINMUX_IPSR_GPSR(IP11_6_4, ET0_ERXD4), 1305 1306 PINMUX_IPSR_MSEL(IP11_9_7, SCK0_A, SEL_SCIF0_0), 1307 PINMUX_IPSR_MSEL(IP11_9_7, HSPI_CS_A, SEL_HSPI_0), 1308 PINMUX_IPSR_GPSR(IP11_9_7, VI0_CLKENB), 1309 PINMUX_IPSR_MSEL(IP11_9_7, RMII0_TXD1_A, SEL_RMII_0), 1310 PINMUX_IPSR_GPSR(IP11_9_7, ET0_ERXD5), 1311 1312 PINMUX_IPSR_MSEL(IP11_11_10, RX0_A, SEL_SCIF0_0), 1313 PINMUX_IPSR_MSEL(IP11_11_10, HSPI_RX_A, SEL_HSPI_0), 1314 PINMUX_IPSR_MSEL(IP11_11_10, RMII0_RXD0_A, SEL_RMII_0), 1315 PINMUX_IPSR_GPSR(IP11_11_10, ET0_ERXD6), 1316 1317 PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0), 1318 PINMUX_IPSR_MSEL(IP11_12, HSPI_TX_A, SEL_HSPI_0), 1319 1320 PINMUX_IPSR_GPSR(IP11_15_13, PENC1), 1321 PINMUX_IPSR_MSEL(IP11_15_13, TX3_D, SEL_SCIF3_3), 1322 PINMUX_IPSR_MSEL(IP11_15_13, CAN1_TX_B, SEL_RCAN1_1), 1323 PINMUX_IPSR_MSEL(IP11_15_13, TX5_D, SEL_SCIF5_3), 1324 PINMUX_IPSR_MSEL(IP11_15_13, IETX_B, SEL_IEBUS_1), 1325 1326 PINMUX_IPSR_GPSR(IP11_18_16, USB_OVC1), 1327 PINMUX_IPSR_MSEL(IP11_18_16, RX3_D, SEL_SCIF3_3), 1328 PINMUX_IPSR_MSEL(IP11_18_16, CAN1_RX_B, SEL_RCAN1_1), 1329 PINMUX_IPSR_MSEL(IP11_18_16, RX5_D, SEL_SCIF5_3), 1330 PINMUX_IPSR_MSEL(IP11_18_16, IERX_B, SEL_IEBUS_1), 1331 1332 PINMUX_IPSR_GPSR(IP11_20_19, DREQ0), 1333 PINMUX_IPSR_MSEL(IP11_20_19, SD1_CLK_A, SEL_SDHI1_0), 1334 PINMUX_IPSR_GPSR(IP11_20_19, ET0_TX_EN), 1335 1336 PINMUX_IPSR_GPSR(IP11_22_21, DACK0), 1337 PINMUX_IPSR_MSEL(IP11_22_21, SD1_DAT3_A, SEL_SDHI1_0), 1338 PINMUX_IPSR_GPSR(IP11_22_21, ET0_TX_ER), 1339 1340 PINMUX_IPSR_GPSR(IP11_25_23, DREQ1), 1341 PINMUX_IPSR_MSEL(IP11_25_23, HSPI_CLK_B, SEL_HSPI_1), 1342 PINMUX_IPSR_MSEL(IP11_25_23, RX4_B, SEL_SCIF4_1), 1343 PINMUX_IPSR_MSEL(IP11_25_23, ET0_PHY_INT_C, SEL_ET0_CTL_0), 1344 PINMUX_IPSR_MSEL(IP11_25_23, ET0_TX_CLK_A, SEL_ET0_0), 1345 1346 PINMUX_IPSR_GPSR(IP11_27_26, DACK1), 1347 PINMUX_IPSR_MSEL(IP11_27_26, HSPI_CS_B, SEL_HSPI_1), 1348 PINMUX_IPSR_MSEL(IP11_27_26, TX4_B, SEL_SCIF3_1), 1349 PINMUX_IPSR_MSEL(IP11_27_26, ET0_RX_CLK_A, SEL_ET0_0), 1350 1351 PINMUX_IPSR_GPSR(IP11_28, PRESETOUT), 1352 PINMUX_IPSR_GPSR(IP11_28, ST_CLKOUT), 1353 }; 1354 1355 static const struct sh_pfc_pin pinmux_pins[] = { 1356 PINMUX_GPIO_GP_ALL(), 1357 }; 1358 1359 #define PINMUX_FN_BASE ARRAY_SIZE(pinmux_pins) 1360 1361 static const struct pinmux_func pinmux_func_gpios[] = { 1362 GPIO_FN(CLKOUT), GPIO_FN(BS), GPIO_FN(CS0), GPIO_FN(EX_CS0), 1363 GPIO_FN(RD), GPIO_FN(WE0), GPIO_FN(WE1), 1364 GPIO_FN(SCL0), GPIO_FN(PENC0), GPIO_FN(USB_OVC0), 1365 GPIO_FN(IRQ2_B), GPIO_FN(IRQ3_B), 1366 1367 /* IPSR0 */ 1368 GPIO_FN(A0), GPIO_FN(ST0_CLKIN), GPIO_FN(LCD_DATA0_A), 1369 GPIO_FN(TCLKA_C), 1370 GPIO_FN(A1), GPIO_FN(ST0_REQ), GPIO_FN(LCD_DATA1_A), 1371 GPIO_FN(TCLKB_C), 1372 GPIO_FN(A2), GPIO_FN(ST0_SYC), GPIO_FN(LCD_DATA2_A), 1373 GPIO_FN(TCLKC_C), 1374 GPIO_FN(A3), GPIO_FN(ST0_VLD), GPIO_FN(LCD_DATA3_A), 1375 GPIO_FN(TCLKD_C), 1376 GPIO_FN(A4), GPIO_FN(ST0_D0), GPIO_FN(LCD_DATA4_A), 1377 GPIO_FN(TIOC0A_C), 1378 GPIO_FN(A5), GPIO_FN(ST0_D1), GPIO_FN(LCD_DATA5_A), 1379 GPIO_FN(TIOC0B_C), 1380 GPIO_FN(A6), GPIO_FN(ST0_D2), GPIO_FN(LCD_DATA6_A), 1381 GPIO_FN(TIOC0C_C), 1382 GPIO_FN(A7), GPIO_FN(ST0_D3), GPIO_FN(LCD_DATA7_A), 1383 GPIO_FN(TIOC0D_C), 1384 GPIO_FN(A8), GPIO_FN(ST0_D4), GPIO_FN(LCD_DATA8_A), 1385 GPIO_FN(TIOC1A_C), 1386 GPIO_FN(A9), GPIO_FN(ST0_D5), GPIO_FN(LCD_DATA9_A), 1387 GPIO_FN(TIOC1B_C), 1388 GPIO_FN(A10), GPIO_FN(ST0_D6), GPIO_FN(LCD_DATA10_A), 1389 GPIO_FN(TIOC2A_C), 1390 GPIO_FN(A11), GPIO_FN(ST0_D7), GPIO_FN(LCD_DATA11_A), 1391 GPIO_FN(TIOC2B_C), 1392 GPIO_FN(A12), GPIO_FN(LCD_DATA12_A), GPIO_FN(TIOC3A_C), 1393 GPIO_FN(A13), GPIO_FN(LCD_DATA13_A), GPIO_FN(TIOC3B_C), 1394 GPIO_FN(A14), GPIO_FN(LCD_DATA14_A), GPIO_FN(TIOC3C_C), 1395 GPIO_FN(A15), GPIO_FN(ST0_VCO_CLKIN), GPIO_FN(LCD_DATA15_A), 1396 GPIO_FN(TIOC3D_C), 1397 1398 /* IPSR1 */ 1399 GPIO_FN(A16), GPIO_FN(ST0_PWM), GPIO_FN(LCD_DON_A), 1400 GPIO_FN(TIOC4A_C), 1401 GPIO_FN(A17), GPIO_FN(ST1_VCO_CLKIN), GPIO_FN(LCD_CL1_A), 1402 GPIO_FN(TIOC4B_C), 1403 GPIO_FN(A18), GPIO_FN(ST1_PWM), GPIO_FN(LCD_CL2_A), 1404 GPIO_FN(TIOC4C_C), 1405 GPIO_FN(A19), GPIO_FN(ST1_CLKIN), GPIO_FN(LCD_CLK_A), 1406 GPIO_FN(TIOC4D_C), 1407 GPIO_FN(A20), GPIO_FN(ST1_REQ), GPIO_FN(LCD_FLM_A), 1408 GPIO_FN(A21), GPIO_FN(ST1_SYC), GPIO_FN(LCD_VCPWC_A), 1409 GPIO_FN(A22), GPIO_FN(ST1_VLD), GPIO_FN(LCD_VEPWC_A), 1410 GPIO_FN(A23), GPIO_FN(ST1_D0), GPIO_FN(LCD_M_DISP_A), 1411 GPIO_FN(A24), GPIO_FN(RX2_D), GPIO_FN(ST1_D1), 1412 GPIO_FN(A25), GPIO_FN(TX2_D), GPIO_FN(ST1_D2), 1413 GPIO_FN(D0), GPIO_FN(SD0_DAT0_A), GPIO_FN(MMC_D0_A), 1414 GPIO_FN(ST1_D3), GPIO_FN(FD0_A), 1415 GPIO_FN(D1), GPIO_FN(SD0_DAT1_A), GPIO_FN(MMC_D1_A), 1416 GPIO_FN(ST1_D4), GPIO_FN(FD1_A), 1417 GPIO_FN(D2), GPIO_FN(SD0_DAT2_A), GPIO_FN(MMC_D2_A), 1418 GPIO_FN(ST1_D5), GPIO_FN(FD2_A), 1419 GPIO_FN(D3), GPIO_FN(SD0_DAT3_A), GPIO_FN(MMC_D3_A), 1420 GPIO_FN(ST1_D6), GPIO_FN(FD3_A), 1421 1422 /* IPSR2 */ 1423 GPIO_FN(D4), GPIO_FN(SD0_CD_A), GPIO_FN(MMC_D4_A), GPIO_FN(ST1_D7), 1424 GPIO_FN(FD4_A), 1425 GPIO_FN(D5), GPIO_FN(SD0_WP_A), GPIO_FN(MMC_D5_A), GPIO_FN(FD5_A), 1426 GPIO_FN(D6), GPIO_FN(RSPI_RSPCK_A), GPIO_FN(MMC_D6_A), 1427 GPIO_FN(QSPCLK_A), 1428 GPIO_FN(FD6_A), 1429 GPIO_FN(D7), GPIO_FN(RSPI_SSL_A), GPIO_FN(MMC_D7_A), GPIO_FN(QSSL_A), 1430 GPIO_FN(FD7_A), 1431 GPIO_FN(D8), GPIO_FN(SD0_CLK_A), GPIO_FN(MMC_CLK_A), GPIO_FN(QIO2_A), 1432 GPIO_FN(FCE_A), GPIO_FN(ET0_GTX_CLK_B), 1433 GPIO_FN(D9), GPIO_FN(SD0_CMD_A), GPIO_FN(MMC_CMD_A), GPIO_FN(QIO3_A), 1434 GPIO_FN(FCLE_A), GPIO_FN(ET0_ETXD1_B), 1435 GPIO_FN(D10), GPIO_FN(RSPI_MOSI_A), GPIO_FN(QMO_QIO0_A), 1436 GPIO_FN(FALE_A), GPIO_FN(ET0_ETXD2_B), 1437 GPIO_FN(D11), GPIO_FN(RSPI_MISO_A), GPIO_FN(QMI_QIO1_A), GPIO_FN(FRE_A), 1438 GPIO_FN(ET0_ETXD3_B), 1439 GPIO_FN(D12), GPIO_FN(FWE_A), GPIO_FN(ET0_ETXD5_B), 1440 GPIO_FN(D13), GPIO_FN(RX2_B), GPIO_FN(FRB_A), GPIO_FN(ET0_ETXD6_B), 1441 GPIO_FN(D14), GPIO_FN(TX2_B), GPIO_FN(FSE_A), GPIO_FN(ET0_TX_CLK_B), 1442 1443 /* IPSR3 */ 1444 GPIO_FN(D15), GPIO_FN(SCK2_B), 1445 GPIO_FN(CS1_A26), GPIO_FN(QIO3_B), 1446 GPIO_FN(EX_CS1), GPIO_FN(RX3_B), GPIO_FN(ATACS0), GPIO_FN(QIO2_B), 1447 GPIO_FN(ET0_ETXD0), 1448 GPIO_FN(EX_CS2), GPIO_FN(TX3_B), GPIO_FN(ATACS1), GPIO_FN(QSPCLK_B), 1449 GPIO_FN(ET0_GTX_CLK_A), 1450 GPIO_FN(EX_CS3), GPIO_FN(SD1_CD_A), GPIO_FN(ATARD), GPIO_FN(QMO_QIO0_B), 1451 GPIO_FN(ET0_ETXD1_A), 1452 GPIO_FN(EX_CS4), GPIO_FN(SD1_WP_A), GPIO_FN(ATAWR), GPIO_FN(QMI_QIO1_B), 1453 GPIO_FN(ET0_ETXD2_A), 1454 GPIO_FN(EX_CS5), GPIO_FN(SD1_CMD_A), GPIO_FN(ATADIR), GPIO_FN(QSSL_B), 1455 GPIO_FN(ET0_ETXD3_A), 1456 GPIO_FN(RD_WR), GPIO_FN(TCLK1_B), 1457 GPIO_FN(EX_WAIT0), GPIO_FN(TCLK1_B), 1458 GPIO_FN(EX_WAIT1), GPIO_FN(SD1_DAT0_A), GPIO_FN(DREQ2), 1459 GPIO_FN(CAN1_TX_C), GPIO_FN(ET0_LINK_C), GPIO_FN(ET0_ETXD5_A), 1460 GPIO_FN(EX_WAIT2), GPIO_FN(SD1_DAT1_A), GPIO_FN(DACK2), 1461 GPIO_FN(CAN1_RX_C), GPIO_FN(ET0_MAGIC_C), GPIO_FN(ET0_ETXD6_A), 1462 GPIO_FN(DRACK0), GPIO_FN(SD1_DAT2_A), GPIO_FN(ATAG), GPIO_FN(TCLK1_A), 1463 GPIO_FN(ET0_ETXD7), 1464 1465 /* IPSR4 */ 1466 GPIO_FN(HCTS0_A), GPIO_FN(CTS1_A), GPIO_FN(VI0_FIELD), 1467 GPIO_FN(RMII0_RXD1_A), GPIO_FN(ET0_ERXD7), 1468 GPIO_FN(HRTS0_A), GPIO_FN(RTS1_A), GPIO_FN(VI0_HSYNC), 1469 GPIO_FN(RMII0_TXD_EN_A), GPIO_FN(ET0_RX_DV), 1470 GPIO_FN(HSCK0_A), GPIO_FN(SCK1_A), GPIO_FN(VI0_VSYNC), 1471 GPIO_FN(RMII0_RX_ER_A), GPIO_FN(ET0_RX_ER), 1472 GPIO_FN(HRX0_A), GPIO_FN(RX1_A), GPIO_FN(VI0_DATA0_VI0_B0), 1473 GPIO_FN(RMII0_CRS_DV_A), GPIO_FN(ET0_CRS), 1474 GPIO_FN(HTX0_A), GPIO_FN(TX1_A), GPIO_FN(VI0_DATA1_VI0_B1), 1475 GPIO_FN(RMII0_MDC_A), GPIO_FN(ET0_COL), 1476 GPIO_FN(CTS0_B), GPIO_FN(VI0_DATA2_VI0_B2), GPIO_FN(RMII0_MDIO_A), 1477 GPIO_FN(ET0_MDC), 1478 GPIO_FN(RTS0_B), GPIO_FN(VI0_DATA3_VI0_B3), GPIO_FN(ET0_MDIO_A), 1479 GPIO_FN(SCK1_B), GPIO_FN(VI0_DATA4_VI0_B4), GPIO_FN(ET0_LINK_A), 1480 GPIO_FN(RX1_B), GPIO_FN(VI0_DATA5_VI0_B5), GPIO_FN(ET0_MAGIC_A), 1481 GPIO_FN(TX1_B), GPIO_FN(VI0_DATA6_VI0_G0), GPIO_FN(ET0_PHY_INT_A), 1482 GPIO_FN(CTS1_B), GPIO_FN(VI0_DATA7_VI0_G1), 1483 GPIO_FN(RTS1_B), GPIO_FN(VI0_G2), 1484 GPIO_FN(SCK2_A), GPIO_FN(VI0_G3), 1485 1486 /* IPSR5 */ 1487 GPIO_FN(REF50CK), GPIO_FN(CTS1_E), GPIO_FN(HCTS0_D), 1488 GPIO_FN(REF125CK), GPIO_FN(ADTRG), GPIO_FN(RX5_C), 1489 GPIO_FN(SD2_WP_A), GPIO_FN(TX5_A), GPIO_FN(VI0_R5), 1490 GPIO_FN(SD2_CD_A), GPIO_FN(RX5_A), GPIO_FN(VI0_R4), 1491 GPIO_FN(ET0_PHY_INT_B), 1492 GPIO_FN(SD2_DAT3_A), GPIO_FN(TX4_A), GPIO_FN(VI0_R3), 1493 GPIO_FN(ET0_MAGIC_B), 1494 GPIO_FN(SD2_DAT2_A), GPIO_FN(RX4_A), GPIO_FN(VI0_R2), 1495 GPIO_FN(ET0_LINK_B), 1496 GPIO_FN(SD2_DAT1_A), GPIO_FN(TX3_A), GPIO_FN(VI0_R1), 1497 GPIO_FN(ET0_MDIO_B), 1498 GPIO_FN(SD2_DAT0_A), GPIO_FN(RX3_A), GPIO_FN(VI0_R0), 1499 GPIO_FN(ET0_ERXD3_B), 1500 GPIO_FN(SD2_CMD_A), GPIO_FN(TX2_A), GPIO_FN(VI0_G5), 1501 GPIO_FN(ET0_ERXD2_B), 1502 GPIO_FN(SD2_CLK_A), GPIO_FN(RX2_A), GPIO_FN(VI0_G4), 1503 GPIO_FN(ET0_RX_CLK_B), 1504 1505 /* IPSR6 */ 1506 GPIO_FN(DU0_DG1), GPIO_FN(CTS1_C), GPIO_FN(HRTS0_D), 1507 GPIO_FN(TIOC1B_A), GPIO_FN(HIFD09), 1508 GPIO_FN(DU0_DG0), GPIO_FN(TX1_C), GPIO_FN(HSCK0_D), 1509 GPIO_FN(IECLK_A), GPIO_FN(TIOC1A_A), GPIO_FN(HIFD08), 1510 GPIO_FN(DU0_DR7), GPIO_FN(RX1_C), GPIO_FN(TIOC0D_A), 1511 GPIO_FN(HIFD07), 1512 GPIO_FN(DU0_DR6), GPIO_FN(SCK1_C), GPIO_FN(TIOC0C_A), 1513 GPIO_FN(HIFD06), 1514 GPIO_FN(DU0_DR5), GPIO_FN(RTS0_C), GPIO_FN(TIOC0B_A), 1515 GPIO_FN(HIFD05), 1516 GPIO_FN(DU0_DR4), GPIO_FN(CTS0_C), GPIO_FN(TIOC0A_A), 1517 GPIO_FN(HIFD04), 1518 GPIO_FN(DU0_DR3), GPIO_FN(TX0_B), GPIO_FN(TCLKD_A), GPIO_FN(HIFD03), 1519 GPIO_FN(DU0_DR2), GPIO_FN(RX0_B), GPIO_FN(TCLKC_A), GPIO_FN(HIFD02), 1520 GPIO_FN(DU0_DR1), GPIO_FN(SCK0_B), GPIO_FN(HTX0_D), 1521 GPIO_FN(IERX_A), GPIO_FN(TCLKB_A), GPIO_FN(HIFD01), 1522 GPIO_FN(DU0_DR0), GPIO_FN(SCIF_CLK_B), GPIO_FN(HRX0_D), 1523 GPIO_FN(IETX_A), GPIO_FN(TCLKA_A), GPIO_FN(HIFD00), 1524 1525 /* IPSR7 */ 1526 GPIO_FN(DU0_DB4), GPIO_FN(HIFINT), 1527 GPIO_FN(DU0_DB3), GPIO_FN(TX5_B), GPIO_FN(TIOC4D_A), GPIO_FN(HIFRD), 1528 GPIO_FN(DU0_DB2), GPIO_FN(RX5_B), GPIO_FN(RMII0_TXD1_B), 1529 GPIO_FN(TIOC4C_A), GPIO_FN(HIFWR), 1530 GPIO_FN(DU0_DB1), GPIO_FN(TX4_C), GPIO_FN(RMII0_TXD0_B), 1531 GPIO_FN(TIOC4B_A), GPIO_FN(HIFRS), 1532 GPIO_FN(DU0_DB0), GPIO_FN(RX4_C), GPIO_FN(RMII0_TXD_EN_B), 1533 GPIO_FN(TIOC4A_A), GPIO_FN(HIFCS), 1534 GPIO_FN(DU0_DG7), GPIO_FN(TX3_C), GPIO_FN(RMII0_RXD1_B), 1535 GPIO_FN(TIOC3D_A), GPIO_FN(HIFD15), 1536 GPIO_FN(DU0_DG6), GPIO_FN(RX3_C), GPIO_FN(RMII0_RXD0_B), 1537 GPIO_FN(TIOC3C_A), GPIO_FN(HIFD14), 1538 GPIO_FN(DU0_DG5), GPIO_FN(TX2_C), GPIO_FN(RMII0_RX_ER_B), 1539 GPIO_FN(TIOC3B_A), GPIO_FN(HIFD13), 1540 GPIO_FN(DU0_DG4), GPIO_FN(RX2_C), GPIO_FN(RMII0_CRS_DV_B), 1541 GPIO_FN(TIOC3A_A), GPIO_FN(HIFD12), 1542 GPIO_FN(DU0_DG3), GPIO_FN(SCK2_C), GPIO_FN(RMII0_MDIO_B), 1543 GPIO_FN(TIOC2B_A), GPIO_FN(HIFD11), 1544 GPIO_FN(DU0_DG2), GPIO_FN(RTS1_C), GPIO_FN(RMII0_MDC_B), 1545 GPIO_FN(TIOC2A_A), GPIO_FN(HIFD10), 1546 1547 /* IPSR8 */ 1548 GPIO_FN(IRQ3_A), GPIO_FN(RTS0_A), GPIO_FN(HRTS0_B), 1549 GPIO_FN(ET0_ERXD3_A), 1550 GPIO_FN(IRQ2_A), GPIO_FN(CTS0_A), GPIO_FN(HCTS0_B), 1551 GPIO_FN(ET0_ERXD2_A), 1552 GPIO_FN(IRQ1_A), GPIO_FN(HSPI_RX_B), GPIO_FN(TX3_E), 1553 GPIO_FN(ET0_ERXD1), 1554 GPIO_FN(IRQ0_A), GPIO_FN(HSPI_TX_B), GPIO_FN(RX3_E), 1555 GPIO_FN(ET0_ERXD0), 1556 GPIO_FN(DU0_CDE), GPIO_FN(HTX0_B), GPIO_FN(AUDIO_CLKB_B), 1557 GPIO_FN(LCD_VCPWC_B), 1558 GPIO_FN(DU0_DISP), GPIO_FN(CAN0_TX_B), GPIO_FN(HRX0_B), 1559 GPIO_FN(AUDIO_CLKA_B), 1560 GPIO_FN(DU0_EXODDF_DU0_ODDF), GPIO_FN(CAN0_RX_B), GPIO_FN(HSCK0_B), 1561 GPIO_FN(SSI_SDATA1_B), 1562 GPIO_FN(DU0_EXVSYNC_DU0_VSYNC), GPIO_FN(HSPI_RX0_C), 1563 GPIO_FN(SSI_WS1_B), 1564 GPIO_FN(DU0_EXHSYNC_DU0_HSYNC), GPIO_FN(HSPI_TX0_C), 1565 GPIO_FN(SSI_SCK1_B), 1566 GPIO_FN(DU0_DOTCLKOUT), GPIO_FN(HSPI_CLK0_C), 1567 GPIO_FN(SSI_SDATA0_B), 1568 GPIO_FN(DU0_DOTCLKIN), GPIO_FN(HSPI_CS0_C), 1569 GPIO_FN(SSI_WS0_B), 1570 GPIO_FN(DU0_DB7), GPIO_FN(SSI_SCK0_B), GPIO_FN(HIFEBL_B), 1571 GPIO_FN(DU0_DB6), GPIO_FN(HIFRDY), 1572 GPIO_FN(DU0_DB5), GPIO_FN(HIFDREQ), 1573 1574 /* IPSR9 */ 1575 GPIO_FN(SSI_SDATA1_A), GPIO_FN(VI1_3_B), GPIO_FN(LCD_DATA14_B), 1576 GPIO_FN(SSI_WS1_A), GPIO_FN(VI1_2_B), GPIO_FN(LCD_DATA13_B), 1577 GPIO_FN(SSI_SCK1_A), GPIO_FN(VI1_1_B), GPIO_FN(TIOC2B_B), 1578 GPIO_FN(LCD_DATA12_B), 1579 GPIO_FN(SSI_SDATA0_A), GPIO_FN(VI1_0_B), GPIO_FN(TIOC2A_B), 1580 GPIO_FN(LCD_DATA11_B), 1581 GPIO_FN(SSI_WS0_A), GPIO_FN(TIOC1B_B), GPIO_FN(LCD_DATA10_B), 1582 GPIO_FN(SSI_SCK0_A), GPIO_FN(TIOC1A_B), GPIO_FN(LCD_DATA9_B), 1583 GPIO_FN(VI1_7_A), GPIO_FN(FCE_B), GPIO_FN(LCD_DATA8_B), 1584 GPIO_FN(VI1_6_A), GPIO_FN(FD7_B), GPIO_FN(LCD_DATA7_B), 1585 GPIO_FN(VI1_5_A), GPIO_FN(FD6_B), GPIO_FN(LCD_DATA6_B), 1586 GPIO_FN(VI1_4_A), GPIO_FN(FD5_B), GPIO_FN(LCD_DATA5_B), 1587 GPIO_FN(VI1_3_A), GPIO_FN(FD4_B), GPIO_FN(LCD_DATA4_B), 1588 GPIO_FN(VI1_2_A), GPIO_FN(FD3_B), GPIO_FN(LCD_DATA3_B), 1589 GPIO_FN(VI1_1_A), GPIO_FN(FD2_B), GPIO_FN(LCD_DATA2_B), 1590 GPIO_FN(VI1_0_A), GPIO_FN(FD1_B), GPIO_FN(LCD_DATA1_B), 1591 GPIO_FN(VI1_CLK_A), GPIO_FN(FD0_B), GPIO_FN(LCD_DATA0_B), 1592 1593 /* IPSR10 */ 1594 GPIO_FN(CAN1_TX_A), GPIO_FN(TX5_C), GPIO_FN(MLB_DAT), 1595 GPIO_FN(CAN0_RX_A), GPIO_FN(IRQ0_B), GPIO_FN(MLB_SIG), 1596 GPIO_FN(CAN1_RX_A), GPIO_FN(IRQ1_B), 1597 GPIO_FN(CAN0_TX_A), GPIO_FN(TX4_D), GPIO_FN(MLB_CLK), 1598 GPIO_FN(CAN_CLK_A), GPIO_FN(RX4_D), 1599 GPIO_FN(AUDIO_CLKOUT), GPIO_FN(TX1_E), GPIO_FN(HRTS0_C), 1600 GPIO_FN(FSE_B), GPIO_FN(LCD_M_DISP_B), 1601 GPIO_FN(AUDIO_CLKC), GPIO_FN(SCK1_E), GPIO_FN(HCTS0_C), 1602 GPIO_FN(FRB_B), GPIO_FN(LCD_VEPWC_B), 1603 GPIO_FN(AUDIO_CLKB_A), GPIO_FN(LCD_CLK_B), 1604 GPIO_FN(AUDIO_CLKA_A), GPIO_FN(VI1_CLK_B), GPIO_FN(SCK1_D), 1605 GPIO_FN(IECLK_B), GPIO_FN(LCD_FLM_B), 1606 GPIO_FN(SSI_SDATA3), GPIO_FN(VI1_7_B), GPIO_FN(HTX0_C), 1607 GPIO_FN(FWE_B), GPIO_FN(LCD_CL2_B), 1608 GPIO_FN(SSI_SDATA2), GPIO_FN(VI1_6_B), GPIO_FN(HRX0_C), 1609 GPIO_FN(FRE_B), GPIO_FN(LCD_CL1_B), 1610 GPIO_FN(SSI_WS23), GPIO_FN(VI1_5_B), GPIO_FN(TX1_D), 1611 GPIO_FN(HSCK0_C), GPIO_FN(FALE_B), GPIO_FN(LCD_DON_B), 1612 GPIO_FN(SSI_SCK23), GPIO_FN(VI1_4_B), GPIO_FN(RX1_D), 1613 GPIO_FN(FCLE_B), GPIO_FN(LCD_DATA15_B), 1614 1615 /* IPSR11 */ 1616 GPIO_FN(PRESETOUT), GPIO_FN(ST_CLKOUT), 1617 GPIO_FN(DACK1), GPIO_FN(HSPI_CS_B), GPIO_FN(TX4_B), 1618 GPIO_FN(ET0_RX_CLK_A), 1619 GPIO_FN(DREQ1), GPIO_FN(HSPI_CLK_B), GPIO_FN(RX4_B), 1620 GPIO_FN(ET0_PHY_INT_C), GPIO_FN(ET0_TX_CLK_A), 1621 GPIO_FN(DACK0), GPIO_FN(SD1_DAT3_A), GPIO_FN(ET0_TX_ER), 1622 GPIO_FN(DREQ0), GPIO_FN(SD1_CLK_A), GPIO_FN(ET0_TX_EN), 1623 GPIO_FN(USB_OVC1), GPIO_FN(RX3_D), GPIO_FN(CAN1_RX_B), 1624 GPIO_FN(RX5_D), GPIO_FN(IERX_B), 1625 GPIO_FN(PENC1), GPIO_FN(TX3_D), GPIO_FN(CAN1_TX_B), 1626 GPIO_FN(TX5_D), GPIO_FN(IETX_B), 1627 GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A), 1628 GPIO_FN(RX0_A), GPIO_FN(HSPI_RX_A), GPIO_FN(RMII0_RXD0_A), 1629 GPIO_FN(ET0_ERXD6), 1630 GPIO_FN(SCK0_A), GPIO_FN(HSPI_CS_A), GPIO_FN(VI0_CLKENB), 1631 GPIO_FN(RMII0_TXD1_A), GPIO_FN(ET0_ERXD5), 1632 GPIO_FN(SCIF_CLK_A), GPIO_FN(HSPI_CLK_A), GPIO_FN(VI0_CLK), 1633 GPIO_FN(RMII0_TXD0_A), GPIO_FN(ET0_ERXD4), 1634 GPIO_FN(SDSELF), GPIO_FN(RTS1_E), 1635 GPIO_FN(SDA0), GPIO_FN(HIFEBL_A), 1636 GPIO_FN(SDA1), GPIO_FN(RX1_E), 1637 GPIO_FN(SCL1), GPIO_FN(SCIF_CLK_C), 1638 }; 1639 1640 static const struct pinmux_cfg_reg pinmux_config_regs[] = { 1641 { PINMUX_CFG_REG("GPSR0", 0xFFFC0004, 32, 1) { 1642 GP_0_31_FN, FN_IP2_2_0, 1643 GP_0_30_FN, FN_IP1_31_29, 1644 GP_0_29_FN, FN_IP1_28_26, 1645 GP_0_28_FN, FN_IP1_25_23, 1646 GP_0_27_FN, FN_IP1_22_20, 1647 GP_0_26_FN, FN_IP1_19_18, 1648 GP_0_25_FN, FN_IP1_17_16, 1649 GP_0_24_FN, FN_IP0_5_4, 1650 GP_0_23_FN, FN_IP0_3_2, 1651 GP_0_22_FN, FN_IP0_1_0, 1652 GP_0_21_FN, FN_IP11_28, 1653 GP_0_20_FN, FN_IP1_7_6, 1654 GP_0_19_FN, FN_IP1_5_4, 1655 GP_0_18_FN, FN_IP1_3_2, 1656 GP_0_17_FN, FN_IP1_1_0, 1657 GP_0_16_FN, FN_IP0_31_30, 1658 GP_0_15_FN, FN_IP0_29_28, 1659 GP_0_14_FN, FN_IP0_27_26, 1660 GP_0_13_FN, FN_IP0_25_24, 1661 GP_0_12_FN, FN_IP0_23_22, 1662 GP_0_11_FN, FN_IP0_21_20, 1663 GP_0_10_FN, FN_IP0_19_18, 1664 GP_0_9_FN, FN_IP0_17_16, 1665 GP_0_8_FN, FN_IP0_15_14, 1666 GP_0_7_FN, FN_IP0_13_12, 1667 GP_0_6_FN, FN_IP0_11_10, 1668 GP_0_5_FN, FN_IP0_9_8, 1669 GP_0_4_FN, FN_IP0_7_6, 1670 GP_0_3_FN, FN_IP1_15_14, 1671 GP_0_2_FN, FN_IP1_13_12, 1672 GP_0_1_FN, FN_IP1_11_10, 1673 GP_0_0_FN, FN_IP1_9_8 } 1674 }, 1675 { PINMUX_CFG_REG("GPSR1", 0xFFFC0008, 32, 1) { 1676 GP_1_31_FN, FN_IP11_25_23, 1677 GP_1_30_FN, FN_IP2_13_11, 1678 GP_1_29_FN, FN_IP2_10_8, 1679 GP_1_28_FN, FN_IP2_7_5, 1680 GP_1_27_FN, FN_IP3_26_24, 1681 GP_1_26_FN, FN_IP3_23_21, 1682 GP_1_25_FN, FN_IP2_4_3, 1683 GP_1_24_FN, FN_WE1, 1684 GP_1_23_FN, FN_WE0, 1685 GP_1_22_FN, FN_IP3_19_18, 1686 GP_1_21_FN, FN_RD, 1687 GP_1_20_FN, FN_IP3_17_15, 1688 GP_1_19_FN, FN_IP3_14_12, 1689 GP_1_18_FN, FN_IP3_11_9, 1690 GP_1_17_FN, FN_IP3_8_6, 1691 GP_1_16_FN, FN_IP3_5_3, 1692 GP_1_15_FN, FN_EX_CS0, 1693 GP_1_14_FN, FN_IP3_2, 1694 GP_1_13_FN, FN_CS0, 1695 GP_1_12_FN, FN_BS, 1696 GP_1_11_FN, FN_CLKOUT, 1697 GP_1_10_FN, FN_IP3_1_0, 1698 GP_1_9_FN, FN_IP2_30_28, 1699 GP_1_8_FN, FN_IP2_27_25, 1700 GP_1_7_FN, FN_IP2_24_23, 1701 GP_1_6_FN, FN_IP2_22_20, 1702 GP_1_5_FN, FN_IP2_19_17, 1703 GP_1_4_FN, FN_IP2_16_14, 1704 GP_1_3_FN, FN_IP11_22_21, 1705 GP_1_2_FN, FN_IP11_20_19, 1706 GP_1_1_FN, FN_IP3_29_27, 1707 GP_1_0_FN, FN_IP3_20 } 1708 }, 1709 { PINMUX_CFG_REG("GPSR2", 0xFFFC000C, 32, 1) { 1710 GP_2_31_FN, FN_IP4_31_30, 1711 GP_2_30_FN, FN_IP5_2_0, 1712 GP_2_29_FN, FN_IP5_5_3, 1713 GP_2_28_FN, FN_IP5_8_6, 1714 GP_2_27_FN, FN_IP5_11_9, 1715 GP_2_26_FN, FN_IP5_14_12, 1716 GP_2_25_FN, FN_IP5_17_15, 1717 GP_2_24_FN, FN_IP5_20_18, 1718 GP_2_23_FN, FN_IP5_22_21, 1719 GP_2_22_FN, FN_IP5_24_23, 1720 GP_2_21_FN, FN_IP5_26_25, 1721 GP_2_20_FN, FN_IP4_29_28, 1722 GP_2_19_FN, FN_IP4_27_26, 1723 GP_2_18_FN, FN_IP4_25_24, 1724 GP_2_17_FN, FN_IP4_23_22, 1725 GP_2_16_FN, FN_IP4_21_20, 1726 GP_2_15_FN, FN_IP4_19_18, 1727 GP_2_14_FN, FN_IP4_17_15, 1728 GP_2_13_FN, FN_IP4_14_12, 1729 GP_2_12_FN, FN_IP4_11_9, 1730 GP_2_11_FN, FN_IP4_8_6, 1731 GP_2_10_FN, FN_IP4_5_3, 1732 GP_2_9_FN, FN_IP8_27_26, 1733 GP_2_8_FN, FN_IP11_12, 1734 GP_2_7_FN, FN_IP8_25_23, 1735 GP_2_6_FN, FN_IP8_22_20, 1736 GP_2_5_FN, FN_IP11_27_26, 1737 GP_2_4_FN, FN_IP8_29_28, 1738 GP_2_3_FN, FN_IP4_2_0, 1739 GP_2_2_FN, FN_IP11_11_10, 1740 GP_2_1_FN, FN_IP11_9_7, 1741 GP_2_0_FN, FN_IP11_6_4 } 1742 }, 1743 { PINMUX_CFG_REG("GPSR3", 0xFFFC0010, 32, 1) { 1744 GP_3_31_FN, FN_IP9_1_0, 1745 GP_3_30_FN, FN_IP8_19_18, 1746 GP_3_29_FN, FN_IP8_17_16, 1747 GP_3_28_FN, FN_IP8_15_14, 1748 GP_3_27_FN, FN_IP8_13_12, 1749 GP_3_26_FN, FN_IP8_11_10, 1750 GP_3_25_FN, FN_IP8_9_8, 1751 GP_3_24_FN, FN_IP8_7_6, 1752 GP_3_23_FN, FN_IP8_5_4, 1753 GP_3_22_FN, FN_IP8_3_2, 1754 GP_3_21_FN, FN_IP8_1_0, 1755 GP_3_20_FN, FN_IP7_30_29, 1756 GP_3_19_FN, FN_IP7_28_27, 1757 GP_3_18_FN, FN_IP7_26_24, 1758 GP_3_17_FN, FN_IP7_23_21, 1759 GP_3_16_FN, FN_IP7_20_18, 1760 GP_3_15_FN, FN_IP7_17_15, 1761 GP_3_14_FN, FN_IP7_14_12, 1762 GP_3_13_FN, FN_IP7_11_9, 1763 GP_3_12_FN, FN_IP7_8_6, 1764 GP_3_11_FN, FN_IP7_5_3, 1765 GP_3_10_FN, FN_IP7_2_0, 1766 GP_3_9_FN, FN_IP6_23_21, 1767 GP_3_8_FN, FN_IP6_20_18, 1768 GP_3_7_FN, FN_IP6_17_16, 1769 GP_3_6_FN, FN_IP6_15_14, 1770 GP_3_5_FN, FN_IP6_13_12, 1771 GP_3_4_FN, FN_IP6_11_10, 1772 GP_3_3_FN, FN_IP6_9_8, 1773 GP_3_2_FN, FN_IP6_7_6, 1774 GP_3_1_FN, FN_IP6_5_3, 1775 GP_3_0_FN, FN_IP6_2_0 } 1776 }, 1777 1778 { PINMUX_CFG_REG("GPSR4", 0xFFFC0014, 32, 1) { 1779 GP_4_31_FN, FN_IP10_24_23, 1780 GP_4_30_FN, FN_IP10_22, 1781 GP_4_29_FN, FN_IP11_18_16, 1782 GP_4_28_FN, FN_USB_OVC0, 1783 GP_4_27_FN, FN_IP11_15_13, 1784 GP_4_26_FN, FN_PENC0, 1785 GP_4_25_FN, FN_IP11_2, 1786 GP_4_24_FN, FN_SCL0, 1787 GP_4_23_FN, FN_IP11_1, 1788 GP_4_22_FN, FN_IP11_0, 1789 GP_4_21_FN, FN_IP10_21_19, 1790 GP_4_20_FN, FN_IP10_18_16, 1791 GP_4_19_FN, FN_IP10_15, 1792 GP_4_18_FN, FN_IP10_14_12, 1793 GP_4_17_FN, FN_IP10_11_9, 1794 GP_4_16_FN, FN_IP10_8_6, 1795 GP_4_15_FN, FN_IP10_5_3, 1796 GP_4_14_FN, FN_IP10_2_0, 1797 GP_4_13_FN, FN_IP9_29_28, 1798 GP_4_12_FN, FN_IP9_27_26, 1799 GP_4_11_FN, FN_IP9_9_8, 1800 GP_4_10_FN, FN_IP9_7_6, 1801 GP_4_9_FN, FN_IP9_5_4, 1802 GP_4_8_FN, FN_IP9_3_2, 1803 GP_4_7_FN, FN_IP9_17_16, 1804 GP_4_6_FN, FN_IP9_15_14, 1805 GP_4_5_FN, FN_IP9_13_12, 1806 GP_4_4_FN, FN_IP9_11_10, 1807 GP_4_3_FN, FN_IP9_25_24, 1808 GP_4_2_FN, FN_IP9_23_22, 1809 GP_4_1_FN, FN_IP9_21_20, 1810 GP_4_0_FN, FN_IP9_19_18 } 1811 }, 1812 { PINMUX_CFG_REG("GPSR5", 0xFFFC0018, 32, 1) { 1813 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 28 */ 1814 0, 0, 0, 0, 0, 0, 0, 0, /* 27 - 24 */ 1815 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 20 */ 1816 0, 0, 0, 0, 0, 0, 0, 0, /* 19 - 16 */ 1817 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */ 1818 GP_5_11_FN, FN_IP10_29_28, 1819 GP_5_10_FN, FN_IP10_27_26, 1820 0, 0, 0, 0, 0, 0, 0, 0, /* 9 - 6 */ 1821 0, 0, 0, 0, /* 5, 4 */ 1822 GP_5_3_FN, FN_IRQ3_B, 1823 GP_5_2_FN, FN_IRQ2_B, 1824 GP_5_1_FN, FN_IP11_3, 1825 GP_5_0_FN, FN_IP10_25 } 1826 }, 1827 1828 { PINMUX_CFG_REG_VAR("IPSR0", 0xFFFC001C, 32, 1829 2, 2, 2, 2, 2, 2, 2, 2, 1830 2, 2, 2, 2, 2, 2, 2, 2) { 1831 /* IP0_31_30 [2] */ 1832 FN_A15, FN_ST0_VCO_CLKIN, FN_LCD_DATA15_A, 1833 FN_TIOC3D_C, 1834 /* IP0_29_28 [2] */ 1835 FN_A14, FN_LCD_DATA14_A, FN_TIOC3C_C, 0, 1836 /* IP0_27_26 [2] */ 1837 FN_A13, FN_LCD_DATA13_A, FN_TIOC3B_C, 0, 1838 /* IP0_25_24 [2] */ 1839 FN_A12, FN_LCD_DATA12_A, FN_TIOC3A_C, 0, 1840 /* IP0_23_22 [2] */ 1841 FN_A11, FN_ST0_D7, FN_LCD_DATA11_A, FN_TIOC2B_C, 1842 /* IP0_21_20 [2] */ 1843 FN_A10, FN_ST0_D6, FN_LCD_DATA10_A, FN_TIOC2A_C, 1844 /* IP0_19_18 [2] */ 1845 FN_A9, FN_ST0_D5, FN_LCD_DATA9_A, FN_TIOC1B_C, 1846 /* IP0_17_16 [2] */ 1847 FN_A8, FN_ST0_D4, FN_LCD_DATA8_A, FN_TIOC1A_C, 1848 /* IP0_15_14 [2] */ 1849 FN_A7, FN_ST0_D3, FN_LCD_DATA7_A, FN_TIOC0D_C, 1850 /* IP0_13_12 [2] */ 1851 FN_A6, FN_ST0_D2, FN_LCD_DATA6_A, FN_TIOC0C_C, 1852 /* IP0_11_10 [2] */ 1853 FN_A5, FN_ST0_D1, FN_LCD_DATA5_A, FN_TIOC0B_C, 1854 /* IP0_9_8 [2] */ 1855 FN_A4, FN_ST0_D0, FN_LCD_DATA4_A, FN_TIOC0A_C, 1856 /* IP0_7_6 [2] */ 1857 FN_A3, FN_ST0_VLD, FN_LCD_DATA3_A, FN_TCLKD_C, 1858 /* IP0_5_4 [2] */ 1859 FN_A2, FN_ST0_SYC, FN_LCD_DATA2_A, FN_TCLKC_C, 1860 /* IP0_3_2 [2] */ 1861 FN_A1, FN_ST0_REQ, FN_LCD_DATA1_A, FN_TCLKB_C, 1862 /* IP0_1_0 [2] */ 1863 FN_A0, FN_ST0_CLKIN, FN_LCD_DATA0_A, FN_TCLKA_C } 1864 }, 1865 { PINMUX_CFG_REG_VAR("IPSR1", 0xFFFC0020, 32, 1866 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 1867 /* IP1_31_29 [3] */ 1868 FN_D3, FN_SD0_DAT3_A, FN_MMC_D3_A, FN_ST1_D6, 1869 FN_FD3_A, 0, 0, 0, 1870 /* IP1_28_26 [3] */ 1871 FN_D2, FN_SD0_DAT2_A, FN_MMC_D2_A, FN_ST1_D5, 1872 FN_FD2_A, 0, 0, 0, 1873 /* IP1_25_23 [3] */ 1874 FN_D1, FN_SD0_DAT1_A, FN_MMC_D1_A, FN_ST1_D4, 1875 FN_FD1_A, 0, 0, 0, 1876 /* IP1_22_20 [3] */ 1877 FN_D0, FN_SD0_DAT0_A, FN_MMC_D0_A, FN_ST1_D3, 1878 FN_FD0_A, 0, 0, 0, 1879 /* IP1_19_18 [2] */ 1880 FN_A25, FN_TX2_D, FN_ST1_D2, 0, 1881 /* IP1_17_16 [2] */ 1882 FN_A24, FN_RX2_D, FN_ST1_D1, 0, 1883 /* IP1_15_14 [2] */ 1884 FN_A23, FN_ST1_D0, FN_LCD_M_DISP_A, 0, 1885 /* IP1_13_12 [2] */ 1886 FN_A22, FN_ST1_VLD, FN_LCD_VEPWC_A, 0, 1887 /* IP1_11_10 [2] */ 1888 FN_A21, FN_ST1_SYC, FN_LCD_VCPWC_A, 0, 1889 /* IP1_9_8 [2] */ 1890 FN_A20, FN_ST1_REQ, FN_LCD_FLM_A, 0, 1891 /* IP1_7_6 [2] */ 1892 FN_A19, FN_ST1_CLKIN, FN_LCD_CLK_A, FN_TIOC4D_C, 1893 /* IP1_5_4 [2] */ 1894 FN_A18, FN_ST1_PWM, FN_LCD_CL2_A, FN_TIOC4C_C, 1895 /* IP1_3_2 [2] */ 1896 FN_A17, FN_ST1_VCO_CLKIN, FN_LCD_CL1_A, FN_TIOC4B_C, 1897 /* IP1_1_0 [2] */ 1898 FN_A16, FN_ST0_PWM, FN_LCD_DON_A, FN_TIOC4A_C } 1899 }, 1900 { PINMUX_CFG_REG_VAR("IPSR2", 0xFFFC0024, 32, 1901 1, 3, 3, 2, 3, 3, 3, 3, 3, 3, 2, 3) { 1902 /* IP2_31 [1] */ 1903 0, 0, 1904 /* IP2_30_28 [3] */ 1905 FN_D14, FN_TX2_B, 0, FN_FSE_A, 1906 FN_ET0_TX_CLK_B, 0, 0, 0, 1907 /* IP2_27_25 [3] */ 1908 FN_D13, FN_RX2_B, 0, FN_FRB_A, 1909 FN_ET0_ETXD6_B, 0, 0, 0, 1910 /* IP2_24_23 [2] */ 1911 FN_D12, 0, FN_FWE_A, FN_ET0_ETXD5_B, 1912 /* IP2_22_20 [3] */ 1913 FN_D11, FN_RSPI_MISO_A, 0, FN_QMI_QIO1_A, 1914 FN_FRE_A, FN_ET0_ETXD3_B, 0, 0, 1915 /* IP2_19_17 [3] */ 1916 FN_D10, FN_RSPI_MOSI_A, 0, FN_QMO_QIO0_A, 1917 FN_FALE_A, FN_ET0_ETXD2_B, 0, 0, 1918 /* IP2_16_14 [3] */ 1919 FN_D9, FN_SD0_CMD_A, FN_MMC_CMD_A, FN_QIO3_A, 1920 FN_FCLE_A, FN_ET0_ETXD1_B, 0, 0, 1921 /* IP2_13_11 [3] */ 1922 FN_D8, FN_SD0_CLK_A, FN_MMC_CLK_A, FN_QIO2_A, 1923 FN_FCE_A, FN_ET0_GTX_CLK_B, 0, 0, 1924 /* IP2_10_8 [3] */ 1925 FN_D7, FN_RSPI_SSL_A, FN_MMC_D7_A, FN_QSSL_A, 1926 FN_FD7_A, 0, 0, 0, 1927 /* IP2_7_5 [3] */ 1928 FN_D6, FN_RSPI_RSPCK_A, FN_MMC_D6_A, FN_QSPCLK_A, 1929 FN_FD6_A, 0, 0, 0, 1930 /* IP2_4_3 [2] */ 1931 FN_D5, FN_SD0_WP_A, FN_MMC_D5_A, FN_FD5_A, 1932 /* IP2_2_0 [3] */ 1933 FN_D4, FN_SD0_CD_A, FN_MMC_D4_A, FN_ST1_D7, 1934 FN_FD4_A, 0, 0, 0 } 1935 }, 1936 { PINMUX_CFG_REG_VAR("IPSR3", 0xFFFC0028, 32, 1937 2, 3, 3, 3, 1, 2, 3, 3, 3, 3, 3, 1, 2) { 1938 /* IP3_31_30 [2] */ 1939 0, 0, 0, 0, 1940 /* IP3_29_27 [3] */ 1941 FN_DRACK0, FN_SD1_DAT2_A, FN_ATAG, FN_TCLK1_A, 1942 FN_ET0_ETXD7, 0, 0, 0, 1943 /* IP3_26_24 [3] */ 1944 FN_EX_WAIT2, FN_SD1_DAT1_A, FN_DACK2, FN_CAN1_RX_C, 1945 FN_ET0_MAGIC_C, FN_ET0_ETXD6_A, 0, 0, 1946 /* IP3_23_21 [3] */ 1947 FN_EX_WAIT1, FN_SD1_DAT0_A, FN_DREQ2, FN_CAN1_TX_C, 1948 FN_ET0_LINK_C, FN_ET0_ETXD5_A, 0, 0, 1949 /* IP3_20 [1] */ 1950 FN_EX_WAIT0, FN_TCLK1_B, 1951 /* IP3_19_18 [2] */ 1952 FN_RD_WR, FN_TCLK1_B, 0, 0, 1953 /* IP3_17_15 [3] */ 1954 FN_EX_CS5, FN_SD1_CMD_A, FN_ATADIR, FN_QSSL_B, 1955 FN_ET0_ETXD3_A, 0, 0, 0, 1956 /* IP3_14_12 [3] */ 1957 FN_EX_CS4, FN_SD1_WP_A, FN_ATAWR, FN_QMI_QIO1_B, 1958 FN_ET0_ETXD2_A, 0, 0, 0, 1959 /* IP3_11_9 [3] */ 1960 FN_EX_CS3, FN_SD1_CD_A, FN_ATARD, FN_QMO_QIO0_B, 1961 FN_ET0_ETXD1_A, 0, 0, 0, 1962 /* IP3_8_6 [3] */ 1963 FN_EX_CS2, FN_TX3_B, FN_ATACS1, FN_QSPCLK_B, 1964 FN_ET0_GTX_CLK_A, 0, 0, 0, 1965 /* IP3_5_3 [3] */ 1966 FN_EX_CS1, FN_RX3_B, FN_ATACS0, FN_QIO2_B, 1967 FN_ET0_ETXD0, 0, 0, 0, 1968 /* IP3_2 [1] */ 1969 FN_CS1_A26, FN_QIO3_B, 1970 /* IP3_1_0 [2] */ 1971 FN_D15, FN_SCK2_B, 0, 0 } 1972 }, 1973 { PINMUX_CFG_REG_VAR("IPSR4", 0xFFFC002C, 32, 1974 2, 2, 2, 2, 2, 2 , 2, 3, 3, 3, 3, 3, 3) { 1975 /* IP4_31_30 [2] */ 1976 0, FN_SCK2_A, FN_VI0_G3, 0, 1977 /* IP4_29_28 [2] */ 1978 0, FN_RTS1_B, FN_VI0_G2, 0, 1979 /* IP4_27_26 [2] */ 1980 0, FN_CTS1_B, FN_VI0_DATA7_VI0_G1, 0, 1981 /* IP4_25_24 [2] */ 1982 0, FN_TX1_B, FN_VI0_DATA6_VI0_G0, FN_ET0_PHY_INT_A, 1983 /* IP4_23_22 [2] */ 1984 0, FN_RX1_B, FN_VI0_DATA5_VI0_B5, FN_ET0_MAGIC_A, 1985 /* IP4_21_20 [2] */ 1986 0, FN_SCK1_B, FN_VI0_DATA4_VI0_B4, FN_ET0_LINK_A, 1987 /* IP4_19_18 [2] */ 1988 0, FN_RTS0_B, FN_VI0_DATA3_VI0_B3, FN_ET0_MDIO_A, 1989 /* IP4_17_15 [3] */ 1990 0, FN_CTS0_B, FN_VI0_DATA2_VI0_B2, FN_RMII0_MDIO_A, 1991 FN_ET0_MDC, 0, 0, 0, 1992 /* IP4_14_12 [3] */ 1993 FN_HTX0_A, FN_TX1_A, FN_VI0_DATA1_VI0_B1, FN_RMII0_MDC_A, 1994 FN_ET0_COL, 0, 0, 0, 1995 /* IP4_11_9 [3] */ 1996 FN_HRX0_A, FN_RX1_A, FN_VI0_DATA0_VI0_B0, FN_RMII0_CRS_DV_A, 1997 FN_ET0_CRS, 0, 0, 0, 1998 /* IP4_8_6 [3] */ 1999 FN_HSCK0_A, FN_SCK1_A, FN_VI0_VSYNC, FN_RMII0_RX_ER_A, 2000 FN_ET0_RX_ER, 0, 0, 0, 2001 /* IP4_5_3 [3] */ 2002 FN_HRTS0_A, FN_RTS1_A, FN_VI0_HSYNC, FN_RMII0_TXD_EN_A, 2003 FN_ET0_RX_DV, 0, 0, 0, 2004 /* IP4_2_0 [3] */ 2005 FN_HCTS0_A, FN_CTS1_A, FN_VI0_FIELD, FN_RMII0_RXD1_A, 2006 FN_ET0_ERXD7, 0, 0, 0 } 2007 }, 2008 { PINMUX_CFG_REG_VAR("IPSR5", 0xFFFC0030, 32, 2009 1, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3) { 2010 /* IP5_31 [1] */ 2011 0, 0, 2012 /* IP5_30 [1] */ 2013 0, 0, 2014 /* IP5_29 [1] */ 2015 0, 0, 2016 /* IP5_28 [1] */ 2017 0, 0, 2018 /* IP5_27 [1] */ 2019 0, 0, 2020 /* IP5_26_25 [2] */ 2021 FN_REF50CK, FN_CTS1_E, FN_HCTS0_D, 0, 2022 /* IP5_24_23 [2] */ 2023 FN_REF125CK, FN_ADTRG, FN_RX5_C, 0, 2024 /* IP5_22_21 [2] */ 2025 FN_SD2_WP_A, FN_TX5_A, FN_VI0_R5, 0, 2026 /* IP5_20_18 [3] */ 2027 FN_SD2_CD_A, FN_RX5_A, FN_VI0_R4, 0, 2028 0, 0, 0, FN_ET0_PHY_INT_B, 2029 /* IP5_17_15 [3] */ 2030 FN_SD2_DAT3_A, FN_TX4_A, FN_VI0_R3, 0, 2031 0, 0, 0, FN_ET0_MAGIC_B, 2032 /* IP5_14_12 [3] */ 2033 FN_SD2_DAT2_A, FN_RX4_A, FN_VI0_R2, 0, 2034 0, 0, 0, FN_ET0_LINK_B, 2035 /* IP5_11_9 [3] */ 2036 FN_SD2_DAT1_A, FN_TX3_A, FN_VI0_R1, 0, 2037 0, 0, 0, FN_ET0_MDIO_B, 2038 /* IP5_8_6 [3] */ 2039 FN_SD2_DAT0_A, FN_RX3_A, FN_VI0_R0, 0, 2040 0, 0, 0, FN_ET0_ERXD3_B, 2041 /* IP5_5_3 [3] */ 2042 FN_SD2_CMD_A, FN_TX2_A, FN_VI0_G5, 0, 2043 0, 0, 0, FN_ET0_ERXD2_B, 2044 /* IP5_2_0 [3] */ 2045 FN_SD2_CLK_A, FN_RX2_A, FN_VI0_G4, 0, 2046 FN_ET0_RX_CLK_B, 0, 0, 0 } 2047 }, 2048 { PINMUX_CFG_REG_VAR("IPSR6", 0xFFFC0034, 32, 2049 1, 1, 1, 1, 1, 1, 1, 1, 2050 3, 3, 2, 2, 2, 2, 2, 2, 3, 3) { 2051 /* IP5_31 [1] */ 2052 0, 0, 2053 /* IP6_30 [1] */ 2054 0, 0, 2055 /* IP6_29 [1] */ 2056 0, 0, 2057 /* IP6_28 [1] */ 2058 0, 0, 2059 /* IP6_27 [1] */ 2060 0, 0, 2061 /* IP6_26 [1] */ 2062 0, 0, 2063 /* IP6_25 [1] */ 2064 0, 0, 2065 /* IP6_24 [1] */ 2066 0, 0, 2067 /* IP6_23_21 [3] */ 2068 FN_DU0_DG1, FN_CTS1_C, FN_HRTS0_D, FN_TIOC1B_A, 2069 FN_HIFD09, 0, 0, 0, 2070 /* IP6_20_18 [3] */ 2071 FN_DU0_DG0, FN_TX1_C, FN_HSCK0_D, FN_IECLK_A, 2072 FN_TIOC1A_A, FN_HIFD08, 0, 0, 2073 /* IP6_17_16 [2] */ 2074 FN_DU0_DR7, FN_RX1_C, FN_TIOC0D_A, FN_HIFD07, 2075 /* IP6_15_14 [2] */ 2076 FN_DU0_DR6, FN_SCK1_C, FN_TIOC0C_A, FN_HIFD06, 2077 /* IP6_13_12 [2] */ 2078 FN_DU0_DR5, FN_RTS0_C, FN_TIOC0B_A, FN_HIFD05, 2079 /* IP6_11_10 [2] */ 2080 FN_DU0_DR4, FN_CTS0_C, FN_TIOC0A_A, FN_HIFD04, 2081 /* IP6_9_8 [2] */ 2082 FN_DU0_DR3, FN_TX0_B, FN_TCLKD_A, FN_HIFD03, 2083 /* IP6_7_6 [2] */ 2084 FN_DU0_DR2, FN_RX0_B, FN_TCLKC_A, FN_HIFD02, 2085 /* IP6_5_3 [3] */ 2086 FN_DU0_DR1, FN_SCK0_B, FN_HTX0_D, FN_IERX_A, 2087 FN_TCLKB_A, FN_HIFD01, 0, 0, 2088 /* IP6_2_0 [3] */ 2089 FN_DU0_DR0, FN_SCIF_CLK_B, FN_HRX0_D, FN_IETX_A, 2090 FN_TCLKA_A, FN_HIFD00, 0, 0 } 2091 }, 2092 { PINMUX_CFG_REG_VAR("IPSR7", 0xFFFC0038, 32, 2093 1, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3) { 2094 /* IP7_31 [1] */ 2095 0, 0, 2096 /* IP7_30_29 [2] */ 2097 FN_DU0_DB4, 0, FN_HIFINT, 0, 2098 /* IP7_28_27 [2] */ 2099 FN_DU0_DB3, FN_TX5_B, FN_TIOC4D_A, FN_HIFRD, 2100 /* IP7_26_24 [3] */ 2101 FN_DU0_DB2, FN_RX5_B, FN_RMII0_TXD1_B, FN_TIOC4C_A, 2102 FN_HIFWR, 0, 0, 0, 2103 /* IP7_23_21 [3] */ 2104 FN_DU0_DB1, FN_TX4_C, FN_RMII0_TXD0_B, FN_TIOC4B_A, 2105 FN_HIFRS, 0, 0, 0, 2106 /* IP7_20_18 [3] */ 2107 FN_DU0_DB0, FN_RX4_C, FN_RMII0_TXD_EN_B, FN_TIOC4A_A, 2108 FN_HIFCS, 0, 0, 0, 2109 /* IP7_17_15 [3] */ 2110 FN_DU0_DG7, FN_TX3_C, FN_RMII0_RXD1_B, FN_TIOC3D_A, 2111 FN_HIFD15, 0, 0, 0, 2112 /* IP7_14_12 [3] */ 2113 FN_DU0_DG6, FN_RX3_C, FN_RMII0_RXD0_B, FN_TIOC3C_A, 2114 FN_HIFD14, 0, 0, 0, 2115 /* IP7_11_9 [3] */ 2116 FN_DU0_DG5, FN_TX2_C, FN_RMII0_RX_ER_B, FN_TIOC3B_A, 2117 FN_HIFD13, 0, 0, 0, 2118 /* IP7_8_6 [3] */ 2119 FN_DU0_DG4, FN_RX2_C, FN_RMII0_CRS_DV_B, FN_TIOC3A_A, 2120 FN_HIFD12, 0, 0, 0, 2121 /* IP7_5_3 [3] */ 2122 FN_DU0_DG3, FN_SCK2_C, FN_RMII0_MDIO_B, FN_TIOC2B_A, 2123 FN_HIFD11, 0, 0, 0, 2124 /* IP7_2_0 [3] */ 2125 FN_DU0_DG2, FN_RTS1_C, FN_RMII0_MDC_B, FN_TIOC2A_A, 2126 FN_HIFD10, 0, 0, 0 } 2127 }, 2128 { PINMUX_CFG_REG_VAR("IPSR8", 0xFFFC003C, 32, 2129 2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2) { 2130 /* IP9_31_30 [2] */ 2131 0, 0, 0, 0, 2132 /* IP8_29_28 [2] */ 2133 FN_IRQ3_A, FN_RTS0_A, FN_HRTS0_B, FN_ET0_ERXD3_A, 2134 /* IP8_27_26 [2] */ 2135 FN_IRQ2_A, FN_CTS0_A, FN_HCTS0_B, FN_ET0_ERXD2_A, 2136 /* IP8_25_23 [3] */ 2137 FN_IRQ1_A, 0, FN_HSPI_RX_B, FN_TX3_E, 2138 FN_ET0_ERXD1, 0, 0, 0, 2139 /* IP8_22_20 [3] */ 2140 FN_IRQ0_A, 0, FN_HSPI_TX_B, FN_RX3_E, 2141 FN_ET0_ERXD0, 0, 0, 0, 2142 /* IP8_19_18 [2] */ 2143 FN_DU0_CDE, FN_HTX0_B, FN_AUDIO_CLKB_B, FN_LCD_VCPWC_B, 2144 /* IP8_17_16 [2] */ 2145 FN_DU0_DISP, FN_CAN0_TX_B, FN_HRX0_B, FN_AUDIO_CLKA_B, 2146 /* IP8_15_14 [2] */ 2147 FN_DU0_EXODDF_DU0_ODDF, FN_CAN0_RX_B, FN_HSCK0_B, 2148 FN_SSI_SDATA1_B, 2149 /* IP8_13_12 [2] */ 2150 FN_DU0_EXVSYNC_DU0_VSYNC, 0, FN_HSPI_RX0_C, FN_SSI_WS1_B, 2151 /* IP8_11_10 [2] */ 2152 FN_DU0_EXHSYNC_DU0_HSYNC, 0, FN_HSPI_TX0_C, FN_SSI_SCK1_B, 2153 /* IP8_9_8 [2] */ 2154 FN_DU0_DOTCLKOUT, 0, FN_HSPI_CLK0_C, FN_SSI_SDATA0_B, 2155 /* IP8_7_6 [2] */ 2156 FN_DU0_DOTCLKIN, 0, FN_HSPI_CS0_C, FN_SSI_WS0_B, 2157 /* IP8_5_4 [2] */ 2158 FN_DU0_DB7, 0, FN_SSI_SCK0_B, FN_HIFEBL_B, 2159 /* IP8_3_2 [2] */ 2160 FN_DU0_DB6, 0, FN_HIFRDY, 0, 2161 /* IP8_1_0 [2] */ 2162 FN_DU0_DB5, 0, FN_HIFDREQ, 0 } 2163 }, 2164 { PINMUX_CFG_REG_VAR("IPSR9", 0xFFFC0040, 32, 2165 2, 2, 2, 2, 2, 2, 2, 2, 2166 2, 2, 2, 2, 2, 2, 2, 2) { 2167 /* IP9_31_30 [2] */ 2168 0, 0, 0, 0, 2169 /* IP9_29_28 [2] */ 2170 FN_SSI_SDATA1_A, FN_VI1_3_B, FN_LCD_DATA14_B, 0, 2171 /* IP9_27_26 [2] */ 2172 FN_SSI_WS1_A, FN_VI1_2_B, FN_LCD_DATA13_B, 0, 2173 /* IP9_25_24 [2] */ 2174 FN_SSI_SCK1_A, FN_VI1_1_B, FN_TIOC2B_B, FN_LCD_DATA12_B, 2175 /* IP9_23_22 [2] */ 2176 FN_SSI_SDATA0_A, FN_VI1_0_B, FN_TIOC2A_B, FN_LCD_DATA11_B, 2177 /* IP9_21_20 [2] */ 2178 FN_SSI_WS0_A, FN_TIOC1B_B, FN_LCD_DATA10_B, 0, 2179 /* IP9_19_18 [2] */ 2180 FN_SSI_SCK0_A, FN_TIOC1A_B, FN_LCD_DATA9_B, 0, 2181 /* IP9_17_16 [2] */ 2182 FN_VI1_7_A, FN_FCE_B, FN_LCD_DATA8_B, 0, 2183 /* IP9_15_14 [2] */ 2184 FN_VI1_6_A, 0, FN_FD7_B, FN_LCD_DATA7_B, 2185 /* IP9_13_12 [2] */ 2186 FN_VI1_5_A, 0, FN_FD6_B, FN_LCD_DATA6_B, 2187 /* IP9_11_10 [2] */ 2188 FN_VI1_4_A, 0, FN_FD5_B, FN_LCD_DATA5_B, 2189 /* IP9_9_8 [2] */ 2190 FN_VI1_3_A, 0, FN_FD4_B, FN_LCD_DATA4_B, 2191 /* IP9_7_6 [2] */ 2192 FN_VI1_2_A, 0, FN_FD3_B, FN_LCD_DATA3_B, 2193 /* IP9_5_4 [2] */ 2194 FN_VI1_1_A, 0, FN_FD2_B, FN_LCD_DATA2_B, 2195 /* IP9_3_2 [2] */ 2196 FN_VI1_0_A, 0, FN_FD1_B, FN_LCD_DATA1_B, 2197 /* IP9_1_0 [2] */ 2198 FN_VI1_CLK_A, 0, FN_FD0_B, FN_LCD_DATA0_B } 2199 }, 2200 { PINMUX_CFG_REG_VAR("IPSR10", 0xFFFC0044, 32, 2201 2, 2, 2, 1, 2, 1, 3, 2202 3, 1, 3, 3, 3, 3, 3) { 2203 /* IP9_31_30 [2] */ 2204 0, 0, 0, 0, 2205 /* IP10_29_28 [2] */ 2206 FN_CAN1_TX_A, FN_TX5_C, FN_MLB_DAT, 0, 2207 /* IP10_27_26 [2] */ 2208 FN_CAN0_RX_A, FN_IRQ0_B, FN_MLB_SIG, 0, 2209 /* IP10_25 [1] */ 2210 FN_CAN1_RX_A, FN_IRQ1_B, 2211 /* IP10_24_23 [2] */ 2212 FN_CAN0_TX_A, FN_TX4_D, FN_MLB_CLK, 0, 2213 /* IP10_22 [1] */ 2214 FN_CAN_CLK_A, FN_RX4_D, 2215 /* IP10_21_19 [3] */ 2216 FN_AUDIO_CLKOUT, FN_TX1_E, FN_HRTS0_C, FN_FSE_B, 2217 FN_LCD_M_DISP_B, 0, 0, 0, 2218 /* IP10_18_16 [3] */ 2219 FN_AUDIO_CLKC, FN_SCK1_E, FN_HCTS0_C, FN_FRB_B, 2220 FN_LCD_VEPWC_B, 0, 0, 0, 2221 /* IP10_15 [1] */ 2222 FN_AUDIO_CLKB_A, FN_LCD_CLK_B, 2223 /* IP10_14_12 [3] */ 2224 FN_AUDIO_CLKA_A, FN_VI1_CLK_B, FN_SCK1_D, FN_IECLK_B, 2225 FN_LCD_FLM_B, 0, 0, 0, 2226 /* IP10_11_9 [3] */ 2227 FN_SSI_SDATA3, FN_VI1_7_B, FN_HTX0_C, FN_FWE_B, 2228 FN_LCD_CL2_B, 0, 0, 0, 2229 /* IP10_8_6 [3] */ 2230 FN_SSI_SDATA2, FN_VI1_6_B, FN_HRX0_C, FN_FRE_B, 2231 FN_LCD_CL1_B, 0, 0, 0, 2232 /* IP10_5_3 [3] */ 2233 FN_SSI_WS23, FN_VI1_5_B, FN_TX1_D, FN_HSCK0_C, FN_FALE_B, 2234 FN_LCD_DON_B, 0, 0, 0, 2235 /* IP10_2_0 [3] */ 2236 FN_SSI_SCK23, FN_VI1_4_B, FN_RX1_D, FN_FCLE_B, 2237 FN_LCD_DATA15_B, 0, 0, 0 } 2238 }, 2239 { PINMUX_CFG_REG_VAR("IPSR11", 0xFFFC0048, 32, 2240 3, 1, 2, 2, 2, 3, 3, 1, 2, 3, 3, 1, 1, 1, 1) { 2241 /* IP11_31_29 [3] */ 2242 0, 0, 0, 0, 0, 0, 0, 0, 2243 /* IP11_28 [1] */ 2244 FN_PRESETOUT, FN_ST_CLKOUT, 2245 /* IP11_27_26 [2] */ 2246 FN_DACK1, FN_HSPI_CS_B, FN_TX4_B, FN_ET0_RX_CLK_A, 2247 /* IP11_25_23 [3] */ 2248 FN_DREQ1, FN_HSPI_CLK_B, FN_RX4_B, FN_ET0_PHY_INT_C, 2249 FN_ET0_TX_CLK_A, 0, 0, 0, 2250 /* IP11_22_21 [2] */ 2251 FN_DACK0, FN_SD1_DAT3_A, FN_ET0_TX_ER, 0, 2252 /* IP11_20_19 [2] */ 2253 FN_DREQ0, FN_SD1_CLK_A, FN_ET0_TX_EN, 0, 2254 /* IP11_18_16 [3] */ 2255 FN_USB_OVC1, FN_RX3_D, FN_CAN1_RX_B, FN_RX5_D, 2256 FN_IERX_B, 0, 0, 0, 2257 /* IP11_15_13 [3] */ 2258 FN_PENC1, FN_TX3_D, FN_CAN1_TX_B, FN_TX5_D, 2259 FN_IETX_B, 0, 0, 0, 2260 /* IP11_12 [1] */ 2261 FN_TX0_A, FN_HSPI_TX_A, 2262 /* IP11_11_10 [2] */ 2263 FN_RX0_A, FN_HSPI_RX_A, FN_RMII0_RXD0_A, FN_ET0_ERXD6, 2264 /* IP11_9_7 [3] */ 2265 FN_SCK0_A, FN_HSPI_CS_A, FN_VI0_CLKENB, FN_RMII0_TXD1_A, 2266 FN_ET0_ERXD5, 0, 0, 0, 2267 /* IP11_6_4 [3] */ 2268 FN_SCIF_CLK_A, FN_HSPI_CLK_A, FN_VI0_CLK, FN_RMII0_TXD0_A, 2269 FN_ET0_ERXD4, 0, 0, 0, 2270 /* IP11_3 [1] */ 2271 FN_SDSELF, FN_RTS1_E, 2272 /* IP11_2 [1] */ 2273 FN_SDA0, FN_HIFEBL_A, 2274 /* IP11_1 [1] */ 2275 FN_SDA1, FN_RX1_E, 2276 /* IP11_0 [1] */ 2277 FN_SCL1, FN_SCIF_CLK_C } 2278 }, 2279 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xFFFC004C, 32, 2280 3, 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2281 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) { 2282 /* SEL1_31_29 [3] */ 2283 0, 0, 0, 0, 0, 0, 0, 0, 2284 /* SEL1_28 [1] */ 2285 FN_SEL_IEBUS_0, FN_SEL_IEBUS_1, 2286 /* SEL1_27 [1] */ 2287 FN_SEL_RQSPI_0, FN_SEL_RQSPI_1, 2288 /* SEL1_26 [1] */ 2289 FN_SEL_VIN1_0, FN_SEL_VIN1_1, 2290 /* SEL1_25 [1] */ 2291 FN_SEL_HIF_0, FN_SEL_HIF_1, 2292 /* SEL1_24 [1] */ 2293 FN_SEL_RSPI_0, FN_SEL_RSPI_1, 2294 /* SEL1_23 [1] */ 2295 FN_SEL_LCDC_0, FN_SEL_LCDC_1, 2296 /* SEL1_22_21 [2] */ 2297 FN_SEL_ET0_CTL_0, FN_SEL_ET0_CTL_1, FN_SEL_ET0_CTL_2, 0, 2298 /* SEL1_20 [1] */ 2299 FN_SEL_ET0_0, FN_SEL_ET0_1, 2300 /* SEL1_19 [1] */ 2301 FN_SEL_RMII_0, FN_SEL_RMII_1, 2302 /* SEL1_18 [1] */ 2303 FN_SEL_TMU_0, FN_SEL_TMU_1, 2304 /* SEL1_17_16 [2] */ 2305 FN_SEL_HSPI_0, FN_SEL_HSPI_1, FN_SEL_HSPI_2, 0, 2306 /* SEL1_15_14 [2] */ 2307 FN_SEL_HSCIF_0, FN_SEL_HSCIF_1, FN_SEL_HSCIF_2, FN_SEL_HSCIF_3, 2308 /* SEL1_13 [1] */ 2309 FN_SEL_RCAN_CLK_0, FN_SEL_RCAN_CLK_1, 2310 /* SEL1_12_11 [2] */ 2311 FN_SEL_RCAN1_0, FN_SEL_RCAN1_1, FN_SEL_RCAN1_2, 0, 2312 /* SEL1_10 [1] */ 2313 FN_SEL_RCAN0_0, FN_SEL_RCAN0_1, 2314 /* SEL1_9 [1] */ 2315 FN_SEL_SDHI2_0, FN_SEL_SDHI2_1, 2316 /* SEL1_8 [1] */ 2317 FN_SEL_SDHI1_0, FN_SEL_SDHI1_1, 2318 /* SEL1_7 [1] */ 2319 FN_SEL_SDHI0_0, FN_SEL_SDHI0_1, 2320 /* SEL1_6 [1] */ 2321 FN_SEL_SSI1_0, FN_SEL_SSI1_1, 2322 /* SEL1_5 [1] */ 2323 FN_SEL_SSI0_0, FN_SEL_SSI0_1, 2324 /* SEL1_4 [1] */ 2325 FN_SEL_AUDIO_CLKB_0, FN_SEL_AUDIO_CLKB_1, 2326 /* SEL1_3 [1] */ 2327 FN_SEL_AUDIO_CLKA_0, FN_SEL_AUDIO_CLKA_1, 2328 /* SEL1_2 [1] */ 2329 FN_SEL_FLCTL_0, FN_SEL_FLCTL_1, 2330 /* SEL1_1 [1] */ 2331 FN_SEL_MMC_0, FN_SEL_MMC_1, 2332 /* SEL1_0 [1] */ 2333 FN_SEL_INTC_0, FN_SEL_INTC_1 } 2334 }, 2335 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xFFFC0050, 32, 2336 1, 1, 1, 1, 1, 1, 1, 1, 2337 1, 1, 1, 2, 2, 1, 2, 2, 3, 2, 3, 2, 2) { 2338 /* SEL2_31 [1] */ 2339 0, 0, 2340 /* SEL2_30 [1] */ 2341 0, 0, 2342 /* SEL2_29 [1] */ 2343 0, 0, 2344 /* SEL2_28 [1] */ 2345 0, 0, 2346 /* SEL2_27 [1] */ 2347 0, 0, 2348 /* SEL2_26 [1] */ 2349 0, 0, 2350 /* SEL2_25 [1] */ 2351 0, 0, 2352 /* SEL2_24 [1] */ 2353 0, 0, 2354 /* SEL2_23 [1] */ 2355 FN_SEL_MTU2_CLK_0, FN_SEL_MTU2_CLK_1, 2356 /* SEL2_22 [1] */ 2357 FN_SEL_MTU2_CH4_0, FN_SEL_MTU2_CH4_1, 2358 /* SEL2_21 [1] */ 2359 FN_SEL_MTU2_CH3_0, FN_SEL_MTU2_CH3_1, 2360 /* SEL2_20_19 [2] */ 2361 FN_SEL_MTU2_CH2_0, FN_SEL_MTU2_CH2_1, FN_SEL_MTU2_CH2_2, 0, 2362 /* SEL2_18_17 [2] */ 2363 FN_SEL_MTU2_CH1_0, FN_SEL_MTU2_CH1_1, FN_SEL_MTU2_CH1_2, 0, 2364 /* SEL2_16 [1] */ 2365 FN_SEL_MTU2_CH0_0, FN_SEL_MTU2_CH0_1, 2366 /* SEL2_15_14 [2] */ 2367 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3, 2368 /* SEL2_13_12 [2] */ 2369 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3, 2370 /* SEL2_11_9 [3] */ 2371 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3, 2372 FN_SEL_SCIF3_4, 0, 0, 0, 2373 /* SEL2_8_7 [2] */ 2374 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3, 2375 /* SEL2_6_4 [3] */ 2376 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3, 2377 FN_SEL_SCIF1_4, 0, 0, 0, 2378 /* SEL2_3_2 [2] */ 2379 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, 0, 2380 /* SEL2_1_0 [2] */ 2381 FN_SEL_SCIF_CLK_0, FN_SEL_SCIF_CLK_1, FN_SEL_SCIF_CLK_2, 0 } 2382 }, 2383 /* GPIO 0 - 5*/ 2384 { PINMUX_CFG_REG("INOUTSEL0", 0xFFC40004, 32, 1) { GP_INOUTSEL(0) } }, 2385 { PINMUX_CFG_REG("INOUTSEL1", 0xFFC41004, 32, 1) { GP_INOUTSEL(1) } }, 2386 { PINMUX_CFG_REG("INOUTSEL2", 0xFFC42004, 32, 1) { GP_INOUTSEL(2) } }, 2387 { PINMUX_CFG_REG("INOUTSEL3", 0xFFC43004, 32, 1) { GP_INOUTSEL(3) } }, 2388 { PINMUX_CFG_REG("INOUTSEL4", 0xFFC44004, 32, 1) { GP_INOUTSEL(4) } }, 2389 { PINMUX_CFG_REG("INOUTSEL5", 0xffc45004, 32, 1) { 2390 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 31 - 24 */ 2391 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* 23 - 16 */ 2392 0, 0, 0, 0, 0, 0, 0, 0, /* 15 - 12 */ 2393 GP_5_11_IN, GP_5_11_OUT, 2394 GP_5_10_IN, GP_5_10_OUT, 2395 GP_5_9_IN, GP_5_9_OUT, 2396 GP_5_8_IN, GP_5_8_OUT, 2397 GP_5_7_IN, GP_5_7_OUT, 2398 GP_5_6_IN, GP_5_6_OUT, 2399 GP_5_5_IN, GP_5_5_OUT, 2400 GP_5_4_IN, GP_5_4_OUT, 2401 GP_5_3_IN, GP_5_3_OUT, 2402 GP_5_2_IN, GP_5_2_OUT, 2403 GP_5_1_IN, GP_5_1_OUT, 2404 GP_5_0_IN, GP_5_0_OUT } 2405 }, 2406 { }, 2407 }; 2408 2409 static const struct pinmux_data_reg pinmux_data_regs[] = { 2410 /* GPIO 0 - 5*/ 2411 { PINMUX_DATA_REG("INDT0", 0xFFC4000C, 32) { GP_INDT(0) } }, 2412 { PINMUX_DATA_REG("INDT1", 0xFFC4100C, 32) { GP_INDT(1) } }, 2413 { PINMUX_DATA_REG("INDT2", 0xFFC4200C, 32) { GP_INDT(2) } }, 2414 { PINMUX_DATA_REG("INDT3", 0xFFC4300C, 32) { GP_INDT(3) } }, 2415 { PINMUX_DATA_REG("INDT4", 0xFFC4400C, 32) { GP_INDT(4) } }, 2416 { PINMUX_DATA_REG("INDT5", 0xFFC4500C, 32) { 2417 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 2418 0, 0, 0, 0, 2419 GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, 2420 GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, 2421 GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } 2422 }, 2423 { }, 2424 }; 2425 2426 const struct sh_pfc_soc_info sh7734_pinmux_info = { 2427 .name = "sh7734_pfc", 2428 2429 .unlock_reg = 0xFFFC0000, 2430 2431 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, 2432 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, 2433 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, 2434 2435 .pins = pinmux_pins, 2436 .nr_pins = ARRAY_SIZE(pinmux_pins), 2437 .func_gpios = pinmux_func_gpios, 2438 .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios), 2439 2440 .cfg_regs = pinmux_config_regs, 2441 .data_regs = pinmux_data_regs, 2442 2443 .pinmux_data = pinmux_data, 2444 .pinmux_data_size = ARRAY_SIZE(pinmux_data), 2445 }; 2446
