1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef HABANALABS_H_ 9 #define HABANALABS_H_ 10 11 #include <linux/types.h> 12 #include <linux/ioctl.h> 13 14 /* 15 * Defines that are asic-specific but constitutes as ABI between kernel driver 16 * and userspace 17 */ 18 #define GOYA_KMD_SRAM_RESERVED_SIZE_FROM_START 0x8000 /* 32KB */ 19 #define GAUDI_DRIVER_SRAM_RESERVED_SIZE_FROM_START 0x80 /* 128 bytes */ 20 21 /* 22 * 128 SOBs reserved for collective wait 23 * 16 SOBs reserved for sync stream 24 */ 25 #define GAUDI_FIRST_AVAILABLE_W_S_SYNC_OBJECT 144 26 27 /* 28 * 64 monitors reserved for collective wait 29 * 8 monitors reserved for sync stream 30 */ 31 #define GAUDI_FIRST_AVAILABLE_W_S_MONITOR 72 32 33 /* 34 * Goya queue Numbering 35 * 36 * The external queues (PCI DMA channels) MUST be before the internal queues 37 * and each group (PCI DMA channels and internal) must be contiguous inside 38 * itself but there can be a gap between the two groups (although not 39 * recommended) 40 */ 41 42 enum goya_queue_id { 43 GOYA_QUEUE_ID_DMA_0 = 0, 44 GOYA_QUEUE_ID_DMA_1 = 1, 45 GOYA_QUEUE_ID_DMA_2 = 2, 46 GOYA_QUEUE_ID_DMA_3 = 3, 47 GOYA_QUEUE_ID_DMA_4 = 4, 48 GOYA_QUEUE_ID_CPU_PQ = 5, 49 GOYA_QUEUE_ID_MME = 6, /* Internal queues start here */ 50 GOYA_QUEUE_ID_TPC0 = 7, 51 GOYA_QUEUE_ID_TPC1 = 8, 52 GOYA_QUEUE_ID_TPC2 = 9, 53 GOYA_QUEUE_ID_TPC3 = 10, 54 GOYA_QUEUE_ID_TPC4 = 11, 55 GOYA_QUEUE_ID_TPC5 = 12, 56 GOYA_QUEUE_ID_TPC6 = 13, 57 GOYA_QUEUE_ID_TPC7 = 14, 58 GOYA_QUEUE_ID_SIZE 59 }; 60 61 /* 62 * Gaudi queue Numbering 63 * External queues (PCI DMA channels) are DMA_0_*, DMA_1_* and DMA_5_*. 64 * Except one CPU queue, all the rest are internal queues. 65 */ 66 67 enum gaudi_queue_id { 68 GAUDI_QUEUE_ID_DMA_0_0 = 0, /* external */ 69 GAUDI_QUEUE_ID_DMA_0_1 = 1, /* external */ 70 GAUDI_QUEUE_ID_DMA_0_2 = 2, /* external */ 71 GAUDI_QUEUE_ID_DMA_0_3 = 3, /* external */ 72 GAUDI_QUEUE_ID_DMA_1_0 = 4, /* external */ 73 GAUDI_QUEUE_ID_DMA_1_1 = 5, /* external */ 74 GAUDI_QUEUE_ID_DMA_1_2 = 6, /* external */ 75 GAUDI_QUEUE_ID_DMA_1_3 = 7, /* external */ 76 GAUDI_QUEUE_ID_CPU_PQ = 8, /* CPU */ 77 GAUDI_QUEUE_ID_DMA_2_0 = 9, /* internal */ 78 GAUDI_QUEUE_ID_DMA_2_1 = 10, /* internal */ 79 GAUDI_QUEUE_ID_DMA_2_2 = 11, /* internal */ 80 GAUDI_QUEUE_ID_DMA_2_3 = 12, /* internal */ 81 GAUDI_QUEUE_ID_DMA_3_0 = 13, /* internal */ 82 GAUDI_QUEUE_ID_DMA_3_1 = 14, /* internal */ 83 GAUDI_QUEUE_ID_DMA_3_2 = 15, /* internal */ 84 GAUDI_QUEUE_ID_DMA_3_3 = 16, /* internal */ 85 GAUDI_QUEUE_ID_DMA_4_0 = 17, /* internal */ 86 GAUDI_QUEUE_ID_DMA_4_1 = 18, /* internal */ 87 GAUDI_QUEUE_ID_DMA_4_2 = 19, /* internal */ 88 GAUDI_QUEUE_ID_DMA_4_3 = 20, /* internal */ 89 GAUDI_QUEUE_ID_DMA_5_0 = 21, /* internal */ 90 GAUDI_QUEUE_ID_DMA_5_1 = 22, /* internal */ 91 GAUDI_QUEUE_ID_DMA_5_2 = 23, /* internal */ 92 GAUDI_QUEUE_ID_DMA_5_3 = 24, /* internal */ 93 GAUDI_QUEUE_ID_DMA_6_0 = 25, /* internal */ 94 GAUDI_QUEUE_ID_DMA_6_1 = 26, /* internal */ 95 GAUDI_QUEUE_ID_DMA_6_2 = 27, /* internal */ 96 GAUDI_QUEUE_ID_DMA_6_3 = 28, /* internal */ 97 GAUDI_QUEUE_ID_DMA_7_0 = 29, /* internal */ 98 GAUDI_QUEUE_ID_DMA_7_1 = 30, /* internal */ 99 GAUDI_QUEUE_ID_DMA_7_2 = 31, /* internal */ 100 GAUDI_QUEUE_ID_DMA_7_3 = 32, /* internal */ 101 GAUDI_QUEUE_ID_MME_0_0 = 33, /* internal */ 102 GAUDI_QUEUE_ID_MME_0_1 = 34, /* internal */ 103 GAUDI_QUEUE_ID_MME_0_2 = 35, /* internal */ 104 GAUDI_QUEUE_ID_MME_0_3 = 36, /* internal */ 105 GAUDI_QUEUE_ID_MME_1_0 = 37, /* internal */ 106 GAUDI_QUEUE_ID_MME_1_1 = 38, /* internal */ 107 GAUDI_QUEUE_ID_MME_1_2 = 39, /* internal */ 108 GAUDI_QUEUE_ID_MME_1_3 = 40, /* internal */ 109 GAUDI_QUEUE_ID_TPC_0_0 = 41, /* internal */ 110 GAUDI_QUEUE_ID_TPC_0_1 = 42, /* internal */ 111 GAUDI_QUEUE_ID_TPC_0_2 = 43, /* internal */ 112 GAUDI_QUEUE_ID_TPC_0_3 = 44, /* internal */ 113 GAUDI_QUEUE_ID_TPC_1_0 = 45, /* internal */ 114 GAUDI_QUEUE_ID_TPC_1_1 = 46, /* internal */ 115 GAUDI_QUEUE_ID_TPC_1_2 = 47, /* internal */ 116 GAUDI_QUEUE_ID_TPC_1_3 = 48, /* internal */ 117 GAUDI_QUEUE_ID_TPC_2_0 = 49, /* internal */ 118 GAUDI_QUEUE_ID_TPC_2_1 = 50, /* internal */ 119 GAUDI_QUEUE_ID_TPC_2_2 = 51, /* internal */ 120 GAUDI_QUEUE_ID_TPC_2_3 = 52, /* internal */ 121 GAUDI_QUEUE_ID_TPC_3_0 = 53, /* internal */ 122 GAUDI_QUEUE_ID_TPC_3_1 = 54, /* internal */ 123 GAUDI_QUEUE_ID_TPC_3_2 = 55, /* internal */ 124 GAUDI_QUEUE_ID_TPC_3_3 = 56, /* internal */ 125 GAUDI_QUEUE_ID_TPC_4_0 = 57, /* internal */ 126 GAUDI_QUEUE_ID_TPC_4_1 = 58, /* internal */ 127 GAUDI_QUEUE_ID_TPC_4_2 = 59, /* internal */ 128 GAUDI_QUEUE_ID_TPC_4_3 = 60, /* internal */ 129 GAUDI_QUEUE_ID_TPC_5_0 = 61, /* internal */ 130 GAUDI_QUEUE_ID_TPC_5_1 = 62, /* internal */ 131 GAUDI_QUEUE_ID_TPC_5_2 = 63, /* internal */ 132 GAUDI_QUEUE_ID_TPC_5_3 = 64, /* internal */ 133 GAUDI_QUEUE_ID_TPC_6_0 = 65, /* internal */ 134 GAUDI_QUEUE_ID_TPC_6_1 = 66, /* internal */ 135 GAUDI_QUEUE_ID_TPC_6_2 = 67, /* internal */ 136 GAUDI_QUEUE_ID_TPC_6_3 = 68, /* internal */ 137 GAUDI_QUEUE_ID_TPC_7_0 = 69, /* internal */ 138 GAUDI_QUEUE_ID_TPC_7_1 = 70, /* internal */ 139 GAUDI_QUEUE_ID_TPC_7_2 = 71, /* internal */ 140 GAUDI_QUEUE_ID_TPC_7_3 = 72, /* internal */ 141 GAUDI_QUEUE_ID_NIC_0_0 = 73, /* internal */ 142 GAUDI_QUEUE_ID_NIC_0_1 = 74, /* internal */ 143 GAUDI_QUEUE_ID_NIC_0_2 = 75, /* internal */ 144 GAUDI_QUEUE_ID_NIC_0_3 = 76, /* internal */ 145 GAUDI_QUEUE_ID_NIC_1_0 = 77, /* internal */ 146 GAUDI_QUEUE_ID_NIC_1_1 = 78, /* internal */ 147 GAUDI_QUEUE_ID_NIC_1_2 = 79, /* internal */ 148 GAUDI_QUEUE_ID_NIC_1_3 = 80, /* internal */ 149 GAUDI_QUEUE_ID_NIC_2_0 = 81, /* internal */ 150 GAUDI_QUEUE_ID_NIC_2_1 = 82, /* internal */ 151 GAUDI_QUEUE_ID_NIC_2_2 = 83, /* internal */ 152 GAUDI_QUEUE_ID_NIC_2_3 = 84, /* internal */ 153 GAUDI_QUEUE_ID_NIC_3_0 = 85, /* internal */ 154 GAUDI_QUEUE_ID_NIC_3_1 = 86, /* internal */ 155 GAUDI_QUEUE_ID_NIC_3_2 = 87, /* internal */ 156 GAUDI_QUEUE_ID_NIC_3_3 = 88, /* internal */ 157 GAUDI_QUEUE_ID_NIC_4_0 = 89, /* internal */ 158 GAUDI_QUEUE_ID_NIC_4_1 = 90, /* internal */ 159 GAUDI_QUEUE_ID_NIC_4_2 = 91, /* internal */ 160 GAUDI_QUEUE_ID_NIC_4_3 = 92, /* internal */ 161 GAUDI_QUEUE_ID_NIC_5_0 = 93, /* internal */ 162 GAUDI_QUEUE_ID_NIC_5_1 = 94, /* internal */ 163 GAUDI_QUEUE_ID_NIC_5_2 = 95, /* internal */ 164 GAUDI_QUEUE_ID_NIC_5_3 = 96, /* internal */ 165 GAUDI_QUEUE_ID_NIC_6_0 = 97, /* internal */ 166 GAUDI_QUEUE_ID_NIC_6_1 = 98, /* internal */ 167 GAUDI_QUEUE_ID_NIC_6_2 = 99, /* internal */ 168 GAUDI_QUEUE_ID_NIC_6_3 = 100, /* internal */ 169 GAUDI_QUEUE_ID_NIC_7_0 = 101, /* internal */ 170 GAUDI_QUEUE_ID_NIC_7_1 = 102, /* internal */ 171 GAUDI_QUEUE_ID_NIC_7_2 = 103, /* internal */ 172 GAUDI_QUEUE_ID_NIC_7_3 = 104, /* internal */ 173 GAUDI_QUEUE_ID_NIC_8_0 = 105, /* internal */ 174 GAUDI_QUEUE_ID_NIC_8_1 = 106, /* internal */ 175 GAUDI_QUEUE_ID_NIC_8_2 = 107, /* internal */ 176 GAUDI_QUEUE_ID_NIC_8_3 = 108, /* internal */ 177 GAUDI_QUEUE_ID_NIC_9_0 = 109, /* internal */ 178 GAUDI_QUEUE_ID_NIC_9_1 = 110, /* internal */ 179 GAUDI_QUEUE_ID_NIC_9_2 = 111, /* internal */ 180 GAUDI_QUEUE_ID_NIC_9_3 = 112, /* internal */ 181 GAUDI_QUEUE_ID_SIZE 182 }; 183 184 /* 185 * Engine Numbering 186 * 187 * Used in the "busy_engines_mask" field in `struct hl_info_hw_idle' 188 */ 189 190 enum goya_engine_id { 191 GOYA_ENGINE_ID_DMA_0 = 0, 192 GOYA_ENGINE_ID_DMA_1, 193 GOYA_ENGINE_ID_DMA_2, 194 GOYA_ENGINE_ID_DMA_3, 195 GOYA_ENGINE_ID_DMA_4, 196 GOYA_ENGINE_ID_MME_0, 197 GOYA_ENGINE_ID_TPC_0, 198 GOYA_ENGINE_ID_TPC_1, 199 GOYA_ENGINE_ID_TPC_2, 200 GOYA_ENGINE_ID_TPC_3, 201 GOYA_ENGINE_ID_TPC_4, 202 GOYA_ENGINE_ID_TPC_5, 203 GOYA_ENGINE_ID_TPC_6, 204 GOYA_ENGINE_ID_TPC_7, 205 GOYA_ENGINE_ID_SIZE 206 }; 207 208 enum gaudi_engine_id { 209 GAUDI_ENGINE_ID_DMA_0 = 0, 210 GAUDI_ENGINE_ID_DMA_1, 211 GAUDI_ENGINE_ID_DMA_2, 212 GAUDI_ENGINE_ID_DMA_3, 213 GAUDI_ENGINE_ID_DMA_4, 214 GAUDI_ENGINE_ID_DMA_5, 215 GAUDI_ENGINE_ID_DMA_6, 216 GAUDI_ENGINE_ID_DMA_7, 217 GAUDI_ENGINE_ID_MME_0, 218 GAUDI_ENGINE_ID_MME_1, 219 GAUDI_ENGINE_ID_MME_2, 220 GAUDI_ENGINE_ID_MME_3, 221 GAUDI_ENGINE_ID_TPC_0, 222 GAUDI_ENGINE_ID_TPC_1, 223 GAUDI_ENGINE_ID_TPC_2, 224 GAUDI_ENGINE_ID_TPC_3, 225 GAUDI_ENGINE_ID_TPC_4, 226 GAUDI_ENGINE_ID_TPC_5, 227 GAUDI_ENGINE_ID_TPC_6, 228 GAUDI_ENGINE_ID_TPC_7, 229 GAUDI_ENGINE_ID_NIC_0, 230 GAUDI_ENGINE_ID_NIC_1, 231 GAUDI_ENGINE_ID_NIC_2, 232 GAUDI_ENGINE_ID_NIC_3, 233 GAUDI_ENGINE_ID_NIC_4, 234 GAUDI_ENGINE_ID_NIC_5, 235 GAUDI_ENGINE_ID_NIC_6, 236 GAUDI_ENGINE_ID_NIC_7, 237 GAUDI_ENGINE_ID_NIC_8, 238 GAUDI_ENGINE_ID_NIC_9, 239 GAUDI_ENGINE_ID_SIZE 240 }; 241 242 /* 243 * ASIC specific PLL index 244 * 245 * Used to retrieve in frequency info of different IPs via 246 * HL_INFO_PLL_FREQUENCY under HL_IOCTL_INFO IOCTL. The enums need to be 247 * used as an index in struct hl_pll_frequency_info 248 */ 249 250 enum hl_goya_pll_index { 251 HL_GOYA_CPU_PLL = 0, 252 HL_GOYA_IC_PLL, 253 HL_GOYA_MC_PLL, 254 HL_GOYA_MME_PLL, 255 HL_GOYA_PCI_PLL, 256 HL_GOYA_EMMC_PLL, 257 HL_GOYA_TPC_PLL, 258 HL_GOYA_PLL_MAX 259 }; 260 261 enum hl_gaudi_pll_index { 262 HL_GAUDI_CPU_PLL = 0, 263 HL_GAUDI_PCI_PLL, 264 HL_GAUDI_SRAM_PLL, 265 HL_GAUDI_HBM_PLL, 266 HL_GAUDI_NIC_PLL, 267 HL_GAUDI_DMA_PLL, 268 HL_GAUDI_MESH_PLL, 269 HL_GAUDI_MME_PLL, 270 HL_GAUDI_TPC_PLL, 271 HL_GAUDI_IF_PLL, 272 HL_GAUDI_PLL_MAX 273 }; 274 275 enum hl_device_status { 276 HL_DEVICE_STATUS_OPERATIONAL, 277 HL_DEVICE_STATUS_IN_RESET, 278 HL_DEVICE_STATUS_MALFUNCTION, 279 HL_DEVICE_STATUS_NEEDS_RESET, 280 HL_DEVICE_STATUS_IN_DEVICE_CREATION, 281 HL_DEVICE_STATUS_LAST = HL_DEVICE_STATUS_IN_DEVICE_CREATION 282 }; 283 284 enum hl_server_type { 285 HL_SERVER_TYPE_UNKNOWN = 0, 286 HL_SERVER_GAUDI_HLS1 = 1, 287 HL_SERVER_GAUDI_HLS1H = 2, 288 HL_SERVER_GAUDI_TYPE1 = 3, 289 HL_SERVER_GAUDI_TYPE2 = 4 290 }; 291 292 /* Opcode for management ioctl 293 * 294 * HW_IP_INFO - Receive information about different IP blocks in the 295 * device. 296 * HL_INFO_HW_EVENTS - Receive an array describing how many times each event 297 * occurred since the last hard reset. 298 * HL_INFO_DRAM_USAGE - Retrieve the dram usage inside the device and of the 299 * specific context. This is relevant only for devices 300 * where the dram is managed by the kernel driver 301 * HL_INFO_HW_IDLE - Retrieve information about the idle status of each 302 * internal engine. 303 * HL_INFO_DEVICE_STATUS - Retrieve the device's status. This opcode doesn't 304 * require an open context. 305 * HL_INFO_DEVICE_UTILIZATION - Retrieve the total utilization of the device 306 * over the last period specified by the user. 307 * The period can be between 100ms to 1s, in 308 * resolution of 100ms. The return value is a 309 * percentage of the utilization rate. 310 * HL_INFO_HW_EVENTS_AGGREGATE - Receive an array describing how many times each 311 * event occurred since the driver was loaded. 312 * HL_INFO_CLK_RATE - Retrieve the current and maximum clock rate 313 * of the device in MHz. The maximum clock rate is 314 * configurable via sysfs parameter 315 * HL_INFO_RESET_COUNT - Retrieve the counts of the soft and hard reset 316 * operations performed on the device since the last 317 * time the driver was loaded. 318 * HL_INFO_TIME_SYNC - Retrieve the device's time alongside the host's time 319 * for synchronization. 320 * HL_INFO_CS_COUNTERS - Retrieve command submission counters 321 * HL_INFO_PCI_COUNTERS - Retrieve PCI counters 322 * HL_INFO_CLK_THROTTLE_REASON - Retrieve clock throttling reason 323 * HL_INFO_SYNC_MANAGER - Retrieve sync manager info per dcore 324 * HL_INFO_TOTAL_ENERGY - Retrieve total energy consumption 325 * HL_INFO_PLL_FREQUENCY - Retrieve PLL frequency 326 * HL_INFO_OPEN_STATS - Retrieve info regarding recent device open calls 327 */ 328 #define HL_INFO_HW_IP_INFO 0 329 #define HL_INFO_HW_EVENTS 1 330 #define HL_INFO_DRAM_USAGE 2 331 #define HL_INFO_HW_IDLE 3 332 #define HL_INFO_DEVICE_STATUS 4 333 #define HL_INFO_DEVICE_UTILIZATION 6 334 #define HL_INFO_HW_EVENTS_AGGREGATE 7 335 #define HL_INFO_CLK_RATE 8 336 #define HL_INFO_RESET_COUNT 9 337 #define HL_INFO_TIME_SYNC 10 338 #define HL_INFO_CS_COUNTERS 11 339 #define HL_INFO_PCI_COUNTERS 12 340 #define HL_INFO_CLK_THROTTLE_REASON 13 341 #define HL_INFO_SYNC_MANAGER 14 342 #define HL_INFO_TOTAL_ENERGY 15 343 #define HL_INFO_PLL_FREQUENCY 16 344 #define HL_INFO_POWER 17 345 #define HL_INFO_OPEN_STATS 18 346 347 #define HL_INFO_VERSION_MAX_LEN 128 348 #define HL_INFO_CARD_NAME_MAX_LEN 16 349 350 /** 351 * struct hl_info_hw_ip_info - hardware information on various IPs in the ASIC 352 * @sram_base_address: The first SRAM physical base address that is free to be 353 * used by the user. 354 * @dram_base_address: The first DRAM virtual or physical base address that is 355 * free to be used by the user. 356 * @dram_size: The DRAM size that is available to the user. 357 * @sram_size: The SRAM size that is available to the user. 358 * @num_of_events: The number of events that can be received from the f/w. This 359 * is needed so the user can what is the size of the h/w events 360 * array he needs to pass to the kernel when he wants to fetch 361 * the event counters. 362 * @device_id: PCI device ID of the ASIC. 363 * @module_id: Module ID of the ASIC for mezzanine cards in servers 364 * (From OCP spec). 365 * @first_available_interrupt_id: The first available interrupt ID for the user 366 * to be used when it works with user interrupts. 367 * @server_type: Server type that the Gaudi ASIC is currently installed in. 368 * The value is according to enum hl_server_type 369 * @cpld_version: CPLD version on the board. 370 * @psoc_pci_pll_nr: PCI PLL NR value. Needed by the profiler in some ASICs. 371 * @psoc_pci_pll_nf: PCI PLL NF value. Needed by the profiler in some ASICs. 372 * @psoc_pci_pll_od: PCI PLL OD value. Needed by the profiler in some ASICs. 373 * @psoc_pci_pll_div_factor: PCI PLL DIV factor value. Needed by the profiler 374 * in some ASICs. 375 * @tpc_enabled_mask: Bit-mask that represents which TPCs are enabled. Relevant 376 * for Goya/Gaudi only. 377 * @dram_enabled: Whether the DRAM is enabled. 378 * @cpucp_version: The CPUCP f/w version. 379 * @card_name: The card name as passed by the f/w. 380 * @dram_page_size: The DRAM physical page size. 381 */ 382 struct hl_info_hw_ip_info { 383 __u64 sram_base_address; 384 __u64 dram_base_address; 385 __u64 dram_size; 386 __u32 sram_size; 387 __u32 num_of_events; 388 __u32 device_id; 389 __u32 module_id; 390 __u32 reserved; 391 __u16 first_available_interrupt_id; 392 __u16 server_type; 393 __u32 cpld_version; 394 __u32 psoc_pci_pll_nr; 395 __u32 psoc_pci_pll_nf; 396 __u32 psoc_pci_pll_od; 397 __u32 psoc_pci_pll_div_factor; 398 __u8 tpc_enabled_mask; 399 __u8 dram_enabled; 400 __u8 pad[2]; 401 __u8 cpucp_version[HL_INFO_VERSION_MAX_LEN]; 402 __u8 card_name[HL_INFO_CARD_NAME_MAX_LEN]; 403 __u64 reserved2; 404 __u64 dram_page_size; 405 }; 406 407 struct hl_info_dram_usage { 408 __u64 dram_free_mem; 409 __u64 ctx_dram_mem; 410 }; 411 412 #define HL_BUSY_ENGINES_MASK_EXT_SIZE 2 413 414 struct hl_info_hw_idle { 415 __u32 is_idle; 416 /* 417 * Bitmask of busy engines. 418 * Bits definition is according to `enum <chip>_enging_id'. 419 */ 420 __u32 busy_engines_mask; 421 422 /* 423 * Extended Bitmask of busy engines. 424 * Bits definition is according to `enum <chip>_enging_id'. 425 */ 426 __u64 busy_engines_mask_ext[HL_BUSY_ENGINES_MASK_EXT_SIZE]; 427 }; 428 429 struct hl_info_device_status { 430 __u32 status; 431 __u32 pad; 432 }; 433 434 struct hl_info_device_utilization { 435 __u32 utilization; 436 __u32 pad; 437 }; 438 439 struct hl_info_clk_rate { 440 __u32 cur_clk_rate_mhz; 441 __u32 max_clk_rate_mhz; 442 }; 443 444 struct hl_info_reset_count { 445 __u32 hard_reset_cnt; 446 __u32 soft_reset_cnt; 447 }; 448 449 struct hl_info_time_sync { 450 __u64 device_time; 451 __u64 host_time; 452 }; 453 454 /** 455 * struct hl_info_pci_counters - pci counters 456 * @rx_throughput: PCI rx throughput KBps 457 * @tx_throughput: PCI tx throughput KBps 458 * @replay_cnt: PCI replay counter 459 */ 460 struct hl_info_pci_counters { 461 __u64 rx_throughput; 462 __u64 tx_throughput; 463 __u64 replay_cnt; 464 }; 465 466 #define HL_CLK_THROTTLE_POWER 0x1 467 #define HL_CLK_THROTTLE_THERMAL 0x2 468 469 /** 470 * struct hl_info_clk_throttle - clock throttling reason 471 * @clk_throttling_reason: each bit represents a clk throttling reason 472 */ 473 struct hl_info_clk_throttle { 474 __u32 clk_throttling_reason; 475 }; 476 477 /** 478 * struct hl_info_energy - device energy information 479 * @total_energy_consumption: total device energy consumption 480 */ 481 struct hl_info_energy { 482 __u64 total_energy_consumption; 483 }; 484 485 #define HL_PLL_NUM_OUTPUTS 4 486 487 struct hl_pll_frequency_info { 488 __u16 output[HL_PLL_NUM_OUTPUTS]; 489 }; 490 491 /** 492 * struct hl_open_stats_info - device open statistics information 493 * @open_counter: ever growing counter, increased on each successful dev open 494 * @last_open_period_ms: duration (ms) device was open last time 495 */ 496 struct hl_open_stats_info { 497 __u64 open_counter; 498 __u64 last_open_period_ms; 499 }; 500 501 /** 502 * struct hl_power_info - power information 503 * @power: power consumption 504 */ 505 struct hl_power_info { 506 __u64 power; 507 }; 508 509 /** 510 * struct hl_info_sync_manager - sync manager information 511 * @first_available_sync_object: first available sob 512 * @first_available_monitor: first available monitor 513 * @first_available_cq: first available cq 514 */ 515 struct hl_info_sync_manager { 516 __u32 first_available_sync_object; 517 __u32 first_available_monitor; 518 __u32 first_available_cq; 519 __u32 reserved; 520 }; 521 522 /** 523 * struct hl_info_cs_counters - command submission counters 524 * @total_out_of_mem_drop_cnt: total dropped due to memory allocation issue 525 * @ctx_out_of_mem_drop_cnt: context dropped due to memory allocation issue 526 * @total_parsing_drop_cnt: total dropped due to error in packet parsing 527 * @ctx_parsing_drop_cnt: context dropped due to error in packet parsing 528 * @total_queue_full_drop_cnt: total dropped due to queue full 529 * @ctx_queue_full_drop_cnt: context dropped due to queue full 530 * @total_device_in_reset_drop_cnt: total dropped due to device in reset 531 * @ctx_device_in_reset_drop_cnt: context dropped due to device in reset 532 * @total_max_cs_in_flight_drop_cnt: total dropped due to maximum CS in-flight 533 * @ctx_max_cs_in_flight_drop_cnt: context dropped due to maximum CS in-flight 534 * @total_validation_drop_cnt: total dropped due to validation error 535 * @ctx_validation_drop_cnt: context dropped due to validation error 536 */ 537 struct hl_info_cs_counters { 538 __u64 total_out_of_mem_drop_cnt; 539 __u64 ctx_out_of_mem_drop_cnt; 540 __u64 total_parsing_drop_cnt; 541 __u64 ctx_parsing_drop_cnt; 542 __u64 total_queue_full_drop_cnt; 543 __u64 ctx_queue_full_drop_cnt; 544 __u64 total_device_in_reset_drop_cnt; 545 __u64 ctx_device_in_reset_drop_cnt; 546 __u64 total_max_cs_in_flight_drop_cnt; 547 __u64 ctx_max_cs_in_flight_drop_cnt; 548 __u64 total_validation_drop_cnt; 549 __u64 ctx_validation_drop_cnt; 550 }; 551 552 enum gaudi_dcores { 553 HL_GAUDI_WS_DCORE, 554 HL_GAUDI_WN_DCORE, 555 HL_GAUDI_EN_DCORE, 556 HL_GAUDI_ES_DCORE 557 }; 558 559 struct hl_info_args { 560 /* Location of relevant struct in userspace */ 561 __u64 return_pointer; 562 /* 563 * The size of the return value. Just like "size" in "snprintf", 564 * it limits how many bytes the kernel can write 565 * 566 * For hw_events array, the size should be 567 * hl_info_hw_ip_info.num_of_events * sizeof(__u32) 568 */ 569 __u32 return_size; 570 571 /* HL_INFO_* */ 572 __u32 op; 573 574 union { 575 /* Dcore id for which the information is relevant. 576 * For Gaudi refer to 'enum gaudi_dcores' 577 */ 578 __u32 dcore_id; 579 /* Context ID - Currently not in use */ 580 __u32 ctx_id; 581 /* Period value for utilization rate (100ms - 1000ms, in 100ms 582 * resolution. 583 */ 584 __u32 period_ms; 585 /* PLL frequency retrieval */ 586 __u32 pll_index; 587 }; 588 589 __u32 pad; 590 }; 591 592 /* Opcode to create a new command buffer */ 593 #define HL_CB_OP_CREATE 0 594 /* Opcode to destroy previously created command buffer */ 595 #define HL_CB_OP_DESTROY 1 596 /* Opcode to retrieve information about a command buffer */ 597 #define HL_CB_OP_INFO 2 598 599 /* 2MB minus 32 bytes for 2xMSG_PROT */ 600 #define HL_MAX_CB_SIZE (0x200000 - 32) 601 602 /* Indicates whether the command buffer should be mapped to the device's MMU */ 603 #define HL_CB_FLAGS_MAP 0x1 604 605 struct hl_cb_in { 606 /* Handle of CB or 0 if we want to create one */ 607 __u64 cb_handle; 608 /* HL_CB_OP_* */ 609 __u32 op; 610 /* Size of CB. Maximum size is HL_MAX_CB_SIZE. The minimum size that 611 * will be allocated, regardless of this parameter's value, is PAGE_SIZE 612 */ 613 __u32 cb_size; 614 /* Context ID - Currently not in use */ 615 __u32 ctx_id; 616 /* HL_CB_FLAGS_* */ 617 __u32 flags; 618 }; 619 620 struct hl_cb_out { 621 union { 622 /* Handle of CB */ 623 __u64 cb_handle; 624 625 /* Information about CB */ 626 struct { 627 /* Usage count of CB */ 628 __u32 usage_cnt; 629 __u32 pad; 630 }; 631 }; 632 }; 633 634 union hl_cb_args { 635 struct hl_cb_in in; 636 struct hl_cb_out out; 637 }; 638 639 /* HL_CS_CHUNK_FLAGS_ values 640 * 641 * HL_CS_CHUNK_FLAGS_USER_ALLOC_CB: 642 * Indicates if the CB was allocated and mapped by userspace. 643 * User allocated CB is a command buffer allocated by the user, via malloc 644 * (or similar). After allocating the CB, the user invokes “memory ioctl” 645 * to map the user memory into a device virtual address. The user provides 646 * this address via the cb_handle field. The interface provides the 647 * ability to create a large CBs, Which aren’t limited to 648 * “HL_MAX_CB_SIZE”. Therefore, it increases the PCI-DMA queues 649 * throughput. This CB allocation method also reduces the use of Linux 650 * DMA-able memory pool. Which are limited and used by other Linux 651 * sub-systems. 652 */ 653 #define HL_CS_CHUNK_FLAGS_USER_ALLOC_CB 0x1 654 655 /* 656 * This structure size must always be fixed to 64-bytes for backward 657 * compatibility 658 */ 659 struct hl_cs_chunk { 660 union { 661 /* For external queue, this represents a Handle of CB on the 662 * Host. 663 * For internal queue in Goya, this represents an SRAM or 664 * a DRAM address of the internal CB. In Gaudi, this might also 665 * represent a mapped host address of the CB. 666 * 667 * A mapped host address is in the device address space, after 668 * a host address was mapped by the device MMU. 669 */ 670 __u64 cb_handle; 671 672 /* Relevant only when HL_CS_FLAGS_WAIT or 673 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 674 * This holds address of array of u64 values that contain 675 * signal CS sequence numbers. The wait described by 676 * this job will listen on all those signals 677 * (wait event per signal) 678 */ 679 __u64 signal_seq_arr; 680 681 /* 682 * Relevant only when HL_CS_FLAGS_WAIT or 683 * HL_CS_FLAGS_COLLECTIVE_WAIT is set 684 * along with HL_CS_FLAGS_ENCAP_SIGNALS. 685 * This is the CS sequence which has the encapsulated signals. 686 */ 687 __u64 encaps_signal_seq; 688 }; 689 690 /* Index of queue to put the CB on */ 691 __u32 queue_index; 692 693 union { 694 /* 695 * Size of command buffer with valid packets 696 * Can be smaller then actual CB size 697 */ 698 __u32 cb_size; 699 700 /* Relevant only when HL_CS_FLAGS_WAIT or 701 * HL_CS_FLAGS_COLLECTIVE_WAIT is set. 702 * Number of entries in signal_seq_arr 703 */ 704 __u32 num_signal_seq_arr; 705 706 /* Relevant only when HL_CS_FLAGS_WAIT or 707 * HL_CS_FLAGS_COLLECTIVE_WAIT is set along 708 * with HL_CS_FLAGS_ENCAP_SIGNALS 709 * This set the signals range that the user want to wait for 710 * out of the whole reserved signals range. 711 * e.g if the signals range is 20, and user don't want 712 * to wait for signal 8, so he set this offset to 7, then 713 * he call the API again with 9 and so on till 20. 714 */ 715 __u32 encaps_signal_offset; 716 }; 717 718 /* HL_CS_CHUNK_FLAGS_* */ 719 __u32 cs_chunk_flags; 720 721 /* Relevant only when HL_CS_FLAGS_COLLECTIVE_WAIT is set. 722 * This holds the collective engine ID. The wait described by this job 723 * will sync with this engine and with all NICs before completion. 724 */ 725 __u32 collective_engine_id; 726 727 /* Align structure to 64 bytes */ 728 __u32 pad[10]; 729 }; 730 731 /* SIGNAL and WAIT/COLLECTIVE_WAIT flags are mutually exclusive */ 732 #define HL_CS_FLAGS_FORCE_RESTORE 0x1 733 #define HL_CS_FLAGS_SIGNAL 0x2 734 #define HL_CS_FLAGS_WAIT 0x4 735 #define HL_CS_FLAGS_COLLECTIVE_WAIT 0x8 736 #define HL_CS_FLAGS_TIMESTAMP 0x20 737 #define HL_CS_FLAGS_STAGED_SUBMISSION 0x40 738 #define HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 0x80 739 #define HL_CS_FLAGS_STAGED_SUBMISSION_LAST 0x100 740 #define HL_CS_FLAGS_CUSTOM_TIMEOUT 0x200 741 #define HL_CS_FLAGS_SKIP_RESET_ON_TIMEOUT 0x400 742 743 /* 744 * The encapsulated signals CS is merged into the existing CS ioctls. 745 * In order to use this feature need to follow the below procedure: 746 * 1. Reserve signals, set the CS type to HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 747 * the output of this API will be the SOB offset from CFG_BASE. 748 * this address will be used to patch CB cmds to do the signaling for this 749 * SOB by incrementing it's value. 750 * for reverting the reservation use HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 751 * CS type, note that this might fail if out-of-sync happened to the SOB 752 * value, in case other signaling request to the same SOB occurred between 753 * reserve-unreserve calls. 754 * 2. Use the staged CS to do the encapsulated signaling jobs. 755 * use HL_CS_FLAGS_STAGED_SUBMISSION and HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 756 * along with HL_CS_FLAGS_ENCAP_SIGNALS flag, and set encaps_signal_offset 757 * field. This offset allows app to wait on part of the reserved signals. 758 * 3. Use WAIT/COLLECTIVE WAIT CS along with HL_CS_FLAGS_ENCAP_SIGNALS flag 759 * to wait for the encapsulated signals. 760 */ 761 #define HL_CS_FLAGS_ENCAP_SIGNALS 0x800 762 #define HL_CS_FLAGS_RESERVE_SIGNALS_ONLY 0x1000 763 #define HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY 0x2000 764 765 #define HL_CS_STATUS_SUCCESS 0 766 767 #define HL_MAX_JOBS_PER_CS 512 768 769 struct hl_cs_in { 770 771 /* this holds address of array of hl_cs_chunk for restore phase */ 772 __u64 chunks_restore; 773 774 /* holds address of array of hl_cs_chunk for execution phase */ 775 __u64 chunks_execute; 776 777 union { 778 /* 779 * Sequence number of a staged submission CS 780 * valid only if HL_CS_FLAGS_STAGED_SUBMISSION is set and 781 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST is unset. 782 */ 783 __u64 seq; 784 785 /* 786 * Encapsulated signals handle id 787 * Valid for two flows: 788 * 1. CS with encapsulated signals: 789 * when HL_CS_FLAGS_STAGED_SUBMISSION and 790 * HL_CS_FLAGS_STAGED_SUBMISSION_FIRST 791 * and HL_CS_FLAGS_ENCAP_SIGNALS are set. 792 * 2. unreserve signals: 793 * valid when HL_CS_FLAGS_UNRESERVE_SIGNALS_ONLY is set. 794 */ 795 __u32 encaps_sig_handle_id; 796 797 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 798 struct { 799 /* Encapsulated signals number */ 800 __u32 encaps_signals_count; 801 802 /* Encapsulated signals queue index (stream) */ 803 __u32 encaps_signals_q_idx; 804 }; 805 }; 806 807 /* Number of chunks in restore phase array. Maximum number is 808 * HL_MAX_JOBS_PER_CS 809 */ 810 __u32 num_chunks_restore; 811 812 /* Number of chunks in execution array. Maximum number is 813 * HL_MAX_JOBS_PER_CS 814 */ 815 __u32 num_chunks_execute; 816 817 /* timeout in seconds - valid only if HL_CS_FLAGS_CUSTOM_TIMEOUT 818 * is set 819 */ 820 __u32 timeout; 821 822 /* HL_CS_FLAGS_* */ 823 __u32 cs_flags; 824 825 /* Context ID - Currently not in use */ 826 __u32 ctx_id; 827 }; 828 829 struct hl_cs_out { 830 union { 831 /* 832 * seq holds the sequence number of the CS to pass to wait 833 * ioctl. All values are valid except for 0 and ULLONG_MAX 834 */ 835 __u64 seq; 836 837 /* Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set */ 838 struct { 839 /* This is the resereved signal handle id */ 840 __u32 handle_id; 841 842 /* This is the signals count */ 843 __u32 count; 844 }; 845 }; 846 847 /* HL_CS_STATUS */ 848 __u32 status; 849 850 /* 851 * SOB base address offset 852 * Valid only when HL_CS_FLAGS_RESERVE_SIGNALS_ONLY is set 853 */ 854 __u32 sob_base_addr_offset; 855 }; 856 857 union hl_cs_args { 858 struct hl_cs_in in; 859 struct hl_cs_out out; 860 }; 861 862 #define HL_WAIT_CS_FLAGS_INTERRUPT 0x2 863 #define HL_WAIT_CS_FLAGS_INTERRUPT_MASK 0xFFF00000 864 #define HL_WAIT_CS_FLAGS_MULTI_CS 0x4 865 866 #define HL_WAIT_MULTI_CS_LIST_MAX_LEN 32 867 868 struct hl_wait_cs_in { 869 union { 870 struct { 871 /* 872 * In case of wait_cs holds the CS sequence number. 873 * In case of wait for multi CS hold a user pointer to 874 * an array of CS sequence numbers 875 */ 876 __u64 seq; 877 /* Absolute timeout to wait for command submission 878 * in microseconds 879 */ 880 __u64 timeout_us; 881 }; 882 883 struct { 884 /* User address for completion comparison. 885 * upon interrupt, driver will compare the value pointed 886 * by this address with the supplied target value. 887 * in order not to perform any comparison, set address 888 * to all 1s. 889 * Relevant only when HL_WAIT_CS_FLAGS_INTERRUPT is set 890 */ 891 __u64 addr; 892 /* Target value for completion comparison */ 893 __u32 target; 894 /* Absolute timeout to wait for interrupt 895 * in microseconds 896 */ 897 __u32 interrupt_timeout_us; 898 }; 899 }; 900 901 /* Context ID - Currently not in use */ 902 __u32 ctx_id; 903 904 /* HL_WAIT_CS_FLAGS_* 905 * If HL_WAIT_CS_FLAGS_INTERRUPT is set, this field should include 906 * interrupt id according to HL_WAIT_CS_FLAGS_INTERRUPT_MASK, in order 907 * not to specify an interrupt id ,set mask to all 1s. 908 */ 909 __u32 flags; 910 911 /* Multi CS API info- valid entries in multi-CS array */ 912 __u8 seq_arr_len; 913 __u8 pad[7]; 914 }; 915 916 #define HL_WAIT_CS_STATUS_COMPLETED 0 917 #define HL_WAIT_CS_STATUS_BUSY 1 918 #define HL_WAIT_CS_STATUS_TIMEDOUT 2 919 #define HL_WAIT_CS_STATUS_ABORTED 3 920 921 #define HL_WAIT_CS_STATUS_FLAG_GONE 0x1 922 #define HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD 0x2 923 924 struct hl_wait_cs_out { 925 /* HL_WAIT_CS_STATUS_* */ 926 __u32 status; 927 /* HL_WAIT_CS_STATUS_FLAG* */ 928 __u32 flags; 929 /* 930 * valid only if HL_WAIT_CS_STATUS_FLAG_TIMESTAMP_VLD is set 931 * for wait_cs: timestamp of CS completion 932 * for wait_multi_cs: timestamp of FIRST CS completion 933 */ 934 __s64 timestamp_nsec; 935 /* multi CS completion bitmap */ 936 __u32 cs_completion_map; 937 __u32 pad; 938 }; 939 940 union hl_wait_cs_args { 941 struct hl_wait_cs_in in; 942 struct hl_wait_cs_out out; 943 }; 944 945 /* Opcode to allocate device memory */ 946 #define HL_MEM_OP_ALLOC 0 947 /* Opcode to free previously allocated device memory */ 948 #define HL_MEM_OP_FREE 1 949 /* Opcode to map host and device memory */ 950 #define HL_MEM_OP_MAP 2 951 /* Opcode to unmap previously mapped host and device memory */ 952 #define HL_MEM_OP_UNMAP 3 953 /* Opcode to map a hw block */ 954 #define HL_MEM_OP_MAP_BLOCK 4 955 956 /* Memory flags */ 957 #define HL_MEM_CONTIGUOUS 0x1 958 #define HL_MEM_SHARED 0x2 959 #define HL_MEM_USERPTR 0x4 960 #define HL_MEM_FORCE_HINT 0x8 961 962 struct hl_mem_in { 963 union { 964 /* HL_MEM_OP_ALLOC- allocate device memory */ 965 struct { 966 /* Size to alloc */ 967 __u64 mem_size; 968 } alloc; 969 970 /* HL_MEM_OP_FREE - free device memory */ 971 struct { 972 /* Handle returned from HL_MEM_OP_ALLOC */ 973 __u64 handle; 974 } free; 975 976 /* HL_MEM_OP_MAP - map device memory */ 977 struct { 978 /* 979 * Requested virtual address of mapped memory. 980 * The driver will try to map the requested region to 981 * this hint address, as long as the address is valid 982 * and not already mapped. The user should check the 983 * returned address of the IOCTL to make sure he got 984 * the hint address. Passing 0 here means that the 985 * driver will choose the address itself. 986 */ 987 __u64 hint_addr; 988 /* Handle returned from HL_MEM_OP_ALLOC */ 989 __u64 handle; 990 } map_device; 991 992 /* HL_MEM_OP_MAP - map host memory */ 993 struct { 994 /* Address of allocated host memory */ 995 __u64 host_virt_addr; 996 /* 997 * Requested virtual address of mapped memory. 998 * The driver will try to map the requested region to 999 * this hint address, as long as the address is valid 1000 * and not already mapped. The user should check the 1001 * returned address of the IOCTL to make sure he got 1002 * the hint address. Passing 0 here means that the 1003 * driver will choose the address itself. 1004 */ 1005 __u64 hint_addr; 1006 /* Size of allocated host memory */ 1007 __u64 mem_size; 1008 } map_host; 1009 1010 /* HL_MEM_OP_MAP_BLOCK - map a hw block */ 1011 struct { 1012 /* 1013 * HW block address to map, a handle and size will be 1014 * returned to the user and will be used to mmap the 1015 * relevant block. Only addresses from configuration 1016 * space are allowed. 1017 */ 1018 __u64 block_addr; 1019 } map_block; 1020 1021 /* HL_MEM_OP_UNMAP - unmap host memory */ 1022 struct { 1023 /* Virtual address returned from HL_MEM_OP_MAP */ 1024 __u64 device_virt_addr; 1025 } unmap; 1026 }; 1027 1028 /* HL_MEM_OP_* */ 1029 __u32 op; 1030 /* HL_MEM_* flags */ 1031 __u32 flags; 1032 /* Context ID - Currently not in use */ 1033 __u32 ctx_id; 1034 __u32 pad; 1035 }; 1036 1037 struct hl_mem_out { 1038 union { 1039 /* 1040 * Used for HL_MEM_OP_MAP as the virtual address that was 1041 * assigned in the device VA space. 1042 * A value of 0 means the requested operation failed. 1043 */ 1044 __u64 device_virt_addr; 1045 1046 /* 1047 * Used in HL_MEM_OP_ALLOC 1048 * This is the assigned handle for the allocated memory 1049 */ 1050 __u64 handle; 1051 1052 struct { 1053 /* 1054 * Used in HL_MEM_OP_MAP_BLOCK. 1055 * This is the assigned handle for the mapped block 1056 */ 1057 __u64 block_handle; 1058 1059 /* 1060 * Used in HL_MEM_OP_MAP_BLOCK 1061 * This is the size of the mapped block 1062 */ 1063 __u32 block_size; 1064 1065 __u32 pad; 1066 }; 1067 }; 1068 }; 1069 1070 union hl_mem_args { 1071 struct hl_mem_in in; 1072 struct hl_mem_out out; 1073 }; 1074 1075 #define HL_DEBUG_MAX_AUX_VALUES 10 1076 1077 struct hl_debug_params_etr { 1078 /* Address in memory to allocate buffer */ 1079 __u64 buffer_address; 1080 1081 /* Size of buffer to allocate */ 1082 __u64 buffer_size; 1083 1084 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1085 __u32 sink_mode; 1086 __u32 pad; 1087 }; 1088 1089 struct hl_debug_params_etf { 1090 /* Address in memory to allocate buffer */ 1091 __u64 buffer_address; 1092 1093 /* Size of buffer to allocate */ 1094 __u64 buffer_size; 1095 1096 /* Sink operation mode: SW fifo, HW fifo, Circular buffer */ 1097 __u32 sink_mode; 1098 __u32 pad; 1099 }; 1100 1101 struct hl_debug_params_stm { 1102 /* Two bit masks for HW event and Stimulus Port */ 1103 __u64 he_mask; 1104 __u64 sp_mask; 1105 1106 /* Trace source ID */ 1107 __u32 id; 1108 1109 /* Frequency for the timestamp register */ 1110 __u32 frequency; 1111 }; 1112 1113 struct hl_debug_params_bmon { 1114 /* Two address ranges that the user can request to filter */ 1115 __u64 start_addr0; 1116 __u64 addr_mask0; 1117 1118 __u64 start_addr1; 1119 __u64 addr_mask1; 1120 1121 /* Capture window configuration */ 1122 __u32 bw_win; 1123 __u32 win_capture; 1124 1125 /* Trace source ID */ 1126 __u32 id; 1127 __u32 pad; 1128 }; 1129 1130 struct hl_debug_params_spmu { 1131 /* Event types selection */ 1132 __u64 event_types[HL_DEBUG_MAX_AUX_VALUES]; 1133 1134 /* Number of event types selection */ 1135 __u32 event_types_num; 1136 __u32 pad; 1137 }; 1138 1139 /* Opcode for ETR component */ 1140 #define HL_DEBUG_OP_ETR 0 1141 /* Opcode for ETF component */ 1142 #define HL_DEBUG_OP_ETF 1 1143 /* Opcode for STM component */ 1144 #define HL_DEBUG_OP_STM 2 1145 /* Opcode for FUNNEL component */ 1146 #define HL_DEBUG_OP_FUNNEL 3 1147 /* Opcode for BMON component */ 1148 #define HL_DEBUG_OP_BMON 4 1149 /* Opcode for SPMU component */ 1150 #define HL_DEBUG_OP_SPMU 5 1151 /* Opcode for timestamp (deprecated) */ 1152 #define HL_DEBUG_OP_TIMESTAMP 6 1153 /* Opcode for setting the device into or out of debug mode. The enable 1154 * variable should be 1 for enabling debug mode and 0 for disabling it 1155 */ 1156 #define HL_DEBUG_OP_SET_MODE 7 1157 1158 struct hl_debug_args { 1159 /* 1160 * Pointer to user input structure. 1161 * This field is relevant to specific opcodes. 1162 */ 1163 __u64 input_ptr; 1164 /* Pointer to user output structure */ 1165 __u64 output_ptr; 1166 /* Size of user input structure */ 1167 __u32 input_size; 1168 /* Size of user output structure */ 1169 __u32 output_size; 1170 /* HL_DEBUG_OP_* */ 1171 __u32 op; 1172 /* 1173 * Register index in the component, taken from the debug_regs_index enum 1174 * in the various ASIC header files 1175 */ 1176 __u32 reg_idx; 1177 /* Enable/disable */ 1178 __u32 enable; 1179 /* Context ID - Currently not in use */ 1180 __u32 ctx_id; 1181 }; 1182 1183 /* 1184 * Various information operations such as: 1185 * - H/W IP information 1186 * - Current dram usage 1187 * 1188 * The user calls this IOCTL with an opcode that describes the required 1189 * information. The user should supply a pointer to a user-allocated memory 1190 * chunk, which will be filled by the driver with the requested information. 1191 * 1192 * The user supplies the maximum amount of size to copy into the user's memory, 1193 * in order to prevent data corruption in case of differences between the 1194 * definitions of structures in kernel and userspace, e.g. in case of old 1195 * userspace and new kernel driver 1196 */ 1197 #define HL_IOCTL_INFO \ 1198 _IOWR('H', 0x01, struct hl_info_args) 1199 1200 /* 1201 * Command Buffer 1202 * - Request a Command Buffer 1203 * - Destroy a Command Buffer 1204 * 1205 * The command buffers are memory blocks that reside in DMA-able address 1206 * space and are physically contiguous so they can be accessed by the device 1207 * directly. They are allocated using the coherent DMA API. 1208 * 1209 * When creating a new CB, the IOCTL returns a handle of it, and the user-space 1210 * process needs to use that handle to mmap the buffer so it can access them. 1211 * 1212 * In some instances, the device must access the command buffer through the 1213 * device's MMU, and thus its memory should be mapped. In these cases, user can 1214 * indicate the driver that such a mapping is required. 1215 * The resulting device virtual address will be used internally by the driver, 1216 * and won't be returned to user. 1217 * 1218 */ 1219 #define HL_IOCTL_CB \ 1220 _IOWR('H', 0x02, union hl_cb_args) 1221 1222 /* 1223 * Command Submission 1224 * 1225 * To submit work to the device, the user need to call this IOCTL with a set 1226 * of JOBS. That set of JOBS constitutes a CS object. 1227 * Each JOB will be enqueued on a specific queue, according to the user's input. 1228 * There can be more then one JOB per queue. 1229 * 1230 * The CS IOCTL will receive two sets of JOBS. One set is for "restore" phase 1231 * and a second set is for "execution" phase. 1232 * The JOBS on the "restore" phase are enqueued only after context-switch 1233 * (or if its the first CS for this context). The user can also order the 1234 * driver to run the "restore" phase explicitly 1235 * 1236 * There are two types of queues - external and internal. External queues 1237 * are DMA queues which transfer data from/to the Host. All other queues are 1238 * internal. The driver will get completion notifications from the device only 1239 * on JOBS which are enqueued in the external queues. 1240 * 1241 * For jobs on external queues, the user needs to create command buffers 1242 * through the CB ioctl and give the CB's handle to the CS ioctl. For jobs on 1243 * internal queues, the user needs to prepare a "command buffer" with packets 1244 * on either the device SRAM/DRAM or the host, and give the device address of 1245 * that buffer to the CS ioctl. 1246 * 1247 * This IOCTL is asynchronous in regard to the actual execution of the CS. This 1248 * means it returns immediately after ALL the JOBS were enqueued on their 1249 * relevant queues. Therefore, the user mustn't assume the CS has been completed 1250 * or has even started to execute. 1251 * 1252 * Upon successful enqueue, the IOCTL returns a sequence number which the user 1253 * can use with the "Wait for CS" IOCTL to check whether the handle's CS 1254 * external JOBS have been completed. Note that if the CS has internal JOBS 1255 * which can execute AFTER the external JOBS have finished, the driver might 1256 * report that the CS has finished executing BEFORE the internal JOBS have 1257 * actually finished executing. 1258 * 1259 * Even though the sequence number increments per CS, the user can NOT 1260 * automatically assume that if CS with sequence number N finished, then CS 1261 * with sequence number N-1 also finished. The user can make this assumption if 1262 * and only if CS N and CS N-1 are exactly the same (same CBs for the same 1263 * queues). 1264 */ 1265 #define HL_IOCTL_CS \ 1266 _IOWR('H', 0x03, union hl_cs_args) 1267 1268 /* 1269 * Wait for Command Submission 1270 * 1271 * The user can call this IOCTL with a handle it received from the CS IOCTL 1272 * to wait until the handle's CS has finished executing. The user will wait 1273 * inside the kernel until the CS has finished or until the user-requested 1274 * timeout has expired. 1275 * 1276 * If the timeout value is 0, the driver won't sleep at all. It will check 1277 * the status of the CS and return immediately 1278 * 1279 * The return value of the IOCTL is a standard Linux error code. The possible 1280 * values are: 1281 * 1282 * EINTR - Kernel waiting has been interrupted, e.g. due to OS signal 1283 * that the user process received 1284 * ETIMEDOUT - The CS has caused a timeout on the device 1285 * EIO - The CS was aborted (usually because the device was reset) 1286 * ENODEV - The device wants to do hard-reset (so user need to close FD) 1287 * 1288 * The driver also returns a custom define in case the IOCTL call returned 0. 1289 * The define can be one of the following: 1290 * 1291 * HL_WAIT_CS_STATUS_COMPLETED - The CS has been completed successfully (0) 1292 * HL_WAIT_CS_STATUS_BUSY - The CS is still executing (0) 1293 * HL_WAIT_CS_STATUS_TIMEDOUT - The CS has caused a timeout on the device 1294 * (ETIMEDOUT) 1295 * HL_WAIT_CS_STATUS_ABORTED - The CS was aborted, usually because the 1296 * device was reset (EIO) 1297 */ 1298 1299 #define HL_IOCTL_WAIT_CS \ 1300 _IOWR('H', 0x04, union hl_wait_cs_args) 1301 1302 /* 1303 * Memory 1304 * - Map host memory to device MMU 1305 * - Unmap host memory from device MMU 1306 * 1307 * This IOCTL allows the user to map host memory to the device MMU 1308 * 1309 * For host memory, the IOCTL doesn't allocate memory. The user is supposed 1310 * to allocate the memory in user-space (malloc/new). The driver pins the 1311 * physical pages (up to the allowed limit by the OS), assigns a virtual 1312 * address in the device VA space and initializes the device MMU. 1313 * 1314 * There is an option for the user to specify the requested virtual address. 1315 * 1316 */ 1317 #define HL_IOCTL_MEMORY \ 1318 _IOWR('H', 0x05, union hl_mem_args) 1319 1320 /* 1321 * Debug 1322 * - Enable/disable the ETR/ETF/FUNNEL/STM/BMON/SPMU debug traces 1323 * 1324 * This IOCTL allows the user to get debug traces from the chip. 1325 * 1326 * Before the user can send configuration requests of the various 1327 * debug/profile engines, it needs to set the device into debug mode. 1328 * This is because the debug/profile infrastructure is shared component in the 1329 * device and we can't allow multiple users to access it at the same time. 1330 * 1331 * Once a user set the device into debug mode, the driver won't allow other 1332 * users to "work" with the device, i.e. open a FD. If there are multiple users 1333 * opened on the device, the driver won't allow any user to debug the device. 1334 * 1335 * For each configuration request, the user needs to provide the register index 1336 * and essential data such as buffer address and size. 1337 * 1338 * Once the user has finished using the debug/profile engines, he should 1339 * set the device into non-debug mode, i.e. disable debug mode. 1340 * 1341 * The driver can decide to "kick out" the user if he abuses this interface. 1342 * 1343 */ 1344 #define HL_IOCTL_DEBUG \ 1345 _IOWR('H', 0x06, struct hl_debug_args) 1346 1347 #define HL_COMMAND_START 0x01 1348 #define HL_COMMAND_END 0x07 1349 1350 #endif /* HABANALABS_H_ */ 1351