1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 */ 6 7 #ifndef __ARM64_KVM_ARM_H__ 8 #define __ARM64_KVM_ARM_H__ 9 10 #include <asm/esr.h> 11 #include <asm/memory.h> 12 #include <asm/types.h> 13 14 /* Hyp Configuration Register (HCR) bits */ 15 #define HCR_ATA (UL(1) << 56) 16 #define HCR_FWB (UL(1) << 46) 17 #define HCR_API (UL(1) << 41) 18 #define HCR_APK (UL(1) << 40) 19 #define HCR_TEA (UL(1) << 37) 20 #define HCR_TERR (UL(1) << 36) 21 #define HCR_TLOR (UL(1) << 35) 22 #define HCR_E2H (UL(1) << 34) 23 #define HCR_ID (UL(1) << 33) 24 #define HCR_CD (UL(1) << 32) 25 #define HCR_RW_SHIFT 31 26 #define HCR_RW (UL(1) << HCR_RW_SHIFT) 27 #define HCR_TRVM (UL(1) << 30) 28 #define HCR_HCD (UL(1) << 29) 29 #define HCR_TDZ (UL(1) << 28) 30 #define HCR_TGE (UL(1) << 27) 31 #define HCR_TVM (UL(1) << 26) 32 #define HCR_TTLB (UL(1) << 25) 33 #define HCR_TPU (UL(1) << 24) 34 #define HCR_TPC (UL(1) << 23) 35 #define HCR_TSW (UL(1) << 22) 36 #define HCR_TAC (UL(1) << 21) 37 #define HCR_TIDCP (UL(1) << 20) 38 #define HCR_TSC (UL(1) << 19) 39 #define HCR_TID3 (UL(1) << 18) 40 #define HCR_TID2 (UL(1) << 17) 41 #define HCR_TID1 (UL(1) << 16) 42 #define HCR_TID0 (UL(1) << 15) 43 #define HCR_TWE (UL(1) << 14) 44 #define HCR_TWI (UL(1) << 13) 45 #define HCR_DC (UL(1) << 12) 46 #define HCR_BSU (3 << 10) 47 #define HCR_BSU_IS (UL(1) << 10) 48 #define HCR_FB (UL(1) << 9) 49 #define HCR_VSE (UL(1) << 8) 50 #define HCR_VI (UL(1) << 7) 51 #define HCR_VF (UL(1) << 6) 52 #define HCR_AMO (UL(1) << 5) 53 #define HCR_IMO (UL(1) << 4) 54 #define HCR_FMO (UL(1) << 3) 55 #define HCR_PTW (UL(1) << 2) 56 #define HCR_SWIO (UL(1) << 1) 57 #define HCR_VM (UL(1) << 0) 58 59 /* 60 * The bits we set in HCR: 61 * TLOR: Trap LORegion register accesses 62 * RW: 64bit by default, can be overridden for 32bit VMs 63 * TAC: Trap ACTLR 64 * TSC: Trap SMC 65 * TSW: Trap cache operations by set/way 66 * TWE: Trap WFE 67 * TWI: Trap WFI 68 * TIDCP: Trap L2CTLR/L2ECTLR 69 * BSU_IS: Upgrade barriers to the inner shareable domain 70 * FB: Force broadcast of all maintenance operations 71 * AMO: Override CPSR.A and enable signaling with VA 72 * IMO: Override CPSR.I and enable signaling with VI 73 * FMO: Override CPSR.F and enable signaling with VF 74 * SWIO: Turn set/way invalidates into set/way clean+invalidate 75 * PTW: Take a stage2 fault if a stage1 walk steps in device memory 76 */ 77 #define HCR_GUEST_FLAGS (HCR_TSC | HCR_TSW | HCR_TWE | HCR_TWI | HCR_VM | \ 78 HCR_BSU_IS | HCR_FB | HCR_TAC | \ 79 HCR_AMO | HCR_SWIO | HCR_TIDCP | HCR_RW | HCR_TLOR | \ 80 HCR_FMO | HCR_IMO | HCR_PTW ) 81 #define HCR_VIRT_EXCP_MASK (HCR_VSE | HCR_VI | HCR_VF) 82 #define HCR_HOST_NVHE_FLAGS (HCR_RW | HCR_API | HCR_APK | HCR_ATA) 83 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) 84 85 /* TCR_EL2 Registers bits */ 86 #define TCR_EL2_RES1 ((1 << 31) | (1 << 23)) 87 #define TCR_EL2_TBI (1 << 20) 88 #define TCR_EL2_PS_SHIFT 16 89 #define TCR_EL2_PS_MASK (7 << TCR_EL2_PS_SHIFT) 90 #define TCR_EL2_PS_40B (2 << TCR_EL2_PS_SHIFT) 91 #define TCR_EL2_TG0_MASK TCR_TG0_MASK 92 #define TCR_EL2_SH0_MASK TCR_SH0_MASK 93 #define TCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 94 #define TCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 95 #define TCR_EL2_T0SZ_MASK 0x3f 96 #define TCR_EL2_MASK (TCR_EL2_TG0_MASK | TCR_EL2_SH0_MASK | \ 97 TCR_EL2_ORGN0_MASK | TCR_EL2_IRGN0_MASK | TCR_EL2_T0SZ_MASK) 98 99 /* VTCR_EL2 Registers bits */ 100 #define VTCR_EL2_RES1 (1U << 31) 101 #define VTCR_EL2_HD (1 << 22) 102 #define VTCR_EL2_HA (1 << 21) 103 #define VTCR_EL2_PS_SHIFT TCR_EL2_PS_SHIFT 104 #define VTCR_EL2_PS_MASK TCR_EL2_PS_MASK 105 #define VTCR_EL2_TG0_MASK TCR_TG0_MASK 106 #define VTCR_EL2_TG0_4K TCR_TG0_4K 107 #define VTCR_EL2_TG0_16K TCR_TG0_16K 108 #define VTCR_EL2_TG0_64K TCR_TG0_64K 109 #define VTCR_EL2_SH0_MASK TCR_SH0_MASK 110 #define VTCR_EL2_SH0_INNER TCR_SH0_INNER 111 #define VTCR_EL2_ORGN0_MASK TCR_ORGN0_MASK 112 #define VTCR_EL2_ORGN0_WBWA TCR_ORGN0_WBWA 113 #define VTCR_EL2_IRGN0_MASK TCR_IRGN0_MASK 114 #define VTCR_EL2_IRGN0_WBWA TCR_IRGN0_WBWA 115 #define VTCR_EL2_SL0_SHIFT 6 116 #define VTCR_EL2_SL0_MASK (3 << VTCR_EL2_SL0_SHIFT) 117 #define VTCR_EL2_T0SZ_MASK 0x3f 118 #define VTCR_EL2_VS_SHIFT 19 119 #define VTCR_EL2_VS_8BIT (0 << VTCR_EL2_VS_SHIFT) 120 #define VTCR_EL2_VS_16BIT (1 << VTCR_EL2_VS_SHIFT) 121 122 #define VTCR_EL2_T0SZ(x) TCR_T0SZ(x) 123 124 /* 125 * We configure the Stage-2 page tables to always restrict the IPA space to be 126 * 40 bits wide (T0SZ = 24). Systems with a PARange smaller than 40 bits are 127 * not known to exist and will break with this configuration. 128 * 129 * The VTCR_EL2 is configured per VM and is initialised in kvm_arm_setup_stage2(). 130 * 131 * Note that when using 4K pages, we concatenate two first level page tables 132 * together. With 16K pages, we concatenate 16 first level page tables. 133 * 134 */ 135 136 #define VTCR_EL2_COMMON_BITS (VTCR_EL2_SH0_INNER | VTCR_EL2_ORGN0_WBWA | \ 137 VTCR_EL2_IRGN0_WBWA | VTCR_EL2_RES1) 138 139 /* 140 * VTCR_EL2:SL0 indicates the entry level for Stage2 translation. 141 * Interestingly, it depends on the page size. 142 * See D.10.2.121, VTCR_EL2, in ARM DDI 0487C.a 143 * 144 * ----------------------------------------- 145 * | Entry level | 4K | 16K/64K | 146 * ------------------------------------------ 147 * | Level: 0 | 2 | - | 148 * ------------------------------------------ 149 * | Level: 1 | 1 | 2 | 150 * ------------------------------------------ 151 * | Level: 2 | 0 | 1 | 152 * ------------------------------------------ 153 * | Level: 3 | - | 0 | 154 * ------------------------------------------ 155 * 156 * The table roughly translates to : 157 * 158 * SL0(PAGE_SIZE, Entry_level) = TGRAN_SL0_BASE - Entry_Level 159 * 160 * Where TGRAN_SL0_BASE is a magic number depending on the page size: 161 * TGRAN_SL0_BASE(4K) = 2 162 * TGRAN_SL0_BASE(16K) = 3 163 * TGRAN_SL0_BASE(64K) = 3 164 * provided we take care of ruling out the unsupported cases and 165 * Entry_Level = 4 - Number_of_levels. 166 * 167 */ 168 #ifdef CONFIG_ARM64_64K_PAGES 169 170 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_64K 171 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 172 173 #elif defined(CONFIG_ARM64_16K_PAGES) 174 175 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_16K 176 #define VTCR_EL2_TGRAN_SL0_BASE 3UL 177 178 #else /* 4K */ 179 180 #define VTCR_EL2_TGRAN VTCR_EL2_TG0_4K 181 #define VTCR_EL2_TGRAN_SL0_BASE 2UL 182 183 #endif 184 185 #define VTCR_EL2_LVLS_TO_SL0(levels) \ 186 ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT) 187 #define VTCR_EL2_SL0_TO_LVLS(sl0) \ 188 ((sl0) + 4 - VTCR_EL2_TGRAN_SL0_BASE) 189 #define VTCR_EL2_LVLS(vtcr) \ 190 VTCR_EL2_SL0_TO_LVLS(((vtcr) & VTCR_EL2_SL0_MASK) >> VTCR_EL2_SL0_SHIFT) 191 192 #define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN) 193 #define VTCR_EL2_IPA(vtcr) (64 - ((vtcr) & VTCR_EL2_T0SZ_MASK)) 194 195 /* 196 * ARM VMSAv8-64 defines an algorithm for finding the translation table 197 * descriptors in section D4.2.8 in ARM DDI 0487C.a. 198 * 199 * The algorithm defines the expectations on the translation table 200 * addresses for each level, based on PAGE_SIZE, entry level 201 * and the translation table size (T0SZ). The variable "x" in the 202 * algorithm determines the alignment of a table base address at a given 203 * level and thus determines the alignment of VTTBR:BADDR for stage2 204 * page table entry level. 205 * Since the number of bits resolved at the entry level could vary 206 * depending on the T0SZ, the value of "x" is defined based on a 207 * Magic constant for a given PAGE_SIZE and Entry Level. The 208 * intermediate levels must be always aligned to the PAGE_SIZE (i.e, 209 * x = PAGE_SHIFT). 210 * 211 * The value of "x" for entry level is calculated as : 212 * x = Magic_N - T0SZ 213 * 214 * where Magic_N is an integer depending on the page size and the entry 215 * level of the page table as below: 216 * 217 * -------------------------------------------- 218 * | Entry level | 4K 16K 64K | 219 * -------------------------------------------- 220 * | Level: 0 (4 levels) | 28 | - | - | 221 * -------------------------------------------- 222 * | Level: 1 (3 levels) | 37 | 31 | 25 | 223 * -------------------------------------------- 224 * | Level: 2 (2 levels) | 46 | 42 | 38 | 225 * -------------------------------------------- 226 * | Level: 3 (1 level) | - | 53 | 51 | 227 * -------------------------------------------- 228 * 229 * We have a magic formula for the Magic_N below: 230 * 231 * Magic_N(PAGE_SIZE, Level) = 64 - ((PAGE_SHIFT - 3) * Number_of_levels) 232 * 233 * where Number_of_levels = (4 - Level). We are only interested in the 234 * value for Entry_Level for the stage2 page table. 235 * 236 * So, given that T0SZ = (64 - IPA_SHIFT), we can compute 'x' as follows: 237 * 238 * x = (64 - ((PAGE_SHIFT - 3) * Number_of_levels)) - (64 - IPA_SHIFT) 239 * = IPA_SHIFT - ((PAGE_SHIFT - 3) * Number of levels) 240 * 241 * Here is one way to explain the Magic Formula: 242 * 243 * x = log2(Size_of_Entry_Level_Table) 244 * 245 * Since, we can resolve (PAGE_SHIFT - 3) bits at each level, and another 246 * PAGE_SHIFT bits in the PTE, we have : 247 * 248 * Bits_Entry_level = IPA_SHIFT - ((PAGE_SHIFT - 3) * (n - 1) + PAGE_SHIFT) 249 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n - 3 250 * where n = number of levels, and since each pointer is 8bytes, we have: 251 * 252 * x = Bits_Entry_Level + 3 253 * = IPA_SHIFT - (PAGE_SHIFT - 3) * n 254 * 255 * The only constraint here is that, we have to find the number of page table 256 * levels for a given IPA size (which we do, see stage2_pt_levels()) 257 */ 258 #define ARM64_VTTBR_X(ipa, levels) ((ipa) - ((levels) * (PAGE_SHIFT - 3))) 259 260 #define VTTBR_CNP_BIT (UL(1)) 261 #define VTTBR_VMID_SHIFT (UL(48)) 262 #define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT) 263 264 /* Hyp System Trap Register */ 265 #define HSTR_EL2_T(x) (1 << x) 266 267 /* Hyp Coprocessor Trap Register Shifts */ 268 #define CPTR_EL2_TFP_SHIFT 10 269 270 /* Hyp Coprocessor Trap Register */ 271 #define CPTR_EL2_TCPAC (1 << 31) 272 #define CPTR_EL2_TAM (1 << 30) 273 #define CPTR_EL2_TTA (1 << 20) 274 #define CPTR_EL2_TFP (1 << CPTR_EL2_TFP_SHIFT) 275 #define CPTR_EL2_TZ (1 << 8) 276 #define CPTR_EL2_RES1 0x000032ff /* known RES1 bits in CPTR_EL2 */ 277 #define CPTR_EL2_DEFAULT CPTR_EL2_RES1 278 279 /* Hyp Debug Configuration Register bits */ 280 #define MDCR_EL2_TPMS (1 << 14) 281 #define MDCR_EL2_E2PB_MASK (UL(0x3)) 282 #define MDCR_EL2_E2PB_SHIFT (UL(12)) 283 #define MDCR_EL2_TDRA (1 << 11) 284 #define MDCR_EL2_TDOSA (1 << 10) 285 #define MDCR_EL2_TDA (1 << 9) 286 #define MDCR_EL2_TDE (1 << 8) 287 #define MDCR_EL2_HPME (1 << 7) 288 #define MDCR_EL2_TPM (1 << 6) 289 #define MDCR_EL2_TPMCR (1 << 5) 290 #define MDCR_EL2_HPMN_MASK (0x1F) 291 292 /* For compatibility with fault code shared with 32-bit */ 293 #define FSC_FAULT ESR_ELx_FSC_FAULT 294 #define FSC_ACCESS ESR_ELx_FSC_ACCESS 295 #define FSC_PERM ESR_ELx_FSC_PERM 296 #define FSC_SEA ESR_ELx_FSC_EXTABT 297 #define FSC_SEA_TTW0 (0x14) 298 #define FSC_SEA_TTW1 (0x15) 299 #define FSC_SEA_TTW2 (0x16) 300 #define FSC_SEA_TTW3 (0x17) 301 #define FSC_SECC (0x18) 302 #define FSC_SECC_TTW0 (0x1c) 303 #define FSC_SECC_TTW1 (0x1d) 304 #define FSC_SECC_TTW2 (0x1e) 305 #define FSC_SECC_TTW3 (0x1f) 306 307 /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */ 308 #define HPFAR_MASK (~UL(0xf)) 309 /* 310 * We have 311 * PAR [PA_Shift - 1 : 12] = PA [PA_Shift - 1 : 12] 312 * HPFAR [PA_Shift - 9 : 4] = FIPA [PA_Shift - 1 : 12] 313 */ 314 #define PAR_TO_HPFAR(par) \ 315 (((par) & GENMASK_ULL(PHYS_MASK_SHIFT - 1, 12)) >> 8) 316 317 #define ECN(x) { ESR_ELx_EC_##x, #x } 318 319 #define kvm_arm_exception_class \ 320 ECN(UNKNOWN), ECN(WFx), ECN(CP15_32), ECN(CP15_64), ECN(CP14_MR), \ 321 ECN(CP14_LS), ECN(FP_ASIMD), ECN(CP10_ID), ECN(PAC), ECN(CP14_64), \ 322 ECN(SVC64), ECN(HVC64), ECN(SMC64), ECN(SYS64), ECN(SVE), \ 323 ECN(IMP_DEF), ECN(IABT_LOW), ECN(IABT_CUR), \ 324 ECN(PC_ALIGN), ECN(DABT_LOW), ECN(DABT_CUR), \ 325 ECN(SP_ALIGN), ECN(FP_EXC32), ECN(FP_EXC64), ECN(SERROR), \ 326 ECN(BREAKPT_LOW), ECN(BREAKPT_CUR), ECN(SOFTSTP_LOW), \ 327 ECN(SOFTSTP_CUR), ECN(WATCHPT_LOW), ECN(WATCHPT_CUR), \ 328 ECN(BKPT32), ECN(VECTOR32), ECN(BRK64) 329 330 #define CPACR_EL1_FPEN (3 << 20) 331 #define CPACR_EL1_TTA (1 << 28) 332 #define CPACR_EL1_DEFAULT (CPACR_EL1_FPEN | CPACR_EL1_ZEN_EL1EN) 333 334 #endif /* __ARM64_KVM_ARM_H__ */ 335
