1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_MAIN_H
5 #define __HCLGE_MAIN_H
6 #include <linux/fs.h>
7 #include <linux/types.h>
8 #include <linux/phy.h>
9 #include <linux/if_vlan.h>
10 #include <linux/kfifo.h>
11
12 #include "hclge_cmd.h"
13 #include "hnae3.h"
14
15 #define HCLGE_MOD_VERSION "1.0"
16 #define HCLGE_DRIVER_NAME "hclge"
17
18 #define HCLGE_MAX_PF_NUM 8
19
20 #define HCLGE_RD_FIRST_STATS_NUM 2
21 #define HCLGE_RD_OTHER_STATS_NUM 4
22
23 #define HCLGE_INVALID_VPORT 0xffff
24
25 #define HCLGE_PF_CFG_BLOCK_SIZE 32
26 #define HCLGE_PF_CFG_DESC_NUM \
27 (HCLGE_PF_CFG_BLOCK_SIZE / HCLGE_CFG_RD_LEN_BYTES)
28
29 #define HCLGE_VECTOR_REG_BASE 0x20000
30 #define HCLGE_MISC_VECTOR_REG_BASE 0x20400
31
32 #define HCLGE_VECTOR_REG_OFFSET 0x4
33 #define HCLGE_VECTOR_VF_OFFSET 0x100000
34
35 #define HCLGE_CMDQ_TX_ADDR_L_REG 0x27000
36 #define HCLGE_CMDQ_TX_ADDR_H_REG 0x27004
37 #define HCLGE_CMDQ_TX_DEPTH_REG 0x27008
38 #define HCLGE_CMDQ_TX_TAIL_REG 0x27010
39 #define HCLGE_CMDQ_TX_HEAD_REG 0x27014
40 #define HCLGE_CMDQ_RX_ADDR_L_REG 0x27018
41 #define HCLGE_CMDQ_RX_ADDR_H_REG 0x2701C
42 #define HCLGE_CMDQ_RX_DEPTH_REG 0x27020
43 #define HCLGE_CMDQ_RX_TAIL_REG 0x27024
44 #define HCLGE_CMDQ_RX_HEAD_REG 0x27028
45 #define HCLGE_CMDQ_INTR_SRC_REG 0x27100
46 #define HCLGE_CMDQ_INTR_STS_REG 0x27104
47 #define HCLGE_CMDQ_INTR_EN_REG 0x27108
48 #define HCLGE_CMDQ_INTR_GEN_REG 0x2710C
49
50 /* bar registers for common func */
51 #define HCLGE_VECTOR0_OTER_EN_REG 0x20600
52 #define HCLGE_RAS_OTHER_STS_REG 0x20B00
53 #define HCLGE_FUNC_RESET_STS_REG 0x20C00
54 #define HCLGE_GRO_EN_REG 0x28000
55
56 /* bar registers for rcb */
57 #define HCLGE_RING_RX_ADDR_L_REG 0x80000
58 #define HCLGE_RING_RX_ADDR_H_REG 0x80004
59 #define HCLGE_RING_RX_BD_NUM_REG 0x80008
60 #define HCLGE_RING_RX_BD_LENGTH_REG 0x8000C
61 #define HCLGE_RING_RX_MERGE_EN_REG 0x80014
62 #define HCLGE_RING_RX_TAIL_REG 0x80018
63 #define HCLGE_RING_RX_HEAD_REG 0x8001C
64 #define HCLGE_RING_RX_FBD_NUM_REG 0x80020
65 #define HCLGE_RING_RX_OFFSET_REG 0x80024
66 #define HCLGE_RING_RX_FBD_OFFSET_REG 0x80028
67 #define HCLGE_RING_RX_STASH_REG 0x80030
68 #define HCLGE_RING_RX_BD_ERR_REG 0x80034
69 #define HCLGE_RING_TX_ADDR_L_REG 0x80040
70 #define HCLGE_RING_TX_ADDR_H_REG 0x80044
71 #define HCLGE_RING_TX_BD_NUM_REG 0x80048
72 #define HCLGE_RING_TX_PRIORITY_REG 0x8004C
73 #define HCLGE_RING_TX_TC_REG 0x80050
74 #define HCLGE_RING_TX_MERGE_EN_REG 0x80054
75 #define HCLGE_RING_TX_TAIL_REG 0x80058
76 #define HCLGE_RING_TX_HEAD_REG 0x8005C
77 #define HCLGE_RING_TX_FBD_NUM_REG 0x80060
78 #define HCLGE_RING_TX_OFFSET_REG 0x80064
79 #define HCLGE_RING_TX_EBD_NUM_REG 0x80068
80 #define HCLGE_RING_TX_EBD_OFFSET_REG 0x80070
81 #define HCLGE_RING_TX_BD_ERR_REG 0x80074
82 #define HCLGE_RING_EN_REG 0x80090
83
84 /* bar registers for tqp interrupt */
85 #define HCLGE_TQP_INTR_CTRL_REG 0x20000
86 #define HCLGE_TQP_INTR_GL0_REG 0x20100
87 #define HCLGE_TQP_INTR_GL1_REG 0x20200
88 #define HCLGE_TQP_INTR_GL2_REG 0x20300
89 #define HCLGE_TQP_INTR_RL_REG 0x20900
90
91 #define HCLGE_RSS_IND_TBL_SIZE 512
92 #define HCLGE_RSS_SET_BITMAP_MSK GENMASK(15, 0)
93 #define HCLGE_RSS_KEY_SIZE 40
94 #define HCLGE_RSS_HASH_ALGO_TOEPLITZ 0
95 #define HCLGE_RSS_HASH_ALGO_SIMPLE 1
96 #define HCLGE_RSS_HASH_ALGO_SYMMETRIC 2
97 #define HCLGE_RSS_HASH_ALGO_MASK GENMASK(3, 0)
98 #define HCLGE_RSS_CFG_TBL_NUM \
99 (HCLGE_RSS_IND_TBL_SIZE / HCLGE_RSS_CFG_TBL_SIZE)
100
101 #define HCLGE_RSS_INPUT_TUPLE_OTHER GENMASK(3, 0)
102 #define HCLGE_RSS_INPUT_TUPLE_SCTP GENMASK(4, 0)
103 #define HCLGE_D_PORT_BIT BIT(0)
104 #define HCLGE_S_PORT_BIT BIT(1)
105 #define HCLGE_D_IP_BIT BIT(2)
106 #define HCLGE_S_IP_BIT BIT(3)
107 #define HCLGE_V_TAG_BIT BIT(4)
108
109 #define HCLGE_RSS_TC_SIZE_0 1
110 #define HCLGE_RSS_TC_SIZE_1 2
111 #define HCLGE_RSS_TC_SIZE_2 4
112 #define HCLGE_RSS_TC_SIZE_3 8
113 #define HCLGE_RSS_TC_SIZE_4 16
114 #define HCLGE_RSS_TC_SIZE_5 32
115 #define HCLGE_RSS_TC_SIZE_6 64
116 #define HCLGE_RSS_TC_SIZE_7 128
117
118 #define HCLGE_UMV_TBL_SIZE 3072
119 #define HCLGE_DEFAULT_UMV_SPACE_PER_PF \
120 (HCLGE_UMV_TBL_SIZE / HCLGE_MAX_PF_NUM)
121
122 #define HCLGE_TQP_RESET_TRY_TIMES 200
123
124 #define HCLGE_PHY_PAGE_MDIX 0
125 #define HCLGE_PHY_PAGE_COPPER 0
126
127 /* Page Selection Reg. */
128 #define HCLGE_PHY_PAGE_REG 22
129
130 /* Copper Specific Control Register */
131 #define HCLGE_PHY_CSC_REG 16
132
133 /* Copper Specific Status Register */
134 #define HCLGE_PHY_CSS_REG 17
135
136 #define HCLGE_PHY_MDIX_CTRL_S 5
137 #define HCLGE_PHY_MDIX_CTRL_M GENMASK(6, 5)
138
139 #define HCLGE_PHY_MDIX_STATUS_B 6
140 #define HCLGE_PHY_SPEED_DUP_RESOLVE_B 11
141
142 #define HCLGE_GET_DFX_REG_TYPE_CNT 4
143
144 /* Factor used to calculate offset and bitmap of VF num */
145 #define HCLGE_VF_NUM_PER_CMD 64
146
147 enum HLCGE_PORT_TYPE {
148 HOST_PORT,
149 NETWORK_PORT
150 };
151
152 #define PF_VPORT_ID 0
153
154 #define HCLGE_PF_ID_S 0
155 #define HCLGE_PF_ID_M GENMASK(2, 0)
156 #define HCLGE_VF_ID_S 3
157 #define HCLGE_VF_ID_M GENMASK(10, 3)
158 #define HCLGE_PORT_TYPE_B 11
159 #define HCLGE_NETWORK_PORT_ID_S 0
160 #define HCLGE_NETWORK_PORT_ID_M GENMASK(3, 0)
161
162 /* Reset related Registers */
163 #define HCLGE_PF_OTHER_INT_REG 0x20600
164 #define HCLGE_MISC_RESET_STS_REG 0x20700
165 #define HCLGE_MISC_VECTOR_INT_STS 0x20800
166 #define HCLGE_GLOBAL_RESET_REG 0x20A00
167 #define HCLGE_GLOBAL_RESET_BIT 0
168 #define HCLGE_CORE_RESET_BIT 1
169 #define HCLGE_IMP_RESET_BIT 2
170 #define HCLGE_RESET_INT_M GENMASK(7, 5)
171 #define HCLGE_FUN_RST_ING 0x20C00
172 #define HCLGE_FUN_RST_ING_B 0
173
174 /* Vector0 register bits define */
175 #define HCLGE_VECTOR0_GLOBALRESET_INT_B 5
176 #define HCLGE_VECTOR0_CORERESET_INT_B 6
177 #define HCLGE_VECTOR0_IMPRESET_INT_B 7
178
179 /* Vector0 interrupt CMDQ event source register(RW) */
180 #define HCLGE_VECTOR0_CMDQ_SRC_REG 0x27100
181 /* CMDQ register bits for RX event(=MBX event) */
182 #define HCLGE_VECTOR0_RX_CMDQ_INT_B 1
183
184 #define HCLGE_VECTOR0_IMP_RESET_INT_B 1
185 #define HCLGE_VECTOR0_IMP_CMDQ_ERR_B 4U
186 #define HCLGE_VECTOR0_IMP_RD_POISON_B 5U
187
188 #define HCLGE_MAC_DEFAULT_FRAME \
189 (ETH_HLEN + ETH_FCS_LEN + 2 * VLAN_HLEN + ETH_DATA_LEN)
190 #define HCLGE_MAC_MIN_FRAME 64
191 #define HCLGE_MAC_MAX_FRAME 9728
192
193 #define HCLGE_SUPPORT_1G_BIT BIT(0)
194 #define HCLGE_SUPPORT_10G_BIT BIT(1)
195 #define HCLGE_SUPPORT_25G_BIT BIT(2)
196 #define HCLGE_SUPPORT_50G_BIT BIT(3)
197 #define HCLGE_SUPPORT_100G_BIT BIT(4)
198 /* to be compatible with exsit board */
199 #define HCLGE_SUPPORT_40G_BIT BIT(5)
200 #define HCLGE_SUPPORT_100M_BIT BIT(6)
201 #define HCLGE_SUPPORT_10M_BIT BIT(7)
202 #define HCLGE_SUPPORT_200G_BIT BIT(8)
203 #define HCLGE_SUPPORT_GE \
204 (HCLGE_SUPPORT_1G_BIT | HCLGE_SUPPORT_100M_BIT | HCLGE_SUPPORT_10M_BIT)
205
206 enum HCLGE_DEV_STATE {
207 HCLGE_STATE_REINITING,
208 HCLGE_STATE_DOWN,
209 HCLGE_STATE_DISABLED,
210 HCLGE_STATE_REMOVING,
211 HCLGE_STATE_NIC_REGISTERED,
212 HCLGE_STATE_ROCE_REGISTERED,
213 HCLGE_STATE_SERVICE_INITED,
214 HCLGE_STATE_RST_SERVICE_SCHED,
215 HCLGE_STATE_RST_HANDLING,
216 HCLGE_STATE_MBX_SERVICE_SCHED,
217 HCLGE_STATE_MBX_HANDLING,
218 HCLGE_STATE_STATISTICS_UPDATING,
219 HCLGE_STATE_CMD_DISABLE,
220 HCLGE_STATE_LINK_UPDATING,
221 HCLGE_STATE_PROMISC_CHANGED,
222 HCLGE_STATE_RST_FAIL,
223 HCLGE_STATE_MAX
224 };
225
226 enum hclge_evt_cause {
227 HCLGE_VECTOR0_EVENT_RST,
228 HCLGE_VECTOR0_EVENT_MBX,
229 HCLGE_VECTOR0_EVENT_ERR,
230 HCLGE_VECTOR0_EVENT_OTHER,
231 };
232
233 enum HCLGE_MAC_SPEED {
234 HCLGE_MAC_SPEED_UNKNOWN = 0, /* unknown */
235 HCLGE_MAC_SPEED_10M = 10, /* 10 Mbps */
236 HCLGE_MAC_SPEED_100M = 100, /* 100 Mbps */
237 HCLGE_MAC_SPEED_1G = 1000, /* 1000 Mbps = 1 Gbps */
238 HCLGE_MAC_SPEED_10G = 10000, /* 10000 Mbps = 10 Gbps */
239 HCLGE_MAC_SPEED_25G = 25000, /* 25000 Mbps = 25 Gbps */
240 HCLGE_MAC_SPEED_40G = 40000, /* 40000 Mbps = 40 Gbps */
241 HCLGE_MAC_SPEED_50G = 50000, /* 50000 Mbps = 50 Gbps */
242 HCLGE_MAC_SPEED_100G = 100000, /* 100000 Mbps = 100 Gbps */
243 HCLGE_MAC_SPEED_200G = 200000 /* 200000 Mbps = 200 Gbps */
244 };
245
246 enum HCLGE_MAC_DUPLEX {
247 HCLGE_MAC_HALF,
248 HCLGE_MAC_FULL
249 };
250
251 #define QUERY_SFP_SPEED 0
252 #define QUERY_ACTIVE_SPEED 1
253
254 struct hclge_mac {
255 u8 mac_id;
256 u8 phy_addr;
257 u8 flag;
258 u8 media_type; /* port media type, e.g. fibre/copper/backplane */
259 u8 mac_addr[ETH_ALEN];
260 u8 autoneg;
261 u8 duplex;
262 u8 support_autoneg;
263 u8 speed_type; /* 0: sfp speed, 1: active speed */
264 u32 speed;
265 u32 max_speed;
266 u32 speed_ability; /* speed ability supported by current media */
267 u32 module_type; /* sub media type, e.g. kr/cr/sr/lr */
268 u32 fec_mode; /* active fec mode */
269 u32 user_fec_mode;
270 u32 fec_ability;
271 int link; /* store the link status of mac & phy (if phy exists) */
272 struct phy_device *phydev;
273 struct mii_bus *mdio_bus;
274 phy_interface_t phy_if;
275 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported);
276 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
277 };
278
279 struct hclge_hw {
280 void __iomem *io_base;
281 struct hclge_mac mac;
282 int num_vec;
283 struct hclge_cmq cmq;
284 };
285
286 /* TQP stats */
287 struct hlcge_tqp_stats {
288 /* query_tqp_tx_queue_statistics ,opcode id: 0x0B03 */
289 u64 rcb_tx_ring_pktnum_rcd; /* 32bit */
290 /* query_tqp_rx_queue_statistics ,opcode id: 0x0B13 */
291 u64 rcb_rx_ring_pktnum_rcd; /* 32bit */
292 };
293
294 struct hclge_tqp {
295 /* copy of device pointer from pci_dev,
296 * used when perform DMA mapping
297 */
298 struct device *dev;
299 struct hnae3_queue q;
300 struct hlcge_tqp_stats tqp_stats;
301 u16 index; /* Global index in a NIC controller */
302
303 bool alloced;
304 };
305
306 enum hclge_fc_mode {
307 HCLGE_FC_NONE,
308 HCLGE_FC_RX_PAUSE,
309 HCLGE_FC_TX_PAUSE,
310 HCLGE_FC_FULL,
311 HCLGE_FC_PFC,
312 HCLGE_FC_DEFAULT
313 };
314
315 enum hclge_link_fail_code {
316 HCLGE_LF_NORMAL,
317 HCLGE_LF_REF_CLOCK_LOST,
318 HCLGE_LF_XSFP_TX_DISABLE,
319 HCLGE_LF_XSFP_ABSENT,
320 };
321
322 #define HCLGE_LINK_STATUS_DOWN 0
323 #define HCLGE_LINK_STATUS_UP 1
324
325 #define HCLGE_PG_NUM 4
326 #define HCLGE_SCH_MODE_SP 0
327 #define HCLGE_SCH_MODE_DWRR 1
328 struct hclge_pg_info {
329 u8 pg_id;
330 u8 pg_sch_mode; /* 0: sp; 1: dwrr */
331 u8 tc_bit_map;
332 u32 bw_limit;
333 u8 tc_dwrr[HNAE3_MAX_TC];
334 };
335
336 struct hclge_tc_info {
337 u8 tc_id;
338 u8 tc_sch_mode; /* 0: sp; 1: dwrr */
339 u8 pgid;
340 u32 bw_limit;
341 };
342
343 struct hclge_cfg {
344 u8 vmdq_vport_num;
345 u8 tc_num;
346 u16 tqp_desc_num;
347 u16 rx_buf_len;
348 u16 rss_size_max;
349 u8 phy_addr;
350 u8 media_type;
351 u8 mac_addr[ETH_ALEN];
352 u8 default_speed;
353 u32 numa_node_map;
354 u16 speed_ability;
355 u16 umv_space;
356 };
357
358 struct hclge_tm_info {
359 u8 num_tc;
360 u8 num_pg; /* It must be 1 if vNET-Base schd */
361 u8 pg_dwrr[HCLGE_PG_NUM];
362 u8 prio_tc[HNAE3_MAX_USER_PRIO];
363 struct hclge_pg_info pg_info[HCLGE_PG_NUM];
364 struct hclge_tc_info tc_info[HNAE3_MAX_TC];
365 enum hclge_fc_mode fc_mode;
366 u8 hw_pfc_map; /* Allow for packet drop or not on this TC */
367 u8 pfc_en; /* PFC enabled or not for user priority */
368 };
369
370 struct hclge_comm_stats_str {
371 char desc[ETH_GSTRING_LEN];
372 unsigned long offset;
373 };
374
375 /* mac stats ,opcode id: 0x0032 */
376 struct hclge_mac_stats {
377 u64 mac_tx_mac_pause_num;
378 u64 mac_rx_mac_pause_num;
379 u64 mac_tx_pfc_pri0_pkt_num;
380 u64 mac_tx_pfc_pri1_pkt_num;
381 u64 mac_tx_pfc_pri2_pkt_num;
382 u64 mac_tx_pfc_pri3_pkt_num;
383 u64 mac_tx_pfc_pri4_pkt_num;
384 u64 mac_tx_pfc_pri5_pkt_num;
385 u64 mac_tx_pfc_pri6_pkt_num;
386 u64 mac_tx_pfc_pri7_pkt_num;
387 u64 mac_rx_pfc_pri0_pkt_num;
388 u64 mac_rx_pfc_pri1_pkt_num;
389 u64 mac_rx_pfc_pri2_pkt_num;
390 u64 mac_rx_pfc_pri3_pkt_num;
391 u64 mac_rx_pfc_pri4_pkt_num;
392 u64 mac_rx_pfc_pri5_pkt_num;
393 u64 mac_rx_pfc_pri6_pkt_num;
394 u64 mac_rx_pfc_pri7_pkt_num;
395 u64 mac_tx_total_pkt_num;
396 u64 mac_tx_total_oct_num;
397 u64 mac_tx_good_pkt_num;
398 u64 mac_tx_bad_pkt_num;
399 u64 mac_tx_good_oct_num;
400 u64 mac_tx_bad_oct_num;
401 u64 mac_tx_uni_pkt_num;
402 u64 mac_tx_multi_pkt_num;
403 u64 mac_tx_broad_pkt_num;
404 u64 mac_tx_undersize_pkt_num;
405 u64 mac_tx_oversize_pkt_num;
406 u64 mac_tx_64_oct_pkt_num;
407 u64 mac_tx_65_127_oct_pkt_num;
408 u64 mac_tx_128_255_oct_pkt_num;
409 u64 mac_tx_256_511_oct_pkt_num;
410 u64 mac_tx_512_1023_oct_pkt_num;
411 u64 mac_tx_1024_1518_oct_pkt_num;
412 u64 mac_tx_1519_2047_oct_pkt_num;
413 u64 mac_tx_2048_4095_oct_pkt_num;
414 u64 mac_tx_4096_8191_oct_pkt_num;
415 u64 rsv0;
416 u64 mac_tx_8192_9216_oct_pkt_num;
417 u64 mac_tx_9217_12287_oct_pkt_num;
418 u64 mac_tx_12288_16383_oct_pkt_num;
419 u64 mac_tx_1519_max_good_oct_pkt_num;
420 u64 mac_tx_1519_max_bad_oct_pkt_num;
421
422 u64 mac_rx_total_pkt_num;
423 u64 mac_rx_total_oct_num;
424 u64 mac_rx_good_pkt_num;
425 u64 mac_rx_bad_pkt_num;
426 u64 mac_rx_good_oct_num;
427 u64 mac_rx_bad_oct_num;
428 u64 mac_rx_uni_pkt_num;
429 u64 mac_rx_multi_pkt_num;
430 u64 mac_rx_broad_pkt_num;
431 u64 mac_rx_undersize_pkt_num;
432 u64 mac_rx_oversize_pkt_num;
433 u64 mac_rx_64_oct_pkt_num;
434 u64 mac_rx_65_127_oct_pkt_num;
435 u64 mac_rx_128_255_oct_pkt_num;
436 u64 mac_rx_256_511_oct_pkt_num;
437 u64 mac_rx_512_1023_oct_pkt_num;
438 u64 mac_rx_1024_1518_oct_pkt_num;
439 u64 mac_rx_1519_2047_oct_pkt_num;
440 u64 mac_rx_2048_4095_oct_pkt_num;
441 u64 mac_rx_4096_8191_oct_pkt_num;
442 u64 rsv1;
443 u64 mac_rx_8192_9216_oct_pkt_num;
444 u64 mac_rx_9217_12287_oct_pkt_num;
445 u64 mac_rx_12288_16383_oct_pkt_num;
446 u64 mac_rx_1519_max_good_oct_pkt_num;
447 u64 mac_rx_1519_max_bad_oct_pkt_num;
448
449 u64 mac_tx_fragment_pkt_num;
450 u64 mac_tx_undermin_pkt_num;
451 u64 mac_tx_jabber_pkt_num;
452 u64 mac_tx_err_all_pkt_num;
453 u64 mac_tx_from_app_good_pkt_num;
454 u64 mac_tx_from_app_bad_pkt_num;
455 u64 mac_rx_fragment_pkt_num;
456 u64 mac_rx_undermin_pkt_num;
457 u64 mac_rx_jabber_pkt_num;
458 u64 mac_rx_fcs_err_pkt_num;
459 u64 mac_rx_send_app_good_pkt_num;
460 u64 mac_rx_send_app_bad_pkt_num;
461 u64 mac_tx_pfc_pause_pkt_num;
462 u64 mac_rx_pfc_pause_pkt_num;
463 u64 mac_tx_ctrl_pkt_num;
464 u64 mac_rx_ctrl_pkt_num;
465 };
466
467 #define HCLGE_STATS_TIMER_INTERVAL 300UL
468
469 struct hclge_vlan_type_cfg {
470 u16 rx_ot_fst_vlan_type;
471 u16 rx_ot_sec_vlan_type;
472 u16 rx_in_fst_vlan_type;
473 u16 rx_in_sec_vlan_type;
474 u16 tx_ot_vlan_type;
475 u16 tx_in_vlan_type;
476 };
477
478 enum HCLGE_FD_MODE {
479 HCLGE_FD_MODE_DEPTH_2K_WIDTH_400B_STAGE_1,
480 HCLGE_FD_MODE_DEPTH_1K_WIDTH_400B_STAGE_2,
481 HCLGE_FD_MODE_DEPTH_4K_WIDTH_200B_STAGE_1,
482 HCLGE_FD_MODE_DEPTH_2K_WIDTH_200B_STAGE_2,
483 };
484
485 enum HCLGE_FD_KEY_TYPE {
486 HCLGE_FD_KEY_BASE_ON_PTYPE,
487 HCLGE_FD_KEY_BASE_ON_TUPLE,
488 };
489
490 enum HCLGE_FD_STAGE {
491 HCLGE_FD_STAGE_1,
492 HCLGE_FD_STAGE_2,
493 MAX_STAGE_NUM,
494 };
495
496 /* OUTER_XXX indicates tuples in tunnel header of tunnel packet
497 * INNER_XXX indicate tuples in tunneled header of tunnel packet or
498 * tuples of non-tunnel packet
499 */
500 enum HCLGE_FD_TUPLE {
501 OUTER_DST_MAC,
502 OUTER_SRC_MAC,
503 OUTER_VLAN_TAG_FST,
504 OUTER_VLAN_TAG_SEC,
505 OUTER_ETH_TYPE,
506 OUTER_L2_RSV,
507 OUTER_IP_TOS,
508 OUTER_IP_PROTO,
509 OUTER_SRC_IP,
510 OUTER_DST_IP,
511 OUTER_L3_RSV,
512 OUTER_SRC_PORT,
513 OUTER_DST_PORT,
514 OUTER_L4_RSV,
515 OUTER_TUN_VNI,
516 OUTER_TUN_FLOW_ID,
517 INNER_DST_MAC,
518 INNER_SRC_MAC,
519 INNER_VLAN_TAG_FST,
520 INNER_VLAN_TAG_SEC,
521 INNER_ETH_TYPE,
522 INNER_L2_RSV,
523 INNER_IP_TOS,
524 INNER_IP_PROTO,
525 INNER_SRC_IP,
526 INNER_DST_IP,
527 INNER_L3_RSV,
528 INNER_SRC_PORT,
529 INNER_DST_PORT,
530 INNER_L4_RSV,
531 MAX_TUPLE,
532 };
533
534 enum HCLGE_FD_META_DATA {
535 PACKET_TYPE_ID,
536 IP_FRAGEMENT,
537 ROCE_TYPE,
538 NEXT_KEY,
539 VLAN_NUMBER,
540 SRC_VPORT,
541 DST_VPORT,
542 TUNNEL_PACKET,
543 MAX_META_DATA,
544 };
545
546 struct key_info {
547 u8 key_type;
548 u8 key_length; /* use bit as unit */
549 };
550
551 #define MAX_KEY_LENGTH 400
552 #define MAX_KEY_DWORDS DIV_ROUND_UP(MAX_KEY_LENGTH / 8, 4)
553 #define MAX_KEY_BYTES (MAX_KEY_DWORDS * 4)
554 #define MAX_META_DATA_LENGTH 32
555
556 /* assigned by firmware, the real filter number for each pf may be less */
557 #define MAX_FD_FILTER_NUM 4096
558 #define HCLGE_ARFS_EXPIRE_INTERVAL 5UL
559
560 enum HCLGE_FD_ACTIVE_RULE_TYPE {
561 HCLGE_FD_RULE_NONE,
562 HCLGE_FD_ARFS_ACTIVE,
563 HCLGE_FD_EP_ACTIVE,
564 };
565
566 enum HCLGE_FD_PACKET_TYPE {
567 NIC_PACKET,
568 ROCE_PACKET,
569 };
570
571 enum HCLGE_FD_ACTION {
572 HCLGE_FD_ACTION_ACCEPT_PACKET,
573 HCLGE_FD_ACTION_DROP_PACKET,
574 };
575
576 struct hclge_fd_key_cfg {
577 u8 key_sel;
578 u8 inner_sipv6_word_en;
579 u8 inner_dipv6_word_en;
580 u8 outer_sipv6_word_en;
581 u8 outer_dipv6_word_en;
582 u32 tuple_active;
583 u32 meta_data_active;
584 };
585
586 struct hclge_fd_cfg {
587 u8 fd_mode;
588 u16 max_key_length; /* use bit as unit */
589 u32 rule_num[MAX_STAGE_NUM]; /* rule entry number */
590 u16 cnt_num[MAX_STAGE_NUM]; /* rule hit counter number */
591 struct hclge_fd_key_cfg key_cfg[MAX_STAGE_NUM];
592 };
593
594 #define IPV4_INDEX 3
595 #define IPV6_SIZE 4
596 struct hclge_fd_rule_tuples {
597 u8 src_mac[ETH_ALEN];
598 u8 dst_mac[ETH_ALEN];
599 /* Be compatible for ip address of both ipv4 and ipv6.
600 * For ipv4 address, we store it in src/dst_ip[3].
601 */
602 u32 src_ip[IPV6_SIZE];
603 u32 dst_ip[IPV6_SIZE];
604 u16 src_port;
605 u16 dst_port;
606 u16 vlan_tag1;
607 u16 ether_proto;
608 u8 ip_tos;
609 u8 ip_proto;
610 };
611
612 struct hclge_fd_rule {
613 struct hlist_node rule_node;
614 struct hclge_fd_rule_tuples tuples;
615 struct hclge_fd_rule_tuples tuples_mask;
616 u32 unused_tuple;
617 u32 flow_type;
618 u8 action;
619 u16 vf_id;
620 u16 queue_id;
621 u16 location;
622 u16 flow_id; /* only used for arfs */
623 enum HCLGE_FD_ACTIVE_RULE_TYPE rule_type;
624 };
625
626 struct hclge_fd_ad_data {
627 u16 ad_id;
628 u8 drop_packet;
629 u8 forward_to_direct_queue;
630 u16 queue_id;
631 u8 use_counter;
632 u8 counter_id;
633 u8 use_next_stage;
634 u8 write_rule_id_to_bd;
635 u8 next_input_key;
636 u16 rule_id;
637 };
638
639 enum HCLGE_MAC_NODE_STATE {
640 HCLGE_MAC_TO_ADD,
641 HCLGE_MAC_TO_DEL,
642 HCLGE_MAC_ACTIVE
643 };
644
645 struct hclge_mac_node {
646 struct list_head node;
647 enum HCLGE_MAC_NODE_STATE state;
648 u8 mac_addr[ETH_ALEN];
649 };
650
651 enum HCLGE_MAC_ADDR_TYPE {
652 HCLGE_MAC_ADDR_UC,
653 HCLGE_MAC_ADDR_MC
654 };
655
656 struct hclge_vport_vlan_cfg {
657 struct list_head node;
658 int hd_tbl_status;
659 u16 vlan_id;
660 };
661
662 struct hclge_rst_stats {
663 u32 reset_done_cnt; /* the number of reset has completed */
664 u32 hw_reset_done_cnt; /* the number of HW reset has completed */
665 u32 pf_rst_cnt; /* the number of PF reset */
666 u32 flr_rst_cnt; /* the number of FLR */
667 u32 global_rst_cnt; /* the number of GLOBAL */
668 u32 imp_rst_cnt; /* the number of IMP reset */
669 u32 reset_cnt; /* the number of reset */
670 u32 reset_fail_cnt; /* the number of reset fail */
671 };
672
673 /* time and register status when mac tunnel interruption occur */
674 struct hclge_mac_tnl_stats {
675 u64 time;
676 u32 status;
677 };
678
679 #define HCLGE_RESET_INTERVAL (10 * HZ)
680 #define HCLGE_WAIT_RESET_DONE 100
681
682 #pragma pack(1)
683 struct hclge_vf_vlan_cfg {
684 u8 mbx_cmd;
685 u8 subcode;
686 u8 is_kill;
687 u16 vlan;
688 u16 proto;
689 };
690
691 #pragma pack()
692
693 /* For each bit of TCAM entry, it uses a pair of 'x' and
694 * 'y' to indicate which value to match, like below:
695 * ----------------------------------
696 * | bit x | bit y | search value |
697 * ----------------------------------
698 * | 0 | 0 | always hit |
699 * ----------------------------------
700 * | 1 | 0 | match '0' |
701 * ----------------------------------
702 * | 0 | 1 | match '1' |
703 * ----------------------------------
704 * | 1 | 1 | invalid |
705 * ----------------------------------
706 * Then for input key(k) and mask(v), we can calculate the value by
707 * the formulae:
708 * x = (~k) & v
709 * y = (k ^ ~v) & k
710 */
711 #define calc_x(x, k, v) ((x) = (~(k) & (v)))
712 #define calc_y(y, k, v) \
713 do { \
714 const typeof(k) _k_ = (k); \
715 const typeof(v) _v_ = (v); \
716 (y) = (_k_ ^ ~_v_) & (_k_); \
717 } while (0)
718
719 #define HCLGE_MAC_TNL_LOG_SIZE 8
720 #define HCLGE_VPORT_NUM 256
721 struct hclge_dev {
722 struct pci_dev *pdev;
723 struct hnae3_ae_dev *ae_dev;
724 struct hclge_hw hw;
725 struct hclge_misc_vector misc_vector;
726 struct hclge_mac_stats mac_stats;
727 unsigned long state;
728 unsigned long flr_state;
729 unsigned long last_reset_time;
730
731 enum hnae3_reset_type reset_type;
732 enum hnae3_reset_type reset_level;
733 unsigned long default_reset_request;
734 unsigned long reset_request; /* reset has been requested */
735 unsigned long reset_pending; /* client rst is pending to be served */
736 struct hclge_rst_stats rst_stats;
737 struct semaphore reset_sem; /* protect reset process */
738 u32 fw_version;
739 u16 num_vmdq_vport; /* Num vmdq vport this PF has set up */
740 u16 num_tqps; /* Num task queue pairs of this PF */
741 u16 num_req_vfs; /* Num VFs requested for this PF */
742
743 u16 base_tqp_pid; /* Base task tqp physical id of this PF */
744 u16 alloc_rss_size; /* Allocated RSS task queue */
745 u16 rss_size_max; /* HW defined max RSS task queue */
746
747 u16 fdir_pf_filter_count; /* Num of guaranteed filters for this PF */
748 u16 num_alloc_vport; /* Num vports this driver supports */
749 u32 numa_node_mask;
750 u16 rx_buf_len;
751 u16 num_tx_desc; /* desc num of per tx queue */
752 u16 num_rx_desc; /* desc num of per rx queue */
753 u8 hw_tc_map;
754 enum hclge_fc_mode fc_mode_last_time;
755 u8 support_sfp_query;
756
757 #define HCLGE_FLAG_TC_BASE_SCH_MODE 1
758 #define HCLGE_FLAG_VNET_BASE_SCH_MODE 2
759 u8 tx_sch_mode;
760 u8 tc_max;
761 u8 pfc_max;
762
763 u8 default_up;
764 u8 dcbx_cap;
765 struct hclge_tm_info tm_info;
766
767 u16 num_msi;
768 u16 num_msi_left;
769 u16 num_msi_used;
770 u16 roce_base_msix_offset;
771 u32 base_msi_vector;
772 u16 *vector_status;
773 int *vector_irq;
774 u16 num_nic_msi; /* Num of nic vectors for this PF */
775 u16 num_roce_msi; /* Num of roce vectors for this PF */
776 int roce_base_vector;
777
778 unsigned long service_timer_period;
779 unsigned long service_timer_previous;
780 struct timer_list reset_timer;
781 struct delayed_work service_task;
782
783 bool cur_promisc;
784 int num_alloc_vfs; /* Actual number of VFs allocated */
785
786 struct hclge_tqp *htqp;
787 struct hclge_vport *vport;
788
789 struct dentry *hclge_dbgfs;
790
791 struct hnae3_client *nic_client;
792 struct hnae3_client *roce_client;
793
794 #define HCLGE_FLAG_MAIN BIT(0)
795 #define HCLGE_FLAG_DCB_CAPABLE BIT(1)
796 #define HCLGE_FLAG_DCB_ENABLE BIT(2)
797 #define HCLGE_FLAG_MQPRIO_ENABLE BIT(3)
798 u32 flag;
799
800 u32 pkt_buf_size; /* Total pf buf size for tx/rx */
801 u32 tx_buf_size; /* Tx buffer size for each TC */
802 u32 dv_buf_size; /* Dv buffer size for each TC */
803
804 u32 mps; /* Max packet size */
805 /* vport_lock protect resource shared by vports */
806 struct mutex vport_lock;
807
808 struct hclge_vlan_type_cfg vlan_type_cfg;
809
810 unsigned long vlan_table[VLAN_N_VID][BITS_TO_LONGS(HCLGE_VPORT_NUM)];
811 unsigned long vf_vlan_full[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
812
813 unsigned long vport_config_block[BITS_TO_LONGS(HCLGE_VPORT_NUM)];
814
815 struct hclge_fd_cfg fd_cfg;
816 struct hlist_head fd_rule_list;
817 spinlock_t fd_rule_lock; /* protect fd_rule_list and fd_bmap */
818 u16 hclge_fd_rule_num;
819 unsigned long serv_processed_cnt;
820 unsigned long last_serv_processed;
821 unsigned long fd_bmap[BITS_TO_LONGS(MAX_FD_FILTER_NUM)];
822 enum HCLGE_FD_ACTIVE_RULE_TYPE fd_active_type;
823 u8 fd_en;
824
825 u16 wanted_umv_size;
826 /* max available unicast mac vlan space */
827 u16 max_umv_size;
828 /* private unicast mac vlan space, it's same for PF and its VFs */
829 u16 priv_umv_size;
830 /* unicast mac vlan space shared by PF and its VFs */
831 u16 share_umv_size;
832
833 DECLARE_KFIFO(mac_tnl_log, struct hclge_mac_tnl_stats,
834 HCLGE_MAC_TNL_LOG_SIZE);
835
836 /* affinity mask and notify for misc interrupt */
837 cpumask_t affinity_mask;
838 struct irq_affinity_notify affinity_notify;
839 };
840
841 /* VPort level vlan tag configuration for TX direction */
842 struct hclge_tx_vtag_cfg {
843 bool accept_tag1; /* Whether accept tag1 packet from host */
844 bool accept_untag1; /* Whether accept untag1 packet from host */
845 bool accept_tag2;
846 bool accept_untag2;
847 bool insert_tag1_en; /* Whether insert inner vlan tag */
848 bool insert_tag2_en; /* Whether insert outer vlan tag */
849 u16 default_tag1; /* The default inner vlan tag to insert */
850 u16 default_tag2; /* The default outer vlan tag to insert */
851 };
852
853 /* VPort level vlan tag configuration for RX direction */
854 struct hclge_rx_vtag_cfg {
855 u8 rx_vlan_offload_en; /* Whether enable rx vlan offload */
856 u8 strip_tag1_en; /* Whether strip inner vlan tag */
857 u8 strip_tag2_en; /* Whether strip outer vlan tag */
858 u8 vlan1_vlan_prionly; /* Inner VLAN Tag up to descriptor Enable */
859 u8 vlan2_vlan_prionly; /* Outer VLAN Tag up to descriptor Enable */
860 };
861
862 struct hclge_rss_tuple_cfg {
863 u8 ipv4_tcp_en;
864 u8 ipv4_udp_en;
865 u8 ipv4_sctp_en;
866 u8 ipv4_fragment_en;
867 u8 ipv6_tcp_en;
868 u8 ipv6_udp_en;
869 u8 ipv6_sctp_en;
870 u8 ipv6_fragment_en;
871 };
872
873 enum HCLGE_VPORT_STATE {
874 HCLGE_VPORT_STATE_ALIVE,
875 HCLGE_VPORT_STATE_MAC_TBL_CHANGE,
876 HCLGE_VPORT_STATE_MAX
877 };
878
879 struct hclge_vlan_info {
880 u16 vlan_proto; /* so far support 802.1Q only */
881 u16 qos;
882 u16 vlan_tag;
883 };
884
885 struct hclge_port_base_vlan_config {
886 u16 state;
887 struct hclge_vlan_info vlan_info;
888 };
889
890 struct hclge_vf_info {
891 int link_state;
892 u8 mac[ETH_ALEN];
893 u32 spoofchk;
894 u32 max_tx_rate;
895 u32 trusted;
896 u16 promisc_enable;
897 };
898
899 struct hclge_vport {
900 u16 alloc_tqps; /* Allocated Tx/Rx queues */
901
902 u8 rss_hash_key[HCLGE_RSS_KEY_SIZE]; /* User configured hash keys */
903 /* User configured lookup table entries */
904 u8 rss_indirection_tbl[HCLGE_RSS_IND_TBL_SIZE];
905 int rss_algo; /* User configured hash algorithm */
906 /* User configured rss tuple sets */
907 struct hclge_rss_tuple_cfg rss_tuple_sets;
908
909 u16 alloc_rss_size;
910
911 u16 qs_offset;
912 u32 bw_limit; /* VSI BW Limit (0 = disabled) */
913 u8 dwrr;
914
915 unsigned long vlan_del_fail_bmap[BITS_TO_LONGS(VLAN_N_VID)];
916 struct hclge_port_base_vlan_config port_base_vlan_cfg;
917 struct hclge_tx_vtag_cfg txvlan_cfg;
918 struct hclge_rx_vtag_cfg rxvlan_cfg;
919
920 u16 used_umv_num;
921
922 u16 vport_id;
923 struct hclge_dev *back; /* Back reference to associated dev */
924 struct hnae3_handle nic;
925 struct hnae3_handle roce;
926
927 unsigned long state;
928 unsigned long last_active_jiffies;
929 u32 mps; /* Max packet size */
930 struct hclge_vf_info vf_info;
931
932 u8 overflow_promisc_flags;
933 u8 last_promisc_flags;
934
935 spinlock_t mac_list_lock; /* protect mac address need to add/detele */
936 struct list_head uc_mac_list; /* Store VF unicast table */
937 struct list_head mc_mac_list; /* Store VF multicast table */
938 struct list_head vlan_list; /* Store VF vlan table */
939 };
940
941 int hclge_set_vport_promisc_mode(struct hclge_vport *vport, bool en_uc_pmc,
942 bool en_mc_pmc, bool en_bc_pmc);
943 int hclge_add_uc_addr_common(struct hclge_vport *vport,
944 const unsigned char *addr);
945 int hclge_rm_uc_addr_common(struct hclge_vport *vport,
946 const unsigned char *addr);
947 int hclge_add_mc_addr_common(struct hclge_vport *vport,
948 const unsigned char *addr);
949 int hclge_rm_mc_addr_common(struct hclge_vport *vport,
950 const unsigned char *addr);
951
952 struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle);
953 int hclge_bind_ring_with_vector(struct hclge_vport *vport,
954 int vector_id, bool en,
955 struct hnae3_ring_chain_node *ring_chain);
956
hclge_get_queue_id(struct hnae3_queue * queue)957 static inline int hclge_get_queue_id(struct hnae3_queue *queue)
958 {
959 struct hclge_tqp *tqp = container_of(queue, struct hclge_tqp, q);
960
961 return tqp->index;
962 }
963
hclge_is_reset_pending(struct hclge_dev * hdev)964 static inline bool hclge_is_reset_pending(struct hclge_dev *hdev)
965 {
966 return !!hdev->reset_pending;
967 }
968
969 int hclge_inform_reset_assert_to_vf(struct hclge_vport *vport);
970 int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex);
971 int hclge_set_vlan_filter(struct hnae3_handle *handle, __be16 proto,
972 u16 vlan_id, bool is_kill);
973 int hclge_en_hw_strip_rxvtag(struct hnae3_handle *handle, bool enable);
974
975 int hclge_buffer_alloc(struct hclge_dev *hdev);
976 int hclge_rss_init_hw(struct hclge_dev *hdev);
977 void hclge_rss_indir_init_cfg(struct hclge_dev *hdev);
978
979 void hclge_mbx_handler(struct hclge_dev *hdev);
980 int hclge_reset_tqp(struct hnae3_handle *handle, u16 queue_id);
981 void hclge_reset_vf_queue(struct hclge_vport *vport, u16 queue_id);
982 int hclge_cfg_flowctrl(struct hclge_dev *hdev);
983 int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id);
984 int hclge_vport_start(struct hclge_vport *vport);
985 void hclge_vport_stop(struct hclge_vport *vport);
986 int hclge_set_vport_mtu(struct hclge_vport *vport, int new_mtu);
987 int hclge_dbg_run_cmd(struct hnae3_handle *handle, const char *cmd_buf);
988 u16 hclge_covert_handle_qid_global(struct hnae3_handle *handle, u16 queue_id);
989 int hclge_notify_client(struct hclge_dev *hdev,
990 enum hnae3_reset_notify_type type);
991 int hclge_update_mac_list(struct hclge_vport *vport,
992 enum HCLGE_MAC_NODE_STATE state,
993 enum HCLGE_MAC_ADDR_TYPE mac_type,
994 const unsigned char *addr);
995 int hclge_update_mac_node_for_dev_addr(struct hclge_vport *vport,
996 const u8 *old_addr, const u8 *new_addr);
997 void hclge_rm_vport_all_mac_table(struct hclge_vport *vport, bool is_del_list,
998 enum HCLGE_MAC_ADDR_TYPE mac_type);
999 void hclge_rm_vport_all_vlan_table(struct hclge_vport *vport, bool is_del_list);
1000 void hclge_uninit_vport_vlan_table(struct hclge_dev *hdev);
1001 void hclge_restore_mac_table_common(struct hclge_vport *vport);
1002 void hclge_restore_vport_vlan_table(struct hclge_vport *vport);
1003 int hclge_update_port_base_vlan_cfg(struct hclge_vport *vport, u16 state,
1004 struct hclge_vlan_info *vlan_info);
1005 int hclge_push_vf_port_base_vlan_info(struct hclge_vport *vport, u8 vfid,
1006 u16 state, u16 vlan_tag, u16 qos,
1007 u16 vlan_proto);
1008 void hclge_task_schedule(struct hclge_dev *hdev, unsigned long delay_time);
1009 int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
1010 struct hclge_desc *desc);
1011 void hclge_report_hw_error(struct hclge_dev *hdev,
1012 enum hnae3_hw_error_type type);
1013 void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
1014 void hclge_dbg_dump_rst_info(struct hclge_dev *hdev);
1015 #endif
1016
