1 /* SPDX-License-Identifier: GPL-2.0+ */
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #ifndef __HCLGE_CMD_H
5 #define __HCLGE_CMD_H
6 #include <linux/types.h>
7 #include <linux/io.h>
8 #include <linux/etherdevice.h>
9 #include "hnae3.h"
10
11 #define HCLGE_CMDQ_TX_TIMEOUT 30000
12 #define HCLGE_DESC_DATA_LEN 6
13
14 struct hclge_dev;
15 struct hclge_desc {
16 __le16 opcode;
17
18 #define HCLGE_CMDQ_RX_INVLD_B 0
19 #define HCLGE_CMDQ_RX_OUTVLD_B 1
20
21 __le16 flag;
22 __le16 retval;
23 __le16 rsv;
24 __le32 data[HCLGE_DESC_DATA_LEN];
25 };
26
27 struct hclge_cmq_ring {
28 dma_addr_t desc_dma_addr;
29 struct hclge_desc *desc;
30 struct hclge_dev *dev;
31 u32 head;
32 u32 tail;
33
34 u16 buf_size;
35 u16 desc_num;
36 int next_to_use;
37 int next_to_clean;
38 u8 ring_type; /* cmq ring type */
39 spinlock_t lock; /* Command queue lock */
40 };
41
42 enum hclge_cmd_return_status {
43 HCLGE_CMD_EXEC_SUCCESS = 0,
44 HCLGE_CMD_NO_AUTH = 1,
45 HCLGE_CMD_NOT_SUPPORTED = 2,
46 HCLGE_CMD_QUEUE_FULL = 3,
47 HCLGE_CMD_NEXT_ERR = 4,
48 HCLGE_CMD_UNEXE_ERR = 5,
49 HCLGE_CMD_PARA_ERR = 6,
50 HCLGE_CMD_RESULT_ERR = 7,
51 HCLGE_CMD_TIMEOUT = 8,
52 HCLGE_CMD_HILINK_ERR = 9,
53 HCLGE_CMD_QUEUE_ILLEGAL = 10,
54 HCLGE_CMD_INVALID = 11,
55 };
56
57 enum hclge_cmd_status {
58 HCLGE_STATUS_SUCCESS = 0,
59 HCLGE_ERR_CSQ_FULL = -1,
60 HCLGE_ERR_CSQ_TIMEOUT = -2,
61 HCLGE_ERR_CSQ_ERROR = -3,
62 };
63
64 struct hclge_misc_vector {
65 u8 __iomem *addr;
66 int vector_irq;
67 char name[HNAE3_INT_NAME_LEN];
68 };
69
70 struct hclge_cmq {
71 struct hclge_cmq_ring csq;
72 struct hclge_cmq_ring crq;
73 u16 tx_timeout;
74 enum hclge_cmd_status last_status;
75 };
76
77 #define HCLGE_CMD_FLAG_IN BIT(0)
78 #define HCLGE_CMD_FLAG_OUT BIT(1)
79 #define HCLGE_CMD_FLAG_NEXT BIT(2)
80 #define HCLGE_CMD_FLAG_WR BIT(3)
81 #define HCLGE_CMD_FLAG_NO_INTR BIT(4)
82 #define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
83
84 enum hclge_opcode_type {
85 /* Generic commands */
86 HCLGE_OPC_QUERY_FW_VER = 0x0001,
87 HCLGE_OPC_CFG_RST_TRIGGER = 0x0020,
88 HCLGE_OPC_GBL_RST_STATUS = 0x0021,
89 HCLGE_OPC_QUERY_FUNC_STATUS = 0x0022,
90 HCLGE_OPC_QUERY_PF_RSRC = 0x0023,
91 HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
92 HCLGE_OPC_GET_CFG_PARAM = 0x0025,
93 HCLGE_OPC_PF_RST_DONE = 0x0026,
94 HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
95
96 HCLGE_OPC_STATS_64_BIT = 0x0030,
97 HCLGE_OPC_STATS_32_BIT = 0x0031,
98 HCLGE_OPC_STATS_MAC = 0x0032,
99 HCLGE_OPC_QUERY_MAC_REG_NUM = 0x0033,
100 HCLGE_OPC_STATS_MAC_ALL = 0x0034,
101
102 HCLGE_OPC_QUERY_REG_NUM = 0x0040,
103 HCLGE_OPC_QUERY_32_BIT_REG = 0x0041,
104 HCLGE_OPC_QUERY_64_BIT_REG = 0x0042,
105 HCLGE_OPC_DFX_BD_NUM = 0x0043,
106 HCLGE_OPC_DFX_BIOS_COMMON_REG = 0x0044,
107 HCLGE_OPC_DFX_SSU_REG_0 = 0x0045,
108 HCLGE_OPC_DFX_SSU_REG_1 = 0x0046,
109 HCLGE_OPC_DFX_IGU_EGU_REG = 0x0047,
110 HCLGE_OPC_DFX_RPU_REG_0 = 0x0048,
111 HCLGE_OPC_DFX_RPU_REG_1 = 0x0049,
112 HCLGE_OPC_DFX_NCSI_REG = 0x004A,
113 HCLGE_OPC_DFX_RTC_REG = 0x004B,
114 HCLGE_OPC_DFX_PPP_REG = 0x004C,
115 HCLGE_OPC_DFX_RCB_REG = 0x004D,
116 HCLGE_OPC_DFX_TQP_REG = 0x004E,
117 HCLGE_OPC_DFX_SSU_REG_2 = 0x004F,
118
119 HCLGE_OPC_QUERY_DEV_SPECS = 0x0050,
120
121 /* MAC command */
122 HCLGE_OPC_CONFIG_MAC_MODE = 0x0301,
123 HCLGE_OPC_CONFIG_AN_MODE = 0x0304,
124 HCLGE_OPC_QUERY_LINK_STATUS = 0x0307,
125 HCLGE_OPC_CONFIG_MAX_FRM_SIZE = 0x0308,
126 HCLGE_OPC_CONFIG_SPEED_DUP = 0x0309,
127 HCLGE_OPC_QUERY_MAC_TNL_INT = 0x0310,
128 HCLGE_OPC_MAC_TNL_INT_EN = 0x0311,
129 HCLGE_OPC_CLEAR_MAC_TNL_INT = 0x0312,
130 HCLGE_OPC_SERDES_LOOPBACK = 0x0315,
131 HCLGE_OPC_CONFIG_FEC_MODE = 0x031A,
132
133 /* PFC/Pause commands */
134 HCLGE_OPC_CFG_MAC_PAUSE_EN = 0x0701,
135 HCLGE_OPC_CFG_PFC_PAUSE_EN = 0x0702,
136 HCLGE_OPC_CFG_MAC_PARA = 0x0703,
137 HCLGE_OPC_CFG_PFC_PARA = 0x0704,
138 HCLGE_OPC_QUERY_MAC_TX_PKT_CNT = 0x0705,
139 HCLGE_OPC_QUERY_MAC_RX_PKT_CNT = 0x0706,
140 HCLGE_OPC_QUERY_PFC_TX_PKT_CNT = 0x0707,
141 HCLGE_OPC_QUERY_PFC_RX_PKT_CNT = 0x0708,
142 HCLGE_OPC_PRI_TO_TC_MAPPING = 0x0709,
143 HCLGE_OPC_QOS_MAP = 0x070A,
144
145 /* ETS/scheduler commands */
146 HCLGE_OPC_TM_PG_TO_PRI_LINK = 0x0804,
147 HCLGE_OPC_TM_QS_TO_PRI_LINK = 0x0805,
148 HCLGE_OPC_TM_NQ_TO_QS_LINK = 0x0806,
149 HCLGE_OPC_TM_RQ_TO_QS_LINK = 0x0807,
150 HCLGE_OPC_TM_PORT_WEIGHT = 0x0808,
151 HCLGE_OPC_TM_PG_WEIGHT = 0x0809,
152 HCLGE_OPC_TM_QS_WEIGHT = 0x080A,
153 HCLGE_OPC_TM_PRI_WEIGHT = 0x080B,
154 HCLGE_OPC_TM_PRI_C_SHAPPING = 0x080C,
155 HCLGE_OPC_TM_PRI_P_SHAPPING = 0x080D,
156 HCLGE_OPC_TM_PG_C_SHAPPING = 0x080E,
157 HCLGE_OPC_TM_PG_P_SHAPPING = 0x080F,
158 HCLGE_OPC_TM_PORT_SHAPPING = 0x0810,
159 HCLGE_OPC_TM_PG_SCH_MODE_CFG = 0x0812,
160 HCLGE_OPC_TM_PRI_SCH_MODE_CFG = 0x0813,
161 HCLGE_OPC_TM_QS_SCH_MODE_CFG = 0x0814,
162 HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
163 HCLGE_OPC_ETS_TC_WEIGHT = 0x0843,
164 HCLGE_OPC_QSET_DFX_STS = 0x0844,
165 HCLGE_OPC_PRI_DFX_STS = 0x0845,
166 HCLGE_OPC_PG_DFX_STS = 0x0846,
167 HCLGE_OPC_PORT_DFX_STS = 0x0847,
168 HCLGE_OPC_SCH_NQ_CNT = 0x0848,
169 HCLGE_OPC_SCH_RQ_CNT = 0x0849,
170 HCLGE_OPC_TM_INTERNAL_STS = 0x0850,
171 HCLGE_OPC_TM_INTERNAL_CNT = 0x0851,
172 HCLGE_OPC_TM_INTERNAL_STS_1 = 0x0852,
173
174 /* Packet buffer allocate commands */
175 HCLGE_OPC_TX_BUFF_ALLOC = 0x0901,
176 HCLGE_OPC_RX_PRIV_BUFF_ALLOC = 0x0902,
177 HCLGE_OPC_RX_PRIV_WL_ALLOC = 0x0903,
178 HCLGE_OPC_RX_COM_THRD_ALLOC = 0x0904,
179 HCLGE_OPC_RX_COM_WL_ALLOC = 0x0905,
180 HCLGE_OPC_RX_GBL_PKT_CNT = 0x0906,
181
182 /* TQP management command */
183 HCLGE_OPC_SET_TQP_MAP = 0x0A01,
184
185 /* TQP commands */
186 HCLGE_OPC_CFG_TX_QUEUE = 0x0B01,
187 HCLGE_OPC_QUERY_TX_POINTER = 0x0B02,
188 HCLGE_OPC_QUERY_TX_STATS = 0x0B03,
189 HCLGE_OPC_TQP_TX_QUEUE_TC = 0x0B04,
190 HCLGE_OPC_CFG_RX_QUEUE = 0x0B11,
191 HCLGE_OPC_QUERY_RX_POINTER = 0x0B12,
192 HCLGE_OPC_QUERY_RX_STATS = 0x0B13,
193 HCLGE_OPC_STASH_RX_QUEUE_LRO = 0x0B16,
194 HCLGE_OPC_CFG_RX_QUEUE_LRO = 0x0B17,
195 HCLGE_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
196 HCLGE_OPC_RESET_TQP_QUEUE = 0x0B22,
197
198 /* PPU commands */
199 HCLGE_OPC_PPU_PF_OTHER_INT_DFX = 0x0B4A,
200
201 /* TSO command */
202 HCLGE_OPC_TSO_GENERIC_CONFIG = 0x0C01,
203 HCLGE_OPC_GRO_GENERIC_CONFIG = 0x0C10,
204
205 /* RSS commands */
206 HCLGE_OPC_RSS_GENERIC_CONFIG = 0x0D01,
207 HCLGE_OPC_RSS_INDIR_TABLE = 0x0D07,
208 HCLGE_OPC_RSS_TC_MODE = 0x0D08,
209 HCLGE_OPC_RSS_INPUT_TUPLE = 0x0D02,
210
211 /* Promisuous mode command */
212 HCLGE_OPC_CFG_PROMISC_MODE = 0x0E01,
213
214 /* Vlan offload commands */
215 HCLGE_OPC_VLAN_PORT_TX_CFG = 0x0F01,
216 HCLGE_OPC_VLAN_PORT_RX_CFG = 0x0F02,
217
218 /* Interrupts commands */
219 HCLGE_OPC_ADD_RING_TO_VECTOR = 0x1503,
220 HCLGE_OPC_DEL_RING_TO_VECTOR = 0x1504,
221
222 /* MAC commands */
223 HCLGE_OPC_MAC_VLAN_ADD = 0x1000,
224 HCLGE_OPC_MAC_VLAN_REMOVE = 0x1001,
225 HCLGE_OPC_MAC_VLAN_TYPE_ID = 0x1002,
226 HCLGE_OPC_MAC_VLAN_INSERT = 0x1003,
227 HCLGE_OPC_MAC_VLAN_ALLOCATE = 0x1004,
228 HCLGE_OPC_MAC_ETHTYPE_ADD = 0x1010,
229 HCLGE_OPC_MAC_ETHTYPE_REMOVE = 0x1011,
230
231 /* MAC VLAN commands */
232 HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
233
234 /* VLAN commands */
235 HCLGE_OPC_VLAN_FILTER_CTRL = 0x1100,
236 HCLGE_OPC_VLAN_FILTER_PF_CFG = 0x1101,
237 HCLGE_OPC_VLAN_FILTER_VF_CFG = 0x1102,
238
239 /* Flow Director commands */
240 HCLGE_OPC_FD_MODE_CTRL = 0x1200,
241 HCLGE_OPC_FD_GET_ALLOCATION = 0x1201,
242 HCLGE_OPC_FD_KEY_CONFIG = 0x1202,
243 HCLGE_OPC_FD_TCAM_OP = 0x1203,
244 HCLGE_OPC_FD_AD_OP = 0x1204,
245
246 /* MDIO command */
247 HCLGE_OPC_MDIO_CONFIG = 0x1900,
248
249 /* QCN commands */
250 HCLGE_OPC_QCN_MOD_CFG = 0x1A01,
251 HCLGE_OPC_QCN_GRP_TMPLT_CFG = 0x1A02,
252 HCLGE_OPC_QCN_SHAPPING_CFG = 0x1A03,
253 HCLGE_OPC_QCN_SHAPPING_BS_CFG = 0x1A04,
254 HCLGE_OPC_QCN_QSET_LINK_CFG = 0x1A05,
255 HCLGE_OPC_QCN_RP_STATUS_GET = 0x1A06,
256 HCLGE_OPC_QCN_AJUST_INIT = 0x1A07,
257 HCLGE_OPC_QCN_DFX_CNT_STATUS = 0x1A08,
258
259 /* Mailbox command */
260 HCLGEVF_OPC_MBX_PF_TO_VF = 0x2000,
261
262 /* Led command */
263 HCLGE_OPC_LED_STATUS_CFG = 0xB000,
264
265 /* NCL config command */
266 HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
267
268 /* M7 stats command */
269 HCLGE_OPC_M7_STATS_BD = 0x7012,
270 HCLGE_OPC_M7_STATS_INFO = 0x7013,
271 HCLGE_OPC_M7_COMPAT_CFG = 0x701A,
272
273 /* SFP command */
274 HCLGE_OPC_GET_SFP_EEPROM = 0x7100,
275 HCLGE_OPC_GET_SFP_EXIST = 0x7101,
276 HCLGE_OPC_GET_SFP_INFO = 0x7104,
277
278 /* Error INT commands */
279 HCLGE_MAC_COMMON_INT_EN = 0x030E,
280 HCLGE_TM_SCH_ECC_INT_EN = 0x0829,
281 HCLGE_SSU_ECC_INT_CMD = 0x0989,
282 HCLGE_SSU_COMMON_INT_CMD = 0x098C,
283 HCLGE_PPU_MPF_ECC_INT_CMD = 0x0B40,
284 HCLGE_PPU_MPF_OTHER_INT_CMD = 0x0B41,
285 HCLGE_PPU_PF_OTHER_INT_CMD = 0x0B42,
286 HCLGE_COMMON_ECC_INT_CFG = 0x1505,
287 HCLGE_QUERY_RAS_INT_STS_BD_NUM = 0x1510,
288 HCLGE_QUERY_CLEAR_MPF_RAS_INT = 0x1511,
289 HCLGE_QUERY_CLEAR_PF_RAS_INT = 0x1512,
290 HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
291 HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT = 0x1514,
292 HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT = 0x1515,
293 HCLGE_CONFIG_ROCEE_RAS_INT_EN = 0x1580,
294 HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
295 HCLGE_ROCEE_PF_RAS_INT_CMD = 0x1584,
296 HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD = 0x1585,
297 HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD = 0x1586,
298 HCLGE_IGU_EGU_TNL_INT_EN = 0x1803,
299 HCLGE_IGU_COMMON_INT_EN = 0x1806,
300 HCLGE_TM_QCN_MEM_INT_CFG = 0x1A14,
301 HCLGE_PPP_CMD0_INT_CMD = 0x2100,
302 HCLGE_PPP_CMD1_INT_CMD = 0x2101,
303 HCLGE_MAC_ETHERTYPE_IDX_RD = 0x2105,
304 HCLGE_NCSI_INT_EN = 0x2401,
305 };
306
307 #define HCLGE_TQP_REG_OFFSET 0x80000
308 #define HCLGE_TQP_REG_SIZE 0x200
309
310 #define HCLGE_RCB_INIT_QUERY_TIMEOUT 10
311 #define HCLGE_RCB_INIT_FLAG_EN_B 0
312 #define HCLGE_RCB_INIT_FLAG_FINI_B 8
313 struct hclge_config_rcb_init_cmd {
314 __le16 rcb_init_flag;
315 u8 rsv[22];
316 };
317
318 struct hclge_tqp_map_cmd {
319 __le16 tqp_id; /* Absolute tqp id for in this pf */
320 u8 tqp_vf; /* VF id */
321 #define HCLGE_TQP_MAP_TYPE_PF 0
322 #define HCLGE_TQP_MAP_TYPE_VF 1
323 #define HCLGE_TQP_MAP_TYPE_B 0
324 #define HCLGE_TQP_MAP_EN_B 1
325 u8 tqp_flag; /* Indicate it's pf or vf tqp */
326 __le16 tqp_vid; /* Virtual id in this pf/vf */
327 u8 rsv[18];
328 };
329
330 #define HCLGE_VECTOR_ELEMENTS_PER_CMD 10
331
332 enum hclge_int_type {
333 HCLGE_INT_TX,
334 HCLGE_INT_RX,
335 HCLGE_INT_EVENT,
336 };
337
338 struct hclge_ctrl_vector_chain_cmd {
339 u8 int_vector_id;
340 u8 int_cause_num;
341 #define HCLGE_INT_TYPE_S 0
342 #define HCLGE_INT_TYPE_M GENMASK(1, 0)
343 #define HCLGE_TQP_ID_S 2
344 #define HCLGE_TQP_ID_M GENMASK(12, 2)
345 #define HCLGE_INT_GL_IDX_S 13
346 #define HCLGE_INT_GL_IDX_M GENMASK(14, 13)
347 __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
348 u8 vfid;
349 u8 rsv;
350 };
351
352 #define HCLGE_MAX_TC_NUM 8
353 #define HCLGE_TC0_PRI_BUF_EN_B 15 /* Bit 15 indicate enable or not */
354 #define HCLGE_BUF_UNIT_S 7 /* Buf size is united by 128 bytes */
355 struct hclge_tx_buff_alloc_cmd {
356 __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
357 u8 tx_buff_rsv[8];
358 };
359
360 struct hclge_rx_priv_buff_cmd {
361 __le16 buf_num[HCLGE_MAX_TC_NUM];
362 __le16 shared_buf;
363 u8 rsv[6];
364 };
365
366 enum HCLGE_CAP_BITS {
367 HCLGE_CAP_UDP_GSO_B,
368 HCLGE_CAP_QB_B,
369 HCLGE_CAP_FD_FORWARD_TC_B,
370 HCLGE_CAP_PTP_B,
371 HCLGE_CAP_INT_QL_B,
372 HCLGE_CAP_SIMPLE_BD_B,
373 HCLGE_CAP_TX_PUSH_B,
374 HCLGE_CAP_PHY_IMP_B,
375 HCLGE_CAP_TQP_TXRX_INDEP_B,
376 HCLGE_CAP_HW_PAD_B,
377 HCLGE_CAP_STASH_B,
378 };
379
380 #define HCLGE_QUERY_CAP_LENGTH 3
381 struct hclge_query_version_cmd {
382 __le32 firmware;
383 __le32 hardware;
384 __le32 rsv;
385 __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
386 };
387
388 #define HCLGE_RX_PRIV_EN_B 15
389 #define HCLGE_TC_NUM_ONE_DESC 4
390 struct hclge_priv_wl {
391 __le16 high;
392 __le16 low;
393 };
394
395 struct hclge_rx_priv_wl_buf {
396 struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
397 };
398
399 struct hclge_rx_com_thrd {
400 struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
401 };
402
403 struct hclge_rx_com_wl {
404 struct hclge_priv_wl com_wl;
405 };
406
407 struct hclge_waterline {
408 u32 low;
409 u32 high;
410 };
411
412 struct hclge_tc_thrd {
413 u32 low;
414 u32 high;
415 };
416
417 struct hclge_priv_buf {
418 struct hclge_waterline wl; /* Waterline for low and high*/
419 u32 buf_size; /* TC private buffer size */
420 u32 tx_buf_size;
421 u32 enable; /* Enable TC private buffer or not */
422 };
423
424 struct hclge_shared_buf {
425 struct hclge_waterline self;
426 struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
427 u32 buf_size;
428 };
429
430 struct hclge_pkt_buf_alloc {
431 struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
432 struct hclge_shared_buf s_buf;
433 };
434
435 #define HCLGE_RX_COM_WL_EN_B 15
436 struct hclge_rx_com_wl_buf_cmd {
437 __le16 high_wl;
438 __le16 low_wl;
439 u8 rsv[20];
440 };
441
442 #define HCLGE_RX_PKT_EN_B 15
443 struct hclge_rx_pkt_buf_cmd {
444 __le16 high_pkt;
445 __le16 low_pkt;
446 u8 rsv[20];
447 };
448
449 #define HCLGE_PF_STATE_DONE_B 0
450 #define HCLGE_PF_STATE_MAIN_B 1
451 #define HCLGE_PF_STATE_BOND_B 2
452 #define HCLGE_PF_STATE_MAC_N_B 6
453 #define HCLGE_PF_MAC_NUM_MASK 0x3
454 #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
455 #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
456 #define HCLGE_VF_RST_STATUS_CMD 4
457
458 struct hclge_func_status_cmd {
459 __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
460 u8 pf_state;
461 u8 mac_id;
462 u8 rsv1;
463 u8 pf_cnt_in_mac;
464 u8 pf_num;
465 u8 vf_num;
466 u8 rsv[2];
467 };
468
469 struct hclge_pf_res_cmd {
470 __le16 tqp_num;
471 __le16 buf_size;
472 __le16 msixcap_localid_ba_nic;
473 __le16 msixcap_localid_ba_rocee;
474 #define HCLGE_MSIX_OFT_ROCEE_S 0
475 #define HCLGE_MSIX_OFT_ROCEE_M GENMASK(15, 0)
476 #define HCLGE_PF_VEC_NUM_S 0
477 #define HCLGE_PF_VEC_NUM_M GENMASK(7, 0)
478 __le16 pf_intr_vector_number;
479 __le16 pf_own_fun_number;
480 __le16 tx_buf_size;
481 __le16 dv_buf_size;
482 __le32 rsv[2];
483 };
484
485 #define HCLGE_CFG_OFFSET_S 0
486 #define HCLGE_CFG_OFFSET_M GENMASK(19, 0)
487 #define HCLGE_CFG_RD_LEN_S 24
488 #define HCLGE_CFG_RD_LEN_M GENMASK(27, 24)
489 #define HCLGE_CFG_RD_LEN_BYTES 16
490 #define HCLGE_CFG_RD_LEN_UNIT 4
491
492 #define HCLGE_CFG_VMDQ_S 0
493 #define HCLGE_CFG_VMDQ_M GENMASK(7, 0)
494 #define HCLGE_CFG_TC_NUM_S 8
495 #define HCLGE_CFG_TC_NUM_M GENMASK(15, 8)
496 #define HCLGE_CFG_TQP_DESC_N_S 16
497 #define HCLGE_CFG_TQP_DESC_N_M GENMASK(31, 16)
498 #define HCLGE_CFG_PHY_ADDR_S 0
499 #define HCLGE_CFG_PHY_ADDR_M GENMASK(7, 0)
500 #define HCLGE_CFG_MEDIA_TP_S 8
501 #define HCLGE_CFG_MEDIA_TP_M GENMASK(15, 8)
502 #define HCLGE_CFG_RX_BUF_LEN_S 16
503 #define HCLGE_CFG_RX_BUF_LEN_M GENMASK(31, 16)
504 #define HCLGE_CFG_MAC_ADDR_H_S 0
505 #define HCLGE_CFG_MAC_ADDR_H_M GENMASK(15, 0)
506 #define HCLGE_CFG_DEFAULT_SPEED_S 16
507 #define HCLGE_CFG_DEFAULT_SPEED_M GENMASK(23, 16)
508 #define HCLGE_CFG_RSS_SIZE_S 24
509 #define HCLGE_CFG_RSS_SIZE_M GENMASK(31, 24)
510 #define HCLGE_CFG_SPEED_ABILITY_S 0
511 #define HCLGE_CFG_SPEED_ABILITY_M GENMASK(7, 0)
512 #define HCLGE_CFG_SPEED_ABILITY_EXT_S 10
513 #define HCLGE_CFG_SPEED_ABILITY_EXT_M GENMASK(15, 10)
514 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
515 #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
516
517 #define HCLGE_CFG_CMD_CNT 4
518
519 struct hclge_cfg_param_cmd {
520 __le32 offset;
521 __le32 rsv;
522 __le32 param[HCLGE_CFG_CMD_CNT];
523 };
524
525 #define HCLGE_MAC_MODE 0x0
526 #define HCLGE_DESC_NUM 0x40
527
528 #define HCLGE_ALLOC_VALID_B 0
529 struct hclge_vf_num_cmd {
530 u8 alloc_valid;
531 u8 rsv[23];
532 };
533
534 #define HCLGE_RSS_DEFAULT_OUTPORT_B 4
535 #define HCLGE_RSS_HASH_KEY_OFFSET_B 4
536 #define HCLGE_RSS_HASH_KEY_NUM 16
537 struct hclge_rss_config_cmd {
538 u8 hash_config;
539 u8 rsv[7];
540 u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
541 };
542
543 struct hclge_rss_input_tuple_cmd {
544 u8 ipv4_tcp_en;
545 u8 ipv4_udp_en;
546 u8 ipv4_sctp_en;
547 u8 ipv4_fragment_en;
548 u8 ipv6_tcp_en;
549 u8 ipv6_udp_en;
550 u8 ipv6_sctp_en;
551 u8 ipv6_fragment_en;
552 u8 rsv[16];
553 };
554
555 #define HCLGE_RSS_CFG_TBL_SIZE 16
556
557 struct hclge_rss_indirection_table_cmd {
558 __le16 start_table_index;
559 __le16 rss_set_bitmap;
560 u8 rsv[4];
561 u8 rss_result[HCLGE_RSS_CFG_TBL_SIZE];
562 };
563
564 #define HCLGE_RSS_TC_OFFSET_S 0
565 #define HCLGE_RSS_TC_OFFSET_M GENMASK(9, 0)
566 #define HCLGE_RSS_TC_SIZE_S 12
567 #define HCLGE_RSS_TC_SIZE_M GENMASK(14, 12)
568 #define HCLGE_RSS_TC_VALID_B 15
569 struct hclge_rss_tc_mode_cmd {
570 __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
571 u8 rsv[8];
572 };
573
574 #define HCLGE_LINK_STATUS_UP_B 0
575 #define HCLGE_LINK_STATUS_UP_M BIT(HCLGE_LINK_STATUS_UP_B)
576 struct hclge_link_status_cmd {
577 u8 status;
578 u8 rsv[23];
579 };
580
581 struct hclge_promisc_param {
582 u8 vf_id;
583 u8 enable;
584 };
585
586 #define HCLGE_PROMISC_TX_EN_B BIT(4)
587 #define HCLGE_PROMISC_RX_EN_B BIT(5)
588 #define HCLGE_PROMISC_EN_B 1
589 #define HCLGE_PROMISC_EN_ALL 0x7
590 #define HCLGE_PROMISC_EN_UC 0x1
591 #define HCLGE_PROMISC_EN_MC 0x2
592 #define HCLGE_PROMISC_EN_BC 0x4
593 struct hclge_promisc_cfg_cmd {
594 u8 flag;
595 u8 vf_id;
596 __le16 rsv0;
597 u8 rsv1[20];
598 };
599
600 enum hclge_promisc_type {
601 HCLGE_UNICAST = 1,
602 HCLGE_MULTICAST = 2,
603 HCLGE_BROADCAST = 3,
604 };
605
606 #define HCLGE_MAC_TX_EN_B 6
607 #define HCLGE_MAC_RX_EN_B 7
608 #define HCLGE_MAC_PAD_TX_B 11
609 #define HCLGE_MAC_PAD_RX_B 12
610 #define HCLGE_MAC_1588_TX_B 13
611 #define HCLGE_MAC_1588_RX_B 14
612 #define HCLGE_MAC_APP_LP_B 15
613 #define HCLGE_MAC_LINE_LP_B 16
614 #define HCLGE_MAC_FCS_TX_B 17
615 #define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B 18
616 #define HCLGE_MAC_RX_FCS_STRIP_B 19
617 #define HCLGE_MAC_RX_FCS_B 20
618 #define HCLGE_MAC_TX_UNDER_MIN_ERR_B 21
619 #define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B 22
620
621 struct hclge_config_mac_mode_cmd {
622 __le32 txrx_pad_fcs_loop_en;
623 u8 rsv[20];
624 };
625
626 struct hclge_pf_rst_sync_cmd {
627 #define HCLGE_PF_RST_ALL_VF_RDY_B 0
628 u8 all_vf_ready;
629 u8 rsv[23];
630 };
631
632 #define HCLGE_CFG_SPEED_S 0
633 #define HCLGE_CFG_SPEED_M GENMASK(5, 0)
634
635 #define HCLGE_CFG_DUPLEX_B 7
636 #define HCLGE_CFG_DUPLEX_M BIT(HCLGE_CFG_DUPLEX_B)
637
638 struct hclge_config_mac_speed_dup_cmd {
639 u8 speed_dup;
640
641 #define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
642 u8 mac_change_fec_en;
643 u8 rsv[22];
644 };
645
646 #define HCLGE_RING_ID_MASK GENMASK(9, 0)
647 #define HCLGE_TQP_ENABLE_B 0
648
649 #define HCLGE_MAC_CFG_AN_EN_B 0
650 #define HCLGE_MAC_CFG_AN_INT_EN_B 1
651 #define HCLGE_MAC_CFG_AN_INT_MSK_B 2
652 #define HCLGE_MAC_CFG_AN_INT_CLR_B 3
653 #define HCLGE_MAC_CFG_AN_RST_B 4
654
655 #define HCLGE_MAC_CFG_AN_EN BIT(HCLGE_MAC_CFG_AN_EN_B)
656
657 struct hclge_config_auto_neg_cmd {
658 __le32 cfg_an_cmd_flag;
659 u8 rsv[20];
660 };
661
662 struct hclge_sfp_info_cmd {
663 __le32 speed;
664 u8 query_type; /* 0: sfp speed, 1: active speed */
665 u8 active_fec;
666 u8 autoneg; /* autoneg state */
667 u8 autoneg_ability; /* whether support autoneg */
668 __le32 speed_ability; /* speed ability for current media */
669 __le32 module_type;
670 u8 rsv[8];
671 };
672
673 #define HCLGE_MAC_CFG_FEC_AUTO_EN_B 0
674 #define HCLGE_MAC_CFG_FEC_MODE_S 1
675 #define HCLGE_MAC_CFG_FEC_MODE_M GENMASK(3, 1)
676 #define HCLGE_MAC_CFG_FEC_SET_DEF_B 0
677 #define HCLGE_MAC_CFG_FEC_CLR_DEF_B 1
678
679 #define HCLGE_MAC_FEC_OFF 0
680 #define HCLGE_MAC_FEC_BASER 1
681 #define HCLGE_MAC_FEC_RS 2
682 struct hclge_config_fec_cmd {
683 u8 fec_mode;
684 u8 default_config;
685 u8 rsv[22];
686 };
687
688 #define HCLGE_MAC_UPLINK_PORT 0x100
689
690 struct hclge_config_max_frm_size_cmd {
691 __le16 max_frm_size;
692 u8 min_frm_size;
693 u8 rsv[21];
694 };
695
696 enum hclge_mac_vlan_tbl_opcode {
697 HCLGE_MAC_VLAN_ADD, /* Add new or modify mac_vlan */
698 HCLGE_MAC_VLAN_UPDATE, /* Modify other fields of this table */
699 HCLGE_MAC_VLAN_REMOVE, /* Remove a entry through mac_vlan key */
700 HCLGE_MAC_VLAN_LKUP, /* Lookup a entry through mac_vlan key */
701 };
702
703 enum hclge_mac_vlan_add_resp_code {
704 HCLGE_ADD_UC_OVERFLOW = 2, /* ADD failed for UC overflow */
705 HCLGE_ADD_MC_OVERFLOW, /* ADD failed for MC overflow */
706 };
707
708 #define HCLGE_MAC_VLAN_BIT0_EN_B 0
709 #define HCLGE_MAC_VLAN_BIT1_EN_B 1
710 #define HCLGE_MAC_EPORT_SW_EN_B 12
711 #define HCLGE_MAC_EPORT_TYPE_B 11
712 #define HCLGE_MAC_EPORT_VFID_S 3
713 #define HCLGE_MAC_EPORT_VFID_M GENMASK(10, 3)
714 #define HCLGE_MAC_EPORT_PFID_S 0
715 #define HCLGE_MAC_EPORT_PFID_M GENMASK(2, 0)
716 struct hclge_mac_vlan_tbl_entry_cmd {
717 u8 flags;
718 u8 resp_code;
719 __le16 vlan_tag;
720 __le32 mac_addr_hi32;
721 __le16 mac_addr_lo16;
722 __le16 rsv1;
723 u8 entry_type;
724 u8 mc_mac_en;
725 __le16 egress_port;
726 __le16 egress_queue;
727 u8 rsv2[6];
728 };
729
730 #define HCLGE_UMV_SPC_ALC_B 0
731 struct hclge_umv_spc_alc_cmd {
732 u8 allocate;
733 u8 rsv1[3];
734 __le32 space_size;
735 u8 rsv2[16];
736 };
737
738 #define HCLGE_MAC_MGR_MASK_VLAN_B BIT(0)
739 #define HCLGE_MAC_MGR_MASK_MAC_B BIT(1)
740 #define HCLGE_MAC_MGR_MASK_ETHERTYPE_B BIT(2)
741
742 struct hclge_mac_mgr_tbl_entry_cmd {
743 u8 flags;
744 u8 resp_code;
745 __le16 vlan_tag;
746 u8 mac_addr[ETH_ALEN];
747 __le16 rsv1;
748 __le16 ethter_type;
749 __le16 egress_port;
750 __le16 egress_queue;
751 u8 sw_port_id_aware;
752 u8 rsv2;
753 u8 i_port_bitmap;
754 u8 i_port_direction;
755 u8 rsv3[2];
756 };
757
758 struct hclge_vlan_filter_ctrl_cmd {
759 u8 vlan_type;
760 u8 vlan_fe;
761 u8 rsv1[2];
762 u8 vf_id;
763 u8 rsv2[19];
764 };
765
766 #define HCLGE_VLAN_ID_OFFSET_STEP 160
767 #define HCLGE_VLAN_BYTE_SIZE 8
768 #define HCLGE_VLAN_OFFSET_BITMAP \
769 (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
770
771 struct hclge_vlan_filter_pf_cfg_cmd {
772 u8 vlan_offset;
773 u8 vlan_cfg;
774 u8 rsv[2];
775 u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
776 };
777
778 #define HCLGE_MAX_VF_BYTES 16
779
780 struct hclge_vlan_filter_vf_cfg_cmd {
781 __le16 vlan_id;
782 u8 resp_code;
783 u8 rsv;
784 u8 vlan_cfg;
785 u8 rsv1[3];
786 u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
787 };
788
789 #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
790 #define HCLGE_SWITCH_ALW_LPBK_B 1U
791 #define HCLGE_SWITCH_ALW_LCL_LPBK_B 2U
792 #define HCLGE_SWITCH_ALW_DST_OVRD_B 3U
793 #define HCLGE_SWITCH_NO_MASK 0x0
794 #define HCLGE_SWITCH_ANTI_SPOOF_MASK 0xFE
795 #define HCLGE_SWITCH_ALW_LPBK_MASK 0xFD
796 #define HCLGE_SWITCH_ALW_LCL_LPBK_MASK 0xFB
797 #define HCLGE_SWITCH_LW_DST_OVRD_MASK 0xF7
798
799 struct hclge_mac_vlan_switch_cmd {
800 u8 roce_sel;
801 u8 rsv1[3];
802 __le32 func_id;
803 u8 switch_param;
804 u8 rsv2[3];
805 u8 param_mask;
806 u8 rsv3[11];
807 };
808
809 enum hclge_mac_vlan_cfg_sel {
810 HCLGE_MAC_VLAN_NIC_SEL = 0,
811 HCLGE_MAC_VLAN_ROCE_SEL,
812 };
813
814 #define HCLGE_ACCEPT_TAG1_B 0
815 #define HCLGE_ACCEPT_UNTAG1_B 1
816 #define HCLGE_PORT_INS_TAG1_EN_B 2
817 #define HCLGE_PORT_INS_TAG2_EN_B 3
818 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
819 #define HCLGE_ACCEPT_TAG2_B 5
820 #define HCLGE_ACCEPT_UNTAG2_B 6
821 #define HCLGE_VF_NUM_PER_BYTE 8
822
823 struct hclge_vport_vtag_tx_cfg_cmd {
824 u8 vport_vlan_cfg;
825 u8 vf_offset;
826 u8 rsv1[2];
827 __le16 def_vlan_tag1;
828 __le16 def_vlan_tag2;
829 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
830 u8 rsv2[8];
831 };
832
833 #define HCLGE_REM_TAG1_EN_B 0
834 #define HCLGE_REM_TAG2_EN_B 1
835 #define HCLGE_SHOW_TAG1_EN_B 2
836 #define HCLGE_SHOW_TAG2_EN_B 3
837 struct hclge_vport_vtag_rx_cfg_cmd {
838 u8 vport_vlan_cfg;
839 u8 vf_offset;
840 u8 rsv1[6];
841 u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
842 u8 rsv2[8];
843 };
844
845 struct hclge_tx_vlan_type_cfg_cmd {
846 __le16 ot_vlan_type;
847 __le16 in_vlan_type;
848 u8 rsv[20];
849 };
850
851 struct hclge_rx_vlan_type_cfg_cmd {
852 __le16 ot_fst_vlan_type;
853 __le16 ot_sec_vlan_type;
854 __le16 in_fst_vlan_type;
855 __le16 in_sec_vlan_type;
856 u8 rsv[16];
857 };
858
859 struct hclge_cfg_com_tqp_queue_cmd {
860 __le16 tqp_id;
861 __le16 stream_id;
862 u8 enable;
863 u8 rsv[19];
864 };
865
866 struct hclge_cfg_tx_queue_pointer_cmd {
867 __le16 tqp_id;
868 __le16 tx_tail;
869 __le16 tx_head;
870 __le16 fbd_num;
871 __le16 ring_offset;
872 u8 rsv[14];
873 };
874
875 #pragma pack(1)
876 struct hclge_mac_ethertype_idx_rd_cmd {
877 u8 flags;
878 u8 resp_code;
879 __le16 vlan_tag;
880 u8 mac_addr[ETH_ALEN];
881 __le16 index;
882 __le16 ethter_type;
883 __le16 egress_port;
884 __le16 egress_queue;
885 __le16 rev0;
886 u8 i_port_bitmap;
887 u8 i_port_direction;
888 u8 rev1[2];
889 };
890
891 #pragma pack()
892
893 #define HCLGE_TSO_MSS_MIN_S 0
894 #define HCLGE_TSO_MSS_MIN_M GENMASK(13, 0)
895
896 #define HCLGE_TSO_MSS_MAX_S 16
897 #define HCLGE_TSO_MSS_MAX_M GENMASK(29, 16)
898
899 struct hclge_cfg_tso_status_cmd {
900 __le16 tso_mss_min;
901 __le16 tso_mss_max;
902 u8 rsv[20];
903 };
904
905 #define HCLGE_GRO_EN_B 0
906 struct hclge_cfg_gro_status_cmd {
907 u8 gro_en;
908 u8 rsv[23];
909 };
910
911 #define HCLGE_TSO_MSS_MIN 256
912 #define HCLGE_TSO_MSS_MAX 9668
913
914 #define HCLGE_TQP_RESET_B 0
915 struct hclge_reset_tqp_queue_cmd {
916 __le16 tqp_id;
917 u8 reset_req;
918 u8 ready_to_reset;
919 u8 rsv[20];
920 };
921
922 #define HCLGE_CFG_RESET_MAC_B 3
923 #define HCLGE_CFG_RESET_FUNC_B 7
924 struct hclge_reset_cmd {
925 u8 mac_func_reset;
926 u8 fun_reset_vfid;
927 u8 rsv[22];
928 };
929
930 #define HCLGE_PF_RESET_DONE_BIT BIT(0)
931
932 struct hclge_pf_rst_done_cmd {
933 u8 pf_rst_done;
934 u8 rsv[23];
935 };
936
937 #define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B BIT(0)
938 #define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B BIT(2)
939 #define HCLGE_CMD_SERDES_DONE_B BIT(0)
940 #define HCLGE_CMD_SERDES_SUCCESS_B BIT(1)
941 struct hclge_serdes_lb_cmd {
942 u8 mask;
943 u8 enable;
944 u8 result;
945 u8 rsv[21];
946 };
947
948 #define HCLGE_DEFAULT_TX_BUF 0x4000 /* 16k bytes */
949 #define HCLGE_TOTAL_PKT_BUF 0x108000 /* 1.03125M bytes */
950 #define HCLGE_DEFAULT_DV 0xA000 /* 40k byte */
951 #define HCLGE_DEFAULT_NON_DCB_DV 0x7800 /* 30K byte */
952 #define HCLGE_NON_DCB_ADDITIONAL_BUF 0x1400 /* 5120 byte */
953
954 #define HCLGE_TYPE_CRQ 0
955 #define HCLGE_TYPE_CSQ 1
956 #define HCLGE_NIC_CSQ_BASEADDR_L_REG 0x27000
957 #define HCLGE_NIC_CSQ_BASEADDR_H_REG 0x27004
958 #define HCLGE_NIC_CSQ_DEPTH_REG 0x27008
959 #define HCLGE_NIC_CSQ_TAIL_REG 0x27010
960 #define HCLGE_NIC_CSQ_HEAD_REG 0x27014
961 #define HCLGE_NIC_CRQ_BASEADDR_L_REG 0x27018
962 #define HCLGE_NIC_CRQ_BASEADDR_H_REG 0x2701c
963 #define HCLGE_NIC_CRQ_DEPTH_REG 0x27020
964 #define HCLGE_NIC_CRQ_TAIL_REG 0x27024
965 #define HCLGE_NIC_CRQ_HEAD_REG 0x27028
966
967 /* this bit indicates that the driver is ready for hardware reset */
968 #define HCLGE_NIC_SW_RST_RDY_B 16
969 #define HCLGE_NIC_SW_RST_RDY BIT(HCLGE_NIC_SW_RST_RDY_B)
970
971 #define HCLGE_NIC_CMQ_DESC_NUM 1024
972 #define HCLGE_NIC_CMQ_DESC_NUM_S 3
973
974 #define HCLGE_LED_LOCATE_STATE_S 0
975 #define HCLGE_LED_LOCATE_STATE_M GENMASK(1, 0)
976
977 struct hclge_set_led_state_cmd {
978 u8 rsv1[3];
979 u8 locate_led_config;
980 u8 rsv2[20];
981 };
982
983 struct hclge_get_fd_mode_cmd {
984 u8 mode;
985 u8 enable;
986 u8 rsv[22];
987 };
988
989 struct hclge_get_fd_allocation_cmd {
990 __le32 stage1_entry_num;
991 __le32 stage2_entry_num;
992 __le16 stage1_counter_num;
993 __le16 stage2_counter_num;
994 u8 rsv[12];
995 };
996
997 struct hclge_set_fd_key_config_cmd {
998 u8 stage;
999 u8 key_select;
1000 u8 inner_sipv6_word_en;
1001 u8 inner_dipv6_word_en;
1002 u8 outer_sipv6_word_en;
1003 u8 outer_dipv6_word_en;
1004 u8 rsv1[2];
1005 __le32 tuple_mask;
1006 __le32 meta_data_mask;
1007 u8 rsv2[8];
1008 };
1009
1010 #define HCLGE_FD_EPORT_SW_EN_B 0
1011 struct hclge_fd_tcam_config_1_cmd {
1012 u8 stage;
1013 u8 xy_sel;
1014 u8 port_info;
1015 u8 rsv1[1];
1016 __le32 index;
1017 u8 entry_vld;
1018 u8 rsv2[7];
1019 u8 tcam_data[8];
1020 };
1021
1022 struct hclge_fd_tcam_config_2_cmd {
1023 u8 tcam_data[24];
1024 };
1025
1026 struct hclge_fd_tcam_config_3_cmd {
1027 u8 tcam_data[20];
1028 u8 rsv[4];
1029 };
1030
1031 #define HCLGE_FD_AD_DROP_B 0
1032 #define HCLGE_FD_AD_DIRECT_QID_B 1
1033 #define HCLGE_FD_AD_QID_S 2
1034 #define HCLGE_FD_AD_QID_M GENMASK(12, 2)
1035 #define HCLGE_FD_AD_USE_COUNTER_B 12
1036 #define HCLGE_FD_AD_COUNTER_NUM_S 13
1037 #define HCLGE_FD_AD_COUNTER_NUM_M GENMASK(20, 13)
1038 #define HCLGE_FD_AD_NXT_STEP_B 20
1039 #define HCLGE_FD_AD_NXT_KEY_S 21
1040 #define HCLGE_FD_AD_NXT_KEY_M GENMASK(26, 21)
1041 #define HCLGE_FD_AD_WR_RULE_ID_B 0
1042 #define HCLGE_FD_AD_RULE_ID_S 1
1043 #define HCLGE_FD_AD_RULE_ID_M GENMASK(13, 1)
1044
1045 struct hclge_fd_ad_config_cmd {
1046 u8 stage;
1047 u8 rsv1[3];
1048 __le32 index;
1049 __le64 ad_data;
1050 u8 rsv2[8];
1051 };
1052
1053 struct hclge_get_m7_bd_cmd {
1054 __le32 bd_num;
1055 u8 rsv[20];
1056 };
1057
1058 struct hclge_query_ppu_pf_other_int_dfx_cmd {
1059 __le16 over_8bd_no_fe_qid;
1060 __le16 over_8bd_no_fe_vf_id;
1061 __le16 tso_mss_cmp_min_err_qid;
1062 __le16 tso_mss_cmp_min_err_vf_id;
1063 __le16 tso_mss_cmp_max_err_qid;
1064 __le16 tso_mss_cmp_max_err_vf_id;
1065 __le16 tx_rd_fbd_poison_qid;
1066 __le16 tx_rd_fbd_poison_vf_id;
1067 __le16 rx_rd_fbd_poison_qid;
1068 __le16 rx_rd_fbd_poison_vf_id;
1069 u8 rsv[4];
1070 };
1071
1072 #define HCLGE_LINK_EVENT_REPORT_EN_B 0
1073 #define HCLGE_NCSI_ERROR_REPORT_EN_B 1
1074 struct hclge_firmware_compat_cmd {
1075 __le32 compat;
1076 u8 rsv[20];
1077 };
1078
1079 #define HCLGE_SFP_INFO_CMD_NUM 6
1080 #define HCLGE_SFP_INFO_BD0_LEN 20
1081 #define HCLGE_SFP_INFO_BDX_LEN 24
1082 #define HCLGE_SFP_INFO_MAX_LEN \
1083 (HCLGE_SFP_INFO_BD0_LEN + \
1084 (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1085
1086 struct hclge_sfp_info_bd0_cmd {
1087 __le16 offset;
1088 __le16 read_len;
1089 u8 data[HCLGE_SFP_INFO_BD0_LEN];
1090 };
1091
1092 #define HCLGE_QUERY_DEV_SPECS_BD_NUM 4
1093
1094 struct hclge_dev_specs_0_cmd {
1095 __le32 rsv0;
1096 __le32 mac_entry_num;
1097 __le32 mng_entry_num;
1098 __le16 rss_ind_tbl_size;
1099 __le16 rss_key_size;
1100 __le16 int_ql_max;
1101 u8 max_non_tso_bd_num;
1102 u8 rsv1;
1103 __le32 max_tm_rate;
1104 };
1105
1106 int hclge_cmd_init(struct hclge_dev *hdev);
hclge_write_reg(void __iomem * base,u32 reg,u32 value)1107 static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1108 {
1109 writel(value, base + reg);
1110 }
1111
1112 #define hclge_write_dev(a, reg, value) \
1113 hclge_write_reg((a)->io_base, (reg), (value))
1114 #define hclge_read_dev(a, reg) \
1115 hclge_read_reg((a)->io_base, (reg))
1116
hclge_read_reg(u8 __iomem * base,u32 reg)1117 static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1118 {
1119 u8 __iomem *reg_addr = READ_ONCE(base);
1120
1121 return readl(reg_addr + reg);
1122 }
1123
1124 #define HCLGE_SEND_SYNC(flag) \
1125 ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1126
1127 struct hclge_hw;
1128 int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1129 void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1130 enum hclge_opcode_type opcode, bool is_read);
1131 void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1132
1133 enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1134 struct hclge_desc *desc);
1135 enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1136 struct hclge_desc *desc);
1137
1138 void hclge_cmd_uninit(struct hclge_dev *hdev);
1139 int hclge_cmd_queue_init(struct hclge_dev *hdev);
1140 #endif
1141
