1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_DEVICE_H__ 7 #define __INTEL_DISPLAY_DEVICE_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_limits.h" 12 13 struct drm_i915_private; 14 struct drm_printer; 15 16 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 17 /* Keep in alphabetical order */ \ 18 func(cursor_needs_physical); \ 19 func(has_cdclk_crawl); \ 20 func(has_cdclk_squash); \ 21 func(has_ddi); \ 22 func(has_dp_mst); \ 23 func(has_dsb); \ 24 func(has_fpga_dbg); \ 25 func(has_gmch); \ 26 func(has_hotplug); \ 27 func(has_hti); \ 28 func(has_ipc); \ 29 func(has_overlay); \ 30 func(has_psr); \ 31 func(has_psr_hw_tracking); \ 32 func(overlay_needs_physical); \ 33 func(supports_tv); 34 35 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 36 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) 37 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) 38 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && DISPLAY_VER(i915) >= 7) 39 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) 40 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) 41 #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) 42 #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) 43 #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) 44 #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) 45 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 46 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) 47 #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) 48 #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) 49 #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) 50 #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) 51 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) > 2) 52 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) 53 #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915)) 54 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch) 55 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 56 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc) 57 #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915)) 58 #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) 59 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 60 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 61 #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) 62 #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) 63 #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) 64 #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) 65 #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) 66 #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ 67 BIT(trans)) != 0) 68 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 69 #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) 70 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) 71 #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) 72 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 73 74 struct intel_display_runtime_info { 75 struct { 76 u16 ver; 77 u16 rel; 78 u16 step; 79 } ip; 80 81 u8 pipe_mask; 82 u8 cpu_transcoder_mask; 83 u16 port_mask; 84 85 u8 num_sprites[I915_MAX_PIPES]; 86 u8 num_scalers[I915_MAX_PIPES]; 87 88 u8 fbc_mask; 89 90 bool has_hdcp; 91 bool has_dmc; 92 bool has_dsc; 93 }; 94 95 struct intel_display_device_info { 96 /* Initial runtime info. */ 97 const struct intel_display_runtime_info __runtime_defaults; 98 99 u8 abox_mask; 100 101 struct { 102 u16 size; /* in blocks */ 103 u8 slice_mask; 104 } dbuf; 105 106 #define DEFINE_FLAG(name) u8 name:1 107 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 108 #undef DEFINE_FLAG 109 110 /* Global register offset for the display engine */ 111 u32 mmio_offset; 112 113 /* Register offsets for the various display pipes and transcoders */ 114 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 115 u32 trans_offsets[I915_MAX_TRANSCODERS]; 116 u32 cursor_offsets[I915_MAX_PIPES]; 117 118 struct { 119 u32 degamma_lut_size; 120 u32 gamma_lut_size; 121 u32 degamma_lut_tests; 122 u32 gamma_lut_tests; 123 } color; 124 }; 125 126 const struct intel_display_device_info * 127 intel_display_device_probe(struct drm_i915_private *i915, bool has_gmdid, 128 u16 *ver, u16 *rel, u16 *step); 129 void intel_display_device_info_runtime_init(struct drm_i915_private *i915); 130 131 void intel_display_device_info_print(const struct intel_display_device_info *info, 132 const struct intel_display_runtime_info *runtime, 133 struct drm_printer *p); 134 135 #endif 136
