1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Hantro VPU codec driver
4 *
5 * Copyright 2018 Google LLC.
6 * Tomasz Figa <tfiga@chromium.org>
7 *
8 * Based on s5p-mfc driver by Samsung Electronics Co., Ltd.
9 * Copyright (C) 2011 Samsung Electronics Co., Ltd.
10 */
11
12 #ifndef HANTRO_H_
13 #define HANTRO_H_
14
15 #include <linux/platform_device.h>
16 #include <linux/videodev2.h>
17 #include <linux/wait.h>
18 #include <linux/clk.h>
19
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-ioctl.h>
23 #include <media/v4l2-mem2mem.h>
24 #include <media/videobuf2-core.h>
25 #include <media/videobuf2-dma-contig.h>
26
27 #include "hantro_hw.h"
28
29 struct hantro_ctx;
30 struct hantro_codec_ops;
31
32 #define HANTRO_JPEG_ENCODER BIT(0)
33 #define HANTRO_ENCODERS 0x0000ffff
34 #define HANTRO_MPEG2_DECODER BIT(16)
35 #define HANTRO_VP8_DECODER BIT(17)
36 #define HANTRO_H264_DECODER BIT(18)
37 #define HANTRO_HEVC_DECODER BIT(19)
38 #define HANTRO_DECODERS 0xffff0000
39
40 /**
41 * struct hantro_irq - irq handler and name
42 *
43 * @name: irq name for device tree lookup
44 * @handler: interrupt handler
45 */
46 struct hantro_irq {
47 const char *name;
48 irqreturn_t (*handler)(int irq, void *priv);
49 };
50
51 /**
52 * struct hantro_variant - information about VPU hardware variant
53 *
54 * @enc_offset: Offset from VPU base to encoder registers.
55 * @dec_offset: Offset from VPU base to decoder registers.
56 * @enc_fmts: Encoder formats.
57 * @num_enc_fmts: Number of encoder formats.
58 * @dec_fmts: Decoder formats.
59 * @num_dec_fmts: Number of decoder formats.
60 * @postproc_fmts: Post-processor formats.
61 * @num_postproc_fmts: Number of post-processor formats.
62 * @codec: Supported codecs
63 * @codec_ops: Codec ops.
64 * @init: Initialize hardware, optional.
65 * @runtime_resume: reenable hardware after power gating, optional.
66 * @irqs: array of irq names and interrupt handlers
67 * @num_irqs: number of irqs in the array
68 * @clk_names: array of clock names
69 * @num_clocks: number of clocks in the array
70 * @reg_names: array of register range names
71 * @num_regs: number of register range names in the array
72 * @postproc_regs: &struct hantro_postproc_regs pointer
73 */
74 struct hantro_variant {
75 unsigned int enc_offset;
76 unsigned int dec_offset;
77 const struct hantro_fmt *enc_fmts;
78 unsigned int num_enc_fmts;
79 const struct hantro_fmt *dec_fmts;
80 unsigned int num_dec_fmts;
81 const struct hantro_fmt *postproc_fmts;
82 unsigned int num_postproc_fmts;
83 unsigned int codec;
84 const struct hantro_codec_ops *codec_ops;
85 int (*init)(struct hantro_dev *vpu);
86 int (*runtime_resume)(struct hantro_dev *vpu);
87 const struct hantro_irq *irqs;
88 int num_irqs;
89 const char * const *clk_names;
90 int num_clocks;
91 const char * const *reg_names;
92 int num_regs;
93 const struct hantro_postproc_regs *postproc_regs;
94 };
95
96 /**
97 * enum hantro_codec_mode - codec operating mode.
98 * @HANTRO_MODE_NONE: No operating mode. Used for RAW video formats.
99 * @HANTRO_MODE_JPEG_ENC: JPEG encoder.
100 * @HANTRO_MODE_H264_DEC: H264 decoder.
101 * @HANTRO_MODE_MPEG2_DEC: MPEG-2 decoder.
102 * @HANTRO_MODE_VP8_DEC: VP8 decoder.
103 * @HANTRO_MODE_HEVC_DEC: HEVC decoder.
104 */
105 enum hantro_codec_mode {
106 HANTRO_MODE_NONE = -1,
107 HANTRO_MODE_JPEG_ENC,
108 HANTRO_MODE_H264_DEC,
109 HANTRO_MODE_MPEG2_DEC,
110 HANTRO_MODE_VP8_DEC,
111 HANTRO_MODE_HEVC_DEC,
112 };
113
114 /*
115 * struct hantro_ctrl - helper type to declare supported controls
116 * @codec: codec id this control belong to (HANTRO_JPEG_ENCODER, etc.)
117 * @cfg: control configuration
118 */
119 struct hantro_ctrl {
120 unsigned int codec;
121 struct v4l2_ctrl_config cfg;
122 };
123
124 /*
125 * struct hantro_func - Hantro VPU functionality
126 *
127 * @id: processing functionality ID (can be
128 * %MEDIA_ENT_F_PROC_VIDEO_ENCODER or
129 * %MEDIA_ENT_F_PROC_VIDEO_DECODER)
130 * @vdev: &struct video_device that exposes the encoder or
131 * decoder functionality
132 * @source_pad: &struct media_pad with the source pad.
133 * @sink: &struct media_entity pointer with the sink entity
134 * @sink_pad: &struct media_pad with the sink pad.
135 * @proc: &struct media_entity pointer with the M2M device itself.
136 * @proc_pads: &struct media_pad with the @proc pads.
137 * @intf_devnode: &struct media_intf devnode pointer with the interface
138 * with controls the M2M device.
139 *
140 * Contains everything needed to attach the video device to the media device.
141 */
142 struct hantro_func {
143 unsigned int id;
144 struct video_device vdev;
145 struct media_pad source_pad;
146 struct media_entity sink;
147 struct media_pad sink_pad;
148 struct media_entity proc;
149 struct media_pad proc_pads[2];
150 struct media_intf_devnode *intf_devnode;
151 };
152
153 static inline struct hantro_func *
hantro_vdev_to_func(struct video_device * vdev)154 hantro_vdev_to_func(struct video_device *vdev)
155 {
156 return container_of(vdev, struct hantro_func, vdev);
157 }
158
159 /**
160 * struct hantro_dev - driver data
161 * @v4l2_dev: V4L2 device to register video devices for.
162 * @m2m_dev: mem2mem device associated to this device.
163 * @mdev: media device associated to this device.
164 * @encoder: encoder functionality.
165 * @decoder: decoder functionality.
166 * @pdev: Pointer to VPU platform device.
167 * @dev: Pointer to device for convenient logging using
168 * dev_ macros.
169 * @clocks: Array of clock handles.
170 * @reg_bases: Mapped addresses of VPU registers.
171 * @enc_base: Mapped address of VPU encoder register for convenience.
172 * @dec_base: Mapped address of VPU decoder register for convenience.
173 * @ctrl_base: Mapped address of VPU control block.
174 * @vpu_mutex: Mutex to synchronize V4L2 calls.
175 * @irqlock: Spinlock to synchronize access to data structures
176 * shared with interrupt handlers.
177 * @variant: Hardware variant-specific parameters.
178 * @watchdog_work: Delayed work for hardware timeout handling.
179 */
180 struct hantro_dev {
181 struct v4l2_device v4l2_dev;
182 struct v4l2_m2m_dev *m2m_dev;
183 struct media_device mdev;
184 struct hantro_func *encoder;
185 struct hantro_func *decoder;
186 struct platform_device *pdev;
187 struct device *dev;
188 struct clk_bulk_data *clocks;
189 void __iomem **reg_bases;
190 void __iomem *enc_base;
191 void __iomem *dec_base;
192 void __iomem *ctrl_base;
193
194 struct mutex vpu_mutex; /* video_device lock */
195 spinlock_t irqlock;
196 const struct hantro_variant *variant;
197 struct delayed_work watchdog_work;
198 };
199
200 /**
201 * struct hantro_ctx - Context (instance) private data.
202 *
203 * @dev: VPU driver data to which the context belongs.
204 * @fh: V4L2 file handler.
205 * @is_encoder: Decoder or encoder context?
206 *
207 * @sequence_cap: Sequence counter for capture queue
208 * @sequence_out: Sequence counter for output queue
209 *
210 * @vpu_src_fmt: Descriptor of active source format.
211 * @src_fmt: V4L2 pixel format of active source format.
212 * @vpu_dst_fmt: Descriptor of active destination format.
213 * @dst_fmt: V4L2 pixel format of active destination format.
214 *
215 * @ctrl_handler: Control handler used to register controls.
216 * @jpeg_quality: User-specified JPEG compression quality.
217 *
218 * @codec_ops: Set of operations related to codec mode.
219 * @postproc: Post-processing context.
220 * @h264_dec: H.264-decoding context.
221 * @jpeg_enc: JPEG-encoding context.
222 * @mpeg2_dec: MPEG-2-decoding context.
223 * @vp8_dec: VP8-decoding context.
224 * @hevc_dec: HEVC-decoding context.
225 */
226 struct hantro_ctx {
227 struct hantro_dev *dev;
228 struct v4l2_fh fh;
229 bool is_encoder;
230
231 u32 sequence_cap;
232 u32 sequence_out;
233
234 const struct hantro_fmt *vpu_src_fmt;
235 struct v4l2_pix_format_mplane src_fmt;
236 const struct hantro_fmt *vpu_dst_fmt;
237 struct v4l2_pix_format_mplane dst_fmt;
238
239 struct v4l2_ctrl_handler ctrl_handler;
240 int jpeg_quality;
241
242 const struct hantro_codec_ops *codec_ops;
243 struct hantro_postproc_ctx postproc;
244
245 /* Specific for particular codec modes. */
246 union {
247 struct hantro_h264_dec_hw_ctx h264_dec;
248 struct hantro_jpeg_enc_hw_ctx jpeg_enc;
249 struct hantro_mpeg2_dec_hw_ctx mpeg2_dec;
250 struct hantro_vp8_dec_hw_ctx vp8_dec;
251 struct hantro_hevc_dec_hw_ctx hevc_dec;
252 };
253 };
254
255 /**
256 * struct hantro_fmt - information about supported video formats.
257 * @name: Human readable name of the format.
258 * @fourcc: FourCC code of the format. See V4L2_PIX_FMT_*.
259 * @codec_mode: Codec mode related to this format. See
260 * enum hantro_codec_mode.
261 * @header_size: Optional header size. Currently used by JPEG encoder.
262 * @max_depth: Maximum depth, for bitstream formats
263 * @enc_fmt: Format identifier for encoder registers.
264 * @frmsize: Supported range of frame sizes (only for bitstream formats).
265 */
266 struct hantro_fmt {
267 char *name;
268 u32 fourcc;
269 enum hantro_codec_mode codec_mode;
270 int header_size;
271 int max_depth;
272 enum hantro_enc_fmt enc_fmt;
273 struct v4l2_frmsize_stepwise frmsize;
274 };
275
276 struct hantro_reg {
277 u32 base;
278 u32 shift;
279 u32 mask;
280 };
281
282 struct hantro_postproc_regs {
283 struct hantro_reg pipeline_en;
284 struct hantro_reg max_burst;
285 struct hantro_reg clk_gate;
286 struct hantro_reg out_swap32;
287 struct hantro_reg out_endian;
288 struct hantro_reg out_luma_base;
289 struct hantro_reg input_width;
290 struct hantro_reg input_height;
291 struct hantro_reg output_width;
292 struct hantro_reg output_height;
293 struct hantro_reg input_fmt;
294 struct hantro_reg output_fmt;
295 struct hantro_reg orig_width;
296 struct hantro_reg display_width;
297 };
298
299 /* Logging helpers */
300
301 /**
302 * DOC: hantro_debug: Module parameter to control level of debugging messages.
303 *
304 * Level of debugging messages can be controlled by bits of
305 * module parameter called "debug". Meaning of particular
306 * bits is as follows:
307 *
308 * bit 0 - global information: mode, size, init, release
309 * bit 1 - each run start/result information
310 * bit 2 - contents of small controls from userspace
311 * bit 3 - contents of big controls from userspace
312 * bit 4 - detail fmt, ctrl, buffer q/dq information
313 * bit 5 - detail function enter/leave trace information
314 * bit 6 - register write/read information
315 */
316 extern int hantro_debug;
317
318 #define vpu_debug(level, fmt, args...) \
319 do { \
320 if (hantro_debug & BIT(level)) \
321 pr_info("%s:%d: " fmt, \
322 __func__, __LINE__, ##args); \
323 } while (0)
324
325 #define vpu_err(fmt, args...) \
326 pr_err("%s:%d: " fmt, __func__, __LINE__, ##args)
327
328 /* Structure access helpers. */
fh_to_ctx(struct v4l2_fh * fh)329 static inline struct hantro_ctx *fh_to_ctx(struct v4l2_fh *fh)
330 {
331 return container_of(fh, struct hantro_ctx, fh);
332 }
333
334 /* Register accessors. */
vepu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)335 static inline void vepu_write_relaxed(struct hantro_dev *vpu,
336 u32 val, u32 reg)
337 {
338 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
339 writel_relaxed(val, vpu->enc_base + reg);
340 }
341
vepu_write(struct hantro_dev * vpu,u32 val,u32 reg)342 static inline void vepu_write(struct hantro_dev *vpu, u32 val, u32 reg)
343 {
344 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
345 writel(val, vpu->enc_base + reg);
346 }
347
vepu_read(struct hantro_dev * vpu,u32 reg)348 static inline u32 vepu_read(struct hantro_dev *vpu, u32 reg)
349 {
350 u32 val = readl(vpu->enc_base + reg);
351
352 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
353 return val;
354 }
355
vdpu_write_relaxed(struct hantro_dev * vpu,u32 val,u32 reg)356 static inline void vdpu_write_relaxed(struct hantro_dev *vpu,
357 u32 val, u32 reg)
358 {
359 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
360 writel_relaxed(val, vpu->dec_base + reg);
361 }
362
vdpu_write(struct hantro_dev * vpu,u32 val,u32 reg)363 static inline void vdpu_write(struct hantro_dev *vpu, u32 val, u32 reg)
364 {
365 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
366 writel(val, vpu->dec_base + reg);
367 }
368
vdpu_read(struct hantro_dev * vpu,u32 reg)369 static inline u32 vdpu_read(struct hantro_dev *vpu, u32 reg)
370 {
371 u32 val = readl(vpu->dec_base + reg);
372
373 vpu_debug(6, "0x%04x = 0x%08x\n", reg / 4, val);
374 return val;
375 }
376
vdpu_read_mask(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)377 static inline u32 vdpu_read_mask(struct hantro_dev *vpu,
378 const struct hantro_reg *reg,
379 u32 val)
380 {
381 u32 v;
382
383 v = vdpu_read(vpu, reg->base);
384 v &= ~(reg->mask << reg->shift);
385 v |= ((val & reg->mask) << reg->shift);
386 return v;
387 }
388
hantro_reg_write(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)389 static inline void hantro_reg_write(struct hantro_dev *vpu,
390 const struct hantro_reg *reg,
391 u32 val)
392 {
393 vdpu_write_relaxed(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
394 }
395
hantro_reg_write_s(struct hantro_dev * vpu,const struct hantro_reg * reg,u32 val)396 static inline void hantro_reg_write_s(struct hantro_dev *vpu,
397 const struct hantro_reg *reg,
398 u32 val)
399 {
400 vdpu_write(vpu, vdpu_read_mask(vpu, reg, val), reg->base);
401 }
402
403 void *hantro_get_ctrl(struct hantro_ctx *ctx, u32 id);
404 dma_addr_t hantro_get_ref(struct hantro_ctx *ctx, u64 ts);
405
406 static inline struct vb2_v4l2_buffer *
hantro_get_src_buf(struct hantro_ctx * ctx)407 hantro_get_src_buf(struct hantro_ctx *ctx)
408 {
409 return v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
410 }
411
412 static inline struct vb2_v4l2_buffer *
hantro_get_dst_buf(struct hantro_ctx * ctx)413 hantro_get_dst_buf(struct hantro_ctx *ctx)
414 {
415 return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
416 }
417
418 bool hantro_needs_postproc(const struct hantro_ctx *ctx,
419 const struct hantro_fmt *fmt);
420
421 static inline dma_addr_t
hantro_get_dec_buf_addr(struct hantro_ctx * ctx,struct vb2_buffer * vb)422 hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb)
423 {
424 if (hantro_needs_postproc(ctx, ctx->vpu_dst_fmt))
425 return ctx->postproc.dec_q[vb->index].dma;
426 return vb2_dma_contig_plane_dma_addr(vb, 0);
427 }
428
429 void hantro_postproc_disable(struct hantro_ctx *ctx);
430 void hantro_postproc_enable(struct hantro_ctx *ctx);
431 void hantro_postproc_free(struct hantro_ctx *ctx);
432 int hantro_postproc_alloc(struct hantro_ctx *ctx);
433
434 #endif /* HANTRO_H_ */
435
