1 // SPDX-License-Identifier: GPL-2.0 2 /****************************************************************************** 3 * 4 * Copyright(c) 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 #include "../halmac_88xx_cfg.h" 15 #include "halmac_8822b_cfg.h" 16 17 /** 18 * ============ip sel item list============ 19 * HALMAC_IP_SEL_INTF_PHY 20 * USB2 : usb2 phy, 1byte value 21 * USB3 : usb3 phy, 2byte value 22 * PCIE1 : pcie gen1 mdio, 2byte value 23 * PCIE2 : pcie gen2 mdio, 2byte value 24 * HALMAC_IP_SEL_MAC 25 * USB2, USB3, PCIE1, PCIE2 : mac ip, 1byte value 26 * HALMAC_IP_SEL_PCIE_DBI 27 * USB2 USB3 : none 28 * PCIE1, PCIE2 : pcie dbi, 1byte value 29 */ 30 31 struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB2_PHY[] = { 32 /* {offset, value, ip sel, cut mask, platform mask} */ 33 {0xFFFF, 0x00, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, 34 HALMAC_INTF_PHY_PLATFORM_ALL}, 35 }; 36 37 struct halmac_intf_phy_para_ HALMAC_RTL8822B_USB3_PHY[] = { 38 /* {offset, value, ip sel, cut mask, platform mask} */ 39 {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_D, 40 HALMAC_INTF_PHY_PLATFORM_ALL}, 41 {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, 42 HALMAC_INTF_PHY_PLATFORM_ALL}, 43 }; 44 45 struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN1[] = { 46 /* {offset, value, ip sel, cut mask, platform mask} */ 47 {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 48 HALMAC_INTF_PHY_PLATFORM_ALL}, 49 {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 50 HALMAC_INTF_PHY_PLATFORM_ALL}, 51 {0x0008, 0x3596, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 52 HALMAC_INTF_PHY_PLATFORM_ALL}, 53 {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 54 HALMAC_INTF_PHY_PLATFORM_ALL}, 55 {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 56 HALMAC_INTF_PHY_PLATFORM_ALL}, 57 {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 58 HALMAC_INTF_PHY_PLATFORM_ALL}, 59 {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 60 HALMAC_INTF_PHY_PLATFORM_ALL}, 61 {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 62 HALMAC_INTF_PHY_PLATFORM_ALL}, 63 {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 64 HALMAC_INTF_PHY_PLATFORM_ALL}, 65 {0x002A, 0x1840, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 66 HALMAC_INTF_PHY_PLATFORM_ALL}, 67 {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, 68 HALMAC_INTF_PHY_PLATFORM_ALL}, 69 }; 70 71 struct halmac_intf_phy_para_ HALMAC_RTL8822B_PCIE_PHY_GEN2[] = { 72 /* {offset, value, ip sel, cut mask, platform mask} */ 73 {0x0001, 0xA841, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 74 HALMAC_INTF_PHY_PLATFORM_ALL}, 75 {0x0002, 0x60C6, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 76 HALMAC_INTF_PHY_PLATFORM_ALL}, 77 {0x0008, 0x3597, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 78 HALMAC_INTF_PHY_PLATFORM_ALL}, 79 {0x0009, 0x321C, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 80 HALMAC_INTF_PHY_PLATFORM_ALL}, 81 {0x000A, 0x9623, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 82 HALMAC_INTF_PHY_PLATFORM_ALL}, 83 {0x0020, 0x94FF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 84 HALMAC_INTF_PHY_PLATFORM_ALL}, 85 {0x0021, 0xFFCF, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 86 HALMAC_INTF_PHY_PLATFORM_ALL}, 87 {0x0026, 0xC006, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 88 HALMAC_INTF_PHY_PLATFORM_ALL}, 89 {0x0029, 0xFF0E, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 90 HALMAC_INTF_PHY_PLATFORM_ALL}, 91 {0x002A, 0x3040, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_C, 92 HALMAC_INTF_PHY_PLATFORM_ALL}, 93 {0xFFFF, 0x0000, HALMAC_IP_SEL_INTF_PHY, HALMAC_INTF_PHY_CUT_ALL, 94 HALMAC_INTF_PHY_PLATFORM_ALL}, 95 }; 96