1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 #ifndef HALMAC_POWER_SEQUENCE_CMD 15 #define HALMAC_POWER_SEQUENCE_CMD 16 17 #include "halmac_2_platform.h" 18 #include "halmac_type.h" 19 20 #define HALMAC_POLLING_READY_TIMEOUT_COUNT 20000 21 22 /* The value of cmd : 4 bits */ 23 24 /* offset : the read register offset 25 * msk : the mask of the read value 26 * value : N/A, left by 0 27 * Note : dirver shall implement this function by read & msk 28 */ 29 #define HALMAC_PWR_CMD_READ 0x00 30 /* 31 * offset: the read register offset 32 * msk: the mask of the write bits 33 * value: write value 34 * Note: driver shall implement this cmd by read & msk after write 35 */ 36 #define HALMAC_PWR_CMD_WRITE 0x01 37 /* offset: the read register offset 38 * msk: the mask of the polled value 39 * value: the value to be polled, masked by the msd field. 40 * Note: driver shall implement this cmd by 41 * do{ 42 * if( (Read(offset) & msk) == (value & msk) ) 43 * break; 44 * } while(not timeout); 45 */ 46 #define HALMAC_PWR_CMD_POLLING 0x02 47 /* offset: the value to delay 48 * msk: N/A 49 * value: the unit of delay, 0: us, 1: ms 50 */ 51 #define HALMAC_PWR_CMD_DELAY 0x03 52 /* offset: N/A 53 * msk: N/A 54 * value: N/A 55 */ 56 #define HALMAC_PWR_CMD_END 0x04 57 58 /* The value of base : 4 bits */ 59 60 /* define the base address of each block */ 61 #define HALMAC_PWR_BASEADDR_MAC 0x00 62 #define HALMAC_PWR_BASEADDR_USB 0x01 63 #define HALMAC_PWR_BASEADDR_PCIE 0x02 64 #define HALMAC_PWR_BASEADDR_SDIO 0x03 65 66 /* The value of interface_msk : 4 bits */ 67 #define HALMAC_PWR_INTF_SDIO_MSK BIT(0) 68 #define HALMAC_PWR_INTF_USB_MSK BIT(1) 69 #define HALMAC_PWR_INTF_PCI_MSK BIT(2) 70 #define HALMAC_PWR_INTF_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 71 72 /* The value of fab_msk : 4 bits */ 73 #define HALMAC_PWR_FAB_TSMC_MSK BIT(0) 74 #define HALMAC_PWR_FAB_UMC_MSK BIT(1) 75 #define HALMAC_PWR_FAB_ALL_MSK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 76 77 /* The value of cut_msk : 8 bits */ 78 #define HALMAC_PWR_CUT_TESTCHIP_MSK BIT(0) 79 #define HALMAC_PWR_CUT_A_MSK BIT(1) 80 #define HALMAC_PWR_CUT_B_MSK BIT(2) 81 #define HALMAC_PWR_CUT_C_MSK BIT(3) 82 #define HALMAC_PWR_CUT_D_MSK BIT(4) 83 #define HALMAC_PWR_CUT_E_MSK BIT(5) 84 #define HALMAC_PWR_CUT_F_MSK BIT(6) 85 #define HALMAC_PWR_CUT_G_MSK BIT(7) 86 #define HALMAC_PWR_CUT_ALL_MSK 0xFF 87 88 enum halmac_pwrseq_cmd_delay_unit_ { 89 HALMAC_PWRSEQ_DELAY_US, 90 HALMAC_PWRSEQ_DELAY_MS, 91 }; 92 93 /*Don't care endian issue, because element of pwer seq vector is fixed address*/ 94 struct halmac_wl_pwr_cfg_ { 95 u16 offset; 96 u8 cut_msk; 97 u8 fab_msk : 4; 98 u8 interface_msk : 4; 99 u8 base : 4; 100 u8 cmd : 4; 101 u8 msk; 102 u8 value; 103 }; 104 105 #endif 106
