1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright © 2014-2019 Intel Corporation
4 */
5
6 #ifndef _INTEL_GUC_FWIF_H
7 #define _INTEL_GUC_FWIF_H
8
9 #include <linux/bits.h>
10 #include <linux/compiler.h>
11 #include <linux/types.h>
12 #include "gt/intel_engine_types.h"
13
14 #include "abi/guc_actions_abi.h"
15 #include "abi/guc_actions_slpc_abi.h"
16 #include "abi/guc_errors_abi.h"
17 #include "abi/guc_communication_mmio_abi.h"
18 #include "abi/guc_communication_ctb_abi.h"
19 #include "abi/guc_klvs_abi.h"
20 #include "abi/guc_messages_abi.h"
21
22 /* Payload length only i.e. don't include G2H header length */
23 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2
24 #define G2H_LEN_DW_DEREGISTER_CONTEXT 1
25
26 #define GUC_CONTEXT_DISABLE 0
27 #define GUC_CONTEXT_ENABLE 1
28
29 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0
30 #define GUC_CLIENT_PRIORITY_HIGH 1
31 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2
32 #define GUC_CLIENT_PRIORITY_NORMAL 3
33 #define GUC_CLIENT_PRIORITY_NUM 4
34
35 #define GUC_MAX_CONTEXT_ID 65535
36 #define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID
37
38 #define GUC_RENDER_ENGINE 0
39 #define GUC_VIDEO_ENGINE 1
40 #define GUC_BLITTER_ENGINE 2
41 #define GUC_VIDEOENHANCE_ENGINE 3
42 #define GUC_VIDEO_ENGINE2 4
43 #define GUC_MAX_ENGINES_NUM (GUC_VIDEO_ENGINE2 + 1)
44
45 #define GUC_RENDER_CLASS 0
46 #define GUC_VIDEO_CLASS 1
47 #define GUC_VIDEOENHANCE_CLASS 2
48 #define GUC_BLITTER_CLASS 3
49 #define GUC_COMPUTE_CLASS 4
50 #define GUC_LAST_ENGINE_CLASS GUC_COMPUTE_CLASS
51 #define GUC_MAX_ENGINE_CLASSES 16
52 #define GUC_MAX_INSTANCES_PER_CLASS 32
53
54 #define GUC_DOORBELL_INVALID 256
55
56 /*
57 * Work queue item header definitions
58 *
59 * Work queue is circular buffer used to submit complex (multi-lrc) submissions
60 * to the GuC. A work queue item is an entry in the circular buffer.
61 */
62 #define WQ_STATUS_ACTIVE 1
63 #define WQ_STATUS_SUSPENDED 2
64 #define WQ_STATUS_CMD_ERROR 3
65 #define WQ_STATUS_ENGINE_ID_NOT_USED 4
66 #define WQ_STATUS_SUSPENDED_FROM_RESET 5
67 #define WQ_TYPE_BATCH_BUF 0x1
68 #define WQ_TYPE_PSEUDO 0x2
69 #define WQ_TYPE_INORDER 0x3
70 #define WQ_TYPE_NOOP 0x4
71 #define WQ_TYPE_MULTI_LRC 0x5
72 #define WQ_TYPE_MASK GENMASK(7, 0)
73 #define WQ_LEN_MASK GENMASK(26, 16)
74
75 #define WQ_GUC_ID_MASK GENMASK(15, 0)
76 #define WQ_RING_TAIL_MASK GENMASK(28, 18)
77
78 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0)
79 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1)
80 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2)
81 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3)
82 #define GUC_STAGE_DESC_ATTR_RESET BIT(4)
83 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5)
84 #define GUC_STAGE_DESC_ATTR_PCH BIT(6)
85 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7)
86
87 #define GUC_CTL_LOG_PARAMS 0
88 #define GUC_LOG_VALID BIT(0)
89 #define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1)
90 #define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2)
91 #define GUC_LOG_LOG_ALLOC_UNITS BIT(3)
92 #define GUC_LOG_CRASH_SHIFT 4
93 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT)
94 #define GUC_LOG_DEBUG_SHIFT 6
95 #define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT)
96 #define GUC_LOG_CAPTURE_SHIFT 10
97 #define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT)
98 #define GUC_LOG_BUF_ADDR_SHIFT 12
99
100 #define GUC_CTL_WA 1
101 #define GUC_WA_GAM_CREDITS BIT(10)
102 #define GUC_WA_DUAL_QUEUE BIT(11)
103 #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13)
104 #define GUC_WA_CONTEXT_ISOLATION BIT(15)
105 #define GUC_WA_PRE_PARSER BIT(14)
106 #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17)
107 #define GUC_WA_POLLCS BIT(18)
108 #define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21)
109
110 #define GUC_CTL_FEATURE 2
111 #define GUC_CTL_ENABLE_SLPC BIT(2)
112 #define GUC_CTL_DISABLE_SCHEDULER BIT(14)
113
114 #define GUC_CTL_DEBUG 3
115 #define GUC_LOG_VERBOSITY_SHIFT 0
116 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT)
117 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT)
118 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT)
119 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT)
120 /* Verbosity range-check limits, without the shift */
121 #define GUC_LOG_VERBOSITY_MIN 0
122 #define GUC_LOG_VERBOSITY_MAX 3
123 #define GUC_LOG_VERBOSITY_MASK 0x0000000f
124 #define GUC_LOG_DESTINATION_MASK (3 << 4)
125 #define GUC_LOG_DISABLED (1 << 6)
126 #define GUC_PROFILE_ENABLED (1 << 7)
127
128 #define GUC_CTL_ADS 4
129 #define GUC_ADS_ADDR_SHIFT 1
130 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT)
131
132 #define GUC_CTL_DEVID 5
133
134 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */
135
136 /* Generic GT SysInfo data types */
137 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0
138 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1
139 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2
140 #define GUC_GENERIC_GT_SYSINFO_MAX 16
141
142 /*
143 * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6].
144 * Bit 7 can be used for operations that apply to all engine classes&instances.
145 */
146 #define GUC_ENGINE_CLASS_SHIFT 0
147 #define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT)
148 #define GUC_ENGINE_INSTANCE_SHIFT 3
149 #define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT)
150 #define GUC_ENGINE_ALL_INSTANCES BIT(7)
151
152 #define MAKE_GUC_ID(class, instance) \
153 (((class) << GUC_ENGINE_CLASS_SHIFT) | \
154 ((instance) << GUC_ENGINE_INSTANCE_SHIFT))
155
156 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \
157 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT)
158 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \
159 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT)
160
161 #define SLPC_EVENT(id, c) (\
162 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \
163 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \
164 )
165
166 /* the GuC arrays don't include OTHER_CLASS */
167 static u8 engine_class_guc_class_map[] = {
168 [RENDER_CLASS] = GUC_RENDER_CLASS,
169 [COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS,
170 [VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS,
171 [VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS,
172 [COMPUTE_CLASS] = GUC_COMPUTE_CLASS,
173 };
174
175 static u8 guc_class_engine_class_map[] = {
176 [GUC_RENDER_CLASS] = RENDER_CLASS,
177 [GUC_BLITTER_CLASS] = COPY_ENGINE_CLASS,
178 [GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS,
179 [GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS,
180 [GUC_COMPUTE_CLASS] = COMPUTE_CLASS,
181 };
182
engine_class_to_guc_class(u8 class)183 static inline u8 engine_class_to_guc_class(u8 class)
184 {
185 BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1);
186 GEM_BUG_ON(class > MAX_ENGINE_CLASS || class == OTHER_CLASS);
187
188 return engine_class_guc_class_map[class];
189 }
190
guc_class_to_engine_class(u8 guc_class)191 static inline u8 guc_class_to_engine_class(u8 guc_class)
192 {
193 BUILD_BUG_ON(ARRAY_SIZE(guc_class_engine_class_map) != GUC_LAST_ENGINE_CLASS + 1);
194 GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS);
195
196 return guc_class_engine_class_map[guc_class];
197 }
198
199 /* Work item for submitting workloads into work queue of GuC. */
200 struct guc_wq_item {
201 u32 header;
202 u32 context_desc;
203 u32 submit_element_info;
204 u32 fence_id;
205 } __packed;
206
207 struct guc_process_desc_v69 {
208 u32 stage_id;
209 u64 db_base_addr;
210 u32 head;
211 u32 tail;
212 u32 error_offset;
213 u64 wq_base_addr;
214 u32 wq_size_bytes;
215 u32 wq_status;
216 u32 engine_presence;
217 u32 priority;
218 u32 reserved[36];
219 } __packed;
220
221 struct guc_sched_wq_desc {
222 u32 head;
223 u32 tail;
224 u32 error_offset;
225 u32 wq_status;
226 u32 reserved[28];
227 } __packed;
228
229 /* Helper for context registration H2G */
230 struct guc_ctxt_registration_info {
231 u32 flags;
232 u32 context_idx;
233 u32 engine_class;
234 u32 engine_submit_mask;
235 u32 wq_desc_lo;
236 u32 wq_desc_hi;
237 u32 wq_base_lo;
238 u32 wq_base_hi;
239 u32 wq_size;
240 u32 hwlrca_lo;
241 u32 hwlrca_hi;
242 };
243 #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0)
244
245 /* Preempt to idle on quantum expiry */
246 #define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE_V69 BIT(0)
247
248 /*
249 * GuC Context registration descriptor.
250 * FIXME: This is only required to exist during context registration.
251 * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC
252 * is not required.
253 */
254 struct guc_lrc_desc_v69 {
255 u32 hw_context_desc;
256 u32 slpm_perf_mode_hint; /* SPLC v1 only */
257 u32 slpm_freq_hint;
258 u32 engine_submit_mask; /* In logical space */
259 u8 engine_class;
260 u8 reserved0[3];
261 u32 priority;
262 u32 process_desc;
263 u32 wq_addr;
264 u32 wq_size;
265 u32 context_flags; /* CONTEXT_REGISTRATION_* */
266 /* Time for one workload to execute. (in micro seconds) */
267 u32 execution_quantum;
268 /* Time to wait for a preemption request to complete before issuing a
269 * reset. (in micro seconds).
270 */
271 u32 preemption_timeout;
272 u32 policy_flags; /* CONTEXT_POLICY_* */
273 u32 reserved1[19];
274 } __packed;
275
276 /* 32-bit KLV structure as used by policy updates and others */
277 struct guc_klv_generic_dw_t {
278 u32 kl;
279 u32 value;
280 } __packed;
281
282 /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */
283 struct guc_update_context_policy_header {
284 u32 action;
285 u32 ctx_id;
286 } __packed;
287
288 struct guc_update_context_policy {
289 struct guc_update_context_policy_header header;
290 struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS];
291 } __packed;
292
293 #define GUC_POWER_UNSPECIFIED 0
294 #define GUC_POWER_D0 1
295 #define GUC_POWER_D1 2
296 #define GUC_POWER_D2 3
297 #define GUC_POWER_D3 4
298
299 /* Scheduling policy settings */
300
301 #define GLOBAL_POLICY_MAX_NUM_WI 15
302
303 /* Don't reset an engine upon preemption failure */
304 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0)
305
306 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000
307
308 struct guc_policies {
309 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES];
310 /* In micro seconds. How much time to allow before DPC processing is
311 * called back via interrupt (to prevent DPC queue drain starving).
312 * Typically 1000s of micro seconds (example only, not granularity). */
313 u32 dpc_promote_time;
314
315 /* Must be set to take these new values. */
316 u32 is_valid;
317
318 /* Max number of WIs to process per call. A large value may keep CS
319 * idle. */
320 u32 max_num_work_items;
321
322 u32 global_flags;
323 u32 reserved[4];
324 } __packed;
325
326 /* GuC MMIO reg state struct */
327 struct guc_mmio_reg {
328 u32 offset;
329 u32 value;
330 u32 flags;
331 #define GUC_REGSET_MASKED BIT(0)
332 #define GUC_REGSET_NEEDS_STEERING BIT(1)
333 #define GUC_REGSET_MASKED_WITH_VALUE BIT(2)
334 #define GUC_REGSET_RESTORE_ONLY BIT(3)
335 #define GUC_REGSET_STEERING_GROUP GENMASK(15, 12)
336 #define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20)
337 u32 mask;
338 } __packed;
339
340 /* GuC register sets */
341 struct guc_mmio_reg_set {
342 u32 address;
343 u16 count;
344 u16 reserved;
345 } __packed;
346
347 /* HW info */
348 struct guc_gt_system_info {
349 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
350 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES];
351 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX];
352 } __packed;
353
354 enum {
355 GUC_CAPTURE_LIST_INDEX_PF = 0,
356 GUC_CAPTURE_LIST_INDEX_VF = 1,
357 GUC_CAPTURE_LIST_INDEX_MAX = 2,
358 };
359
360 /*Register-types of GuC capture register lists */
361 enum guc_capture_type {
362 GUC_CAPTURE_LIST_TYPE_GLOBAL = 0,
363 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS,
364 GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE,
365 GUC_CAPTURE_LIST_TYPE_MAX,
366 };
367
368 /* GuC Additional Data Struct */
369 struct guc_ads {
370 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
371 u32 reserved0;
372 u32 scheduler_policies;
373 u32 gt_system_info;
374 u32 reserved1;
375 u32 control_data;
376 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES];
377 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES];
378 u32 private_data;
379 u32 reserved2;
380 u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
381 u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES];
382 u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX];
383 u32 reserved[14];
384 } __packed;
385
386 /* Engine usage stats */
387 struct guc_engine_usage_record {
388 u32 current_context_index;
389 u32 last_switch_in_stamp;
390 u32 reserved0;
391 u32 total_runtime;
392 u32 reserved1[4];
393 } __packed;
394
395 struct guc_engine_usage {
396 struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS];
397 } __packed;
398
399 /* GuC logging structures */
400
401 enum guc_log_buffer_type {
402 GUC_DEBUG_LOG_BUFFER,
403 GUC_CRASH_DUMP_LOG_BUFFER,
404 GUC_CAPTURE_LOG_BUFFER,
405 GUC_MAX_LOG_BUFFER
406 };
407
408 /**
409 * struct guc_log_buffer_state - GuC log buffer state
410 *
411 * Below state structure is used for coordination of retrieval of GuC firmware
412 * logs. Separate state is maintained for each log buffer type.
413 * read_ptr points to the location where i915 read last in log buffer and
414 * is read only for GuC firmware. write_ptr is incremented by GuC with number
415 * of bytes written for each log entry and is read only for i915.
416 * When any type of log buffer becomes half full, GuC sends a flush interrupt.
417 * GuC firmware expects that while it is writing to 2nd half of the buffer,
418 * first half would get consumed by Host and then get a flush completed
419 * acknowledgment from Host, so that it does not end up doing any overwrite
420 * causing loss of logs. So when buffer gets half filled & i915 has requested
421 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr
422 * to the value of write_ptr and raise the interrupt.
423 * On receiving the interrupt i915 should read the buffer, clear flush_to_file
424 * field and also update read_ptr with the value of sample_write_ptr, before
425 * sending an acknowledgment to GuC. marker & version fields are for internal
426 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every
427 * time GuC detects the log buffer overflow.
428 */
429 struct guc_log_buffer_state {
430 u32 marker[2];
431 u32 read_ptr;
432 u32 write_ptr;
433 u32 size;
434 u32 sampled_write_ptr;
435 u32 wrap_offset;
436 union {
437 struct {
438 u32 flush_to_file:1;
439 u32 buffer_full_cnt:4;
440 u32 reserved:27;
441 };
442 u32 flags;
443 };
444 u32 version;
445 } __packed;
446
447 struct guc_ctx_report {
448 u32 report_return_status;
449 u32 reserved1[64];
450 u32 affected_count;
451 u32 reserved2[2];
452 } __packed;
453
454 /* GuC Shared Context Data Struct */
455 struct guc_shared_ctx_data {
456 u32 addr_of_last_preempted_data_low;
457 u32 addr_of_last_preempted_data_high;
458 u32 addr_of_last_preempted_data_high_tmp;
459 u32 padding;
460 u32 is_mapped_to_proxy;
461 u32 proxy_ctx_id;
462 u32 engine_reset_ctx_id;
463 u32 media_reset_count;
464 u32 reserved1[8];
465 u32 uk_last_ctx_switch_reason;
466 u32 was_reset;
467 u32 lrca_gpu_addr;
468 u64 execlist_ctx;
469 u32 reserved2[66];
470 struct guc_ctx_report preempt_ctx_report[GUC_MAX_ENGINES_NUM];
471 } __packed;
472
473 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */
474 enum intel_guc_recv_message {
475 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1),
476 INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30),
477 };
478
479 #endif
480
