1 /* 2 * Copyright (c) 2014-2017 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #ifndef __BCMGENET_H__ 10 #define __BCMGENET_H__ 11 12 #include <linux/skbuff.h> 13 #include <linux/netdevice.h> 14 #include <linux/spinlock.h> 15 #include <linux/clk.h> 16 #include <linux/mii.h> 17 #include <linux/if_vlan.h> 18 #include <linux/phy.h> 19 #include <linux/net_dim.h> 20 21 /* total number of Buffer Descriptors, same for Rx/Tx */ 22 #define TOTAL_DESC 256 23 24 /* which ring is descriptor based */ 25 #define DESC_INDEX 16 26 27 /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528. 28 * 1536 is multiple of 256 bytes 29 */ 30 #define ENET_BRCM_TAG_LEN 6 31 #define ENET_PAD 8 32 #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + VLAN_HLEN + \ 33 ENET_BRCM_TAG_LEN + ETH_FCS_LEN + ENET_PAD) 34 #define DMA_MAX_BURST_LENGTH 0x10 35 36 /* misc. configuration */ 37 #define CLEAR_ALL_HFB 0xFF 38 #define DMA_FC_THRESH_HI (TOTAL_DESC >> 4) 39 #define DMA_FC_THRESH_LO 5 40 41 /* 64B receive/transmit status block */ 42 struct status_64 { 43 u32 length_status; /* length and peripheral status */ 44 u32 ext_status; /* Extended status*/ 45 u32 rx_csum; /* partial rx checksum */ 46 u32 unused1[9]; /* unused */ 47 u32 tx_csum_info; /* Tx checksum info. */ 48 u32 unused2[3]; /* unused */ 49 }; 50 51 /* Rx status bits */ 52 #define STATUS_RX_EXT_MASK 0x1FFFFF 53 #define STATUS_RX_CSUM_MASK 0xFFFF 54 #define STATUS_RX_CSUM_OK 0x10000 55 #define STATUS_RX_CSUM_FR 0x20000 56 #define STATUS_RX_PROTO_TCP 0 57 #define STATUS_RX_PROTO_UDP 1 58 #define STATUS_RX_PROTO_ICMP 2 59 #define STATUS_RX_PROTO_OTHER 3 60 #define STATUS_RX_PROTO_MASK 3 61 #define STATUS_RX_PROTO_SHIFT 18 62 #define STATUS_FILTER_INDEX_MASK 0xFFFF 63 /* Tx status bits */ 64 #define STATUS_TX_CSUM_START_MASK 0X7FFF 65 #define STATUS_TX_CSUM_START_SHIFT 16 66 #define STATUS_TX_CSUM_PROTO_UDP 0x8000 67 #define STATUS_TX_CSUM_OFFSET_MASK 0x7FFF 68 #define STATUS_TX_CSUM_LV 0x80000000 69 70 /* DMA Descriptor */ 71 #define DMA_DESC_LENGTH_STATUS 0x00 /* in bytes of data in buffer */ 72 #define DMA_DESC_ADDRESS_LO 0x04 /* lower bits of PA */ 73 #define DMA_DESC_ADDRESS_HI 0x08 /* upper 32 bits of PA, GENETv4+ */ 74 75 /* Rx/Tx common counter group */ 76 struct bcmgenet_pkt_counters { 77 u32 cnt_64; /* RO Received/Transmited 64 bytes packet */ 78 u32 cnt_127; /* RO Rx/Tx 127 bytes packet */ 79 u32 cnt_255; /* RO Rx/Tx 65-255 bytes packet */ 80 u32 cnt_511; /* RO Rx/Tx 256-511 bytes packet */ 81 u32 cnt_1023; /* RO Rx/Tx 512-1023 bytes packet */ 82 u32 cnt_1518; /* RO Rx/Tx 1024-1518 bytes packet */ 83 u32 cnt_mgv; /* RO Rx/Tx 1519-1522 good VLAN packet */ 84 u32 cnt_2047; /* RO Rx/Tx 1522-2047 bytes packet*/ 85 u32 cnt_4095; /* RO Rx/Tx 2048-4095 bytes packet*/ 86 u32 cnt_9216; /* RO Rx/Tx 4096-9216 bytes packet*/ 87 }; 88 89 /* RSV, Receive Status Vector */ 90 struct bcmgenet_rx_counters { 91 struct bcmgenet_pkt_counters pkt_cnt; 92 u32 pkt; /* RO (0x428) Received pkt count*/ 93 u32 bytes; /* RO Received byte count */ 94 u32 mca; /* RO # of Received multicast pkt */ 95 u32 bca; /* RO # of Receive broadcast pkt */ 96 u32 fcs; /* RO # of Received FCS error */ 97 u32 cf; /* RO # of Received control frame pkt*/ 98 u32 pf; /* RO # of Received pause frame pkt */ 99 u32 uo; /* RO # of unknown op code pkt */ 100 u32 aln; /* RO # of alignment error count */ 101 u32 flr; /* RO # of frame length out of range count */ 102 u32 cde; /* RO # of code error pkt */ 103 u32 fcr; /* RO # of carrier sense error pkt */ 104 u32 ovr; /* RO # of oversize pkt*/ 105 u32 jbr; /* RO # of jabber count */ 106 u32 mtue; /* RO # of MTU error pkt*/ 107 u32 pok; /* RO # of Received good pkt */ 108 u32 uc; /* RO # of unicast pkt */ 109 u32 ppp; /* RO # of PPP pkt */ 110 u32 rcrc; /* RO (0x470),# of CRC match pkt */ 111 }; 112 113 /* TSV, Transmit Status Vector */ 114 struct bcmgenet_tx_counters { 115 struct bcmgenet_pkt_counters pkt_cnt; 116 u32 pkts; /* RO (0x4a8) Transmited pkt */ 117 u32 mca; /* RO # of xmited multicast pkt */ 118 u32 bca; /* RO # of xmited broadcast pkt */ 119 u32 pf; /* RO # of xmited pause frame count */ 120 u32 cf; /* RO # of xmited control frame count */ 121 u32 fcs; /* RO # of xmited FCS error count */ 122 u32 ovr; /* RO # of xmited oversize pkt */ 123 u32 drf; /* RO # of xmited deferral pkt */ 124 u32 edf; /* RO # of xmited Excessive deferral pkt*/ 125 u32 scl; /* RO # of xmited single collision pkt */ 126 u32 mcl; /* RO # of xmited multiple collision pkt*/ 127 u32 lcl; /* RO # of xmited late collision pkt */ 128 u32 ecl; /* RO # of xmited excessive collision pkt*/ 129 u32 frg; /* RO # of xmited fragments pkt*/ 130 u32 ncl; /* RO # of xmited total collision count */ 131 u32 jbr; /* RO # of xmited jabber count*/ 132 u32 bytes; /* RO # of xmited byte count */ 133 u32 pok; /* RO # of xmited good pkt */ 134 u32 uc; /* RO (0x0x4f0)# of xmited unitcast pkt */ 135 }; 136 137 struct bcmgenet_mib_counters { 138 struct bcmgenet_rx_counters rx; 139 struct bcmgenet_tx_counters tx; 140 u32 rx_runt_cnt; 141 u32 rx_runt_fcs; 142 u32 rx_runt_fcs_align; 143 u32 rx_runt_bytes; 144 u32 rbuf_ovflow_cnt; 145 u32 rbuf_err_cnt; 146 u32 mdf_err_cnt; 147 u32 alloc_rx_buff_failed; 148 u32 rx_dma_failed; 149 u32 tx_dma_failed; 150 }; 151 152 #define UMAC_HD_BKP_CTRL 0x004 153 #define HD_FC_EN (1 << 0) 154 #define HD_FC_BKOFF_OK (1 << 1) 155 #define IPG_CONFIG_RX_SHIFT 2 156 #define IPG_CONFIG_RX_MASK 0x1F 157 158 #define UMAC_CMD 0x008 159 #define CMD_TX_EN (1 << 0) 160 #define CMD_RX_EN (1 << 1) 161 #define UMAC_SPEED_10 0 162 #define UMAC_SPEED_100 1 163 #define UMAC_SPEED_1000 2 164 #define UMAC_SPEED_2500 3 165 #define CMD_SPEED_SHIFT 2 166 #define CMD_SPEED_MASK 3 167 #define CMD_PROMISC (1 << 4) 168 #define CMD_PAD_EN (1 << 5) 169 #define CMD_CRC_FWD (1 << 6) 170 #define CMD_PAUSE_FWD (1 << 7) 171 #define CMD_RX_PAUSE_IGNORE (1 << 8) 172 #define CMD_TX_ADDR_INS (1 << 9) 173 #define CMD_HD_EN (1 << 10) 174 #define CMD_SW_RESET (1 << 13) 175 #define CMD_LCL_LOOP_EN (1 << 15) 176 #define CMD_AUTO_CONFIG (1 << 22) 177 #define CMD_CNTL_FRM_EN (1 << 23) 178 #define CMD_NO_LEN_CHK (1 << 24) 179 #define CMD_RMT_LOOP_EN (1 << 25) 180 #define CMD_PRBL_EN (1 << 27) 181 #define CMD_TX_PAUSE_IGNORE (1 << 28) 182 #define CMD_TX_RX_EN (1 << 29) 183 #define CMD_RUNT_FILTER_DIS (1 << 30) 184 185 #define UMAC_MAC0 0x00C 186 #define UMAC_MAC1 0x010 187 #define UMAC_MAX_FRAME_LEN 0x014 188 189 #define UMAC_MODE 0x44 190 #define MODE_LINK_STATUS (1 << 5) 191 192 #define UMAC_EEE_CTRL 0x064 193 #define EN_LPI_RX_PAUSE (1 << 0) 194 #define EN_LPI_TX_PFC (1 << 1) 195 #define EN_LPI_TX_PAUSE (1 << 2) 196 #define EEE_EN (1 << 3) 197 #define RX_FIFO_CHECK (1 << 4) 198 #define EEE_TX_CLK_DIS (1 << 5) 199 #define DIS_EEE_10M (1 << 6) 200 #define LP_IDLE_PREDICTION_MODE (1 << 7) 201 202 #define UMAC_EEE_LPI_TIMER 0x068 203 #define UMAC_EEE_WAKE_TIMER 0x06C 204 #define UMAC_EEE_REF_COUNT 0x070 205 #define EEE_REFERENCE_COUNT_MASK 0xffff 206 207 #define UMAC_TX_FLUSH 0x334 208 209 #define UMAC_MIB_START 0x400 210 211 #define UMAC_MDIO_CMD 0x614 212 #define MDIO_START_BUSY (1 << 29) 213 #define MDIO_READ_FAIL (1 << 28) 214 #define MDIO_RD (2 << 26) 215 #define MDIO_WR (1 << 26) 216 #define MDIO_PMD_SHIFT 21 217 #define MDIO_PMD_MASK 0x1F 218 #define MDIO_REG_SHIFT 16 219 #define MDIO_REG_MASK 0x1F 220 221 #define UMAC_RBUF_OVFL_CNT_V1 0x61C 222 #define RBUF_OVFL_CNT_V2 0x80 223 #define RBUF_OVFL_CNT_V3PLUS 0x94 224 225 #define UMAC_MPD_CTRL 0x620 226 #define MPD_EN (1 << 0) 227 #define MPD_PW_EN (1 << 27) 228 #define MPD_MSEQ_LEN_SHIFT 16 229 #define MPD_MSEQ_LEN_MASK 0xFF 230 231 #define UMAC_MPD_PW_MS 0x624 232 #define UMAC_MPD_PW_LS 0x628 233 #define UMAC_RBUF_ERR_CNT_V1 0x634 234 #define RBUF_ERR_CNT_V2 0x84 235 #define RBUF_ERR_CNT_V3PLUS 0x98 236 #define UMAC_MDF_ERR_CNT 0x638 237 #define UMAC_MDF_CTRL 0x650 238 #define UMAC_MDF_ADDR 0x654 239 #define UMAC_MIB_CTRL 0x580 240 #define MIB_RESET_RX (1 << 0) 241 #define MIB_RESET_RUNT (1 << 1) 242 #define MIB_RESET_TX (1 << 2) 243 244 #define RBUF_CTRL 0x00 245 #define RBUF_64B_EN (1 << 0) 246 #define RBUF_ALIGN_2B (1 << 1) 247 #define RBUF_BAD_DIS (1 << 2) 248 249 #define RBUF_STATUS 0x0C 250 #define RBUF_STATUS_WOL (1 << 0) 251 #define RBUF_STATUS_MPD_INTR_ACTIVE (1 << 1) 252 #define RBUF_STATUS_ACPI_INTR_ACTIVE (1 << 2) 253 254 #define RBUF_CHK_CTRL 0x14 255 #define RBUF_RXCHK_EN (1 << 0) 256 #define RBUF_SKIP_FCS (1 << 4) 257 258 #define RBUF_ENERGY_CTRL 0x9c 259 #define RBUF_EEE_EN (1 << 0) 260 #define RBUF_PM_EN (1 << 1) 261 262 #define RBUF_TBUF_SIZE_CTRL 0xb4 263 264 #define RBUF_HFB_CTRL_V1 0x38 265 #define RBUF_HFB_FILTER_EN_SHIFT 16 266 #define RBUF_HFB_FILTER_EN_MASK 0xffff0000 267 #define RBUF_HFB_EN (1 << 0) 268 #define RBUF_HFB_256B (1 << 1) 269 #define RBUF_ACPI_EN (1 << 2) 270 271 #define RBUF_HFB_LEN_V1 0x3C 272 #define RBUF_FLTR_LEN_MASK 0xFF 273 #define RBUF_FLTR_LEN_SHIFT 8 274 275 #define TBUF_CTRL 0x00 276 #define TBUF_BP_MC 0x0C 277 #define TBUF_ENERGY_CTRL 0x14 278 #define TBUF_EEE_EN (1 << 0) 279 #define TBUF_PM_EN (1 << 1) 280 281 #define TBUF_CTRL_V1 0x80 282 #define TBUF_BP_MC_V1 0xA0 283 284 #define HFB_CTRL 0x00 285 #define HFB_FLT_ENABLE_V3PLUS 0x04 286 #define HFB_FLT_LEN_V2 0x04 287 #define HFB_FLT_LEN_V3PLUS 0x1C 288 289 /* uniMac intrl2 registers */ 290 #define INTRL2_CPU_STAT 0x00 291 #define INTRL2_CPU_SET 0x04 292 #define INTRL2_CPU_CLEAR 0x08 293 #define INTRL2_CPU_MASK_STATUS 0x0C 294 #define INTRL2_CPU_MASK_SET 0x10 295 #define INTRL2_CPU_MASK_CLEAR 0x14 296 297 /* INTRL2 instance 0 definitions */ 298 #define UMAC_IRQ_SCB (1 << 0) 299 #define UMAC_IRQ_EPHY (1 << 1) 300 #define UMAC_IRQ_PHY_DET_R (1 << 2) 301 #define UMAC_IRQ_PHY_DET_F (1 << 3) 302 #define UMAC_IRQ_LINK_UP (1 << 4) 303 #define UMAC_IRQ_LINK_DOWN (1 << 5) 304 #define UMAC_IRQ_LINK_EVENT (UMAC_IRQ_LINK_UP | UMAC_IRQ_LINK_DOWN) 305 #define UMAC_IRQ_UMAC (1 << 6) 306 #define UMAC_IRQ_UMAC_TSV (1 << 7) 307 #define UMAC_IRQ_TBUF_UNDERRUN (1 << 8) 308 #define UMAC_IRQ_RBUF_OVERFLOW (1 << 9) 309 #define UMAC_IRQ_HFB_SM (1 << 10) 310 #define UMAC_IRQ_HFB_MM (1 << 11) 311 #define UMAC_IRQ_MPD_R (1 << 12) 312 #define UMAC_IRQ_RXDMA_MBDONE (1 << 13) 313 #define UMAC_IRQ_RXDMA_PDONE (1 << 14) 314 #define UMAC_IRQ_RXDMA_BDONE (1 << 15) 315 #define UMAC_IRQ_RXDMA_DONE UMAC_IRQ_RXDMA_MBDONE 316 #define UMAC_IRQ_TXDMA_MBDONE (1 << 16) 317 #define UMAC_IRQ_TXDMA_PDONE (1 << 17) 318 #define UMAC_IRQ_TXDMA_BDONE (1 << 18) 319 #define UMAC_IRQ_TXDMA_DONE UMAC_IRQ_TXDMA_MBDONE 320 321 /* Only valid for GENETv3+ */ 322 #define UMAC_IRQ_MDIO_DONE (1 << 23) 323 #define UMAC_IRQ_MDIO_ERROR (1 << 24) 324 325 /* INTRL2 instance 1 definitions */ 326 #define UMAC_IRQ1_TX_INTR_MASK 0xFFFF 327 #define UMAC_IRQ1_RX_INTR_MASK 0xFFFF 328 #define UMAC_IRQ1_RX_INTR_SHIFT 16 329 330 /* Register block offsets */ 331 #define GENET_SYS_OFF 0x0000 332 #define GENET_GR_BRIDGE_OFF 0x0040 333 #define GENET_EXT_OFF 0x0080 334 #define GENET_INTRL2_0_OFF 0x0200 335 #define GENET_INTRL2_1_OFF 0x0240 336 #define GENET_RBUF_OFF 0x0300 337 #define GENET_UMAC_OFF 0x0800 338 339 /* SYS block offsets and register definitions */ 340 #define SYS_REV_CTRL 0x00 341 #define SYS_PORT_CTRL 0x04 342 #define PORT_MODE_INT_EPHY 0 343 #define PORT_MODE_INT_GPHY 1 344 #define PORT_MODE_EXT_EPHY 2 345 #define PORT_MODE_EXT_GPHY 3 346 #define PORT_MODE_EXT_RVMII_25 (4 | BIT(4)) 347 #define PORT_MODE_EXT_RVMII_50 4 348 #define LED_ACT_SOURCE_MAC (1 << 9) 349 350 #define SYS_RBUF_FLUSH_CTRL 0x08 351 #define SYS_TBUF_FLUSH_CTRL 0x0C 352 #define RBUF_FLUSH_CTRL_V1 0x04 353 354 /* Ext block register offsets and definitions */ 355 #define EXT_EXT_PWR_MGMT 0x00 356 #define EXT_PWR_DOWN_BIAS (1 << 0) 357 #define EXT_PWR_DOWN_DLL (1 << 1) 358 #define EXT_PWR_DOWN_PHY (1 << 2) 359 #define EXT_PWR_DN_EN_LD (1 << 3) 360 #define EXT_ENERGY_DET (1 << 4) 361 #define EXT_IDDQ_FROM_PHY (1 << 5) 362 #define EXT_IDDQ_GLBL_PWR (1 << 7) 363 #define EXT_PHY_RESET (1 << 8) 364 #define EXT_ENERGY_DET_MASK (1 << 12) 365 #define EXT_PWR_DOWN_PHY_TX (1 << 16) 366 #define EXT_PWR_DOWN_PHY_RX (1 << 17) 367 #define EXT_PWR_DOWN_PHY_SD (1 << 18) 368 #define EXT_PWR_DOWN_PHY_RD (1 << 19) 369 #define EXT_PWR_DOWN_PHY_EN (1 << 20) 370 371 #define EXT_RGMII_OOB_CTRL 0x0C 372 #define RGMII_LINK (1 << 4) 373 #define OOB_DISABLE (1 << 5) 374 #define RGMII_MODE_EN (1 << 6) 375 #define ID_MODE_DIS (1 << 16) 376 377 #define EXT_GPHY_CTRL 0x1C 378 #define EXT_CFG_IDDQ_BIAS (1 << 0) 379 #define EXT_CFG_PWR_DOWN (1 << 1) 380 #define EXT_CK25_DIS (1 << 4) 381 #define EXT_GPHY_RESET (1 << 5) 382 383 /* DMA rings size */ 384 #define DMA_RING_SIZE (0x40) 385 #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DESC_INDEX + 1)) 386 387 /* DMA registers common definitions */ 388 #define DMA_RW_POINTER_MASK 0x1FF 389 #define DMA_P_INDEX_DISCARD_CNT_MASK 0xFFFF 390 #define DMA_P_INDEX_DISCARD_CNT_SHIFT 16 391 #define DMA_BUFFER_DONE_CNT_MASK 0xFFFF 392 #define DMA_BUFFER_DONE_CNT_SHIFT 16 393 #define DMA_P_INDEX_MASK 0xFFFF 394 #define DMA_C_INDEX_MASK 0xFFFF 395 396 /* DMA ring size register */ 397 #define DMA_RING_SIZE_MASK 0xFFFF 398 #define DMA_RING_SIZE_SHIFT 16 399 #define DMA_RING_BUFFER_SIZE_MASK 0xFFFF 400 401 /* DMA interrupt threshold register */ 402 #define DMA_INTR_THRESHOLD_MASK 0x01FF 403 404 /* DMA XON/XOFF register */ 405 #define DMA_XON_THREHOLD_MASK 0xFFFF 406 #define DMA_XOFF_THRESHOLD_MASK 0xFFFF 407 #define DMA_XOFF_THRESHOLD_SHIFT 16 408 409 /* DMA flow period register */ 410 #define DMA_FLOW_PERIOD_MASK 0xFFFF 411 #define DMA_MAX_PKT_SIZE_MASK 0xFFFF 412 #define DMA_MAX_PKT_SIZE_SHIFT 16 413 414 415 /* DMA control register */ 416 #define DMA_EN (1 << 0) 417 #define DMA_RING_BUF_EN_SHIFT 0x01 418 #define DMA_RING_BUF_EN_MASK 0xFFFF 419 #define DMA_TSB_SWAP_EN (1 << 20) 420 421 /* DMA status register */ 422 #define DMA_DISABLED (1 << 0) 423 #define DMA_DESC_RAM_INIT_BUSY (1 << 1) 424 425 /* DMA SCB burst size register */ 426 #define DMA_SCB_BURST_SIZE_MASK 0x1F 427 428 /* DMA activity vector register */ 429 #define DMA_ACTIVITY_VECTOR_MASK 0x1FFFF 430 431 /* DMA backpressure mask register */ 432 #define DMA_BACKPRESSURE_MASK 0x1FFFF 433 #define DMA_PFC_ENABLE (1 << 31) 434 435 /* DMA backpressure status register */ 436 #define DMA_BACKPRESSURE_STATUS_MASK 0x1FFFF 437 438 /* DMA override register */ 439 #define DMA_LITTLE_ENDIAN_MODE (1 << 0) 440 #define DMA_REGISTER_MODE (1 << 1) 441 442 /* DMA timeout register */ 443 #define DMA_TIMEOUT_MASK 0xFFFF 444 #define DMA_TIMEOUT_VAL 5000 /* micro seconds */ 445 446 /* TDMA rate limiting control register */ 447 #define DMA_RATE_LIMIT_EN_MASK 0xFFFF 448 449 /* TDMA arbitration control register */ 450 #define DMA_ARBITER_MODE_MASK 0x03 451 #define DMA_RING_BUF_PRIORITY_MASK 0x1F 452 #define DMA_RING_BUF_PRIORITY_SHIFT 5 453 #define DMA_PRIO_REG_INDEX(q) ((q) / 6) 454 #define DMA_PRIO_REG_SHIFT(q) (((q) % 6) * DMA_RING_BUF_PRIORITY_SHIFT) 455 #define DMA_RATE_ADJ_MASK 0xFF 456 457 /* Tx/Rx Dma Descriptor common bits*/ 458 #define DMA_BUFLENGTH_MASK 0x0fff 459 #define DMA_BUFLENGTH_SHIFT 16 460 #define DMA_OWN 0x8000 461 #define DMA_EOP 0x4000 462 #define DMA_SOP 0x2000 463 #define DMA_WRAP 0x1000 464 /* Tx specific Dma descriptor bits */ 465 #define DMA_TX_UNDERRUN 0x0200 466 #define DMA_TX_APPEND_CRC 0x0040 467 #define DMA_TX_OW_CRC 0x0020 468 #define DMA_TX_DO_CSUM 0x0010 469 #define DMA_TX_QTAG_SHIFT 7 470 471 /* Rx Specific Dma descriptor bits */ 472 #define DMA_RX_CHK_V3PLUS 0x8000 473 #define DMA_RX_CHK_V12 0x1000 474 #define DMA_RX_BRDCAST 0x0040 475 #define DMA_RX_MULT 0x0020 476 #define DMA_RX_LG 0x0010 477 #define DMA_RX_NO 0x0008 478 #define DMA_RX_RXER 0x0004 479 #define DMA_RX_CRC_ERROR 0x0002 480 #define DMA_RX_OV 0x0001 481 #define DMA_RX_FI_MASK 0x001F 482 #define DMA_RX_FI_SHIFT 0x0007 483 #define DMA_DESC_ALLOC_MASK 0x00FF 484 485 #define DMA_ARBITER_RR 0x00 486 #define DMA_ARBITER_WRR 0x01 487 #define DMA_ARBITER_SP 0x02 488 489 struct enet_cb { 490 struct sk_buff *skb; 491 void __iomem *bd_addr; 492 DEFINE_DMA_UNMAP_ADDR(dma_addr); 493 DEFINE_DMA_UNMAP_LEN(dma_len); 494 }; 495 496 /* power management mode */ 497 enum bcmgenet_power_mode { 498 GENET_POWER_CABLE_SENSE = 0, 499 GENET_POWER_PASSIVE, 500 GENET_POWER_WOL_MAGIC, 501 }; 502 503 struct bcmgenet_priv; 504 505 /* We support both runtime GENET detection and compile-time 506 * to optimize code-paths for a given hardware 507 */ 508 enum bcmgenet_version { 509 GENET_V1 = 1, 510 GENET_V2, 511 GENET_V3, 512 GENET_V4, 513 GENET_V5 514 }; 515 516 #define GENET_IS_V1(p) ((p)->version == GENET_V1) 517 #define GENET_IS_V2(p) ((p)->version == GENET_V2) 518 #define GENET_IS_V3(p) ((p)->version == GENET_V3) 519 #define GENET_IS_V4(p) ((p)->version == GENET_V4) 520 #define GENET_IS_V5(p) ((p)->version == GENET_V5) 521 522 /* Hardware flags */ 523 #define GENET_HAS_40BITS (1 << 0) 524 #define GENET_HAS_EXT (1 << 1) 525 #define GENET_HAS_MDIO_INTR (1 << 2) 526 #define GENET_HAS_MOCA_LINK_DET (1 << 3) 527 528 /* BCMGENET hardware parameters, keep this structure nicely aligned 529 * since it is going to be used in hot paths 530 */ 531 struct bcmgenet_hw_params { 532 u8 tx_queues; 533 u8 tx_bds_per_q; 534 u8 rx_queues; 535 u8 rx_bds_per_q; 536 u8 bp_in_en_shift; 537 u32 bp_in_mask; 538 u8 hfb_filter_cnt; 539 u8 hfb_filter_size; 540 u8 qtag_mask; 541 u16 tbuf_offset; 542 u32 hfb_offset; 543 u32 hfb_reg_offset; 544 u32 rdma_offset; 545 u32 tdma_offset; 546 u32 words_per_bd; 547 u32 flags; 548 }; 549 550 struct bcmgenet_skb_cb { 551 struct enet_cb *first_cb; /* First control block of SKB */ 552 struct enet_cb *last_cb; /* Last control block of SKB */ 553 unsigned int bytes_sent; /* bytes on the wire (no TSB) */ 554 }; 555 556 #define GENET_CB(skb) ((struct bcmgenet_skb_cb *)((skb)->cb)) 557 558 struct bcmgenet_tx_ring { 559 spinlock_t lock; /* ring lock */ 560 struct napi_struct napi; /* NAPI per tx queue */ 561 unsigned long packets; 562 unsigned long bytes; 563 unsigned int index; /* ring index */ 564 unsigned int queue; /* queue index */ 565 struct enet_cb *cbs; /* tx ring buffer control block*/ 566 unsigned int size; /* size of each tx ring */ 567 unsigned int clean_ptr; /* Tx ring clean pointer */ 568 unsigned int c_index; /* last consumer index of each ring*/ 569 unsigned int free_bds; /* # of free bds for each ring */ 570 unsigned int write_ptr; /* Tx ring write pointer SW copy */ 571 unsigned int prod_index; /* Tx ring producer index SW copy */ 572 unsigned int cb_ptr; /* Tx ring initial CB ptr */ 573 unsigned int end_ptr; /* Tx ring end CB ptr */ 574 void (*int_enable)(struct bcmgenet_tx_ring *); 575 void (*int_disable)(struct bcmgenet_tx_ring *); 576 struct bcmgenet_priv *priv; 577 }; 578 579 struct bcmgenet_net_dim { 580 u16 use_dim; 581 u16 event_ctr; 582 unsigned long packets; 583 unsigned long bytes; 584 struct net_dim dim; 585 }; 586 587 struct bcmgenet_rx_ring { 588 struct napi_struct napi; /* Rx NAPI struct */ 589 unsigned long bytes; 590 unsigned long packets; 591 unsigned long errors; 592 unsigned long dropped; 593 unsigned int index; /* Rx ring index */ 594 struct enet_cb *cbs; /* Rx ring buffer control block */ 595 unsigned int size; /* Rx ring size */ 596 unsigned int c_index; /* Rx last consumer index */ 597 unsigned int read_ptr; /* Rx ring read pointer */ 598 unsigned int cb_ptr; /* Rx ring initial CB ptr */ 599 unsigned int end_ptr; /* Rx ring end CB ptr */ 600 unsigned int old_discards; 601 struct bcmgenet_net_dim dim; 602 u32 rx_max_coalesced_frames; 603 u32 rx_coalesce_usecs; 604 void (*int_enable)(struct bcmgenet_rx_ring *); 605 void (*int_disable)(struct bcmgenet_rx_ring *); 606 struct bcmgenet_priv *priv; 607 }; 608 609 /* device context */ 610 struct bcmgenet_priv { 611 void __iomem *base; 612 enum bcmgenet_version version; 613 struct net_device *dev; 614 615 /* transmit variables */ 616 void __iomem *tx_bds; 617 struct enet_cb *tx_cbs; 618 unsigned int num_tx_bds; 619 620 struct bcmgenet_tx_ring tx_rings[DESC_INDEX + 1]; 621 622 /* receive variables */ 623 void __iomem *rx_bds; 624 struct enet_cb *rx_cbs; 625 unsigned int num_rx_bds; 626 unsigned int rx_buf_len; 627 628 struct bcmgenet_rx_ring rx_rings[DESC_INDEX + 1]; 629 630 /* other misc variables */ 631 struct bcmgenet_hw_params *hw_params; 632 633 /* MDIO bus variables */ 634 wait_queue_head_t wq; 635 bool internal_phy; 636 struct device_node *phy_dn; 637 struct device_node *mdio_dn; 638 struct mii_bus *mii_bus; 639 u16 gphy_rev; 640 struct clk *clk_eee; 641 bool clk_eee_enabled; 642 643 /* PHY device variables */ 644 int old_link; 645 int old_speed; 646 int old_duplex; 647 int old_pause; 648 phy_interface_t phy_interface; 649 int phy_addr; 650 int ext_phy; 651 652 /* Interrupt variables */ 653 struct work_struct bcmgenet_irq_work; 654 int irq0; 655 int irq1; 656 int wol_irq; 657 bool wol_irq_disabled; 658 659 /* shared status */ 660 spinlock_t lock; 661 unsigned int irq0_stat; 662 663 /* HW descriptors/checksum variables */ 664 bool desc_64b_en; 665 bool desc_rxchk_en; 666 bool crc_fwd_en; 667 668 unsigned int dma_rx_chk_bit; 669 670 u32 msg_enable; 671 672 struct clk *clk; 673 struct platform_device *pdev; 674 struct platform_device *mii_pdev; 675 676 /* WOL */ 677 struct clk *clk_wol; 678 u32 wolopts; 679 680 struct bcmgenet_mib_counters mib; 681 682 struct ethtool_eee eee; 683 }; 684 685 #define GENET_IO_MACRO(name, offset) \ 686 static inline u32 bcmgenet_##name##_readl(struct bcmgenet_priv *priv, \ 687 u32 off) \ 688 { \ 689 /* MIPS chips strapped for BE will automagically configure the \ 690 * peripheral registers for CPU-native byte order. \ 691 */ \ 692 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 693 return __raw_readl(priv->base + offset + off); \ 694 else \ 695 return readl_relaxed(priv->base + offset + off); \ 696 } \ 697 static inline void bcmgenet_##name##_writel(struct bcmgenet_priv *priv, \ 698 u32 val, u32 off) \ 699 { \ 700 if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) \ 701 __raw_writel(val, priv->base + offset + off); \ 702 else \ 703 writel_relaxed(val, priv->base + offset + off); \ 704 } 705 706 GENET_IO_MACRO(ext, GENET_EXT_OFF); 707 GENET_IO_MACRO(umac, GENET_UMAC_OFF); 708 GENET_IO_MACRO(sys, GENET_SYS_OFF); 709 710 /* interrupt l2 registers accessors */ 711 GENET_IO_MACRO(intrl2_0, GENET_INTRL2_0_OFF); 712 GENET_IO_MACRO(intrl2_1, GENET_INTRL2_1_OFF); 713 714 /* HFB register accessors */ 715 GENET_IO_MACRO(hfb, priv->hw_params->hfb_offset); 716 717 /* GENET v2+ HFB control and filter len helpers */ 718 GENET_IO_MACRO(hfb_reg, priv->hw_params->hfb_reg_offset); 719 720 /* RBUF register accessors */ 721 GENET_IO_MACRO(rbuf, GENET_RBUF_OFF); 722 723 /* MDIO routines */ 724 int bcmgenet_mii_init(struct net_device *dev); 725 int bcmgenet_mii_config(struct net_device *dev, bool init); 726 int bcmgenet_mii_probe(struct net_device *dev); 727 void bcmgenet_mii_exit(struct net_device *dev); 728 void bcmgenet_phy_power_set(struct net_device *dev, bool enable); 729 void bcmgenet_mii_setup(struct net_device *dev); 730 731 /* Wake-on-LAN routines */ 732 void bcmgenet_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 733 int bcmgenet_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol); 734 int bcmgenet_wol_power_down_cfg(struct bcmgenet_priv *priv, 735 enum bcmgenet_power_mode mode); 736 void bcmgenet_wol_power_up_cfg(struct bcmgenet_priv *priv, 737 enum bcmgenet_power_mode mode); 738 739 #endif /* __BCMGENET_H__ */ 740
