1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef __ASM_ARCH_REGS_AC97_H 3 #define __ASM_ARCH_REGS_AC97_H 4 5 #include <mach/hardware.h> 6 7 /* 8 * AC97 Controller registers 9 */ 10 11 #define POCR __REG(0x40500000) /* PCM Out Control Register */ 12 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 13 #define POCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 14 15 #define PICR __REG(0x40500004) /* PCM In Control Register */ 16 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 17 #define PICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 18 19 #define MCCR __REG(0x40500008) /* Mic In Control Register */ 20 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */ 21 #define MCCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 22 23 #define GCR __REG(0x4050000C) /* Global Control Register */ 24 #ifdef CONFIG_PXA3xx 25 #define GCR_CLKBPB (1 << 31) /* Internal clock enable */ 26 #endif 27 #define GCR_nDMAEN (1 << 24) /* non DMA Enable */ 28 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */ 29 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */ 30 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */ 31 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */ 32 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */ 33 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */ 34 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */ 35 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */ 36 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */ 37 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */ 38 39 #define POSR __REG(0x40500010) /* PCM Out Status Register */ 40 #define POSR_FIFOE (1 << 4) /* FIFO error */ 41 #define POSR_FSR (1 << 2) /* FIFO Service Request */ 42 43 #define PISR __REG(0x40500014) /* PCM In Status Register */ 44 #define PISR_FIFOE (1 << 4) /* FIFO error */ 45 #define PISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 46 #define PISR_FSR (1 << 2) /* FIFO Service Request */ 47 48 #define MCSR __REG(0x40500018) /* Mic In Status Register */ 49 #define MCSR_FIFOE (1 << 4) /* FIFO error */ 50 #define MCSR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 51 #define MCSR_FSR (1 << 2) /* FIFO Service Request */ 52 53 #define GSR __REG(0x4050001C) /* Global Status Register */ 54 #define GSR_CDONE (1 << 19) /* Command Done */ 55 #define GSR_SDONE (1 << 18) /* Status Done */ 56 #define GSR_RDCS (1 << 15) /* Read Completion Status */ 57 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */ 58 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */ 59 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */ 60 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */ 61 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */ 62 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */ 63 #define GSR_PCR (1 << 8) /* Primary Codec Ready */ 64 #define GSR_MCINT (1 << 7) /* Mic In Interrupt */ 65 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */ 66 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */ 67 #define GSR_ACOFFD (1 << 3) /* AC-link Shut Off Done */ 68 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */ 69 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */ 70 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */ 71 72 #define CAR __REG(0x40500020) /* CODEC Access Register */ 73 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */ 74 75 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */ 76 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */ 77 78 #define MOCR __REG(0x40500100) /* Modem Out Control Register */ 79 #define MOCR_FEIE (1 << 3) /* FIFO Error */ 80 #define MOCR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 81 82 #define MICR __REG(0x40500108) /* Modem In Control Register */ 83 #define MICR_FEIE (1 << 3) /* FIFO Error */ 84 #define MICR_FSRIE (1 << 1) /* FIFO Service Request Interrupt Enable */ 85 86 #define MOSR __REG(0x40500110) /* Modem Out Status Register */ 87 #define MOSR_FIFOE (1 << 4) /* FIFO error */ 88 #define MOSR_FSR (1 << 2) /* FIFO Service Request */ 89 90 #define MISR __REG(0x40500118) /* Modem In Status Register */ 91 #define MISR_FIFOE (1 << 4) /* FIFO error */ 92 #define MISR_EOC (1 << 3) /* DMA End-of-Chain (exclusive clear) */ 93 #define MISR_FSR (1 << 2) /* FIFO Service Request */ 94 95 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */ 96 97 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */ 98 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */ 99 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */ 100 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */ 101 102 #endif /* __ASM_ARCH_REGS_AC97_H */ 103
