1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2019-2021 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 #ifndef GAUDI2_FW_IF_H 9 #define GAUDI2_FW_IF_H 10 11 #define GAUDI2_EVENT_QUEUE_MSIX_IDX 0 12 13 #define UBOOT_FW_OFFSET 0x100000 /* 1MB in SRAM */ 14 #define LINUX_FW_OFFSET 0x800000 /* 8BM in DDR */ 15 16 #define GAUDI2_PLL_FREQ_LOW 200000000 /* 200 MHz */ 17 18 #define GAUDI2_SP_SRAM_BASE_ADDR 0x27FE0000 19 #define GAUDI2_MAILBOX_BASE_ADDR 0x27FE1800 20 21 #define GAUDI2_NUM_MME 4 22 23 #define GAUDI2_ARCPID_TX_MB_SIZE 0x1000 24 #define GAUDI2_ARCPID_RX_MB_SIZE 0x400 25 #define GAUDI2_ARM_TX_MB_SIZE 0x400 26 #define GAUDI2_ARM_RX_MB_SIZE 0x1800 27 28 #define GAUDI2_DCCM_BASE_ADDR 0x27020000 29 #define GAUDI2_ARCPID_TX_MB_ADDR GAUDI2_DCCM_BASE_ADDR 30 31 #define GAUDI2_ARCPID_RX_MB_ADDR (GAUDI2_ARCPID_TX_MB_ADDR + \ 32 GAUDI2_ARCPID_TX_MB_SIZE) 33 34 #define GAUDI2_ARM_TX_MB_ADDR GAUDI2_MAILBOX_BASE_ADDR 35 36 #define GAUDI2_ARM_RX_MB_ADDR (GAUDI2_ARM_TX_MB_ADDR + \ 37 GAUDI2_ARM_TX_MB_SIZE) 38 39 #define GAUDI2_ARM_TX_MB_OFFSET (GAUDI2_ARM_TX_MB_ADDR - \ 40 GAUDI2_SP_SRAM_BASE_ADDR) 41 42 #define GAUDI2_ARM_RX_MB_OFFSET (GAUDI2_ARM_RX_MB_ADDR - \ 43 GAUDI2_SP_SRAM_BASE_ADDR) 44 45 enum gaudi2_fw_status { 46 GAUDI2_PID_STATUS_UP = 0x1, /* PID on ARC0 is up */ 47 GAUDI2_ARM_STATUS_UP = 0x2, /* ARM Linux Boot complete */ 48 GAUDI2_MGMT_STATUS_UP = 0x3, /* ARC1 Mgmt is up */ 49 GAUDI2_STATUS_LAST = 0xFF 50 }; 51 52 struct gaudi2_cold_rst_data { 53 union { 54 struct { 55 u32 recovery_flag: 1; 56 u32 validation_flag: 1; 57 u32 efuse_read_flag: 1; 58 u32 spsram_init_done : 1; 59 u32 fake_security_enable : 1; 60 u32 fake_sig_validation_en : 1; 61 u32 reserved : 26; 62 }; 63 __le32 data; 64 }; 65 }; 66 67 enum gaudi2_rst_src { 68 HL_COLD_RST = 1, 69 HL_MANUAL_RST = 2, 70 HL_PRSTN_RST = 4, 71 HL_SOFT_RST = 8, 72 HL_WD_RST = 16, 73 HL_FW_ALL_RST = 32, 74 HL_SW_ALL_RST = 64, 75 HL_FLR_RST = 128, 76 HL_ECC_DERR_RST = 256 77 }; 78 79 struct gaudi2_redundancy_ctx { 80 int redundant_hbm; 81 int redundant_edma; 82 int redundant_tpc; 83 int redundant_vdec; 84 __le64 hbm_mask; 85 __le64 edma_mask; 86 __le64 tpc_mask; 87 __le64 vdec_mask; 88 __le64 mme_mask; 89 __le64 nic_mask; 90 __le64 rtr_mask; 91 __le64 hmmu_hif_iso; 92 __le64 xbar_edge_iso; 93 __le64 hmmu_hif_mask; 94 __le64 xbar_edge_mask; 95 __u8 mme_pe_iso[GAUDI2_NUM_MME]; 96 __le32 full_hbm_mode; /* true on full (non binning hbm)*/ 97 } __packed; 98 99 #endif /* GAUDI2_FW_IF_H */ 100
