1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************/ 3 4 /* 5 * fec.h -- Fast Ethernet Controller for Motorola ColdFire SoC 6 * processors. 7 * 8 * (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com) 9 * (C) Copyright 2000-2001, Lineo (www.lineo.com) 10 */ 11 12 /****************************************************************************/ 13 #ifndef FEC_H 14 #define FEC_H 15 /****************************************************************************/ 16 17 #include <linux/clocksource.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/ptp_clock_kernel.h> 20 #include <linux/timecounter.h> 21 22 #if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 23 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARM) || \ 24 defined(CONFIG_ARM64) || defined(CONFIG_COMPILE_TEST) 25 /* 26 * Just figures, Motorola would have to change the offsets for 27 * registers in the same peripheral device on different models 28 * of the ColdFire! 29 */ 30 #define FEC_IEVENT 0x004 /* Interrupt event reg */ 31 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 32 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 33 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 34 #define FEC_ECNTRL 0x024 /* Ethernet control reg */ 35 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 36 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 37 #define FEC_MIB_CTRLSTAT 0x064 /* MIB control/status reg */ 38 #define FEC_R_CNTRL 0x084 /* Receive control reg */ 39 #define FEC_X_CNTRL 0x0c4 /* Transmit Control reg */ 40 #define FEC_ADDR_LOW 0x0e4 /* Low 32bits MAC address */ 41 #define FEC_ADDR_HIGH 0x0e8 /* High 16bits MAC address */ 42 #define FEC_OPD 0x0ec /* Opcode + Pause duration */ 43 #define FEC_TXIC0 0x0f0 /* Tx Interrupt Coalescing for ring 0 */ 44 #define FEC_TXIC1 0x0f4 /* Tx Interrupt Coalescing for ring 1 */ 45 #define FEC_TXIC2 0x0f8 /* Tx Interrupt Coalescing for ring 2 */ 46 #define FEC_RXIC0 0x100 /* Rx Interrupt Coalescing for ring 0 */ 47 #define FEC_RXIC1 0x104 /* Rx Interrupt Coalescing for ring 1 */ 48 #define FEC_RXIC2 0x108 /* Rx Interrupt Coalescing for ring 2 */ 49 #define FEC_HASH_TABLE_HIGH 0x118 /* High 32bits hash table */ 50 #define FEC_HASH_TABLE_LOW 0x11c /* Low 32bits hash table */ 51 #define FEC_GRP_HASH_TABLE_HIGH 0x120 /* High 32bits hash table */ 52 #define FEC_GRP_HASH_TABLE_LOW 0x124 /* Low 32bits hash table */ 53 #define FEC_X_WMRK 0x144 /* FIFO transmit water mark */ 54 #define FEC_R_BOUND 0x14c /* FIFO receive bound reg */ 55 #define FEC_R_FSTART 0x150 /* FIFO receive start reg */ 56 #define FEC_R_DES_START_1 0x160 /* Receive descriptor ring 1 */ 57 #define FEC_X_DES_START_1 0x164 /* Transmit descriptor ring 1 */ 58 #define FEC_R_BUFF_SIZE_1 0x168 /* Maximum receive buff ring1 size */ 59 #define FEC_R_DES_START_2 0x16c /* Receive descriptor ring 2 */ 60 #define FEC_X_DES_START_2 0x170 /* Transmit descriptor ring 2 */ 61 #define FEC_R_BUFF_SIZE_2 0x174 /* Maximum receive buff ring2 size */ 62 #define FEC_R_DES_START_0 0x180 /* Receive descriptor ring */ 63 #define FEC_X_DES_START_0 0x184 /* Transmit descriptor ring */ 64 #define FEC_R_BUFF_SIZE_0 0x188 /* Maximum receive buff size */ 65 #define FEC_R_FIFO_RSFL 0x190 /* Receive FIFO section full threshold */ 66 #define FEC_R_FIFO_RSEM 0x194 /* Receive FIFO section empty threshold */ 67 #define FEC_R_FIFO_RAEM 0x198 /* Receive FIFO almost empty threshold */ 68 #define FEC_R_FIFO_RAFL 0x19c /* Receive FIFO almost full threshold */ 69 #define FEC_FTRL 0x1b0 /* Frame truncation receive length*/ 70 #define FEC_RACC 0x1c4 /* Receive Accelerator function */ 71 #define FEC_RCMR_1 0x1c8 /* Receive classification match ring 1 */ 72 #define FEC_RCMR_2 0x1cc /* Receive classification match ring 2 */ 73 #define FEC_DMA_CFG_1 0x1d8 /* DMA class configuration for ring 1 */ 74 #define FEC_DMA_CFG_2 0x1dc /* DMA class Configuration for ring 2 */ 75 #define FEC_R_DES_ACTIVE_1 0x1e0 /* Rx descriptor active for ring 1 */ 76 #define FEC_X_DES_ACTIVE_1 0x1e4 /* Tx descriptor active for ring 1 */ 77 #define FEC_R_DES_ACTIVE_2 0x1e8 /* Rx descriptor active for ring 2 */ 78 #define FEC_X_DES_ACTIVE_2 0x1ec /* Tx descriptor active for ring 2 */ 79 #define FEC_QOS_SCHEME 0x1f0 /* Set multi queues Qos scheme */ 80 #define FEC_MIIGSK_CFGR 0x300 /* MIIGSK Configuration reg */ 81 #define FEC_MIIGSK_ENR 0x308 /* MIIGSK Enable reg */ 82 83 #define BM_MIIGSK_CFGR_MII 0x00 84 #define BM_MIIGSK_CFGR_RMII 0x01 85 #define BM_MIIGSK_CFGR_FRCONT_10M 0x40 86 87 #define RMON_T_DROP 0x200 /* Count of frames not cntd correctly */ 88 #define RMON_T_PACKETS 0x204 /* RMON TX packet count */ 89 #define RMON_T_BC_PKT 0x208 /* RMON TX broadcast pkts */ 90 #define RMON_T_MC_PKT 0x20c /* RMON TX multicast pkts */ 91 #define RMON_T_CRC_ALIGN 0x210 /* RMON TX pkts with CRC align err */ 92 #define RMON_T_UNDERSIZE 0x214 /* RMON TX pkts < 64 bytes, good CRC */ 93 #define RMON_T_OVERSIZE 0x218 /* RMON TX pkts > MAX_FL bytes good CRC */ 94 #define RMON_T_FRAG 0x21c /* RMON TX pkts < 64 bytes, bad CRC */ 95 #define RMON_T_JAB 0x220 /* RMON TX pkts > MAX_FL bytes, bad CRC */ 96 #define RMON_T_COL 0x224 /* RMON TX collision count */ 97 #define RMON_T_P64 0x228 /* RMON TX 64 byte pkts */ 98 #define RMON_T_P65TO127 0x22c /* RMON TX 65 to 127 byte pkts */ 99 #define RMON_T_P128TO255 0x230 /* RMON TX 128 to 255 byte pkts */ 100 #define RMON_T_P256TO511 0x234 /* RMON TX 256 to 511 byte pkts */ 101 #define RMON_T_P512TO1023 0x238 /* RMON TX 512 to 1023 byte pkts */ 102 #define RMON_T_P1024TO2047 0x23c /* RMON TX 1024 to 2047 byte pkts */ 103 #define RMON_T_P_GTE2048 0x240 /* RMON TX pkts > 2048 bytes */ 104 #define RMON_T_OCTETS 0x244 /* RMON TX octets */ 105 #define IEEE_T_DROP 0x248 /* Count of frames not counted crtly */ 106 #define IEEE_T_FRAME_OK 0x24c /* Frames tx'd OK */ 107 #define IEEE_T_1COL 0x250 /* Frames tx'd with single collision */ 108 #define IEEE_T_MCOL 0x254 /* Frames tx'd with multiple collision */ 109 #define IEEE_T_DEF 0x258 /* Frames tx'd after deferral delay */ 110 #define IEEE_T_LCOL 0x25c /* Frames tx'd with late collision */ 111 #define IEEE_T_EXCOL 0x260 /* Frames tx'd with excesv collisions */ 112 #define IEEE_T_MACERR 0x264 /* Frames tx'd with TX FIFO underrun */ 113 #define IEEE_T_CSERR 0x268 /* Frames tx'd with carrier sense err */ 114 #define IEEE_T_SQE 0x26c /* Frames tx'd with SQE err */ 115 #define IEEE_T_FDXFC 0x270 /* Flow control pause frames tx'd */ 116 #define IEEE_T_OCTETS_OK 0x274 /* Octet count for frames tx'd w/o err */ 117 #define RMON_R_PACKETS 0x284 /* RMON RX packet count */ 118 #define RMON_R_BC_PKT 0x288 /* RMON RX broadcast pkts */ 119 #define RMON_R_MC_PKT 0x28c /* RMON RX multicast pkts */ 120 #define RMON_R_CRC_ALIGN 0x290 /* RMON RX pkts with CRC alignment err */ 121 #define RMON_R_UNDERSIZE 0x294 /* RMON RX pkts < 64 bytes, good CRC */ 122 #define RMON_R_OVERSIZE 0x298 /* RMON RX pkts > MAX_FL bytes good CRC */ 123 #define RMON_R_FRAG 0x29c /* RMON RX pkts < 64 bytes, bad CRC */ 124 #define RMON_R_JAB 0x2a0 /* RMON RX pkts > MAX_FL bytes, bad CRC */ 125 #define RMON_R_RESVD_O 0x2a4 /* Reserved */ 126 #define RMON_R_P64 0x2a8 /* RMON RX 64 byte pkts */ 127 #define RMON_R_P65TO127 0x2ac /* RMON RX 65 to 127 byte pkts */ 128 #define RMON_R_P128TO255 0x2b0 /* RMON RX 128 to 255 byte pkts */ 129 #define RMON_R_P256TO511 0x2b4 /* RMON RX 256 to 511 byte pkts */ 130 #define RMON_R_P512TO1023 0x2b8 /* RMON RX 512 to 1023 byte pkts */ 131 #define RMON_R_P1024TO2047 0x2bc /* RMON RX 1024 to 2047 byte pkts */ 132 #define RMON_R_P_GTE2048 0x2c0 /* RMON RX pkts > 2048 bytes */ 133 #define RMON_R_OCTETS 0x2c4 /* RMON RX octets */ 134 #define IEEE_R_DROP 0x2c8 /* Count frames not counted correctly */ 135 #define IEEE_R_FRAME_OK 0x2cc /* Frames rx'd OK */ 136 #define IEEE_R_CRC 0x2d0 /* Frames rx'd with CRC err */ 137 #define IEEE_R_ALIGN 0x2d4 /* Frames rx'd with alignment err */ 138 #define IEEE_R_MACERR 0x2d8 /* Receive FIFO overflow count */ 139 #define IEEE_R_FDXFC 0x2dc /* Flow control pause frames rx'd */ 140 #define IEEE_R_OCTETS_OK 0x2e0 /* Octet cnt for frames rx'd w/o err */ 141 142 #else 143 144 #define FEC_ECNTRL 0x000 /* Ethernet control reg */ 145 #define FEC_IEVENT 0x004 /* Interrupt even reg */ 146 #define FEC_IMASK 0x008 /* Interrupt mask reg */ 147 #define FEC_IVEC 0x00c /* Interrupt vec status reg */ 148 #define FEC_R_DES_ACTIVE_0 0x010 /* Receive descriptor reg */ 149 #define FEC_R_DES_ACTIVE_1 FEC_R_DES_ACTIVE_0 150 #define FEC_R_DES_ACTIVE_2 FEC_R_DES_ACTIVE_0 151 #define FEC_X_DES_ACTIVE_0 0x014 /* Transmit descriptor reg */ 152 #define FEC_X_DES_ACTIVE_1 FEC_X_DES_ACTIVE_0 153 #define FEC_X_DES_ACTIVE_2 FEC_X_DES_ACTIVE_0 154 #define FEC_MII_DATA 0x040 /* MII manage frame reg */ 155 #define FEC_MII_SPEED 0x044 /* MII speed control reg */ 156 #define FEC_R_BOUND 0x08c /* FIFO receive bound reg */ 157 #define FEC_R_FSTART 0x090 /* FIFO receive start reg */ 158 #define FEC_X_WMRK 0x0a4 /* FIFO transmit water mark */ 159 #define FEC_X_FSTART 0x0ac /* FIFO transmit start reg */ 160 #define FEC_R_CNTRL 0x104 /* Receive control reg */ 161 #define FEC_MAX_FRM_LEN 0x108 /* Maximum frame length reg */ 162 #define FEC_X_CNTRL 0x144 /* Transmit Control reg */ 163 #define FEC_ADDR_LOW 0x3c0 /* Low 32bits MAC address */ 164 #define FEC_ADDR_HIGH 0x3c4 /* High 16bits MAC address */ 165 #define FEC_GRP_HASH_TABLE_HIGH 0x3c8 /* High 32bits hash table */ 166 #define FEC_GRP_HASH_TABLE_LOW 0x3cc /* Low 32bits hash table */ 167 #define FEC_R_DES_START_0 0x3d0 /* Receive descriptor ring */ 168 #define FEC_R_DES_START_1 FEC_R_DES_START_0 169 #define FEC_R_DES_START_2 FEC_R_DES_START_0 170 #define FEC_X_DES_START_0 0x3d4 /* Transmit descriptor ring */ 171 #define FEC_X_DES_START_1 FEC_X_DES_START_0 172 #define FEC_X_DES_START_2 FEC_X_DES_START_0 173 #define FEC_R_BUFF_SIZE_0 0x3d8 /* Maximum receive buff size */ 174 #define FEC_R_BUFF_SIZE_1 FEC_R_BUFF_SIZE_0 175 #define FEC_R_BUFF_SIZE_2 FEC_R_BUFF_SIZE_0 176 #define FEC_FIFO_RAM 0x400 /* FIFO RAM buffer */ 177 /* Not existed in real chip 178 * Just for pass build. 179 */ 180 #define FEC_RCMR_1 0xfff 181 #define FEC_RCMR_2 0xfff 182 #define FEC_DMA_CFG_1 0xfff 183 #define FEC_DMA_CFG_2 0xfff 184 #define FEC_TXIC0 0xfff 185 #define FEC_TXIC1 0xfff 186 #define FEC_TXIC2 0xfff 187 #define FEC_RXIC0 0xfff 188 #define FEC_RXIC1 0xfff 189 #define FEC_RXIC2 0xfff 190 #endif /* CONFIG_M5272 */ 191 192 193 /* 194 * Define the buffer descriptor structure. 195 * 196 * Evidently, ARM SoCs have the FEC block generated in a 197 * little endian mode so adjust endianness accordingly. 198 */ 199 #if defined(CONFIG_ARM) || defined(CONFIG_ARM64) 200 #define fec32_to_cpu le32_to_cpu 201 #define fec16_to_cpu le16_to_cpu 202 #define cpu_to_fec32 cpu_to_le32 203 #define cpu_to_fec16 cpu_to_le16 204 #define __fec32 __le32 205 #define __fec16 __le16 206 207 struct bufdesc { 208 __fec16 cbd_datlen; /* Data length */ 209 __fec16 cbd_sc; /* Control and status info */ 210 __fec32 cbd_bufaddr; /* Buffer address */ 211 }; 212 #else 213 #define fec32_to_cpu be32_to_cpu 214 #define fec16_to_cpu be16_to_cpu 215 #define cpu_to_fec32 cpu_to_be32 216 #define cpu_to_fec16 cpu_to_be16 217 #define __fec32 __be32 218 #define __fec16 __be16 219 220 struct bufdesc { 221 __fec16 cbd_sc; /* Control and status info */ 222 __fec16 cbd_datlen; /* Data length */ 223 __fec32 cbd_bufaddr; /* Buffer address */ 224 }; 225 #endif 226 227 struct bufdesc_ex { 228 struct bufdesc desc; 229 __fec32 cbd_esc; 230 __fec32 cbd_prot; 231 __fec32 cbd_bdu; 232 __fec32 ts; 233 __fec16 res0[4]; 234 }; 235 236 /* 237 * The following definitions courtesy of commproc.h, which where 238 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net). 239 */ 240 #define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ 241 #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ 242 #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ 243 #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ 244 #define BD_SC_CM ((ushort)0x0200) /* Continuous mode */ 245 #define BD_SC_ID ((ushort)0x0100) /* Rec'd too many idles */ 246 #define BD_SC_P ((ushort)0x0100) /* xmt preamble */ 247 #define BD_SC_BR ((ushort)0x0020) /* Break received */ 248 #define BD_SC_FR ((ushort)0x0010) /* Framing error */ 249 #define BD_SC_PR ((ushort)0x0008) /* Parity error */ 250 #define BD_SC_OV ((ushort)0x0002) /* Overrun */ 251 #define BD_SC_CD ((ushort)0x0001) /* ?? */ 252 253 /* Buffer descriptor control/status used by Ethernet receive. 254 */ 255 #define BD_ENET_RX_EMPTY ((ushort)0x8000) 256 #define BD_ENET_RX_WRAP ((ushort)0x2000) 257 #define BD_ENET_RX_INTR ((ushort)0x1000) 258 #define BD_ENET_RX_LAST ((ushort)0x0800) 259 #define BD_ENET_RX_FIRST ((ushort)0x0400) 260 #define BD_ENET_RX_MISS ((ushort)0x0100) 261 #define BD_ENET_RX_LG ((ushort)0x0020) 262 #define BD_ENET_RX_NO ((ushort)0x0010) 263 #define BD_ENET_RX_SH ((ushort)0x0008) 264 #define BD_ENET_RX_CR ((ushort)0x0004) 265 #define BD_ENET_RX_OV ((ushort)0x0002) 266 #define BD_ENET_RX_CL ((ushort)0x0001) 267 #define BD_ENET_RX_STATS ((ushort)0x013f) /* All status bits */ 268 269 /* Enhanced buffer descriptor control/status used by Ethernet receive */ 270 #define BD_ENET_RX_VLAN 0x00000004 271 272 /* Buffer descriptor control/status used by Ethernet transmit. 273 */ 274 #define BD_ENET_TX_READY ((ushort)0x8000) 275 #define BD_ENET_TX_PAD ((ushort)0x4000) 276 #define BD_ENET_TX_WRAP ((ushort)0x2000) 277 #define BD_ENET_TX_INTR ((ushort)0x1000) 278 #define BD_ENET_TX_LAST ((ushort)0x0800) 279 #define BD_ENET_TX_TC ((ushort)0x0400) 280 #define BD_ENET_TX_DEF ((ushort)0x0200) 281 #define BD_ENET_TX_HB ((ushort)0x0100) 282 #define BD_ENET_TX_LC ((ushort)0x0080) 283 #define BD_ENET_TX_RL ((ushort)0x0040) 284 #define BD_ENET_TX_RCMASK ((ushort)0x003c) 285 #define BD_ENET_TX_UN ((ushort)0x0002) 286 #define BD_ENET_TX_CSL ((ushort)0x0001) 287 #define BD_ENET_TX_STATS ((ushort)0x0fff) /* All status bits */ 288 289 /* enhanced buffer descriptor control/status used by Ethernet transmit */ 290 #define BD_ENET_TX_INT 0x40000000 291 #define BD_ENET_TX_TS 0x20000000 292 #define BD_ENET_TX_PINS 0x10000000 293 #define BD_ENET_TX_IINS 0x08000000 294 295 296 /* This device has up to three irqs on some platforms */ 297 #define FEC_IRQ_NUM 3 298 299 /* Maximum number of queues supported 300 * ENET with AVB IP can support up to 3 independent tx queues and rx queues. 301 * User can point the queue number that is less than or equal to 3. 302 */ 303 #define FEC_ENET_MAX_TX_QS 3 304 #define FEC_ENET_MAX_RX_QS 3 305 306 #define FEC_R_DES_START(X) (((X) == 1) ? FEC_R_DES_START_1 : \ 307 (((X) == 2) ? \ 308 FEC_R_DES_START_2 : FEC_R_DES_START_0)) 309 #define FEC_X_DES_START(X) (((X) == 1) ? FEC_X_DES_START_1 : \ 310 (((X) == 2) ? \ 311 FEC_X_DES_START_2 : FEC_X_DES_START_0)) 312 #define FEC_R_BUFF_SIZE(X) (((X) == 1) ? FEC_R_BUFF_SIZE_1 : \ 313 (((X) == 2) ? \ 314 FEC_R_BUFF_SIZE_2 : FEC_R_BUFF_SIZE_0)) 315 316 #define FEC_DMA_CFG(X) (((X) == 2) ? FEC_DMA_CFG_2 : FEC_DMA_CFG_1) 317 318 #define DMA_CLASS_EN (1 << 16) 319 #define FEC_RCMR(X) (((X) == 2) ? FEC_RCMR_2 : FEC_RCMR_1) 320 #define IDLE_SLOPE_MASK 0xffff 321 #define IDLE_SLOPE_1 0x200 /* BW fraction: 0.5 */ 322 #define IDLE_SLOPE_2 0x200 /* BW fraction: 0.5 */ 323 #define IDLE_SLOPE(X) (((X) == 1) ? \ 324 (IDLE_SLOPE_1 & IDLE_SLOPE_MASK) : \ 325 (IDLE_SLOPE_2 & IDLE_SLOPE_MASK)) 326 #define RCMR_MATCHEN (0x1 << 16) 327 #define RCMR_CMP_CFG(v, n) (((v) & 0x7) << (n << 2)) 328 #define RCMR_CMP_1 (RCMR_CMP_CFG(0, 0) | RCMR_CMP_CFG(1, 1) | \ 329 RCMR_CMP_CFG(2, 2) | RCMR_CMP_CFG(3, 3)) 330 #define RCMR_CMP_2 (RCMR_CMP_CFG(4, 0) | RCMR_CMP_CFG(5, 1) | \ 331 RCMR_CMP_CFG(6, 2) | RCMR_CMP_CFG(7, 3)) 332 #define RCMR_CMP(X) (((X) == 1) ? RCMR_CMP_1 : RCMR_CMP_2) 333 #define FEC_TX_BD_FTYPE(X) (((X) & 0xf) << 20) 334 335 /* The number of Tx and Rx buffers. These are allocated from the page 336 * pool. The code may assume these are power of two, so it it best 337 * to keep them that size. 338 * We don't need to allocate pages for the transmitter. We just use 339 * the skbuffer directly. 340 */ 341 342 #define FEC_ENET_RX_PAGES 256 343 #define FEC_ENET_RX_FRSIZE 2048 344 #define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 345 #define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 346 #define FEC_ENET_TX_FRSIZE 2048 347 #define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 348 #define TX_RING_SIZE 512 /* Must be power of two */ 349 #define TX_RING_MOD_MASK 511 /* for this to work */ 350 351 #define BD_ENET_RX_INT 0x00800000 352 #define BD_ENET_RX_PTP ((ushort)0x0400) 353 #define BD_ENET_RX_ICE 0x00000020 354 #define BD_ENET_RX_PCR 0x00000010 355 #define FLAG_RX_CSUM_ENABLED (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 356 #define FLAG_RX_CSUM_ERROR (BD_ENET_RX_ICE | BD_ENET_RX_PCR) 357 358 /* Interrupt events/masks. */ 359 #define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 360 #define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 361 #define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 362 #define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 363 #define FEC_ENET_TXF_0 ((uint)0x08000000) /* Full frame transmitted */ 364 #define FEC_ENET_TXF_1 ((uint)0x00000008) /* Full frame transmitted */ 365 #define FEC_ENET_TXF_2 ((uint)0x00000080) /* Full frame transmitted */ 366 #define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 367 #define FEC_ENET_RXF_0 ((uint)0x02000000) /* Full frame received */ 368 #define FEC_ENET_RXF_1 ((uint)0x00000002) /* Full frame received */ 369 #define FEC_ENET_RXF_2 ((uint)0x00000020) /* Full frame received */ 370 #define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 371 #define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 372 #define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 373 #define FEC_ENET_WAKEUP ((uint)0x00020000) /* Wakeup request */ 374 #define FEC_ENET_TXF (FEC_ENET_TXF_0 | FEC_ENET_TXF_1 | FEC_ENET_TXF_2) 375 #define FEC_ENET_RXF (FEC_ENET_RXF_0 | FEC_ENET_RXF_1 | FEC_ENET_RXF_2) 376 #define FEC_ENET_TS_AVAIL ((uint)0x00010000) 377 #define FEC_ENET_TS_TIMER ((uint)0x00008000) 378 379 #define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 380 #define FEC_NAPI_IMASK FEC_ENET_MII 381 #define FEC_RX_DISABLED_IMASK (FEC_DEFAULT_IMASK & (~FEC_ENET_RXF)) 382 383 /* ENET interrupt coalescing macro define */ 384 #define FEC_ITR_CLK_SEL (0x1 << 30) 385 #define FEC_ITR_EN (0x1 << 31) 386 #define FEC_ITR_ICFT(X) (((X) & 0xff) << 20) 387 #define FEC_ITR_ICTT(X) ((X) & 0xffff) 388 #define FEC_ITR_ICFT_DEFAULT 200 /* Set 200 frame count threshold */ 389 #define FEC_ITR_ICTT_DEFAULT 1000 /* Set 1000us timer threshold */ 390 391 #define FEC_VLAN_TAG_LEN 0x04 392 #define FEC_ETHTYPE_LEN 0x02 393 394 /* Controller is ENET-MAC */ 395 #define FEC_QUIRK_ENET_MAC (1 << 0) 396 /* Controller needs driver to swap frame */ 397 #define FEC_QUIRK_SWAP_FRAME (1 << 1) 398 /* Controller uses gasket */ 399 #define FEC_QUIRK_USE_GASKET (1 << 2) 400 /* Controller has GBIT support */ 401 #define FEC_QUIRK_HAS_GBIT (1 << 3) 402 /* Controller has extend desc buffer */ 403 #define FEC_QUIRK_HAS_BUFDESC_EX (1 << 4) 404 /* Controller has hardware checksum support */ 405 #define FEC_QUIRK_HAS_CSUM (1 << 5) 406 /* Controller has hardware vlan support */ 407 #define FEC_QUIRK_HAS_VLAN (1 << 6) 408 /* ENET IP errata ERR006358 409 * 410 * If the ready bit in the transmit buffer descriptor (TxBD[R]) is previously 411 * detected as not set during a prior frame transmission, then the 412 * ENET_TDAR[TDAR] bit is cleared at a later time, even if additional TxBDs 413 * were added to the ring and the ENET_TDAR[TDAR] bit is set. This results in 414 * frames not being transmitted until there is a 0-to-1 transition on 415 * ENET_TDAR[TDAR]. 416 */ 417 #define FEC_QUIRK_ERR006358 (1 << 7) 418 /* ENET IP hw AVB 419 * 420 * i.MX6SX ENET IP add Audio Video Bridging (AVB) feature support. 421 * - Two class indicators on receive with configurable priority 422 * - Two class indicators and line speed timer on transmit allowing 423 * implementation class credit based shapers externally 424 * - Additional DMA registers provisioned to allow managing up to 3 425 * independent rings 426 */ 427 #define FEC_QUIRK_HAS_AVB (1 << 8) 428 /* There is a TDAR race condition for mutliQ when the software sets TDAR 429 * and the UDMA clears TDAR simultaneously or in a small window (2-4 cycles). 430 * This will cause the udma_tx and udma_tx_arbiter state machines to hang. 431 * The issue exist at i.MX6SX enet IP. 432 */ 433 #define FEC_QUIRK_ERR007885 (1 << 9) 434 /* ENET Block Guide/ Chapter for the iMX6SX (PELE) address one issue: 435 * After set ENET_ATCR[Capture], there need some time cycles before the counter 436 * value is capture in the register clock domain. 437 * The wait-time-cycles is at least 6 clock cycles of the slower clock between 438 * the register clock and the 1588 clock. The 1588 ts_clk is fixed to 25Mhz, 439 * register clock is 66Mhz, so the wait-time-cycles must be greater than 240ns 440 * (40ns * 6). 441 */ 442 #define FEC_QUIRK_BUG_CAPTURE (1 << 10) 443 /* Controller has only one MDIO bus */ 444 #define FEC_QUIRK_SINGLE_MDIO (1 << 11) 445 /* Controller supports RACC register */ 446 #define FEC_QUIRK_HAS_RACC (1 << 12) 447 /* Controller supports interrupt coalesc */ 448 #define FEC_QUIRK_HAS_COALESCE (1 << 13) 449 /* Interrupt doesn't wake CPU from deep idle */ 450 #define FEC_QUIRK_ERR006687 (1 << 14) 451 /* The MIB counters should be cleared and enabled during 452 * initialisation. 453 */ 454 #define FEC_QUIRK_MIB_CLEAR (1 << 15) 455 /* Only i.MX25/i.MX27/i.MX28 controller supports FRBR,FRSR registers, 456 * those FIFO receive registers are resolved in other platforms. 457 */ 458 #define FEC_QUIRK_HAS_FRREG (1 << 16) 459 460 struct bufdesc_prop { 461 int qid; 462 /* Address of Rx and Tx buffers */ 463 struct bufdesc *base; 464 struct bufdesc *last; 465 struct bufdesc *cur; 466 void __iomem *reg_desc_active; 467 dma_addr_t dma; 468 unsigned short ring_size; 469 unsigned char dsize; 470 unsigned char dsize_log2; 471 }; 472 473 struct fec_enet_priv_tx_q { 474 struct bufdesc_prop bd; 475 unsigned char *tx_bounce[TX_RING_SIZE]; 476 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 477 478 unsigned short tx_stop_threshold; 479 unsigned short tx_wake_threshold; 480 481 struct bufdesc *dirty_tx; 482 char *tso_hdrs; 483 dma_addr_t tso_hdrs_dma; 484 }; 485 486 struct fec_enet_priv_rx_q { 487 struct bufdesc_prop bd; 488 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 489 }; 490 491 /* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 492 * tx_bd_base always point to the base of the buffer descriptors. The 493 * cur_rx and cur_tx point to the currently available buffer. 494 * The dirty_tx tracks the current buffer that is being sent by the 495 * controller. The cur_tx and dirty_tx are equal under both completely 496 * empty and completely full conditions. The empty/ready indicator in 497 * the buffer descriptor determines the actual condition. 498 */ 499 struct fec_enet_private { 500 /* Hardware registers of the FEC device */ 501 void __iomem *hwp; 502 503 struct net_device *netdev; 504 505 struct clk *clk_ipg; 506 struct clk *clk_ahb; 507 struct clk *clk_ref; 508 struct clk *clk_enet_out; 509 struct clk *clk_ptp; 510 511 bool ptp_clk_on; 512 struct mutex ptp_clk_mutex; 513 unsigned int num_tx_queues; 514 unsigned int num_rx_queues; 515 516 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 517 struct fec_enet_priv_tx_q *tx_queue[FEC_ENET_MAX_TX_QS]; 518 struct fec_enet_priv_rx_q *rx_queue[FEC_ENET_MAX_RX_QS]; 519 520 unsigned int total_tx_ring_size; 521 unsigned int total_rx_ring_size; 522 523 unsigned long work_tx; 524 unsigned long work_rx; 525 unsigned long work_ts; 526 unsigned long work_mdio; 527 528 struct platform_device *pdev; 529 530 int dev_id; 531 532 /* Phylib and MDIO interface */ 533 struct mii_bus *mii_bus; 534 int mii_timeout; 535 uint phy_speed; 536 phy_interface_t phy_interface; 537 struct device_node *phy_node; 538 int link; 539 int full_duplex; 540 int speed; 541 struct completion mdio_done; 542 int irq[FEC_IRQ_NUM]; 543 bool bufdesc_ex; 544 int pause_flag; 545 int wol_flag; 546 u32 quirks; 547 548 struct napi_struct napi; 549 int csum_flags; 550 551 struct work_struct tx_timeout_work; 552 553 struct ptp_clock *ptp_clock; 554 struct ptp_clock_info ptp_caps; 555 unsigned long last_overflow_check; 556 spinlock_t tmreg_lock; 557 struct cyclecounter cc; 558 struct timecounter tc; 559 int rx_hwtstamp_filter; 560 u32 base_incval; 561 u32 cycle_speed; 562 int hwts_rx_en; 563 int hwts_tx_en; 564 struct delayed_work time_keep; 565 struct regulator *reg_phy; 566 567 unsigned int tx_align; 568 unsigned int rx_align; 569 570 /* hw interrupt coalesce */ 571 unsigned int rx_pkts_itr; 572 unsigned int rx_time_itr; 573 unsigned int tx_pkts_itr; 574 unsigned int tx_time_itr; 575 unsigned int itr_clk_rate; 576 577 u32 rx_copybreak; 578 579 /* ptp clock period in ns*/ 580 unsigned int ptp_inc; 581 582 /* pps */ 583 int pps_channel; 584 unsigned int reload_period; 585 int pps_enable; 586 unsigned int next_counter; 587 588 u64 ethtool_stats[0]; 589 }; 590 591 void fec_ptp_init(struct platform_device *pdev, int irq_idx); 592 void fec_ptp_stop(struct platform_device *pdev); 593 void fec_ptp_start_cyclecounter(struct net_device *ndev); 594 int fec_ptp_set(struct net_device *ndev, struct ifreq *ifr); 595 int fec_ptp_get(struct net_device *ndev, struct ifreq *ifr); 596 597 /****************************************************************************/ 598 #endif /* FEC_H */ 599
