1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* to be used by qlogicfas and qlogic_cs */ 3 #ifndef __QLOGICFAS408_H 4 #define __QLOGICFAS408_H 5 6 /*----------------------------------------------------------------*/ 7 /* Configuration */ 8 9 /* Set the following to max out the speed of the PIO PseudoDMA transfers, 10 again, 0 tends to be slower, but more stable. */ 11 12 #define QL_TURBO_PDMA 1 13 14 /* This should be 1 to enable parity detection */ 15 16 #define QL_ENABLE_PARITY 1 17 18 /* This will reset all devices when the driver is initialized (during bootup). 19 The other linux drivers don't do this, but the DOS drivers do, and after 20 using DOS or some kind of crash or lockup this will bring things back 21 without requiring a cold boot. It does take some time to recover from a 22 reset, so it is slower, and I have seen timeouts so that devices weren't 23 recognized when this was set. */ 24 25 #define QL_RESET_AT_START 0 26 27 /* crystal frequency in megahertz (for offset 5 and 9) 28 Please set this for your card. Most Qlogic cards are 40 Mhz. The 29 Control Concepts ISA (not VLB) is 24 Mhz */ 30 31 #define XTALFREQ 40 32 33 /**********/ 34 /* DANGER! modify these at your own risk */ 35 /* SLOWCABLE can usually be reset to zero if you have a clean setup and 36 proper termination. The rest are for synchronous transfers and other 37 advanced features if your device can transfer faster than 5Mb/sec. 38 If you are really curious, email me for a quick howto until I have 39 something official */ 40 /**********/ 41 42 /*****/ 43 /* config register 1 (offset 8) options */ 44 /* This needs to be set to 1 if your cabling is long or noisy */ 45 #define SLOWCABLE 1 46 47 /*****/ 48 /* offset 0xc */ 49 /* This will set fast (10Mhz) synchronous timing when set to 1 50 For this to have an effect, FASTCLK must also be 1 */ 51 #define FASTSCSI 0 52 53 /* This when set to 1 will set a faster sync transfer rate */ 54 #define FASTCLK 0 /*(XTALFREQ>25?1:0)*/ 55 56 /*****/ 57 /* offset 6 */ 58 /* This is the sync transfer divisor, XTALFREQ/X will be the maximum 59 achievable data rate (assuming the rest of the system is capable 60 and set properly) */ 61 #define SYNCXFRPD 5 /*(XTALFREQ/5)*/ 62 63 /*****/ 64 /* offset 7 */ 65 /* This is the count of how many synchronous transfers can take place 66 i.e. how many reqs can occur before an ack is given. 67 The maximum value for this is 15, the upper bits can modify 68 REQ/ACK assertion and deassertion during synchronous transfers 69 If this is 0, the bus will only transfer asynchronously */ 70 #define SYNCOFFST 0 71 /* for the curious, bits 7&6 control the deassertion delay in 1/2 cycles 72 of the 40Mhz clock. If FASTCLK is 1, specifying 01 (1/2) will 73 cause the deassertion to be early by 1/2 clock. Bits 5&4 control 74 the assertion delay, also in 1/2 clocks (FASTCLK is ignored here). */ 75 76 /*----------------------------------------------------------------*/ 77 78 struct qlogicfas408_priv { 79 int qbase; /* Port */ 80 int qinitid; /* initiator ID */ 81 int qabort; /* Flag to cause an abort */ 82 int qlirq; /* IRQ being used */ 83 int int_type; /* type of irq, 2 for ISA board, 0 for PCMCIA */ 84 char qinfo[80]; /* description */ 85 struct scsi_cmnd *qlcmd; /* current command being processed */ 86 struct Scsi_Host *shost; /* pointer back to host */ 87 struct qlogicfas408_priv *next; /* next private struct */ 88 }; 89 90 /* The qlogic card uses two register maps - These macros select which one */ 91 #define REG0 ( outb( inb( qbase + 0xd ) & 0x7f , qbase + 0xd ), outb( 4 , qbase + 0xd )) 92 #define REG1 ( outb( inb( qbase + 0xd ) | 0x80 , qbase + 0xd ), outb( 0xb4 | int_type, qbase + 0xd )) 93 94 /* following is watchdog timeout in microseconds */ 95 #define WATCHDOG 5000000 96 97 /*----------------------------------------------------------------*/ 98 /* the following will set the monitor border color (useful to find 99 where something crashed or gets stuck at and as a simple profiler) */ 100 101 #define rtrc(i) {} 102 103 #define get_priv_by_cmd(x) (struct qlogicfas408_priv *)&((x)->device->host->hostdata[0]) 104 #define get_priv_by_host(x) (struct qlogicfas408_priv *)&((x)->hostdata[0]) 105 106 irqreturn_t qlogicfas408_ihandl(int irq, void *dev_id); 107 int qlogicfas408_queuecommand(struct Scsi_Host *h, struct scsi_cmnd * cmd); 108 int qlogicfas408_biosparam(struct scsi_device * disk, 109 struct block_device *dev, 110 sector_t capacity, int ip[]); 111 int qlogicfas408_abort(struct scsi_cmnd * cmd); 112 extern int qlogicfas408_host_reset(struct scsi_cmnd *cmd); 113 const char *qlogicfas408_info(struct Scsi_Host *host); 114 int qlogicfas408_get_chip_type(int qbase, int int_type); 115 void qlogicfas408_setup(int qbase, int id, int int_type); 116 int qlogicfas408_detect(int qbase, int int_type); 117 void qlogicfas408_disable_ints(struct qlogicfas408_priv *priv); 118 #endif /* __QLOGICFAS408_H */ 119 120
