1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries. 4 * All rights reserved. 5 */ 6 7 #ifndef WILC_WLAN_H 8 #define WILC_WLAN_H 9 10 #include <linux/types.h> 11 12 /******************************************** 13 * 14 * Mac eth header length 15 * 16 ********************************************/ 17 #define DRIVER_HANDLER_SIZE 4 18 #define MAX_MAC_HDR_LEN 26 /* QOS_MAC_HDR_LEN */ 19 #define SUB_MSDU_HEADER_LENGTH 14 20 #define SNAP_HDR_LEN 8 21 #define ETHERNET_HDR_LEN 14 22 #define WORD_ALIGNMENT_PAD 0 23 24 #define ETH_ETHERNET_HDR_OFFSET (MAX_MAC_HDR_LEN + \ 25 SUB_MSDU_HEADER_LENGTH + \ 26 SNAP_HDR_LEN - \ 27 ETHERNET_HDR_LEN + \ 28 WORD_ALIGNMENT_PAD) 29 30 #define HOST_HDR_OFFSET 4 31 #define ETHERNET_HDR_LEN 14 32 #define IP_HDR_LEN 20 33 #define IP_HDR_OFFSET ETHERNET_HDR_LEN 34 #define UDP_HDR_OFFSET (IP_HDR_LEN + IP_HDR_OFFSET) 35 #define UDP_HDR_LEN 8 36 #define UDP_DATA_OFFSET (UDP_HDR_OFFSET + UDP_HDR_LEN) 37 #define ETH_CONFIG_PKT_HDR_LEN UDP_DATA_OFFSET 38 39 #define ETH_CONFIG_PKT_HDR_OFFSET (ETH_ETHERNET_HDR_OFFSET + \ 40 ETH_CONFIG_PKT_HDR_LEN) 41 42 /******************************************** 43 * 44 * Register Defines 45 * 46 ********************************************/ 47 #define WILC_PERIPH_REG_BASE 0x1000 48 #define WILC_CHANGING_VIR_IF 0x108c 49 #define WILC_CHIPID WILC_PERIPH_REG_BASE 50 #define WILC_GLB_RESET_0 (WILC_PERIPH_REG_BASE + 0x400) 51 #define WILC_PIN_MUX_0 (WILC_PERIPH_REG_BASE + 0x408) 52 #define WILC_HOST_TX_CTRL (WILC_PERIPH_REG_BASE + 0x6c) 53 #define WILC_HOST_RX_CTRL_0 (WILC_PERIPH_REG_BASE + 0x70) 54 #define WILC_HOST_RX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x74) 55 #define WILC_HOST_VMM_CTL (WILC_PERIPH_REG_BASE + 0x78) 56 #define WILC_HOST_RX_CTRL (WILC_PERIPH_REG_BASE + 0x80) 57 #define WILC_HOST_RX_EXTRA_SIZE (WILC_PERIPH_REG_BASE + 0x84) 58 #define WILC_HOST_TX_CTRL_1 (WILC_PERIPH_REG_BASE + 0x88) 59 #define WILC_MISC (WILC_PERIPH_REG_BASE + 0x428) 60 #define WILC_INTR_REG_BASE (WILC_PERIPH_REG_BASE + 0xa00) 61 #define WILC_INTR_ENABLE WILC_INTR_REG_BASE 62 #define WILC_INTR2_ENABLE (WILC_INTR_REG_BASE + 4) 63 64 #define WILC_INTR_POLARITY (WILC_INTR_REG_BASE + 0x10) 65 #define WILC_INTR_TYPE (WILC_INTR_REG_BASE + 0x20) 66 #define WILC_INTR_CLEAR (WILC_INTR_REG_BASE + 0x30) 67 #define WILC_INTR_STATUS (WILC_INTR_REG_BASE + 0x40) 68 69 #define WILC_VMM_TBL_SIZE 64 70 #define WILC_VMM_TX_TBL_BASE 0x150400 71 #define WILC_VMM_RX_TBL_BASE 0x150500 72 73 #define WILC_VMM_BASE 0x150000 74 #define WILC_VMM_CORE_CTL WILC_VMM_BASE 75 #define WILC_VMM_TBL_CTL (WILC_VMM_BASE + 0x4) 76 #define WILC_VMM_TBL_ENTRY (WILC_VMM_BASE + 0x8) 77 #define WILC_VMM_TBL0_SIZE (WILC_VMM_BASE + 0xc) 78 #define WILC_VMM_TO_HOST_SIZE (WILC_VMM_BASE + 0x10) 79 #define WILC_VMM_CORE_CFG (WILC_VMM_BASE + 0x14) 80 #define WILC_VMM_TBL_ACTIVE (WILC_VMM_BASE + 040) 81 #define WILC_VMM_TBL_STATUS (WILC_VMM_BASE + 0x44) 82 83 #define WILC_SPI_REG_BASE 0xe800 84 #define WILC_SPI_CTL WILC_SPI_REG_BASE 85 #define WILC_SPI_MASTER_DMA_ADDR (WILC_SPI_REG_BASE + 0x4) 86 #define WILC_SPI_MASTER_DMA_COUNT (WILC_SPI_REG_BASE + 0x8) 87 #define WILC_SPI_SLAVE_DMA_ADDR (WILC_SPI_REG_BASE + 0xc) 88 #define WILC_SPI_SLAVE_DMA_COUNT (WILC_SPI_REG_BASE + 0x10) 89 #define WILC_SPI_TX_MODE (WILC_SPI_REG_BASE + 0x20) 90 #define WILC_SPI_PROTOCOL_CONFIG (WILC_SPI_REG_BASE + 0x24) 91 #define WILC_SPI_INTR_CTL (WILC_SPI_REG_BASE + 0x2c) 92 93 #define WILC_SPI_PROTOCOL_OFFSET (WILC_SPI_PROTOCOL_CONFIG - \ 94 WILC_SPI_REG_BASE) 95 96 #define WILC_AHB_DATA_MEM_BASE 0x30000 97 #define WILC_AHB_SHARE_MEM_BASE 0xd0000 98 99 #define WILC_VMM_TBL_RX_SHADOW_BASE WILC_AHB_SHARE_MEM_BASE 100 #define WILC_VMM_TBL_RX_SHADOW_SIZE 256 101 102 #define WILC_GP_REG_0 0x149c 103 #define WILC_GP_REG_1 0x14a0 104 105 #define WILC_HAVE_SDIO_IRQ_GPIO BIT(0) 106 #define WILC_HAVE_USE_PMU BIT(1) 107 #define WILC_HAVE_SLEEP_CLK_SRC_RTC BIT(2) 108 #define WILC_HAVE_SLEEP_CLK_SRC_XO BIT(3) 109 #define WILC_HAVE_EXT_PA_INV_TX_RX BIT(4) 110 #define WILC_HAVE_LEGACY_RF_SETTINGS BIT(5) 111 #define WILC_HAVE_XTAL_24 BIT(6) 112 #define WILC_HAVE_DISABLE_WILC_UART BIT(7) 113 #define WILC_HAVE_USE_IRQ_AS_HOST_WAKE BIT(8) 114 115 /******************************************** 116 * 117 * Wlan Defines 118 * 119 ********************************************/ 120 #define WILC_CFG_PKT 1 121 #define WILC_NET_PKT 0 122 #define WILC_MGMT_PKT 2 123 124 #define WILC_CFG_SET 1 125 #define WILC_CFG_QUERY 0 126 127 #define WILC_CFG_RSP 1 128 #define WILC_CFG_RSP_STATUS 2 129 #define WILC_CFG_RSP_SCAN 3 130 131 #define WILC_PLL_TO_SDIO 4 132 #define WILC_PLL_TO_SPI 2 133 #define ABORT_INT BIT(31) 134 135 #define LINUX_RX_SIZE (96 * 1024) 136 #define LINUX_TX_SIZE (64 * 1024) 137 138 #define MODALIAS "WILC_SPI" 139 #define GPIO_NUM 0x44 140 /*******************************************/ 141 /* E0 and later Interrupt flags. */ 142 /*******************************************/ 143 /*******************************************/ 144 /* E0 and later Interrupt flags. */ 145 /* IRQ Status word */ 146 /* 15:0 = DMA count in words. */ 147 /* 16: INT0 flag */ 148 /* 17: INT1 flag */ 149 /* 18: INT2 flag */ 150 /* 19: INT3 flag */ 151 /* 20: INT4 flag */ 152 /* 21: INT5 flag */ 153 /*******************************************/ 154 #define IRG_FLAGS_OFFSET 16 155 #define IRQ_DMA_WD_CNT_MASK ((1ul << IRG_FLAGS_OFFSET) - 1) 156 #define INT_0 BIT(IRG_FLAGS_OFFSET) 157 #define INT_1 BIT(IRG_FLAGS_OFFSET + 1) 158 #define INT_2 BIT(IRG_FLAGS_OFFSET + 2) 159 #define INT_3 BIT(IRG_FLAGS_OFFSET + 3) 160 #define INT_4 BIT(IRG_FLAGS_OFFSET + 4) 161 #define INT_5 BIT(IRG_FLAGS_OFFSET + 5) 162 #define MAX_NUM_INT 6 163 164 /*******************************************/ 165 /* E0 and later Interrupt flags. */ 166 /* IRQ Clear word */ 167 /* 0: Clear INT0 */ 168 /* 1: Clear INT1 */ 169 /* 2: Clear INT2 */ 170 /* 3: Clear INT3 */ 171 /* 4: Clear INT4 */ 172 /* 5: Clear INT5 */ 173 /* 6: Select VMM table 1 */ 174 /* 7: Select VMM table 2 */ 175 /* 8: Enable VMM */ 176 /*******************************************/ 177 #define CLR_INT0 BIT(0) 178 #define CLR_INT1 BIT(1) 179 #define CLR_INT2 BIT(2) 180 #define CLR_INT3 BIT(3) 181 #define CLR_INT4 BIT(4) 182 #define CLR_INT5 BIT(5) 183 #define SEL_VMM_TBL0 BIT(6) 184 #define SEL_VMM_TBL1 BIT(7) 185 #define EN_VMM BIT(8) 186 187 #define DATA_INT_EXT INT_0 188 #define PLL_INT_EXT INT_1 189 #define SLEEP_INT_EXT INT_2 190 #define ALL_INT_EXT (DATA_INT_EXT | PLL_INT_EXT | SLEEP_INT_EXT) 191 #define NUM_INT_EXT 3 192 193 #define DATA_INT_CLR CLR_INT0 194 #define PLL_INT_CLR CLR_INT1 195 #define SLEEP_INT_CLR CLR_INT2 196 197 #define ENABLE_RX_VMM (SEL_VMM_TBL1 | EN_VMM) 198 #define ENABLE_TX_VMM (SEL_VMM_TBL0 | EN_VMM) 199 /*time for expiring the completion of cfg packets*/ 200 #define CFG_PKTS_TIMEOUT 2000 201 202 #define IS_MANAGMEMENT 0x100 203 #define IS_MANAGMEMENT_CALLBACK 0x080 204 #define IS_MGMT_STATUS_SUCCES 0x040 205 206 /******************************************** 207 * 208 * Tx/Rx Queue Structure 209 * 210 ********************************************/ 211 212 struct txq_entry_t { 213 struct list_head list; 214 int type; 215 int tcp_pending_ack_idx; 216 u8 *buffer; 217 int buffer_size; 218 void *priv; 219 int status; 220 void (*tx_complete_func)(void *priv, int status); 221 }; 222 223 struct rxq_entry_t { 224 struct list_head list; 225 u8 *buffer; 226 int buffer_size; 227 }; 228 229 /******************************************** 230 * 231 * Host IF Structure 232 * 233 ********************************************/ 234 struct wilc; 235 struct wilc_hif_func { 236 int (*hif_init)(struct wilc *wilc, bool resume); 237 int (*hif_deinit)(struct wilc *wilc); 238 int (*hif_read_reg)(struct wilc *wilc, u32 addr, u32 *data); 239 int (*hif_write_reg)(struct wilc *wilc, u32 addr, u32 data); 240 int (*hif_block_rx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size); 241 int (*hif_block_tx)(struct wilc *wilc, u32 addr, u8 *buf, u32 size); 242 int (*hif_read_int)(struct wilc *wilc, u32 *int_status); 243 int (*hif_clear_int_ext)(struct wilc *wilc, u32 val); 244 int (*hif_read_size)(struct wilc *wilc, u32 *size); 245 int (*hif_block_tx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size); 246 int (*hif_block_rx_ext)(struct wilc *wilc, u32 addr, u8 *buf, u32 size); 247 int (*hif_sync_ext)(struct wilc *wilc, int nint); 248 int (*enable_interrupt)(struct wilc *nic); 249 void (*disable_interrupt)(struct wilc *nic); 250 }; 251 252 #define MAX_CFG_FRAME_SIZE 1468 253 254 struct wilc_cfg_frame { 255 u8 wid_header[8]; 256 u8 frame[MAX_CFG_FRAME_SIZE]; 257 }; 258 259 struct wilc_cfg_rsp { 260 int type; 261 u32 seq_no; 262 }; 263 264 struct wilc; 265 struct wilc_vif; 266 267 int wilc_wlan_firmware_download(struct wilc *wilc, const u8 *buffer, 268 u32 buffer_size); 269 int wilc_wlan_start(struct wilc *wilc); 270 int wilc_wlan_stop(struct wilc *wilc); 271 int wilc_wlan_txq_add_net_pkt(struct net_device *dev, void *priv, u8 *buffer, 272 u32 buffer_size, wilc_tx_complete_func_t func); 273 int wilc_wlan_handle_txq(struct net_device *dev, u32 *txq_count); 274 void wilc_handle_isr(struct wilc *wilc); 275 void wilc_wlan_cleanup(struct net_device *dev); 276 int wilc_wlan_cfg_set(struct wilc_vif *vif, int start, u16 wid, u8 *buffer, 277 u32 buffer_size, int commit, u32 drv_handler); 278 int wilc_wlan_cfg_get(struct wilc_vif *vif, int start, u16 wid, int commit, 279 u32 drv_handler); 280 int wilc_wlan_cfg_get_val(u16 wid, u8 *buffer, u32 buffer_size); 281 int wilc_wlan_txq_add_mgmt_pkt(struct net_device *dev, void *priv, u8 *buffer, 282 u32 buffer_size, wilc_tx_complete_func_t func); 283 void wilc_chip_sleep_manually(struct wilc *wilc); 284 285 void wilc_enable_tcp_ack_filter(bool value); 286 int wilc_wlan_get_num_conn_ifcs(struct wilc *wilc); 287 netdev_tx_t wilc_mac_xmit(struct sk_buff *skb, struct net_device *dev); 288 289 void wilc_wfi_p2p_rx(struct net_device *dev, u8 *buff, u32 size); 290 void host_wakeup_notify(struct wilc *wilc); 291 void host_sleep_notify(struct wilc *wilc); 292 extern bool wilc_enable_ps; 293 void chip_allow_sleep(struct wilc *wilc); 294 void chip_wakeup(struct wilc *wilc); 295 int wilc_send_config_pkt(struct wilc_vif *vif, u8 mode, struct wid *wids, 296 u32 count, u32 drv); 297 #endif 298
