1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 */
6
7 #ifndef __ASM_ESR_H
8 #define __ASM_ESR_H
9
10 #include <asm/memory.h>
11 #include <asm/sysreg.h>
12
13 #define ESR_ELx_EC_UNKNOWN (0x00)
14 #define ESR_ELx_EC_WFx (0x01)
15 /* Unallocated EC: 0x02 */
16 #define ESR_ELx_EC_CP15_32 (0x03)
17 #define ESR_ELx_EC_CP15_64 (0x04)
18 #define ESR_ELx_EC_CP14_MR (0x05)
19 #define ESR_ELx_EC_CP14_LS (0x06)
20 #define ESR_ELx_EC_FP_ASIMD (0x07)
21 #define ESR_ELx_EC_CP10_ID (0x08) /* EL2 only */
22 #define ESR_ELx_EC_PAC (0x09) /* EL2 and above */
23 /* Unallocated EC: 0x0A - 0x0B */
24 #define ESR_ELx_EC_CP14_64 (0x0C)
25 /* Unallocated EC: 0x0d */
26 #define ESR_ELx_EC_ILL (0x0E)
27 /* Unallocated EC: 0x0F - 0x10 */
28 #define ESR_ELx_EC_SVC32 (0x11)
29 #define ESR_ELx_EC_HVC32 (0x12) /* EL2 only */
30 #define ESR_ELx_EC_SMC32 (0x13) /* EL2 and above */
31 /* Unallocated EC: 0x14 */
32 #define ESR_ELx_EC_SVC64 (0x15)
33 #define ESR_ELx_EC_HVC64 (0x16) /* EL2 and above */
34 #define ESR_ELx_EC_SMC64 (0x17) /* EL2 and above */
35 #define ESR_ELx_EC_SYS64 (0x18)
36 #define ESR_ELx_EC_SVE (0x19)
37 #define ESR_ELx_EC_ERET (0x1a) /* EL2 only */
38 /* Unallocated EC: 0x1b - 0x1E */
39 #define ESR_ELx_EC_IMP_DEF (0x1f) /* EL3 only */
40 #define ESR_ELx_EC_IABT_LOW (0x20)
41 #define ESR_ELx_EC_IABT_CUR (0x21)
42 #define ESR_ELx_EC_PC_ALIGN (0x22)
43 /* Unallocated EC: 0x23 */
44 #define ESR_ELx_EC_DABT_LOW (0x24)
45 #define ESR_ELx_EC_DABT_CUR (0x25)
46 #define ESR_ELx_EC_SP_ALIGN (0x26)
47 /* Unallocated EC: 0x27 */
48 #define ESR_ELx_EC_FP_EXC32 (0x28)
49 /* Unallocated EC: 0x29 - 0x2B */
50 #define ESR_ELx_EC_FP_EXC64 (0x2C)
51 /* Unallocated EC: 0x2D - 0x2E */
52 #define ESR_ELx_EC_SERROR (0x2F)
53 #define ESR_ELx_EC_BREAKPT_LOW (0x30)
54 #define ESR_ELx_EC_BREAKPT_CUR (0x31)
55 #define ESR_ELx_EC_SOFTSTP_LOW (0x32)
56 #define ESR_ELx_EC_SOFTSTP_CUR (0x33)
57 #define ESR_ELx_EC_WATCHPT_LOW (0x34)
58 #define ESR_ELx_EC_WATCHPT_CUR (0x35)
59 /* Unallocated EC: 0x36 - 0x37 */
60 #define ESR_ELx_EC_BKPT32 (0x38)
61 /* Unallocated EC: 0x39 */
62 #define ESR_ELx_EC_VECTOR32 (0x3A) /* EL2 only */
63 /* Unallocted EC: 0x3B */
64 #define ESR_ELx_EC_BRK64 (0x3C)
65 /* Unallocated EC: 0x3D - 0x3F */
66 #define ESR_ELx_EC_MAX (0x3F)
67
68 #define ESR_ELx_EC_SHIFT (26)
69 #define ESR_ELx_EC_MASK (UL(0x3F) << ESR_ELx_EC_SHIFT)
70 #define ESR_ELx_EC(esr) (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
71
72 #define ESR_ELx_IL_SHIFT (25)
73 #define ESR_ELx_IL (UL(1) << ESR_ELx_IL_SHIFT)
74 #define ESR_ELx_ISS_MASK (ESR_ELx_IL - 1)
75
76 /* ISS field definitions shared by different classes */
77 #define ESR_ELx_WNR_SHIFT (6)
78 #define ESR_ELx_WNR (UL(1) << ESR_ELx_WNR_SHIFT)
79
80 /* Asynchronous Error Type */
81 #define ESR_ELx_IDS_SHIFT (24)
82 #define ESR_ELx_IDS (UL(1) << ESR_ELx_IDS_SHIFT)
83 #define ESR_ELx_AET_SHIFT (10)
84 #define ESR_ELx_AET (UL(0x7) << ESR_ELx_AET_SHIFT)
85
86 #define ESR_ELx_AET_UC (UL(0) << ESR_ELx_AET_SHIFT)
87 #define ESR_ELx_AET_UEU (UL(1) << ESR_ELx_AET_SHIFT)
88 #define ESR_ELx_AET_UEO (UL(2) << ESR_ELx_AET_SHIFT)
89 #define ESR_ELx_AET_UER (UL(3) << ESR_ELx_AET_SHIFT)
90 #define ESR_ELx_AET_CE (UL(6) << ESR_ELx_AET_SHIFT)
91
92 /* Shared ISS field definitions for Data/Instruction aborts */
93 #define ESR_ELx_SET_SHIFT (11)
94 #define ESR_ELx_SET_MASK (UL(3) << ESR_ELx_SET_SHIFT)
95 #define ESR_ELx_FnV_SHIFT (10)
96 #define ESR_ELx_FnV (UL(1) << ESR_ELx_FnV_SHIFT)
97 #define ESR_ELx_EA_SHIFT (9)
98 #define ESR_ELx_EA (UL(1) << ESR_ELx_EA_SHIFT)
99 #define ESR_ELx_S1PTW_SHIFT (7)
100 #define ESR_ELx_S1PTW (UL(1) << ESR_ELx_S1PTW_SHIFT)
101
102 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
103 #define ESR_ELx_FSC (0x3F)
104 #define ESR_ELx_FSC_TYPE (0x3C)
105 #define ESR_ELx_FSC_EXTABT (0x10)
106 #define ESR_ELx_FSC_SERROR (0x11)
107 #define ESR_ELx_FSC_ACCESS (0x08)
108 #define ESR_ELx_FSC_FAULT (0x04)
109 #define ESR_ELx_FSC_PERM (0x0C)
110
111 /* ISS field definitions for Data Aborts */
112 #define ESR_ELx_ISV_SHIFT (24)
113 #define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
114 #define ESR_ELx_SAS_SHIFT (22)
115 #define ESR_ELx_SAS (UL(3) << ESR_ELx_SAS_SHIFT)
116 #define ESR_ELx_SSE_SHIFT (21)
117 #define ESR_ELx_SSE (UL(1) << ESR_ELx_SSE_SHIFT)
118 #define ESR_ELx_SRT_SHIFT (16)
119 #define ESR_ELx_SRT_MASK (UL(0x1F) << ESR_ELx_SRT_SHIFT)
120 #define ESR_ELx_SF_SHIFT (15)
121 #define ESR_ELx_SF (UL(1) << ESR_ELx_SF_SHIFT)
122 #define ESR_ELx_AR_SHIFT (14)
123 #define ESR_ELx_AR (UL(1) << ESR_ELx_AR_SHIFT)
124 #define ESR_ELx_CM_SHIFT (8)
125 #define ESR_ELx_CM (UL(1) << ESR_ELx_CM_SHIFT)
126
127 /* ISS field definitions for exceptions taken in to Hyp */
128 #define ESR_ELx_CV (UL(1) << 24)
129 #define ESR_ELx_COND_SHIFT (20)
130 #define ESR_ELx_COND_MASK (UL(0xF) << ESR_ELx_COND_SHIFT)
131 #define ESR_ELx_WFx_ISS_TI (UL(1) << 0)
132 #define ESR_ELx_WFx_ISS_WFI (UL(0) << 0)
133 #define ESR_ELx_WFx_ISS_WFE (UL(1) << 0)
134 #define ESR_ELx_xVC_IMM_MASK ((1UL << 16) - 1)
135
136 #define DISR_EL1_IDS (UL(1) << 24)
137 /*
138 * DISR_EL1 and ESR_ELx share the bottom 13 bits, but the RES0 bits may mean
139 * different things in the future...
140 */
141 #define DISR_EL1_ESR_MASK (ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
142
143 /* ESR value templates for specific events */
144 #define ESR_ELx_WFx_MASK (ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
145 #define ESR_ELx_WFx_WFI_VAL ((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) | \
146 ESR_ELx_WFx_ISS_WFI)
147
148 /* BRK instruction trap from AArch64 state */
149 #define ESR_ELx_BRK64_ISS_COMMENT_MASK 0xffff
150
151 /* ISS field definitions for System instruction traps */
152 #define ESR_ELx_SYS64_ISS_RES0_SHIFT 22
153 #define ESR_ELx_SYS64_ISS_RES0_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_RES0_SHIFT)
154 #define ESR_ELx_SYS64_ISS_DIR_MASK 0x1
155 #define ESR_ELx_SYS64_ISS_DIR_READ 0x1
156 #define ESR_ELx_SYS64_ISS_DIR_WRITE 0x0
157
158 #define ESR_ELx_SYS64_ISS_RT_SHIFT 5
159 #define ESR_ELx_SYS64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_SYS64_ISS_RT_SHIFT)
160 #define ESR_ELx_SYS64_ISS_CRM_SHIFT 1
161 #define ESR_ELx_SYS64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRM_SHIFT)
162 #define ESR_ELx_SYS64_ISS_CRN_SHIFT 10
163 #define ESR_ELx_SYS64_ISS_CRN_MASK (UL(0xf) << ESR_ELx_SYS64_ISS_CRN_SHIFT)
164 #define ESR_ELx_SYS64_ISS_OP1_SHIFT 14
165 #define ESR_ELx_SYS64_ISS_OP1_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP1_SHIFT)
166 #define ESR_ELx_SYS64_ISS_OP2_SHIFT 17
167 #define ESR_ELx_SYS64_ISS_OP2_MASK (UL(0x7) << ESR_ELx_SYS64_ISS_OP2_SHIFT)
168 #define ESR_ELx_SYS64_ISS_OP0_SHIFT 20
169 #define ESR_ELx_SYS64_ISS_OP0_MASK (UL(0x3) << ESR_ELx_SYS64_ISS_OP0_SHIFT)
170 #define ESR_ELx_SYS64_ISS_SYS_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
171 ESR_ELx_SYS64_ISS_OP1_MASK | \
172 ESR_ELx_SYS64_ISS_OP2_MASK | \
173 ESR_ELx_SYS64_ISS_CRN_MASK | \
174 ESR_ELx_SYS64_ISS_CRM_MASK)
175 #define ESR_ELx_SYS64_ISS_SYS_VAL(op0, op1, op2, crn, crm) \
176 (((op0) << ESR_ELx_SYS64_ISS_OP0_SHIFT) | \
177 ((op1) << ESR_ELx_SYS64_ISS_OP1_SHIFT) | \
178 ((op2) << ESR_ELx_SYS64_ISS_OP2_SHIFT) | \
179 ((crn) << ESR_ELx_SYS64_ISS_CRN_SHIFT) | \
180 ((crm) << ESR_ELx_SYS64_ISS_CRM_SHIFT))
181
182 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK (ESR_ELx_SYS64_ISS_SYS_MASK | \
183 ESR_ELx_SYS64_ISS_DIR_MASK)
184 #define ESR_ELx_SYS64_ISS_RT(esr) \
185 (((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
186 /*
187 * User space cache operations have the following sysreg encoding
188 * in System instructions.
189 * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
190 */
191 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC 14
192 #define ESR_ELx_SYS64_ISS_CRM_DC_CVADP 13
193 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP 12
194 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU 11
195 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC 10
196 #define ESR_ELx_SYS64_ISS_CRM_IC_IVAU 5
197
198 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
199 ESR_ELx_SYS64_ISS_OP1_MASK | \
200 ESR_ELx_SYS64_ISS_OP2_MASK | \
201 ESR_ELx_SYS64_ISS_CRN_MASK | \
202 ESR_ELx_SYS64_ISS_DIR_MASK)
203 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
204 (ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
205 ESR_ELx_SYS64_ISS_DIR_WRITE)
206 /*
207 * User space MRS operations which are supported for emulation
208 * have the following sysreg encoding in System instructions.
209 * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
210 */
211 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK (ESR_ELx_SYS64_ISS_OP0_MASK | \
212 ESR_ELx_SYS64_ISS_OP1_MASK | \
213 ESR_ELx_SYS64_ISS_CRN_MASK | \
214 ESR_ELx_SYS64_ISS_DIR_MASK)
215 #define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
216 (ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
217 ESR_ELx_SYS64_ISS_DIR_READ)
218
219 #define ESR_ELx_SYS64_ISS_SYS_CTR ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
220 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
221 ESR_ELx_SYS64_ISS_DIR_READ)
222
223 #define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
224 ESR_ELx_SYS64_ISS_DIR_READ)
225
226 #define ESR_ELx_SYS64_ISS_SYS_CNTFRQ (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 0, 14, 0) | \
227 ESR_ELx_SYS64_ISS_DIR_READ)
228
229 #define esr_sys64_to_sysreg(e) \
230 sys_reg((((e) & ESR_ELx_SYS64_ISS_OP0_MASK) >> \
231 ESR_ELx_SYS64_ISS_OP0_SHIFT), \
232 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
233 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
234 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
235 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
236 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
237 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
238 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
239 ESR_ELx_SYS64_ISS_OP2_SHIFT))
240
241 #define esr_cp15_to_sysreg(e) \
242 sys_reg(3, \
243 (((e) & ESR_ELx_SYS64_ISS_OP1_MASK) >> \
244 ESR_ELx_SYS64_ISS_OP1_SHIFT), \
245 (((e) & ESR_ELx_SYS64_ISS_CRN_MASK) >> \
246 ESR_ELx_SYS64_ISS_CRN_SHIFT), \
247 (((e) & ESR_ELx_SYS64_ISS_CRM_MASK) >> \
248 ESR_ELx_SYS64_ISS_CRM_SHIFT), \
249 (((e) & ESR_ELx_SYS64_ISS_OP2_MASK) >> \
250 ESR_ELx_SYS64_ISS_OP2_SHIFT))
251
252 /*
253 * ISS field definitions for floating-point exception traps
254 * (FP_EXC_32/FP_EXC_64).
255 *
256 * (The FPEXC_* constants are used instead for common bits.)
257 */
258
259 #define ESR_ELx_FP_EXC_TFV (UL(1) << 23)
260
261 /*
262 * ISS field definitions for CP15 accesses
263 */
264 #define ESR_ELx_CP15_32_ISS_DIR_MASK 0x1
265 #define ESR_ELx_CP15_32_ISS_DIR_READ 0x1
266 #define ESR_ELx_CP15_32_ISS_DIR_WRITE 0x0
267
268 #define ESR_ELx_CP15_32_ISS_RT_SHIFT 5
269 #define ESR_ELx_CP15_32_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
270 #define ESR_ELx_CP15_32_ISS_CRM_SHIFT 1
271 #define ESR_ELx_CP15_32_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
272 #define ESR_ELx_CP15_32_ISS_CRN_SHIFT 10
273 #define ESR_ELx_CP15_32_ISS_CRN_MASK (UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
274 #define ESR_ELx_CP15_32_ISS_OP1_SHIFT 14
275 #define ESR_ELx_CP15_32_ISS_OP1_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
276 #define ESR_ELx_CP15_32_ISS_OP2_SHIFT 17
277 #define ESR_ELx_CP15_32_ISS_OP2_MASK (UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
278
279 #define ESR_ELx_CP15_32_ISS_SYS_MASK (ESR_ELx_CP15_32_ISS_OP1_MASK | \
280 ESR_ELx_CP15_32_ISS_OP2_MASK | \
281 ESR_ELx_CP15_32_ISS_CRN_MASK | \
282 ESR_ELx_CP15_32_ISS_CRM_MASK | \
283 ESR_ELx_CP15_32_ISS_DIR_MASK)
284 #define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
285 (((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
286 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
287 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
288 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
289
290 #define ESR_ELx_CP15_64_ISS_DIR_MASK 0x1
291 #define ESR_ELx_CP15_64_ISS_DIR_READ 0x1
292 #define ESR_ELx_CP15_64_ISS_DIR_WRITE 0x0
293
294 #define ESR_ELx_CP15_64_ISS_RT_SHIFT 5
295 #define ESR_ELx_CP15_64_ISS_RT_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
296
297 #define ESR_ELx_CP15_64_ISS_RT2_SHIFT 10
298 #define ESR_ELx_CP15_64_ISS_RT2_MASK (UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
299
300 #define ESR_ELx_CP15_64_ISS_OP1_SHIFT 16
301 #define ESR_ELx_CP15_64_ISS_OP1_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
302 #define ESR_ELx_CP15_64_ISS_CRM_SHIFT 1
303 #define ESR_ELx_CP15_64_ISS_CRM_MASK (UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
304
305 #define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
306 (((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
307 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
308
309 #define ESR_ELx_CP15_64_ISS_SYS_MASK (ESR_ELx_CP15_64_ISS_OP1_MASK | \
310 ESR_ELx_CP15_64_ISS_CRM_MASK | \
311 ESR_ELx_CP15_64_ISS_DIR_MASK)
312
313 #define ESR_ELx_CP15_64_ISS_SYS_CNTVCT (ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
314 ESR_ELx_CP15_64_ISS_DIR_READ)
315
316 #define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ (ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
317 ESR_ELx_CP15_32_ISS_DIR_READ)
318
319 #ifndef __ASSEMBLY__
320 #include <asm/types.h>
321
esr_is_data_abort(u32 esr)322 static inline bool esr_is_data_abort(u32 esr)
323 {
324 const u32 ec = ESR_ELx_EC(esr);
325
326 return ec == ESR_ELx_EC_DABT_LOW || ec == ESR_ELx_EC_DABT_CUR;
327 }
328
329 const char *esr_get_class_string(u32 esr);
330 #endif /* __ASSEMBLY */
331
332 #endif /* __ASM_ESR_H */
333
