1 /* 2 * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Device Tree binding constants clock controllers of Samsung S3C2443 and later. 9 */ 10 11 #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 12 #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H 13 14 /* 15 * Let each exported clock get a unique index, which is used on DT-enabled 16 * platforms to lookup the clock from a clock specifier. These indices are 17 * therefore considered an ABI and so must not be changed. This implies 18 * that new clocks should be added either in free spaces between clock groups 19 * or at the end. 20 */ 21 22 /* Core clocks. */ 23 #define MSYSCLK 1 24 #define ESYSCLK 2 25 #define ARMDIV 3 26 #define ARMCLK 4 27 #define HCLK 5 28 #define PCLK 6 29 #define MPLL 7 30 #define EPLL 8 31 32 /* Special clocks */ 33 #define SCLK_HSSPI0 16 34 #define SCLK_FIMD 17 35 #define SCLK_I2S0 18 36 #define SCLK_I2S1 19 37 #define SCLK_HSMMC1 20 38 #define SCLK_HSMMC_EXT 21 39 #define SCLK_CAM 22 40 #define SCLK_UART 23 41 #define SCLK_USBH 24 42 43 /* Muxes */ 44 #define MUX_HSSPI0 32 45 #define MUX_HSSPI1 33 46 #define MUX_HSMMC0 34 47 #define MUX_HSMMC1 35 48 49 /* hclk-gates */ 50 #define HCLK_DMA0 48 51 #define HCLK_DMA1 49 52 #define HCLK_DMA2 50 53 #define HCLK_DMA3 51 54 #define HCLK_DMA4 52 55 #define HCLK_DMA5 53 56 #define HCLK_DMA6 54 57 #define HCLK_DMA7 55 58 #define HCLK_CAM 56 59 #define HCLK_LCD 57 60 #define HCLK_USBH 58 61 #define HCLK_USBD 59 62 #define HCLK_IROM 60 63 #define HCLK_HSMMC0 61 64 #define HCLK_HSMMC1 62 65 #define HCLK_CFC 63 66 #define HCLK_SSMC 64 67 #define HCLK_DRAM 65 68 #define HCLK_2D 66 69 70 /* pclk-gates */ 71 #define PCLK_UART0 72 72 #define PCLK_UART1 73 73 #define PCLK_UART2 74 74 #define PCLK_UART3 75 75 #define PCLK_I2C0 76 76 #define PCLK_SDI 77 77 #define PCLK_SPI0 78 78 #define PCLK_ADC 79 79 #define PCLK_AC97 80 80 #define PCLK_I2S0 81 81 #define PCLK_PWM 82 82 #define PCLK_WDT 83 83 #define PCLK_RTC 84 84 #define PCLK_GPIO 85 85 #define PCLK_SPI1 86 86 #define PCLK_CHIPID 87 87 #define PCLK_I2C1 88 88 #define PCLK_I2S1 89 89 #define PCLK_PCM 90 90 91 /* Total number of clocks. */ 92 #define NR_CLKS (PCLK_PCM + 1) 93 94 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */ 95
