1 /*
2 * Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
3 * Copyright 2001-2012 IBM Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #ifndef _POWERPC_EEH_H
21 #define _POWERPC_EEH_H
22 #ifdef __KERNEL__
23
24 #include <linux/init.h>
25 #include <linux/list.h>
26 #include <linux/string.h>
27 #include <linux/time.h>
28 #include <linux/atomic.h>
29
30 #include <uapi/asm/eeh.h>
31
32 struct pci_dev;
33 struct pci_bus;
34 struct pci_dn;
35
36 #ifdef CONFIG_EEH
37
38 /* EEH subsystem flags */
39 #define EEH_ENABLED 0x01 /* EEH enabled */
40 #define EEH_FORCE_DISABLED 0x02 /* EEH disabled */
41 #define EEH_PROBE_MODE_DEV 0x04 /* From PCI device */
42 #define EEH_PROBE_MODE_DEVTREE 0x08 /* From device tree */
43 #define EEH_VALID_PE_ZERO 0x10 /* PE#0 is valid */
44 #define EEH_ENABLE_IO_FOR_LOG 0x20 /* Enable IO for log */
45 #define EEH_EARLY_DUMP_LOG 0x40 /* Dump log immediately */
46 #define EEH_POSTPONED_PROBE 0x80 /* Powernv may postpone device probe */
47
48 /*
49 * Delay for PE reset, all in ms
50 *
51 * PCI specification has reset hold time of 100 milliseconds.
52 * We have 250 milliseconds here. The PCI bus settlement time
53 * is specified as 1.5 seconds and we have 1.8 seconds.
54 */
55 #define EEH_PE_RST_HOLD_TIME 250
56 #define EEH_PE_RST_SETTLE_TIME 1800
57
58 /*
59 * The struct is used to trace PE related EEH functionality.
60 * In theory, there will have one instance of the struct to
61 * be created against particular PE. In nature, PEs correlate
62 * to each other. the struct has to reflect that hierarchy in
63 * order to easily pick up those affected PEs when one particular
64 * PE has EEH errors.
65 *
66 * Also, one particular PE might be composed of PCI device, PCI
67 * bus and its subordinate components. The struct also need ship
68 * the information. Further more, one particular PE is only meaingful
69 * in the corresponding PHB. Therefore, the root PEs should be created
70 * against existing PHBs in on-to-one fashion.
71 */
72 #define EEH_PE_INVALID (1 << 0) /* Invalid */
73 #define EEH_PE_PHB (1 << 1) /* PHB PE */
74 #define EEH_PE_DEVICE (1 << 2) /* Device PE */
75 #define EEH_PE_BUS (1 << 3) /* Bus PE */
76 #define EEH_PE_VF (1 << 4) /* VF PE */
77
78 #define EEH_PE_ISOLATED (1 << 0) /* Isolated PE */
79 #define EEH_PE_RECOVERING (1 << 1) /* Recovering PE */
80 #define EEH_PE_CFG_BLOCKED (1 << 2) /* Block config access */
81 #define EEH_PE_RESET (1 << 3) /* PE reset in progress */
82
83 #define EEH_PE_KEEP (1 << 8) /* Keep PE on hotplug */
84 #define EEH_PE_CFG_RESTRICTED (1 << 9) /* Block config on error */
85 #define EEH_PE_REMOVED (1 << 10) /* Removed permanently */
86 #define EEH_PE_PRI_BUS (1 << 11) /* Cached primary bus */
87
88 struct eeh_pe {
89 int type; /* PE type: PHB/Bus/Device */
90 int state; /* PE EEH dependent mode */
91 int config_addr; /* Traditional PCI address */
92 int addr; /* PE configuration address */
93 struct pci_controller *phb; /* Associated PHB */
94 struct pci_bus *bus; /* Top PCI bus for bus PE */
95 int check_count; /* Times of ignored error */
96 int freeze_count; /* Times of froze up */
97 time64_t tstamp; /* Time on first-time freeze */
98 int false_positives; /* Times of reported #ff's */
99 atomic_t pass_dev_cnt; /* Count of passed through devs */
100 struct eeh_pe *parent; /* Parent PE */
101 void *data; /* PE auxillary data */
102 struct list_head child_list; /* Link PE to the child list */
103 struct list_head edevs; /* Link list of EEH devices */
104 struct list_head child; /* Child PEs */
105 };
106
107 #define eeh_pe_for_each_dev(pe, edev, tmp) \
108 list_for_each_entry_safe(edev, tmp, &pe->edevs, list)
109
110 #define eeh_for_each_pe(root, pe) \
111 for (pe = root; pe; pe = eeh_pe_next(pe, root))
112
eeh_pe_passed(struct eeh_pe * pe)113 static inline bool eeh_pe_passed(struct eeh_pe *pe)
114 {
115 return pe ? !!atomic_read(&pe->pass_dev_cnt) : false;
116 }
117
118 /*
119 * The struct is used to trace EEH state for the associated
120 * PCI device node or PCI device. In future, it might
121 * represent PE as well so that the EEH device to form
122 * another tree except the currently existing tree of PCI
123 * buses and PCI devices
124 */
125 #define EEH_DEV_BRIDGE (1 << 0) /* PCI bridge */
126 #define EEH_DEV_ROOT_PORT (1 << 1) /* PCIe root port */
127 #define EEH_DEV_DS_PORT (1 << 2) /* Downstream port */
128 #define EEH_DEV_IRQ_DISABLED (1 << 3) /* Interrupt disabled */
129 #define EEH_DEV_DISCONNECTED (1 << 4) /* Removing from PE */
130
131 #define EEH_DEV_NO_HANDLER (1 << 8) /* No error handler */
132 #define EEH_DEV_SYSFS (1 << 9) /* Sysfs created */
133 #define EEH_DEV_REMOVED (1 << 10) /* Removed permanently */
134
135 struct eeh_dev {
136 int mode; /* EEH mode */
137 int class_code; /* Class code of the device */
138 int pe_config_addr; /* PE config address */
139 u32 config_space[16]; /* Saved PCI config space */
140 int pcix_cap; /* Saved PCIx capability */
141 int pcie_cap; /* Saved PCIe capability */
142 int aer_cap; /* Saved AER capability */
143 int af_cap; /* Saved AF capability */
144 struct eeh_pe *pe; /* Associated PE */
145 struct list_head list; /* Form link list in the PE */
146 struct list_head rmv_list; /* Record the removed edevs */
147 struct pci_dn *pdn; /* Associated PCI device node */
148 struct pci_dev *pdev; /* Associated PCI device */
149 bool in_error; /* Error flag for edev */
150 struct pci_dev *physfn; /* Associated SRIOV PF */
151 struct pci_bus *bus; /* PCI bus for partial hotplug */
152 };
153
eeh_dev_to_pdn(struct eeh_dev * edev)154 static inline struct pci_dn *eeh_dev_to_pdn(struct eeh_dev *edev)
155 {
156 return edev ? edev->pdn : NULL;
157 }
158
eeh_dev_to_pci_dev(struct eeh_dev * edev)159 static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
160 {
161 return edev ? edev->pdev : NULL;
162 }
163
eeh_dev_to_pe(struct eeh_dev * edev)164 static inline struct eeh_pe *eeh_dev_to_pe(struct eeh_dev* edev)
165 {
166 return edev ? edev->pe : NULL;
167 }
168
169 /* Return values from eeh_ops::next_error */
170 enum {
171 EEH_NEXT_ERR_NONE = 0,
172 EEH_NEXT_ERR_INF,
173 EEH_NEXT_ERR_FROZEN_PE,
174 EEH_NEXT_ERR_FENCED_PHB,
175 EEH_NEXT_ERR_DEAD_PHB,
176 EEH_NEXT_ERR_DEAD_IOC
177 };
178
179 /*
180 * The struct is used to trace the registered EEH operation
181 * callback functions. Actually, those operation callback
182 * functions are heavily platform dependent. That means the
183 * platform should register its own EEH operation callback
184 * functions before any EEH further operations.
185 */
186 #define EEH_OPT_DISABLE 0 /* EEH disable */
187 #define EEH_OPT_ENABLE 1 /* EEH enable */
188 #define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
189 #define EEH_OPT_THAW_DMA 3 /* DMA enable */
190 #define EEH_OPT_FREEZE_PE 4 /* Freeze PE */
191 #define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
192 #define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
193 #define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
194 #define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
195 #define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
196 #define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
197 #define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
198 #define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
199 #define EEH_RESET_HOT 1 /* Hot reset */
200 #define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
201 #define EEH_LOG_TEMP 1 /* EEH temporary error log */
202 #define EEH_LOG_PERM 2 /* EEH permanent error log */
203
204 struct eeh_ops {
205 char *name;
206 int (*init)(void);
207 void* (*probe)(struct pci_dn *pdn, void *data);
208 int (*set_option)(struct eeh_pe *pe, int option);
209 int (*get_pe_addr)(struct eeh_pe *pe);
210 int (*get_state)(struct eeh_pe *pe, int *state);
211 int (*reset)(struct eeh_pe *pe, int option);
212 int (*wait_state)(struct eeh_pe *pe, int max_wait);
213 int (*get_log)(struct eeh_pe *pe, int severity, char *drv_log, unsigned long len);
214 int (*configure_bridge)(struct eeh_pe *pe);
215 int (*err_inject)(struct eeh_pe *pe, int type, int func,
216 unsigned long addr, unsigned long mask);
217 int (*read_config)(struct pci_dn *pdn, int where, int size, u32 *val);
218 int (*write_config)(struct pci_dn *pdn, int where, int size, u32 val);
219 int (*next_error)(struct eeh_pe **pe);
220 int (*restore_config)(struct pci_dn *pdn);
221 int (*notify_resume)(struct pci_dn *pdn);
222 };
223
224 extern int eeh_subsystem_flags;
225 extern int eeh_max_freezes;
226 extern struct eeh_ops *eeh_ops;
227 extern raw_spinlock_t confirm_error_lock;
228
eeh_add_flag(int flag)229 static inline void eeh_add_flag(int flag)
230 {
231 eeh_subsystem_flags |= flag;
232 }
233
eeh_clear_flag(int flag)234 static inline void eeh_clear_flag(int flag)
235 {
236 eeh_subsystem_flags &= ~flag;
237 }
238
eeh_has_flag(int flag)239 static inline bool eeh_has_flag(int flag)
240 {
241 return !!(eeh_subsystem_flags & flag);
242 }
243
eeh_enabled(void)244 static inline bool eeh_enabled(void)
245 {
246 if (eeh_has_flag(EEH_FORCE_DISABLED) ||
247 !eeh_has_flag(EEH_ENABLED))
248 return false;
249
250 return true;
251 }
252
eeh_serialize_lock(unsigned long * flags)253 static inline void eeh_serialize_lock(unsigned long *flags)
254 {
255 raw_spin_lock_irqsave(&confirm_error_lock, *flags);
256 }
257
eeh_serialize_unlock(unsigned long flags)258 static inline void eeh_serialize_unlock(unsigned long flags)
259 {
260 raw_spin_unlock_irqrestore(&confirm_error_lock, flags);
261 }
262
eeh_state_active(int state)263 static inline bool eeh_state_active(int state)
264 {
265 return (state & (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE))
266 == (EEH_STATE_MMIO_ACTIVE | EEH_STATE_DMA_ACTIVE);
267 }
268
269 typedef void *(*eeh_edev_traverse_func)(struct eeh_dev *edev, void *flag);
270 typedef void *(*eeh_pe_traverse_func)(struct eeh_pe *pe, void *flag);
271 void eeh_set_pe_aux_size(int size);
272 int eeh_phb_pe_create(struct pci_controller *phb);
273 struct eeh_pe *eeh_phb_pe_get(struct pci_controller *phb);
274 struct eeh_pe *eeh_pe_next(struct eeh_pe *pe, struct eeh_pe *root);
275 struct eeh_pe *eeh_pe_get(struct pci_controller *phb,
276 int pe_no, int config_addr);
277 int eeh_add_to_parent_pe(struct eeh_dev *edev);
278 int eeh_rmv_from_parent_pe(struct eeh_dev *edev);
279 void eeh_pe_update_time_stamp(struct eeh_pe *pe);
280 void *eeh_pe_traverse(struct eeh_pe *root,
281 eeh_pe_traverse_func fn, void *flag);
282 void *eeh_pe_dev_traverse(struct eeh_pe *root,
283 eeh_edev_traverse_func fn, void *flag);
284 void eeh_pe_restore_bars(struct eeh_pe *pe);
285 const char *eeh_pe_loc_get(struct eeh_pe *pe);
286 struct pci_bus *eeh_pe_bus_get(struct eeh_pe *pe);
287
288 struct eeh_dev *eeh_dev_init(struct pci_dn *pdn);
289 void eeh_dev_phb_init_dynamic(struct pci_controller *phb);
290 void eeh_probe_devices(void);
291 int __init eeh_ops_register(struct eeh_ops *ops);
292 int __exit eeh_ops_unregister(const char *name);
293 int eeh_check_failure(const volatile void __iomem *token);
294 int eeh_dev_check_failure(struct eeh_dev *edev);
295 void eeh_addr_cache_build(void);
296 void eeh_add_device_early(struct pci_dn *);
297 void eeh_add_device_tree_early(struct pci_dn *);
298 void eeh_add_device_late(struct pci_dev *);
299 void eeh_add_device_tree_late(struct pci_bus *);
300 void eeh_add_sysfs_files(struct pci_bus *);
301 void eeh_remove_device(struct pci_dev *);
302 int eeh_unfreeze_pe(struct eeh_pe *pe, bool sw_state);
303 int eeh_pe_reset_and_recover(struct eeh_pe *pe);
304 int eeh_dev_open(struct pci_dev *pdev);
305 void eeh_dev_release(struct pci_dev *pdev);
306 struct eeh_pe *eeh_iommu_group_to_pe(struct iommu_group *group);
307 int eeh_pe_set_option(struct eeh_pe *pe, int option);
308 int eeh_pe_get_state(struct eeh_pe *pe);
309 int eeh_pe_reset(struct eeh_pe *pe, int option);
310 int eeh_pe_configure(struct eeh_pe *pe);
311 int eeh_pe_inject_err(struct eeh_pe *pe, int type, int func,
312 unsigned long addr, unsigned long mask);
313 int eeh_restore_vf_config(struct pci_dn *pdn);
314
315 /**
316 * EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
317 *
318 * If this macro yields TRUE, the caller relays to eeh_check_failure()
319 * which does further tests out of line.
320 */
321 #define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_enabled())
322
323 /*
324 * Reads from a device which has been isolated by EEH will return
325 * all 1s. This macro gives an all-1s value of the given size (in
326 * bytes: 1, 2, or 4) for comparing with the result of a read.
327 */
328 #define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
329
330 #else /* !CONFIG_EEH */
331
eeh_enabled(void)332 static inline bool eeh_enabled(void)
333 {
334 return false;
335 }
336
eeh_probe_devices(void)337 static inline void eeh_probe_devices(void) { }
338
eeh_dev_init(struct pci_dn * pdn,void * data)339 static inline void *eeh_dev_init(struct pci_dn *pdn, void *data)
340 {
341 return NULL;
342 }
343
eeh_dev_phb_init_dynamic(struct pci_controller * phb)344 static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
345
eeh_check_failure(const volatile void __iomem * token)346 static inline int eeh_check_failure(const volatile void __iomem *token)
347 {
348 return 0;
349 }
350
351 #define eeh_dev_check_failure(x) (0)
352
eeh_addr_cache_build(void)353 static inline void eeh_addr_cache_build(void) { }
354
eeh_add_device_early(struct pci_dn * pdn)355 static inline void eeh_add_device_early(struct pci_dn *pdn) { }
356
eeh_add_device_tree_early(struct pci_dn * pdn)357 static inline void eeh_add_device_tree_early(struct pci_dn *pdn) { }
358
eeh_add_device_late(struct pci_dev * dev)359 static inline void eeh_add_device_late(struct pci_dev *dev) { }
360
eeh_add_device_tree_late(struct pci_bus * bus)361 static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
362
eeh_add_sysfs_files(struct pci_bus * bus)363 static inline void eeh_add_sysfs_files(struct pci_bus *bus) { }
364
eeh_remove_device(struct pci_dev * dev)365 static inline void eeh_remove_device(struct pci_dev *dev) { }
366
367 #define EEH_POSSIBLE_ERROR(val, type) (0)
368 #define EEH_IO_ERROR_VALUE(size) (-1UL)
369 #endif /* CONFIG_EEH */
370
371 #ifdef CONFIG_PPC64
372 /*
373 * MMIO read/write operations with EEH support.
374 */
eeh_readb(const volatile void __iomem * addr)375 static inline u8 eeh_readb(const volatile void __iomem *addr)
376 {
377 u8 val = in_8(addr);
378 if (EEH_POSSIBLE_ERROR(val, u8))
379 eeh_check_failure(addr);
380 return val;
381 }
382
eeh_readw(const volatile void __iomem * addr)383 static inline u16 eeh_readw(const volatile void __iomem *addr)
384 {
385 u16 val = in_le16(addr);
386 if (EEH_POSSIBLE_ERROR(val, u16))
387 eeh_check_failure(addr);
388 return val;
389 }
390
eeh_readl(const volatile void __iomem * addr)391 static inline u32 eeh_readl(const volatile void __iomem *addr)
392 {
393 u32 val = in_le32(addr);
394 if (EEH_POSSIBLE_ERROR(val, u32))
395 eeh_check_failure(addr);
396 return val;
397 }
398
eeh_readq(const volatile void __iomem * addr)399 static inline u64 eeh_readq(const volatile void __iomem *addr)
400 {
401 u64 val = in_le64(addr);
402 if (EEH_POSSIBLE_ERROR(val, u64))
403 eeh_check_failure(addr);
404 return val;
405 }
406
eeh_readw_be(const volatile void __iomem * addr)407 static inline u16 eeh_readw_be(const volatile void __iomem *addr)
408 {
409 u16 val = in_be16(addr);
410 if (EEH_POSSIBLE_ERROR(val, u16))
411 eeh_check_failure(addr);
412 return val;
413 }
414
eeh_readl_be(const volatile void __iomem * addr)415 static inline u32 eeh_readl_be(const volatile void __iomem *addr)
416 {
417 u32 val = in_be32(addr);
418 if (EEH_POSSIBLE_ERROR(val, u32))
419 eeh_check_failure(addr);
420 return val;
421 }
422
eeh_readq_be(const volatile void __iomem * addr)423 static inline u64 eeh_readq_be(const volatile void __iomem *addr)
424 {
425 u64 val = in_be64(addr);
426 if (EEH_POSSIBLE_ERROR(val, u64))
427 eeh_check_failure(addr);
428 return val;
429 }
430
eeh_memcpy_fromio(void * dest,const volatile void __iomem * src,unsigned long n)431 static inline void eeh_memcpy_fromio(void *dest, const
432 volatile void __iomem *src,
433 unsigned long n)
434 {
435 _memcpy_fromio(dest, src, n);
436
437 /* Look for ffff's here at dest[n]. Assume that at least 4 bytes
438 * were copied. Check all four bytes.
439 */
440 if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
441 eeh_check_failure(src);
442 }
443
444 /* in-string eeh macros */
eeh_readsb(const volatile void __iomem * addr,void * buf,int ns)445 static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
446 int ns)
447 {
448 _insb(addr, buf, ns);
449 if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
450 eeh_check_failure(addr);
451 }
452
eeh_readsw(const volatile void __iomem * addr,void * buf,int ns)453 static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
454 int ns)
455 {
456 _insw(addr, buf, ns);
457 if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
458 eeh_check_failure(addr);
459 }
460
eeh_readsl(const volatile void __iomem * addr,void * buf,int nl)461 static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
462 int nl)
463 {
464 _insl(addr, buf, nl);
465 if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
466 eeh_check_failure(addr);
467 }
468
469 #endif /* CONFIG_PPC64 */
470 #endif /* __KERNEL__ */
471 #endif /* _POWERPC_EEH_H */
472
