1 /* 2 * Copyright 2016 Linaro Ltd. 3 * Copyright 2016 ZTE Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #ifndef __ZX_VOU_REGS_H__ 12 #define __ZX_VOU_REGS_H__ 13 14 /* Sub-module offset */ 15 #define MAIN_GL_OFFSET 0x130 16 #define MAIN_GL_CSC_OFFSET 0x580 17 #define MAIN_CHN_CSC_OFFSET 0x6c0 18 #define MAIN_HBSC_OFFSET 0x820 19 #define MAIN_DITHER_OFFSET 0x960 20 #define MAIN_RSZ_OFFSET 0x600 /* OTFPPU sub-module */ 21 22 #define AUX_GL_OFFSET 0x200 23 #define AUX_GL_CSC_OFFSET 0x5d0 24 #define AUX_CHN_CSC_OFFSET 0x710 25 #define AUX_HBSC_OFFSET 0x860 26 #define AUX_DITHER_OFFSET 0x970 27 #define AUX_RSZ_OFFSET 0x800 28 29 #define OSD_VL0_OFFSET 0x040 30 #define OSD_VL_OFFSET(i) (OSD_VL0_OFFSET + 0x050 * (i)) 31 32 #define HBSC_VL0_OFFSET 0x760 33 #define HBSC_VL_OFFSET(i) (HBSC_VL0_OFFSET + 0x040 * (i)) 34 35 #define RSZ_VL1_U0 0xa00 36 #define RSZ_VL_OFFSET(i) (RSZ_VL1_U0 + 0x200 * (i)) 37 38 /* OSD (GPC_GLOBAL) registers */ 39 #define OSD_INT_STA 0x04 40 #define OSD_INT_CLRSTA 0x08 41 #define OSD_INT_MSK 0x0c 42 #define OSD_INT_AUX_UPT BIT(14) 43 #define OSD_INT_MAIN_UPT BIT(13) 44 #define OSD_INT_GL1_LBW BIT(10) 45 #define OSD_INT_GL0_LBW BIT(9) 46 #define OSD_INT_VL2_LBW BIT(8) 47 #define OSD_INT_VL1_LBW BIT(7) 48 #define OSD_INT_VL0_LBW BIT(6) 49 #define OSD_INT_BUS_ERR BIT(3) 50 #define OSD_INT_CFG_ERR BIT(2) 51 #define OSD_INT_ERROR (\ 52 OSD_INT_GL1_LBW | OSD_INT_GL0_LBW | \ 53 OSD_INT_VL2_LBW | OSD_INT_VL1_LBW | OSD_INT_VL0_LBW | \ 54 OSD_INT_BUS_ERR | OSD_INT_CFG_ERR \ 55 ) 56 #define OSD_INT_ENABLE (OSD_INT_ERROR | OSD_INT_AUX_UPT | OSD_INT_MAIN_UPT) 57 #define OSD_CTRL0 0x10 58 #define OSD_CTRL0_VL0_EN BIT(13) 59 #define OSD_CTRL0_VL0_SEL BIT(12) 60 #define OSD_CTRL0_VL1_EN BIT(11) 61 #define OSD_CTRL0_VL1_SEL BIT(10) 62 #define OSD_CTRL0_VL2_EN BIT(9) 63 #define OSD_CTRL0_VL2_SEL BIT(8) 64 #define OSD_CTRL0_GL0_EN BIT(7) 65 #define OSD_CTRL0_GL0_SEL BIT(6) 66 #define OSD_CTRL0_GL1_EN BIT(5) 67 #define OSD_CTRL0_GL1_SEL BIT(4) 68 #define OSD_RST_CLR 0x1c 69 #define RST_PER_FRAME BIT(19) 70 71 /* Main/Aux channel registers */ 72 #define OSD_MAIN_CHN 0x470 73 #define OSD_AUX_CHN 0x4d0 74 #define CHN_CTRL0 0x00 75 #define CHN_ENABLE BIT(0) 76 #define CHN_CTRL1 0x04 77 #define CHN_SCREEN_W_SHIFT 18 78 #define CHN_SCREEN_W_MASK (0x1fff << CHN_SCREEN_W_SHIFT) 79 #define CHN_SCREEN_H_SHIFT 5 80 #define CHN_SCREEN_H_MASK (0x1fff << CHN_SCREEN_H_SHIFT) 81 #define CHN_UPDATE 0x08 82 #define CHN_INTERLACE_BUF_CTRL 0x24 83 #define CHN_INTERLACE_EN BIT(2) 84 85 /* Dither registers */ 86 #define OSD_DITHER_CTRL0 0x00 87 #define DITHER_BYSPASS BIT(31) 88 89 /* TIMING_CTRL registers */ 90 #define TIMING_TC_ENABLE 0x04 91 #define AUX_TC_EN BIT(1) 92 #define MAIN_TC_EN BIT(0) 93 #define FIR_MAIN_ACTIVE 0x08 94 #define FIR_AUX_ACTIVE 0x0c 95 #define V_ACTIVE_SHIFT 16 96 #define V_ACTIVE_MASK (0xffff << V_ACTIVE_SHIFT) 97 #define H_ACTIVE_SHIFT 0 98 #define H_ACTIVE_MASK (0xffff << H_ACTIVE_SHIFT) 99 #define FIR_MAIN_H_TIMING 0x10 100 #define FIR_MAIN_V_TIMING 0x14 101 #define FIR_AUX_H_TIMING 0x18 102 #define FIR_AUX_V_TIMING 0x1c 103 #define SYNC_WIDE_SHIFT 22 104 #define SYNC_WIDE_MASK (0x3ff << SYNC_WIDE_SHIFT) 105 #define BACK_PORCH_SHIFT 11 106 #define BACK_PORCH_MASK (0x7ff << BACK_PORCH_SHIFT) 107 #define FRONT_PORCH_SHIFT 0 108 #define FRONT_PORCH_MASK (0x7ff << FRONT_PORCH_SHIFT) 109 #define TIMING_CTRL 0x20 110 #define AUX_POL_SHIFT 3 111 #define AUX_POL_MASK (0x7 << AUX_POL_SHIFT) 112 #define MAIN_POL_SHIFT 0 113 #define MAIN_POL_MASK (0x7 << MAIN_POL_SHIFT) 114 #define POL_DE_SHIFT 2 115 #define POL_VSYNC_SHIFT 1 116 #define POL_HSYNC_SHIFT 0 117 #define TIMING_INT_CTRL 0x24 118 #define TIMING_INT_STATE 0x28 119 #define TIMING_INT_AUX_FRAME BIT(3) 120 #define TIMING_INT_MAIN_FRAME BIT(1) 121 #define TIMING_INT_AUX_FRAME_SEL_VSW (0x2 << 10) 122 #define TIMING_INT_MAIN_FRAME_SEL_VSW (0x2 << 6) 123 #define TIMING_INT_ENABLE (\ 124 TIMING_INT_MAIN_FRAME_SEL_VSW | TIMING_INT_AUX_FRAME_SEL_VSW | \ 125 TIMING_INT_MAIN_FRAME | TIMING_INT_AUX_FRAME \ 126 ) 127 #define TIMING_MAIN_SHIFT 0x2c 128 #define TIMING_AUX_SHIFT 0x30 129 #define H_SHIFT_VAL 0x0048 130 #define V_SHIFT_VAL 0x0001 131 #define SCAN_CTRL 0x34 132 #define AUX_PI_EN BIT(19) 133 #define MAIN_PI_EN BIT(18) 134 #define AUX_INTERLACE_SEL BIT(1) 135 #define MAIN_INTERLACE_SEL BIT(0) 136 #define SEC_V_ACTIVE 0x38 137 #define SEC_VACT_MAIN_SHIFT 0 138 #define SEC_VACT_MAIN_MASK (0xffff << SEC_VACT_MAIN_SHIFT) 139 #define SEC_VACT_AUX_SHIFT 16 140 #define SEC_VACT_AUX_MASK (0xffff << SEC_VACT_AUX_SHIFT) 141 #define SEC_MAIN_V_TIMING 0x3c 142 #define SEC_AUX_V_TIMING 0x40 143 #define TIMING_MAIN_PI_SHIFT 0x68 144 #define TIMING_AUX_PI_SHIFT 0x6c 145 #define H_PI_SHIFT_VAL 0x000f 146 147 #define V_ACTIVE(x) (((x) << V_ACTIVE_SHIFT) & V_ACTIVE_MASK) 148 #define H_ACTIVE(x) (((x) << H_ACTIVE_SHIFT) & H_ACTIVE_MASK) 149 150 #define SYNC_WIDE(x) (((x) << SYNC_WIDE_SHIFT) & SYNC_WIDE_MASK) 151 #define BACK_PORCH(x) (((x) << BACK_PORCH_SHIFT) & BACK_PORCH_MASK) 152 #define FRONT_PORCH(x) (((x) << FRONT_PORCH_SHIFT) & FRONT_PORCH_MASK) 153 154 /* DTRC registers */ 155 #define DTRC_F0_CTRL 0x2c 156 #define DTRC_F1_CTRL 0x5c 157 #define DTRC_DECOMPRESS_BYPASS BIT(17) 158 #define DTRC_DETILE_CTRL 0x68 159 #define TILE2RASTESCAN_BYPASS_MODE BIT(30) 160 #define DETILE_ARIDR_MODE_MASK (0x3 << 0) 161 #define DETILE_ARID_ALL 0 162 #define DETILE_ARID_IN_ARIDR 1 163 #define DETILE_ARID_BYP_BUT_ARIDR 2 164 #define DETILE_ARID_IN_ARIDR2 3 165 #define DTRC_ARID 0x6c 166 #define DTRC_ARID3_SHIFT 24 167 #define DTRC_ARID3_MASK (0xff << DTRC_ARID3_SHIFT) 168 #define DTRC_ARID2_SHIFT 16 169 #define DTRC_ARID2_MASK (0xff << DTRC_ARID2_SHIFT) 170 #define DTRC_ARID1_SHIFT 8 171 #define DTRC_ARID1_MASK (0xff << DTRC_ARID1_SHIFT) 172 #define DTRC_ARID0_SHIFT 0 173 #define DTRC_ARID0_MASK (0xff << DTRC_ARID0_SHIFT) 174 #define DTRC_DEC2DDR_ARID 0x70 175 176 #define DTRC_ARID3(x) (((x) << DTRC_ARID3_SHIFT) & DTRC_ARID3_MASK) 177 #define DTRC_ARID2(x) (((x) << DTRC_ARID2_SHIFT) & DTRC_ARID2_MASK) 178 #define DTRC_ARID1(x) (((x) << DTRC_ARID1_SHIFT) & DTRC_ARID1_MASK) 179 #define DTRC_ARID0(x) (((x) << DTRC_ARID0_SHIFT) & DTRC_ARID0_MASK) 180 181 /* VOU_CTRL registers */ 182 #define VOU_INF_EN 0x00 183 #define VOU_INF_CH_SEL 0x04 184 #define VOU_INF_DATA_SEL 0x08 185 #define VOU_SOFT_RST 0x14 186 #define VOU_CLK_SEL 0x18 187 #define VGA_AUX_DIV_SHIFT 29 188 #define VGA_MAIN_DIV_SHIFT 26 189 #define PIC_MAIN_DIV_SHIFT 23 190 #define PIC_AUX_DIV_SHIFT 20 191 #define VOU_CLK_VL2_SEL BIT(8) 192 #define VOU_CLK_VL1_SEL BIT(7) 193 #define VOU_CLK_VL0_SEL BIT(6) 194 #define VOU_CLK_GL1_SEL BIT(5) 195 #define VOU_CLK_GL0_SEL BIT(4) 196 #define VOU_DIV_PARA 0x1c 197 #define DIV_PARA_UPDATE BIT(31) 198 #define TVENC_AUX_DIV_SHIFT 28 199 #define HDMI_AUX_PNX_DIV_SHIFT 25 200 #define HDMI_MAIN_PNX_DIV_SHIFT 22 201 #define HDMI_AUX_DIV_SHIFT 19 202 #define HDMI_MAIN_DIV_SHIFT 16 203 #define TVENC_MAIN_DIV_SHIFT 13 204 #define INF_AUX_DIV_SHIFT 9 205 #define INF_MAIN_DIV_SHIFT 6 206 #define LAYER_AUX_DIV_SHIFT 3 207 #define LAYER_MAIN_DIV_SHIFT 0 208 #define VOU_CLK_REQEN 0x20 209 #define VOU_CLK_EN 0x24 210 #define VOU_INF_HDMI_CTRL 0x30 211 #define VOU_HDMI_AUD_MASK 0x1f 212 213 /* OTFPPU_CTRL registers */ 214 #define OTFPPU_RSZ_DATA_SOURCE 0x04 215 216 #endif /* __ZX_VOU_REGS_H__ */ 217
