1 /*
2 * Copyright (C) 2009 Nokia Corporation
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4 *
5 * Some code and ideas taken from drivers/video/omap/ driver
6 * by Imre Deak.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #ifndef __OMAP2_DSS_H
22 #define __OMAP2_DSS_H
23
24 #include <linux/interrupt.h>
25
26 #include "omapdss.h"
27
28 struct dispc_device;
29 struct dss_debugfs_entry;
30 struct platform_device;
31 struct seq_file;
32
33 #define MAX_DSS_LCD_MANAGERS 3
34 #define MAX_NUM_DSI 2
35
36 #ifdef pr_fmt
37 #undef pr_fmt
38 #endif
39
40 #ifdef DSS_SUBSYS_NAME
41 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
42 #else
43 #define pr_fmt(fmt) fmt
44 #endif
45
46 #define DSSDBG(format, ...) \
47 pr_debug(format, ## __VA_ARGS__)
48
49 #ifdef DSS_SUBSYS_NAME
50 #define DSSERR(format, ...) \
51 pr_err("omapdss " DSS_SUBSYS_NAME " error: " format, ##__VA_ARGS__)
52 #else
53 #define DSSERR(format, ...) \
54 pr_err("omapdss error: " format, ##__VA_ARGS__)
55 #endif
56
57 #ifdef DSS_SUBSYS_NAME
58 #define DSSINFO(format, ...) \
59 pr_info("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
60 #else
61 #define DSSINFO(format, ...) \
62 pr_info("omapdss: " format, ## __VA_ARGS__)
63 #endif
64
65 #ifdef DSS_SUBSYS_NAME
66 #define DSSWARN(format, ...) \
67 pr_warn("omapdss " DSS_SUBSYS_NAME ": " format, ##__VA_ARGS__)
68 #else
69 #define DSSWARN(format, ...) \
70 pr_warn("omapdss: " format, ##__VA_ARGS__)
71 #endif
72
73 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
74 number. For example 7:0 */
75 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
76 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
77 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
78 #define FLD_MOD(orig, val, start, end) \
79 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
80
81 enum dss_model {
82 DSS_MODEL_OMAP2,
83 DSS_MODEL_OMAP3,
84 DSS_MODEL_OMAP4,
85 DSS_MODEL_OMAP5,
86 DSS_MODEL_DRA7,
87 };
88
89 enum dss_io_pad_mode {
90 DSS_IO_PAD_MODE_RESET,
91 DSS_IO_PAD_MODE_RFBI,
92 DSS_IO_PAD_MODE_BYPASS,
93 };
94
95 enum dss_hdmi_venc_clk_source_select {
96 DSS_VENC_TV_CLK = 0,
97 DSS_HDMI_M_PCLK = 1,
98 };
99
100 enum dss_dsi_content_type {
101 DSS_DSI_CONTENT_DCS,
102 DSS_DSI_CONTENT_GENERIC,
103 };
104
105 enum dss_clk_source {
106 DSS_CLK_SRC_FCK = 0,
107
108 DSS_CLK_SRC_PLL1_1,
109 DSS_CLK_SRC_PLL1_2,
110 DSS_CLK_SRC_PLL1_3,
111
112 DSS_CLK_SRC_PLL2_1,
113 DSS_CLK_SRC_PLL2_2,
114 DSS_CLK_SRC_PLL2_3,
115
116 DSS_CLK_SRC_HDMI_PLL,
117 };
118
119 enum dss_pll_id {
120 DSS_PLL_DSI1,
121 DSS_PLL_DSI2,
122 DSS_PLL_HDMI,
123 DSS_PLL_VIDEO1,
124 DSS_PLL_VIDEO2,
125 };
126
127 struct dss_pll;
128
129 #define DSS_PLL_MAX_HSDIVS 4
130
131 enum dss_pll_type {
132 DSS_PLL_TYPE_A,
133 DSS_PLL_TYPE_B,
134 };
135
136 /*
137 * Type-A PLLs: clkout[]/mX[] refer to hsdiv outputs m4, m5, m6, m7.
138 * Type-B PLLs: clkout[0] refers to m2.
139 */
140 struct dss_pll_clock_info {
141 /* rates that we get with dividers below */
142 unsigned long fint;
143 unsigned long clkdco;
144 unsigned long clkout[DSS_PLL_MAX_HSDIVS];
145
146 /* dividers */
147 u16 n;
148 u16 m;
149 u32 mf;
150 u16 mX[DSS_PLL_MAX_HSDIVS];
151 u16 sd;
152 };
153
154 struct dss_pll_ops {
155 int (*enable)(struct dss_pll *pll);
156 void (*disable)(struct dss_pll *pll);
157 int (*set_config)(struct dss_pll *pll,
158 const struct dss_pll_clock_info *cinfo);
159 };
160
161 struct dss_pll_hw {
162 enum dss_pll_type type;
163
164 unsigned int n_max;
165 unsigned int m_min;
166 unsigned int m_max;
167 unsigned int mX_max;
168
169 unsigned long fint_min, fint_max;
170 unsigned long clkdco_min, clkdco_low, clkdco_max;
171
172 u8 n_msb, n_lsb;
173 u8 m_msb, m_lsb;
174 u8 mX_msb[DSS_PLL_MAX_HSDIVS], mX_lsb[DSS_PLL_MAX_HSDIVS];
175
176 bool has_stopmode;
177 bool has_freqsel;
178 bool has_selfreqdco;
179 bool has_refsel;
180
181 /* DRA7 errata i886: use high N & M to avoid jitter */
182 bool errata_i886;
183
184 /* DRA7 errata i932: retry pll lock on failure */
185 bool errata_i932;
186 };
187
188 struct dss_pll {
189 const char *name;
190 enum dss_pll_id id;
191 struct dss_device *dss;
192
193 struct clk *clkin;
194 struct regulator *regulator;
195
196 void __iomem *base;
197
198 const struct dss_pll_hw *hw;
199
200 const struct dss_pll_ops *ops;
201
202 struct dss_pll_clock_info cinfo;
203 };
204
205 /* Defines a generic omap register field */
206 struct dss_reg_field {
207 u8 start, end;
208 };
209
210 struct dispc_clock_info {
211 /* rates that we get with dividers below */
212 unsigned long lck;
213 unsigned long pck;
214
215 /* dividers */
216 u16 lck_div;
217 u16 pck_div;
218 };
219
220 struct dss_lcd_mgr_config {
221 enum dss_io_pad_mode io_pad_mode;
222
223 bool stallmode;
224 bool fifohandcheck;
225
226 struct dispc_clock_info clock_info;
227
228 int video_port_width;
229
230 int lcden_sig_polarity;
231 };
232
233 #define DSS_SZ_REGS SZ_512
234
235 struct dss_device {
236 struct platform_device *pdev;
237 void __iomem *base;
238 struct regmap *syscon_pll_ctrl;
239 u32 syscon_pll_ctrl_offset;
240
241 struct clk *parent_clk;
242 struct clk *dss_clk;
243 unsigned long dss_clk_rate;
244
245 unsigned long cache_req_pck;
246 unsigned long cache_prate;
247 struct dispc_clock_info cache_dispc_cinfo;
248
249 enum dss_clk_source dsi_clk_source[MAX_NUM_DSI];
250 enum dss_clk_source dispc_clk_source;
251 enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
252
253 bool ctx_valid;
254 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
255
256 const struct dss_features *feat;
257
258 struct {
259 struct dentry *root;
260 struct dss_debugfs_entry *clk;
261 struct dss_debugfs_entry *dss;
262 } debugfs;
263
264 struct dss_pll *plls[4];
265 struct dss_pll *video1_pll;
266 struct dss_pll *video2_pll;
267
268 struct dispc_device *dispc;
269 const struct dispc_ops *dispc_ops;
270 };
271
272 /* core */
dss_set_min_bus_tput(struct device * dev,unsigned long tput)273 static inline int dss_set_min_bus_tput(struct device *dev, unsigned long tput)
274 {
275 /* To be implemented when the OMAP platform will provide this feature */
276 return 0;
277 }
278
dss_mgr_is_lcd(enum omap_channel id)279 static inline bool dss_mgr_is_lcd(enum omap_channel id)
280 {
281 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
282 id == OMAP_DSS_CHANNEL_LCD3)
283 return true;
284 else
285 return false;
286 }
287
288 /* DSS */
289 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
290 struct dss_debugfs_entry *
291 dss_debugfs_create_file(struct dss_device *dss, const char *name,
292 int (*show_fn)(struct seq_file *s, void *data),
293 void *data);
294 void dss_debugfs_remove_file(struct dss_debugfs_entry *entry);
295 #else
296 static inline struct dss_debugfs_entry *
dss_debugfs_create_file(struct dss_device * dss,const char * name,int (* show_fn)(struct seq_file * s,void * data),void * data)297 dss_debugfs_create_file(struct dss_device *dss, const char *name,
298 int (*show_fn)(struct seq_file *s, void *data),
299 void *data)
300 {
301 return NULL;
302 }
303
dss_debugfs_remove_file(struct dss_debugfs_entry * entry)304 static inline void dss_debugfs_remove_file(struct dss_debugfs_entry *entry)
305 {
306 }
307 #endif /* CONFIG_OMAP2_DSS_DEBUGFS */
308
309 struct dss_device *dss_get_device(struct device *dev);
310
311 int dss_runtime_get(struct dss_device *dss);
312 void dss_runtime_put(struct dss_device *dss);
313
314 unsigned long dss_get_dispc_clk_rate(struct dss_device *dss);
315 unsigned long dss_get_max_fck_rate(struct dss_device *dss);
316 enum omap_dss_output_id dss_get_supported_outputs(struct dss_device *dss,
317 enum omap_channel channel);
318 int dss_dpi_select_source(struct dss_device *dss, int port,
319 enum omap_channel channel);
320 void dss_select_hdmi_venc_clk_source(struct dss_device *dss,
321 enum dss_hdmi_venc_clk_source_select src);
322 const char *dss_get_clk_source_name(enum dss_clk_source clk_src);
323
324 /* DSS VIDEO PLL */
325 struct dss_pll *dss_video_pll_init(struct dss_device *dss,
326 struct platform_device *pdev, int id,
327 struct regulator *regulator);
328 void dss_video_pll_uninit(struct dss_pll *pll);
329
330 void dss_ctrl_pll_enable(struct dss_pll *pll, bool enable);
331
332 void dss_sdi_init(struct dss_device *dss, int datapairs);
333 int dss_sdi_enable(struct dss_device *dss);
334 void dss_sdi_disable(struct dss_device *dss);
335
336 void dss_select_dsi_clk_source(struct dss_device *dss, int dsi_module,
337 enum dss_clk_source clk_src);
338 void dss_select_lcd_clk_source(struct dss_device *dss,
339 enum omap_channel channel,
340 enum dss_clk_source clk_src);
341 enum dss_clk_source dss_get_dispc_clk_source(struct dss_device *dss);
342 enum dss_clk_source dss_get_dsi_clk_source(struct dss_device *dss,
343 int dsi_module);
344 enum dss_clk_source dss_get_lcd_clk_source(struct dss_device *dss,
345 enum omap_channel channel);
346
347 void dss_set_venc_output(struct dss_device *dss, enum omap_dss_venc_type type);
348 void dss_set_dac_pwrdn_bgz(struct dss_device *dss, bool enable);
349
350 int dss_set_fck_rate(struct dss_device *dss, unsigned long rate);
351
352 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
353 bool dss_div_calc(struct dss_device *dss, unsigned long pck,
354 unsigned long fck_min, dss_div_calc_func func, void *data);
355
356 /* SDI */
357 #ifdef CONFIG_OMAP2_DSS_SDI
358 int sdi_init_port(struct dss_device *dss, struct platform_device *pdev,
359 struct device_node *port);
360 void sdi_uninit_port(struct device_node *port);
361 #else
sdi_init_port(struct dss_device * dss,struct platform_device * pdev,struct device_node * port)362 static inline int sdi_init_port(struct dss_device *dss,
363 struct platform_device *pdev,
364 struct device_node *port)
365 {
366 return 0;
367 }
sdi_uninit_port(struct device_node * port)368 static inline void sdi_uninit_port(struct device_node *port)
369 {
370 }
371 #endif
372
373 /* DSI */
374
375 #ifdef CONFIG_OMAP2_DSS_DSI
376
377 void dsi_dump_clocks(struct seq_file *s);
378
379 void dsi_irq_handler(void);
380
381 #endif
382
383 /* DPI */
384 #ifdef CONFIG_OMAP2_DSS_DPI
385 int dpi_init_port(struct dss_device *dss, struct platform_device *pdev,
386 struct device_node *port, enum dss_model dss_model);
387 void dpi_uninit_port(struct device_node *port);
388 #else
dpi_init_port(struct dss_device * dss,struct platform_device * pdev,struct device_node * port,enum dss_model dss_model)389 static inline int dpi_init_port(struct dss_device *dss,
390 struct platform_device *pdev,
391 struct device_node *port,
392 enum dss_model dss_model)
393 {
394 return 0;
395 }
dpi_uninit_port(struct device_node * port)396 static inline void dpi_uninit_port(struct device_node *port)
397 {
398 }
399 #endif
400
401 /* DISPC */
402 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s);
403
404 int dispc_runtime_get(struct dispc_device *dispc);
405 void dispc_runtime_put(struct dispc_device *dispc);
406
407 void dispc_enable_sidle(struct dispc_device *dispc);
408 void dispc_disable_sidle(struct dispc_device *dispc);
409
410 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable);
411 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable);
412 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable);
413
414 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
415 unsigned long pck, void *data);
416 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq,
417 unsigned long pck_min, unsigned long pck_max,
418 dispc_div_calc_func func, void *data);
419
420 bool dispc_mgr_timings_ok(struct dispc_device *dispc,
421 enum omap_channel channel,
422 const struct videomode *vm);
423 int dispc_calc_clock_rates(struct dispc_device *dispc,
424 unsigned long dispc_fclk_rate,
425 struct dispc_clock_info *cinfo);
426
427
428 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc,
429 enum omap_plane_id plane, u32 low, u32 high);
430 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc,
431 enum omap_plane_id plane,
432 u32 *fifo_low, u32 *fifo_high,
433 bool use_fifomerge, bool manual_update);
434
435 void dispc_mgr_set_clock_div(struct dispc_device *dispc,
436 enum omap_channel channel,
437 const struct dispc_clock_info *cinfo);
438 int dispc_mgr_get_clock_div(struct dispc_device *dispc,
439 enum omap_channel channel,
440 struct dispc_clock_info *cinfo);
441 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk);
442
443 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
dss_collect_irq_stats(u32 irqstatus,unsigned int * irq_arr)444 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned int *irq_arr)
445 {
446 int b;
447 for (b = 0; b < 32; ++b) {
448 if (irqstatus & (1 << b))
449 irq_arr[b]++;
450 }
451 }
452 #endif
453
454 /* PLL */
455 typedef bool (*dss_pll_calc_func)(int n, int m, unsigned long fint,
456 unsigned long clkdco, void *data);
457 typedef bool (*dss_hsdiv_calc_func)(int m_dispc, unsigned long dispc,
458 void *data);
459
460 int dss_pll_register(struct dss_device *dss, struct dss_pll *pll);
461 void dss_pll_unregister(struct dss_pll *pll);
462 struct dss_pll *dss_pll_find(struct dss_device *dss, const char *name);
463 struct dss_pll *dss_pll_find_by_src(struct dss_device *dss,
464 enum dss_clk_source src);
465 unsigned int dss_pll_get_clkout_idx_for_src(enum dss_clk_source src);
466 int dss_pll_enable(struct dss_pll *pll);
467 void dss_pll_disable(struct dss_pll *pll);
468 int dss_pll_set_config(struct dss_pll *pll,
469 const struct dss_pll_clock_info *cinfo);
470
471 bool dss_pll_hsdiv_calc_a(const struct dss_pll *pll, unsigned long clkdco,
472 unsigned long out_min, unsigned long out_max,
473 dss_hsdiv_calc_func func, void *data);
474 bool dss_pll_calc_a(const struct dss_pll *pll, unsigned long clkin,
475 unsigned long pll_min, unsigned long pll_max,
476 dss_pll_calc_func func, void *data);
477
478 bool dss_pll_calc_b(const struct dss_pll *pll, unsigned long clkin,
479 unsigned long target_clkout, struct dss_pll_clock_info *cinfo);
480
481 int dss_pll_write_config_type_a(struct dss_pll *pll,
482 const struct dss_pll_clock_info *cinfo);
483 int dss_pll_write_config_type_b(struct dss_pll *pll,
484 const struct dss_pll_clock_info *cinfo);
485 int dss_pll_wait_reset_done(struct dss_pll *pll);
486
487 extern struct platform_driver omap_dsshw_driver;
488 extern struct platform_driver omap_dispchw_driver;
489 #ifdef CONFIG_OMAP2_DSS_DSI
490 extern struct platform_driver omap_dsihw_driver;
491 #endif
492 #ifdef CONFIG_OMAP2_DSS_VENC
493 extern struct platform_driver omap_venchw_driver;
494 #endif
495 #ifdef CONFIG_OMAP4_DSS_HDMI
496 extern struct platform_driver omapdss_hdmi4hw_driver;
497 #endif
498 #ifdef CONFIG_OMAP5_DSS_HDMI
499 extern struct platform_driver omapdss_hdmi5hw_driver;
500 #endif
501
502 #endif
503
