1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_VDSC_REGS_H__ 7 #define __INTEL_VDSC_REGS_H__ 8 9 #include "intel_display_reg_defs.h" 10 11 /* Display Stream Splitter Control */ 12 #define DSS_CTL1 _MMIO(0x67400) 13 #define SPLITTER_ENABLE (1 << 31) 14 #define JOINER_ENABLE (1 << 30) 15 #define DUAL_LINK_MODE_INTERLEAVE (1 << 24) 16 #define DUAL_LINK_MODE_FRONTBACK (0 << 24) 17 #define OVERLAP_PIXELS_MASK (0xf << 16) 18 #define OVERLAP_PIXELS(pixels) ((pixels) << 16) 19 #define LEFT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 20 #define LEFT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 21 #define MAX_DL_BUFFER_TARGET_DEPTH 0x5a0 22 23 #define DSS_CTL2 _MMIO(0x67404) 24 #define LEFT_BRANCH_VDSC_ENABLE (1 << 31) 25 #define RIGHT_BRANCH_VDSC_ENABLE (1 << 15) 26 #define RIGHT_DL_BUF_TARGET_DEPTH_MASK (0xfff << 0) 27 #define RIGHT_DL_BUF_TARGET_DEPTH(pixels) ((pixels) << 0) 28 29 #define _ICL_PIPE_DSS_CTL1_PB 0x78200 30 #define _ICL_PIPE_DSS_CTL1_PC 0x78400 31 #define ICL_PIPE_DSS_CTL1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 32 _ICL_PIPE_DSS_CTL1_PB, \ 33 _ICL_PIPE_DSS_CTL1_PC) 34 #define BIG_JOINER_ENABLE (1 << 29) 35 #define MASTER_BIG_JOINER_ENABLE (1 << 28) 36 #define VGA_CENTERING_ENABLE (1 << 27) 37 #define SPLITTER_CONFIGURATION_MASK REG_GENMASK(26, 25) 38 #define SPLITTER_CONFIGURATION_2_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 0) 39 #define SPLITTER_CONFIGURATION_4_SEGMENT REG_FIELD_PREP(SPLITTER_CONFIGURATION_MASK, 1) 40 #define UNCOMPRESSED_JOINER_MASTER (1 << 21) 41 #define UNCOMPRESSED_JOINER_SLAVE (1 << 20) 42 43 #define _ICL_PIPE_DSS_CTL2_PB 0x78204 44 #define _ICL_PIPE_DSS_CTL2_PC 0x78404 45 #define ICL_PIPE_DSS_CTL2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 46 _ICL_PIPE_DSS_CTL2_PB, \ 47 _ICL_PIPE_DSS_CTL2_PC) 48 49 /* MTL Display Stream Compression registers */ 50 #define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB 0x782B4 51 #define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB 0x783B4 52 #define _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC 0x784B4 53 #define _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC 0x785B4 54 #define MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 55 _MTL_DSC0_PICTURE_PARAMETER_SET_17_PB, \ 56 _MTL_DSC0_PICTURE_PARAMETER_SET_17_PC) 57 #define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 58 _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \ 59 _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC) 60 #define DSC_SL_BPG_OFFSET(offset) ((offset) << 27) 61 62 #define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB 0x782B8 63 #define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB 0x783B8 64 #define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC 0x784B8 65 #define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC 0x785B8 66 #define MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 67 _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB, \ 68 _MTL_DSC0_PICTURE_PARAMETER_SET_18_PC) 69 #define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 70 _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \ 71 _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC) 72 #define DSC_NSL_BPG_OFFSET(offset) ((offset) << 16) 73 #define DSC_SL_OFFSET_ADJ(offset) ((offset) << 0) 74 75 /* Icelake Display Stream Compression Registers */ 76 #define DSCA_PICTURE_PARAMETER_SET_0 _MMIO(0x6B200) 77 #define DSCC_PICTURE_PARAMETER_SET_0 _MMIO(0x6BA00) 78 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270 79 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370 80 #define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470 81 #define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570 82 #define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 83 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \ 84 _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC) 85 #define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 86 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \ 87 _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC) 88 #define DSC_NATIVE_422_ENABLE BIT(23) 89 #define DSC_NATIVE_420_ENABLE BIT(22) 90 #define DSC_ALT_ICH_SEL (1 << 20) 91 #define DSC_VBR_ENABLE (1 << 19) 92 #define DSC_422_ENABLE (1 << 18) 93 #define DSC_COLOR_SPACE_CONVERSION (1 << 17) 94 #define DSC_BLOCK_PREDICTION (1 << 16) 95 #define DSC_LINE_BUF_DEPTH_SHIFT 12 96 #define DSC_BPC_SHIFT 8 97 #define DSC_VER_MIN_SHIFT 4 98 #define DSC_VER_MAJ (0x1 << 0) 99 100 #define DSCA_PICTURE_PARAMETER_SET_1 _MMIO(0x6B204) 101 #define DSCC_PICTURE_PARAMETER_SET_1 _MMIO(0x6BA04) 102 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274 103 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374 104 #define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474 105 #define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574 106 #define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 107 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \ 108 _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC) 109 #define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 110 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \ 111 _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC) 112 #define DSC_BPP(bpp) ((bpp) << 0) 113 114 #define DSCA_PICTURE_PARAMETER_SET_2 _MMIO(0x6B208) 115 #define DSCC_PICTURE_PARAMETER_SET_2 _MMIO(0x6BA08) 116 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278 117 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378 118 #define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478 119 #define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578 120 #define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 121 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \ 122 _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC) 123 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 124 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \ 125 _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC) 126 #define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16) 127 #define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0) 128 129 #define DSCA_PICTURE_PARAMETER_SET_3 _MMIO(0x6B20C) 130 #define DSCC_PICTURE_PARAMETER_SET_3 _MMIO(0x6BA0C) 131 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C 132 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C 133 #define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C 134 #define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C 135 #define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 136 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \ 137 _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC) 138 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 139 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \ 140 _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC) 141 #define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16) 142 #define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0) 143 144 #define DSCA_PICTURE_PARAMETER_SET_4 _MMIO(0x6B210) 145 #define DSCC_PICTURE_PARAMETER_SET_4 _MMIO(0x6BA10) 146 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280 147 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380 148 #define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480 149 #define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580 150 #define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 151 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \ 152 _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC) 153 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 154 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \ 155 _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC) 156 #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16) 157 #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0) 158 159 #define DSCA_PICTURE_PARAMETER_SET_5 _MMIO(0x6B214) 160 #define DSCC_PICTURE_PARAMETER_SET_5 _MMIO(0x6BA14) 161 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284 162 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384 163 #define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484 164 #define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584 165 #define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 166 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \ 167 _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC) 168 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 169 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \ 170 _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC) 171 #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16) 172 #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0) 173 174 #define DSCA_PICTURE_PARAMETER_SET_6 _MMIO(0x6B218) 175 #define DSCC_PICTURE_PARAMETER_SET_6 _MMIO(0x6BA18) 176 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288 177 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388 178 #define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488 179 #define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588 180 #define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 181 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \ 182 _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC) 183 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 184 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \ 185 _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC) 186 #define DSC_FLATNESS_MAX_QP(max_qp) ((max_qp) << 24) 187 #define DSC_FLATNESS_MIN_QP(min_qp) ((min_qp) << 16) 188 #define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8) 189 #define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0) 190 191 #define DSCA_PICTURE_PARAMETER_SET_7 _MMIO(0x6B21C) 192 #define DSCC_PICTURE_PARAMETER_SET_7 _MMIO(0x6BA1C) 193 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C 194 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C 195 #define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C 196 #define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C 197 #define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 198 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \ 199 _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC) 200 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 201 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \ 202 _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC) 203 #define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16) 204 #define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0) 205 206 #define DSCA_PICTURE_PARAMETER_SET_8 _MMIO(0x6B220) 207 #define DSCC_PICTURE_PARAMETER_SET_8 _MMIO(0x6BA20) 208 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290 209 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390 210 #define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490 211 #define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590 212 #define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 213 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \ 214 _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC) 215 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 216 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \ 217 _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC) 218 #define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16) 219 #define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0) 220 221 #define DSCA_PICTURE_PARAMETER_SET_9 _MMIO(0x6B224) 222 #define DSCC_PICTURE_PARAMETER_SET_9 _MMIO(0x6BA24) 223 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294 224 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394 225 #define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494 226 #define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594 227 #define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 228 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \ 229 _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC) 230 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 231 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \ 232 _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC) 233 #define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16) 234 #define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0) 235 236 #define DSCA_PICTURE_PARAMETER_SET_10 _MMIO(0x6B228) 237 #define DSCC_PICTURE_PARAMETER_SET_10 _MMIO(0x6BA28) 238 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298 239 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398 240 #define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498 241 #define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598 242 #define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 243 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \ 244 _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC) 245 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 246 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \ 247 _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC) 248 #define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20) 249 #define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16) 250 #define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8) 251 #define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0) 252 253 #define DSCA_PICTURE_PARAMETER_SET_11 _MMIO(0x6B22C) 254 #define DSCC_PICTURE_PARAMETER_SET_11 _MMIO(0x6BA2C) 255 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C 256 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C 257 #define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C 258 #define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C 259 #define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 260 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \ 261 _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC) 262 #define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 263 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \ 264 _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC) 265 266 #define DSCA_PICTURE_PARAMETER_SET_12 _MMIO(0x6B260) 267 #define DSCC_PICTURE_PARAMETER_SET_12 _MMIO(0x6BA60) 268 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0 269 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0 270 #define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0 271 #define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0 272 #define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 273 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \ 274 _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC) 275 #define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 276 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \ 277 _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC) 278 279 #define DSCA_PICTURE_PARAMETER_SET_13 _MMIO(0x6B264) 280 #define DSCC_PICTURE_PARAMETER_SET_13 _MMIO(0x6BA64) 281 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4 282 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4 283 #define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4 284 #define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4 285 #define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 286 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \ 287 _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC) 288 #define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 289 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \ 290 _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC) 291 292 #define DSCA_PICTURE_PARAMETER_SET_14 _MMIO(0x6B268) 293 #define DSCC_PICTURE_PARAMETER_SET_14 _MMIO(0x6BA68) 294 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8 295 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8 296 #define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8 297 #define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8 298 #define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 299 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \ 300 _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC) 301 #define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 302 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \ 303 _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC) 304 305 #define DSCA_PICTURE_PARAMETER_SET_15 _MMIO(0x6B26C) 306 #define DSCC_PICTURE_PARAMETER_SET_15 _MMIO(0x6BA6C) 307 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC 308 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC 309 #define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC 310 #define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC 311 #define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 312 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \ 313 _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC) 314 #define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 315 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \ 316 _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC) 317 318 #define DSCA_PICTURE_PARAMETER_SET_16 _MMIO(0x6B270) 319 #define DSCC_PICTURE_PARAMETER_SET_16 _MMIO(0x6BA70) 320 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0 321 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0 322 #define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0 323 #define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0 324 #define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 325 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \ 326 _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC) 327 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 328 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ 329 _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) 330 #define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) 331 #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) 332 #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) 333 334 /* Icelake Rate Control Buffer Threshold Registers */ 335 #define DSCA_RC_BUF_THRESH_0 _MMIO(0x6B230) 336 #define DSCA_RC_BUF_THRESH_0_UDW _MMIO(0x6B230 + 4) 337 #define DSCC_RC_BUF_THRESH_0 _MMIO(0x6BA30) 338 #define DSCC_RC_BUF_THRESH_0_UDW _MMIO(0x6BA30 + 4) 339 #define _ICL_DSC0_RC_BUF_THRESH_0_PB (0x78254) 340 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB (0x78254 + 4) 341 #define _ICL_DSC1_RC_BUF_THRESH_0_PB (0x78354) 342 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB (0x78354 + 4) 343 #define _ICL_DSC0_RC_BUF_THRESH_0_PC (0x78454) 344 #define _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC (0x78454 + 4) 345 #define _ICL_DSC1_RC_BUF_THRESH_0_PC (0x78554) 346 #define _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC (0x78554 + 4) 347 #define ICL_DSC0_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 348 _ICL_DSC0_RC_BUF_THRESH_0_PB, \ 349 _ICL_DSC0_RC_BUF_THRESH_0_PC) 350 #define ICL_DSC0_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 351 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PB, \ 352 _ICL_DSC0_RC_BUF_THRESH_0_UDW_PC) 353 #define ICL_DSC1_RC_BUF_THRESH_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 354 _ICL_DSC1_RC_BUF_THRESH_0_PB, \ 355 _ICL_DSC1_RC_BUF_THRESH_0_PC) 356 #define ICL_DSC1_RC_BUF_THRESH_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 357 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PB, \ 358 _ICL_DSC1_RC_BUF_THRESH_0_UDW_PC) 359 360 #define DSCA_RC_BUF_THRESH_1 _MMIO(0x6B238) 361 #define DSCA_RC_BUF_THRESH_1_UDW _MMIO(0x6B238 + 4) 362 #define DSCC_RC_BUF_THRESH_1 _MMIO(0x6BA38) 363 #define DSCC_RC_BUF_THRESH_1_UDW _MMIO(0x6BA38 + 4) 364 #define _ICL_DSC0_RC_BUF_THRESH_1_PB (0x7825C) 365 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB (0x7825C + 4) 366 #define _ICL_DSC1_RC_BUF_THRESH_1_PB (0x7835C) 367 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB (0x7835C + 4) 368 #define _ICL_DSC0_RC_BUF_THRESH_1_PC (0x7845C) 369 #define _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC (0x7845C + 4) 370 #define _ICL_DSC1_RC_BUF_THRESH_1_PC (0x7855C) 371 #define _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC (0x7855C + 4) 372 #define ICL_DSC0_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 373 _ICL_DSC0_RC_BUF_THRESH_1_PB, \ 374 _ICL_DSC0_RC_BUF_THRESH_1_PC) 375 #define ICL_DSC0_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 376 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PB, \ 377 _ICL_DSC0_RC_BUF_THRESH_1_UDW_PC) 378 #define ICL_DSC1_RC_BUF_THRESH_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 379 _ICL_DSC1_RC_BUF_THRESH_1_PB, \ 380 _ICL_DSC1_RC_BUF_THRESH_1_PC) 381 #define ICL_DSC1_RC_BUF_THRESH_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 382 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PB, \ 383 _ICL_DSC1_RC_BUF_THRESH_1_UDW_PC) 384 385 /* Icelake DSC Rate Control Range Parameter Registers */ 386 #define DSCA_RC_RANGE_PARAMETERS_0 _MMIO(0x6B240) 387 #define DSCA_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6B240 + 4) 388 #define DSCC_RC_RANGE_PARAMETERS_0 _MMIO(0x6BA40) 389 #define DSCC_RC_RANGE_PARAMETERS_0_UDW _MMIO(0x6BA40 + 4) 390 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB (0x78208) 391 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB (0x78208 + 4) 392 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB (0x78308) 393 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB (0x78308 + 4) 394 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC (0x78408) 395 #define _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC (0x78408 + 4) 396 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC (0x78508) 397 #define _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC (0x78508 + 4) 398 #define ICL_DSC0_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 399 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PB, \ 400 _ICL_DSC0_RC_RANGE_PARAMETERS_0_PC) 401 #define ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 402 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PB, \ 403 _ICL_DSC0_RC_RANGE_PARAMETERS_0_UDW_PC) 404 #define ICL_DSC1_RC_RANGE_PARAMETERS_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 405 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PB, \ 406 _ICL_DSC1_RC_RANGE_PARAMETERS_0_PC) 407 #define ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 408 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PB, \ 409 _ICL_DSC1_RC_RANGE_PARAMETERS_0_UDW_PC) 410 #define RC_BPG_OFFSET_SHIFT 10 411 #define RC_MAX_QP_SHIFT 5 412 #define RC_MIN_QP_SHIFT 0 413 414 #define DSCA_RC_RANGE_PARAMETERS_1 _MMIO(0x6B248) 415 #define DSCA_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6B248 + 4) 416 #define DSCC_RC_RANGE_PARAMETERS_1 _MMIO(0x6BA48) 417 #define DSCC_RC_RANGE_PARAMETERS_1_UDW _MMIO(0x6BA48 + 4) 418 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB (0x78210) 419 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB (0x78210 + 4) 420 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB (0x78310) 421 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB (0x78310 + 4) 422 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC (0x78410) 423 #define _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC (0x78410 + 4) 424 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC (0x78510) 425 #define _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC (0x78510 + 4) 426 #define ICL_DSC0_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 427 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PB, \ 428 _ICL_DSC0_RC_RANGE_PARAMETERS_1_PC) 429 #define ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 430 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PB, \ 431 _ICL_DSC0_RC_RANGE_PARAMETERS_1_UDW_PC) 432 #define ICL_DSC1_RC_RANGE_PARAMETERS_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 433 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PB, \ 434 _ICL_DSC1_RC_RANGE_PARAMETERS_1_PC) 435 #define ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 436 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PB, \ 437 _ICL_DSC1_RC_RANGE_PARAMETERS_1_UDW_PC) 438 439 #define DSCA_RC_RANGE_PARAMETERS_2 _MMIO(0x6B250) 440 #define DSCA_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6B250 + 4) 441 #define DSCC_RC_RANGE_PARAMETERS_2 _MMIO(0x6BA50) 442 #define DSCC_RC_RANGE_PARAMETERS_2_UDW _MMIO(0x6BA50 + 4) 443 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB (0x78218) 444 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB (0x78218 + 4) 445 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB (0x78318) 446 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB (0x78318 + 4) 447 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC (0x78418) 448 #define _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC (0x78418 + 4) 449 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC (0x78518) 450 #define _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC (0x78518 + 4) 451 #define ICL_DSC0_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 452 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PB, \ 453 _ICL_DSC0_RC_RANGE_PARAMETERS_2_PC) 454 #define ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 455 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PB, \ 456 _ICL_DSC0_RC_RANGE_PARAMETERS_2_UDW_PC) 457 #define ICL_DSC1_RC_RANGE_PARAMETERS_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 458 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PB, \ 459 _ICL_DSC1_RC_RANGE_PARAMETERS_2_PC) 460 #define ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 461 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PB, \ 462 _ICL_DSC1_RC_RANGE_PARAMETERS_2_UDW_PC) 463 464 #define DSCA_RC_RANGE_PARAMETERS_3 _MMIO(0x6B258) 465 #define DSCA_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6B258 + 4) 466 #define DSCC_RC_RANGE_PARAMETERS_3 _MMIO(0x6BA58) 467 #define DSCC_RC_RANGE_PARAMETERS_3_UDW _MMIO(0x6BA58 + 4) 468 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB (0x78220) 469 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB (0x78220 + 4) 470 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB (0x78320) 471 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB (0x78320 + 4) 472 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC (0x78420) 473 #define _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC (0x78420 + 4) 474 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC (0x78520) 475 #define _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC (0x78520 + 4) 476 #define ICL_DSC0_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 477 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PB, \ 478 _ICL_DSC0_RC_RANGE_PARAMETERS_3_PC) 479 #define ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 480 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PB, \ 481 _ICL_DSC0_RC_RANGE_PARAMETERS_3_UDW_PC) 482 #define ICL_DSC1_RC_RANGE_PARAMETERS_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 483 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PB, \ 484 _ICL_DSC1_RC_RANGE_PARAMETERS_3_PC) 485 #define ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ 486 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PB, \ 487 _ICL_DSC1_RC_RANGE_PARAMETERS_3_UDW_PC) 488 489 #endif /* __INTEL_VDSC_REGS_H__ */ 490
