1 /* 2 * Copyright 2016 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_DP_TYPES_H 27 #define DC_DP_TYPES_H 28 29 #include "os_types.h" 30 31 enum dc_lane_count { 32 LANE_COUNT_UNKNOWN = 0, 33 LANE_COUNT_ONE = 1, 34 LANE_COUNT_TWO = 2, 35 LANE_COUNT_FOUR = 4, 36 LANE_COUNT_EIGHT = 8, 37 LANE_COUNT_DP_MAX = LANE_COUNT_FOUR 38 }; 39 40 /* This is actually a reference clock (27MHz) multiplier 41 * 162MBps bandwidth for 1.62GHz like rate, 42 * 270MBps for 2.70GHz, 43 * 324MBps for 3.24Ghz, 44 * 540MBps for 5.40GHz 45 * 810MBps for 8.10GHz 46 */ 47 enum dc_link_rate { 48 LINK_RATE_UNKNOWN = 0, 49 LINK_RATE_LOW = 0x06, // Rate_1 (RBR) - 1.62 Gbps/Lane 50 LINK_RATE_RATE_2 = 0x08, // Rate_2 - 2.16 Gbps/Lane 51 LINK_RATE_RATE_3 = 0x09, // Rate_3 - 2.43 Gbps/Lane 52 LINK_RATE_HIGH = 0x0A, // Rate_4 (HBR) - 2.70 Gbps/Lane 53 LINK_RATE_RBR2 = 0x0C, // Rate_5 (RBR2)- 3.24 Gbps/Lane 54 LINK_RATE_RATE_6 = 0x10, // Rate_6 - 4.32 Gbps/Lane 55 LINK_RATE_HIGH2 = 0x14, // Rate_7 (HBR2)- 5.40 Gbps/Lane 56 LINK_RATE_HIGH3 = 0x1E // Rate_8 (HBR3)- 8.10 Gbps/Lane 57 }; 58 59 enum dc_link_spread { 60 LINK_SPREAD_DISABLED = 0x00, 61 /* 0.5 % downspread 30 kHz */ 62 LINK_SPREAD_05_DOWNSPREAD_30KHZ = 0x10, 63 /* 0.5 % downspread 33 kHz */ 64 LINK_SPREAD_05_DOWNSPREAD_33KHZ = 0x11 65 }; 66 67 enum dc_voltage_swing { 68 VOLTAGE_SWING_LEVEL0 = 0, /* direct HW translation! */ 69 VOLTAGE_SWING_LEVEL1, 70 VOLTAGE_SWING_LEVEL2, 71 VOLTAGE_SWING_LEVEL3, 72 VOLTAGE_SWING_MAX_LEVEL = VOLTAGE_SWING_LEVEL3 73 }; 74 75 enum dc_pre_emphasis { 76 PRE_EMPHASIS_DISABLED = 0, /* direct HW translation! */ 77 PRE_EMPHASIS_LEVEL1, 78 PRE_EMPHASIS_LEVEL2, 79 PRE_EMPHASIS_LEVEL3, 80 PRE_EMPHASIS_MAX_LEVEL = PRE_EMPHASIS_LEVEL3 81 }; 82 /* Post Cursor 2 is optional for transmitter 83 * and it applies only to the main link operating at HBR2 84 */ 85 enum dc_post_cursor2 { 86 POST_CURSOR2_DISABLED = 0, /* direct HW translation! */ 87 POST_CURSOR2_LEVEL1, 88 POST_CURSOR2_LEVEL2, 89 POST_CURSOR2_LEVEL3, 90 POST_CURSOR2_MAX_LEVEL = POST_CURSOR2_LEVEL3, 91 }; 92 93 enum dc_dp_training_pattern { 94 DP_TRAINING_PATTERN_SEQUENCE_1 = 0, 95 DP_TRAINING_PATTERN_SEQUENCE_2, 96 DP_TRAINING_PATTERN_SEQUENCE_3, 97 DP_TRAINING_PATTERN_SEQUENCE_4, 98 DP_TRAINING_PATTERN_VIDEOIDLE, 99 }; 100 101 enum dp_link_encoding { 102 DP_UNKNOWN_ENCODING = 0, 103 DP_8b_10b_ENCODING = 1, 104 }; 105 106 struct dc_link_settings { 107 enum dc_lane_count lane_count; 108 enum dc_link_rate link_rate; 109 enum dc_link_spread link_spread; 110 bool use_link_rate_set; 111 uint8_t link_rate_set; 112 bool dpcd_source_device_specific_field_support; 113 }; 114 115 struct dc_lane_settings { 116 enum dc_voltage_swing VOLTAGE_SWING; 117 enum dc_pre_emphasis PRE_EMPHASIS; 118 enum dc_post_cursor2 POST_CURSOR2; 119 }; 120 121 struct dc_link_training_settings { 122 struct dc_link_settings link; 123 struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]; 124 }; 125 126 struct dc_link_training_overrides { 127 enum dc_voltage_swing *voltage_swing; 128 enum dc_pre_emphasis *pre_emphasis; 129 enum dc_post_cursor2 *post_cursor2; 130 131 uint16_t *cr_pattern_time; 132 uint16_t *eq_pattern_time; 133 enum dc_dp_training_pattern *pattern_for_cr; 134 enum dc_dp_training_pattern *pattern_for_eq; 135 136 enum dc_link_spread *downspread; 137 bool *alternate_scrambler_reset; 138 bool *enhanced_framing; 139 bool *mst_enable; 140 bool *fec_enable; 141 }; 142 143 union dpcd_rev { 144 struct { 145 uint8_t MINOR:4; 146 uint8_t MAJOR:4; 147 } bits; 148 uint8_t raw; 149 }; 150 151 union max_lane_count { 152 struct { 153 uint8_t MAX_LANE_COUNT:5; 154 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1; 155 uint8_t TPS3_SUPPORTED:1; 156 uint8_t ENHANCED_FRAME_CAP:1; 157 } bits; 158 uint8_t raw; 159 }; 160 161 union max_down_spread { 162 struct { 163 uint8_t MAX_DOWN_SPREAD:1; 164 uint8_t RESERVED:5; 165 uint8_t NO_AUX_HANDSHAKE_LINK_TRAINING:1; 166 uint8_t TPS4_SUPPORTED:1; 167 } bits; 168 uint8_t raw; 169 }; 170 171 union mstm_cap { 172 struct { 173 uint8_t MST_CAP:1; 174 uint8_t RESERVED:7; 175 } bits; 176 uint8_t raw; 177 }; 178 179 union lane_count_set { 180 struct { 181 uint8_t LANE_COUNT_SET:5; 182 uint8_t POST_LT_ADJ_REQ_GRANTED:1; 183 uint8_t RESERVED:1; 184 uint8_t ENHANCED_FRAMING:1; 185 } bits; 186 uint8_t raw; 187 }; 188 189 union lane_status { 190 struct { 191 uint8_t CR_DONE_0:1; 192 uint8_t CHANNEL_EQ_DONE_0:1; 193 uint8_t SYMBOL_LOCKED_0:1; 194 uint8_t RESERVED0:1; 195 uint8_t CR_DONE_1:1; 196 uint8_t CHANNEL_EQ_DONE_1:1; 197 uint8_t SYMBOL_LOCKED_1:1; 198 uint8_t RESERVED_1:1; 199 } bits; 200 uint8_t raw; 201 }; 202 203 union device_service_irq { 204 struct { 205 uint8_t REMOTE_CONTROL_CMD_PENDING:1; 206 uint8_t AUTOMATED_TEST:1; 207 uint8_t CP_IRQ:1; 208 uint8_t MCCS_IRQ:1; 209 uint8_t DOWN_REP_MSG_RDY:1; 210 uint8_t UP_REQ_MSG_RDY:1; 211 uint8_t SINK_SPECIFIC:1; 212 uint8_t reserved:1; 213 } bits; 214 uint8_t raw; 215 }; 216 217 union sink_count { 218 struct { 219 uint8_t SINK_COUNT:6; 220 uint8_t CPREADY:1; 221 uint8_t RESERVED:1; 222 } bits; 223 uint8_t raw; 224 }; 225 226 union lane_align_status_updated { 227 struct { 228 uint8_t INTERLANE_ALIGN_DONE:1; 229 uint8_t POST_LT_ADJ_REQ_IN_PROGRESS:1; 230 uint8_t RESERVED:4; 231 uint8_t DOWNSTREAM_PORT_STATUS_CHANGED:1; 232 uint8_t LINK_STATUS_UPDATED:1; 233 } bits; 234 uint8_t raw; 235 }; 236 237 union lane_adjust { 238 struct { 239 uint8_t VOLTAGE_SWING_LANE:2; 240 uint8_t PRE_EMPHASIS_LANE:2; 241 uint8_t RESERVED:4; 242 } bits; 243 uint8_t raw; 244 }; 245 246 union dpcd_training_pattern { 247 struct { 248 uint8_t TRAINING_PATTERN_SET:4; 249 uint8_t RECOVERED_CLOCK_OUT_EN:1; 250 uint8_t SCRAMBLING_DISABLE:1; 251 uint8_t SYMBOL_ERROR_COUNT_SEL:2; 252 } v1_4; 253 struct { 254 uint8_t TRAINING_PATTERN_SET:2; 255 uint8_t LINK_QUAL_PATTERN_SET:2; 256 uint8_t RESERVED:4; 257 } v1_3; 258 uint8_t raw; 259 }; 260 261 /* Training Lane is used to configure downstream DP device's voltage swing 262 and pre-emphasis levels*/ 263 /* The DPCD addresses are from 0x103 to 0x106*/ 264 union dpcd_training_lane { 265 struct { 266 uint8_t VOLTAGE_SWING_SET:2; 267 uint8_t MAX_SWING_REACHED:1; 268 uint8_t PRE_EMPHASIS_SET:2; 269 uint8_t MAX_PRE_EMPHASIS_REACHED:1; 270 uint8_t RESERVED:2; 271 } bits; 272 uint8_t raw; 273 }; 274 275 /* TMDS-converter related */ 276 union dwnstream_port_caps_byte0 { 277 struct { 278 uint8_t DWN_STRM_PORTX_TYPE:3; 279 uint8_t DWN_STRM_PORTX_HPD:1; 280 uint8_t RESERVERD:4; 281 } bits; 282 uint8_t raw; 283 }; 284 285 /* these are the detailed types stored at DWN_STRM_PORTX_CAP (00080h)*/ 286 enum dpcd_downstream_port_detailed_type { 287 DOWN_STREAM_DETAILED_DP = 0, 288 DOWN_STREAM_DETAILED_VGA, 289 DOWN_STREAM_DETAILED_DVI, 290 DOWN_STREAM_DETAILED_HDMI, 291 DOWN_STREAM_DETAILED_NONDDC,/* has no EDID (TV,CV)*/ 292 DOWN_STREAM_DETAILED_DP_PLUS_PLUS 293 }; 294 295 union dwnstream_port_caps_byte2 { 296 struct { 297 uint8_t MAX_BITS_PER_COLOR_COMPONENT:2; 298 uint8_t RESERVED:6; 299 } bits; 300 uint8_t raw; 301 }; 302 303 union dp_downstream_port_present { 304 uint8_t byte; 305 struct { 306 uint8_t PORT_PRESENT:1; 307 uint8_t PORT_TYPE:2; 308 uint8_t FMT_CONVERSION:1; 309 uint8_t DETAILED_CAPS:1; 310 uint8_t RESERVED:3; 311 } fields; 312 }; 313 314 union dwnstream_port_caps_byte3_dvi { 315 struct { 316 uint8_t RESERVED1:1; 317 uint8_t DUAL_LINK:1; 318 uint8_t HIGH_COLOR_DEPTH:1; 319 uint8_t RESERVED2:5; 320 } bits; 321 uint8_t raw; 322 }; 323 324 union dwnstream_port_caps_byte3_hdmi { 325 struct { 326 uint8_t FRAME_SEQ_TO_FRAME_PACK:1; 327 uint8_t YCrCr422_PASS_THROUGH:1; 328 uint8_t YCrCr420_PASS_THROUGH:1; 329 uint8_t YCrCr422_CONVERSION:1; 330 uint8_t YCrCr420_CONVERSION:1; 331 uint8_t RESERVED:3; 332 } bits; 333 uint8_t raw; 334 }; 335 336 /*4-byte structure for detailed capabilities of a down-stream port 337 (DP-to-TMDS converter).*/ 338 union dwnstream_portxcaps { 339 struct { 340 union dwnstream_port_caps_byte0 byte0; 341 unsigned char max_TMDS_clock; //byte1 342 union dwnstream_port_caps_byte2 byte2; 343 344 union { 345 union dwnstream_port_caps_byte3_dvi byteDVI; 346 union dwnstream_port_caps_byte3_hdmi byteHDMI; 347 } byte3; 348 } bytes; 349 350 unsigned char raw[4]; 351 }; 352 353 union downstream_port { 354 struct { 355 unsigned char present:1; 356 unsigned char type:2; 357 unsigned char format_conv:1; 358 unsigned char detailed_caps:1; 359 unsigned char reserved:3; 360 } bits; 361 unsigned char raw; 362 }; 363 364 365 union sink_status { 366 struct { 367 uint8_t RX_PORT0_STATUS:1; 368 uint8_t RX_PORT1_STATUS:1; 369 uint8_t RESERVED:6; 370 } bits; 371 uint8_t raw; 372 }; 373 374 /*6-byte structure corresponding to 6 registers (200h-205h) 375 read during handling of HPD-IRQ*/ 376 union hpd_irq_data { 377 struct { 378 union sink_count sink_cnt;/* 200h */ 379 union device_service_irq device_service_irq;/* 201h */ 380 union lane_status lane01_status;/* 202h */ 381 union lane_status lane23_status;/* 203h */ 382 union lane_align_status_updated lane_status_updated;/* 204h */ 383 union sink_status sink_status; 384 } bytes; 385 uint8_t raw[6]; 386 }; 387 388 union down_stream_port_count { 389 struct { 390 uint8_t DOWN_STR_PORT_COUNT:4; 391 uint8_t RESERVED:2; /*Bits 5:4 = RESERVED. Read all 0s.*/ 392 /*Bit 6 = MSA_TIMING_PAR_IGNORED 393 0 = Sink device requires the MSA timing parameters 394 1 = Sink device is capable of rendering incoming video 395 stream without MSA timing parameters*/ 396 uint8_t IGNORE_MSA_TIMING_PARAM:1; 397 /*Bit 7 = OUI Support 398 0 = OUI not supported 399 1 = OUI supported 400 (OUI and Device Identification mandatory for DP 1.2)*/ 401 uint8_t OUI_SUPPORT:1; 402 } bits; 403 uint8_t raw; 404 }; 405 406 union down_spread_ctrl { 407 struct { 408 uint8_t RESERVED1:4;/* Bit 3:0 = RESERVED. Read all 0s*/ 409 /* Bits 4 = SPREAD_AMP. Spreading amplitude 410 0 = Main link signal is not downspread 411 1 = Main link signal is downspread <= 0.5% 412 with frequency in the range of 30kHz ~ 33kHz*/ 413 uint8_t SPREAD_AMP:1; 414 uint8_t RESERVED2:2;/*Bit 6:5 = RESERVED. Read all 0s*/ 415 /*Bit 7 = MSA_TIMING_PAR_IGNORE_EN 416 0 = Source device will send valid data for the MSA Timing Params 417 1 = Source device may send invalid data for these MSA Timing Params*/ 418 uint8_t IGNORE_MSA_TIMING_PARAM:1; 419 } bits; 420 uint8_t raw; 421 }; 422 423 union dpcd_edp_config { 424 struct { 425 uint8_t PANEL_MODE_EDP:1; 426 uint8_t FRAMING_CHANGE_ENABLE:1; 427 uint8_t RESERVED:5; 428 uint8_t PANEL_SELF_TEST_ENABLE:1; 429 } bits; 430 uint8_t raw; 431 }; 432 433 struct dp_device_vendor_id { 434 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 435 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 436 }; 437 438 struct dp_sink_hw_fw_revision { 439 uint8_t ieee_hw_rev; 440 uint8_t ieee_fw_rev[2]; 441 }; 442 443 struct dpcd_vendor_signature { 444 bool is_valid; 445 446 union dpcd_ieee_vendor_signature { 447 struct { 448 uint8_t ieee_oui[3];/*24-bit IEEE OUI*/ 449 uint8_t ieee_device_id[6];/*usually 6-byte ASCII name*/ 450 uint8_t ieee_hw_rev; 451 uint8_t ieee_fw_rev[2]; 452 }; 453 uint8_t raw[12]; 454 } data; 455 }; 456 457 struct dpcd_amd_signature { 458 uint8_t AMD_IEEE_TxSignature_byte1; 459 uint8_t AMD_IEEE_TxSignature_byte2; 460 uint8_t AMD_IEEE_TxSignature_byte3; 461 }; 462 463 struct dpcd_amd_device_id { 464 uint8_t device_id_byte1; 465 uint8_t device_id_byte2; 466 uint8_t zero[4]; 467 uint8_t dce_version; 468 uint8_t dal_version_byte1; 469 uint8_t dal_version_byte2; 470 }; 471 472 struct dpcd_source_backlight_set { 473 struct { 474 uint8_t byte0; 475 uint8_t byte1; 476 uint8_t byte2; 477 uint8_t byte3; 478 } backlight_level_millinits; 479 480 struct { 481 uint8_t byte0; 482 uint8_t byte1; 483 } backlight_transition_time_ms; 484 }; 485 486 union dpcd_source_backlight_get { 487 struct { 488 uint32_t backlight_millinits_peak; /* 326h */ 489 uint32_t backlight_millinits_avg; /* 32Ah */ 490 } bytes; 491 uint8_t raw[8]; 492 }; 493 494 /*DPCD register of DP receiver capability field bits-*/ 495 union edp_configuration_cap { 496 struct { 497 uint8_t ALT_SCRAMBLER_RESET:1; 498 uint8_t FRAMING_CHANGE:1; 499 uint8_t RESERVED:1; 500 uint8_t DPCD_DISPLAY_CONTROL_CAPABLE:1; 501 uint8_t RESERVED2:4; 502 } bits; 503 uint8_t raw; 504 }; 505 506 union dprx_feature { 507 struct { 508 uint8_t GTC_CAP:1; // bit 0: DP 1.3+ 509 uint8_t SST_SPLIT_SDP_CAP:1; // bit 1: DP 1.4 510 uint8_t AV_SYNC_CAP:1; // bit 2: DP 1.3+ 511 uint8_t VSC_SDP_COLORIMETRY_SUPPORTED:1; // bit 3: DP 1.3+ 512 uint8_t VSC_EXT_VESA_SDP_SUPPORTED:1; // bit 4: DP 1.4 513 uint8_t VSC_EXT_VESA_SDP_CHAINING_SUPPORTED:1; // bit 5: DP 1.4 514 uint8_t VSC_EXT_CEA_SDP_SUPPORTED:1; // bit 6: DP 1.4 515 uint8_t VSC_EXT_CEA_SDP_CHAINING_SUPPORTED:1; // bit 7: DP 1.4 516 } bits; 517 uint8_t raw; 518 }; 519 520 union training_aux_rd_interval { 521 struct { 522 uint8_t TRAINIG_AUX_RD_INTERVAL:7; 523 uint8_t EXT_RECEIVER_CAP_FIELD_PRESENT:1; 524 } bits; 525 uint8_t raw; 526 }; 527 528 /* Automated test structures */ 529 union test_request { 530 struct { 531 uint8_t LINK_TRAINING :1; 532 uint8_t LINK_TEST_PATTRN :1; 533 uint8_t EDID_READ :1; 534 uint8_t PHY_TEST_PATTERN :1; 535 uint8_t RESERVED :1; 536 uint8_t AUDIO_TEST_PATTERN :1; 537 uint8_t TEST_AUDIO_DISABLED_VIDEO :1; 538 } bits; 539 uint8_t raw; 540 }; 541 542 union test_response { 543 struct { 544 uint8_t ACK :1; 545 uint8_t NO_ACK :1; 546 uint8_t EDID_CHECKSUM_WRITE:1; 547 uint8_t RESERVED :5; 548 } bits; 549 uint8_t raw; 550 }; 551 552 union phy_test_pattern { 553 struct { 554 /* DpcdPhyTestPatterns. This field is 2 bits for DP1.1 555 * and 3 bits for DP1.2. 556 */ 557 uint8_t PATTERN :3; 558 /* BY speci, bit7:2 is 0 for DP1.1. */ 559 uint8_t RESERVED :5; 560 } bits; 561 uint8_t raw; 562 }; 563 564 /* States of Compliance Test Specification (CTS DP1.2). */ 565 union compliance_test_state { 566 struct { 567 unsigned char STEREO_3D_RUNNING : 1; 568 unsigned char RESERVED : 7; 569 } bits; 570 unsigned char raw; 571 }; 572 573 union link_test_pattern { 574 struct { 575 /* dpcd_link_test_patterns */ 576 unsigned char PATTERN :2; 577 unsigned char RESERVED:6; 578 } bits; 579 unsigned char raw; 580 }; 581 582 union test_misc { 583 struct dpcd_test_misc_bits { 584 unsigned char SYNC_CLOCK :1; 585 /* dpcd_test_color_format */ 586 unsigned char CLR_FORMAT :2; 587 /* dpcd_test_dyn_range */ 588 unsigned char DYN_RANGE :1; 589 unsigned char YCBCR_COEFS :1; 590 /* dpcd_test_bit_depth */ 591 unsigned char BPC :3; 592 } bits; 593 unsigned char raw; 594 }; 595 596 union audio_test_mode { 597 struct { 598 unsigned char sampling_rate :4; 599 unsigned char channel_count :4; 600 } bits; 601 unsigned char raw; 602 }; 603 604 union audio_test_pattern_period { 605 struct { 606 unsigned char pattern_period :4; 607 unsigned char reserved :4; 608 } bits; 609 unsigned char raw; 610 }; 611 612 struct audio_test_pattern_type { 613 unsigned char value; 614 }; 615 616 struct dp_audio_test_data_flags { 617 uint8_t test_requested :1; 618 uint8_t disable_video :1; 619 }; 620 621 struct dp_audio_test_data { 622 623 struct dp_audio_test_data_flags flags; 624 uint8_t sampling_rate; 625 uint8_t channel_count; 626 uint8_t pattern_type; 627 uint8_t pattern_period[8]; 628 }; 629 630 /* FEC capability DPCD register field bits-*/ 631 union dpcd_fec_capability { 632 struct { 633 uint8_t FEC_CAPABLE:1; 634 uint8_t UNCORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 635 uint8_t CORRECTED_BLOCK_ERROR_COUNT_CAPABLE:1; 636 uint8_t BIT_ERROR_COUNT_CAPABLE:1; 637 uint8_t RESERVED:4; 638 } bits; 639 uint8_t raw; 640 }; 641 642 /* DSC capability DPCD register field bits-*/ 643 struct dpcd_dsc_support { 644 uint8_t DSC_SUPPORT :1; 645 uint8_t DSC_PASSTHROUGH_SUPPORT :1; 646 uint8_t RESERVED :6; 647 }; 648 649 struct dpcd_dsc_algorithm_revision { 650 uint8_t DSC_VERSION_MAJOR :4; 651 uint8_t DSC_VERSION_MINOR :4; 652 }; 653 654 struct dpcd_dsc_rc_buffer_block_size { 655 uint8_t RC_BLOCK_BUFFER_SIZE :2; 656 uint8_t RESERVED :6; 657 }; 658 659 struct dpcd_dsc_slice_capability1 { 660 uint8_t ONE_SLICE_PER_DP_DSC_SINK_DEVICE :1; 661 uint8_t TWO_SLICES_PER_DP_DSC_SINK_DEVICE :1; 662 uint8_t RESERVED :1; 663 uint8_t FOUR_SLICES_PER_DP_DSC_SINK_DEVICE :1; 664 uint8_t SIX_SLICES_PER_DP_DSC_SINK_DEVICE :1; 665 uint8_t EIGHT_SLICES_PER_DP_DSC_SINK_DEVICE :1; 666 uint8_t TEN_SLICES_PER_DP_DSC_SINK_DEVICE :1; 667 uint8_t TWELVE_SLICES_PER_DP_DSC_SINK_DEVICE :1; 668 }; 669 670 struct dpcd_dsc_line_buffer_bit_depth { 671 uint8_t LINE_BUFFER_BIT_DEPTH :4; 672 uint8_t RESERVED :4; 673 }; 674 675 struct dpcd_dsc_block_prediction_support { 676 uint8_t BLOCK_PREDICTION_SUPPORT:1; 677 uint8_t RESERVED :7; 678 }; 679 680 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor { 681 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_LOW :7; 682 uint8_t MAXIMUM_BITS_PER_PIXEL_SUPPORTED_BY_THE_DECOMPRESSOR_HIGH :7; 683 uint8_t RESERVED :2; 684 }; 685 686 struct dpcd_dsc_decoder_color_format_capabilities { 687 uint8_t RGB_SUPPORT :1; 688 uint8_t Y_CB_CR_444_SUPPORT :1; 689 uint8_t Y_CB_CR_SIMPLE_422_SUPPORT :1; 690 uint8_t Y_CB_CR_NATIVE_422_SUPPORT :1; 691 uint8_t Y_CB_CR_NATIVE_420_SUPPORT :1; 692 uint8_t RESERVED :3; 693 }; 694 695 struct dpcd_dsc_decoder_color_depth_capabilities { 696 uint8_t RESERVED0 :1; 697 uint8_t EIGHT_BITS_PER_COLOR_SUPPORT :1; 698 uint8_t TEN_BITS_PER_COLOR_SUPPORT :1; 699 uint8_t TWELVE_BITS_PER_COLOR_SUPPORT :1; 700 uint8_t RESERVED1 :4; 701 }; 702 703 struct dpcd_peak_dsc_throughput_dsc_sink { 704 uint8_t THROUGHPUT_MODE_0:4; 705 uint8_t THROUGHPUT_MODE_1:4; 706 }; 707 708 struct dpcd_dsc_slice_capabilities_2 { 709 uint8_t SIXTEEN_SLICES_PER_DSC_SINK_DEVICE :1; 710 uint8_t TWENTY_SLICES_PER_DSC_SINK_DEVICE :1; 711 uint8_t TWENTYFOUR_SLICES_PER_DSC_SINK_DEVICE :1; 712 uint8_t RESERVED :5; 713 }; 714 715 struct dpcd_bits_per_pixel_increment{ 716 uint8_t INCREMENT_OF_BITS_PER_PIXEL_SUPPORTED :3; 717 uint8_t RESERVED :5; 718 }; 719 union dpcd_dsc_basic_capabilities { 720 struct { 721 struct dpcd_dsc_support dsc_support; 722 struct dpcd_dsc_algorithm_revision dsc_algorithm_revision; 723 struct dpcd_dsc_rc_buffer_block_size dsc_rc_buffer_block_size; 724 uint8_t dsc_rc_buffer_size; 725 struct dpcd_dsc_slice_capability1 dsc_slice_capabilities_1; 726 struct dpcd_dsc_line_buffer_bit_depth dsc_line_buffer_bit_depth; 727 struct dpcd_dsc_block_prediction_support dsc_block_prediction_support; 728 struct dpcd_maximum_bits_per_pixel_supported_by_the_decompressor maximum_bits_per_pixel_supported_by_the_decompressor; 729 struct dpcd_dsc_decoder_color_format_capabilities dsc_decoder_color_format_capabilities; 730 struct dpcd_dsc_decoder_color_depth_capabilities dsc_decoder_color_depth_capabilities; 731 struct dpcd_peak_dsc_throughput_dsc_sink peak_dsc_throughput_dsc_sink; 732 uint8_t dsc_maximum_slice_width; 733 struct dpcd_dsc_slice_capabilities_2 dsc_slice_capabilities_2; 734 uint8_t reserved; 735 struct dpcd_bits_per_pixel_increment bits_per_pixel_increment; 736 } fields; 737 uint8_t raw[16]; 738 }; 739 740 union dpcd_dsc_branch_decoder_capabilities { 741 struct { 742 uint8_t BRANCH_OVERALL_THROUGHPUT_0; 743 uint8_t BRANCH_OVERALL_THROUGHPUT_1; 744 uint8_t BRANCH_MAX_LINE_WIDTH; 745 } fields; 746 uint8_t raw[3]; 747 }; 748 749 struct dpcd_dsc_capabilities { 750 union dpcd_dsc_basic_capabilities dsc_basic_caps; 751 union dpcd_dsc_branch_decoder_capabilities dsc_branch_decoder_caps; 752 }; 753 754 /* These parameters are from PSR capabilities reported by Sink DPCD */ 755 struct psr_caps { 756 unsigned char psr_version; 757 unsigned int psr_rfb_setup_time; 758 bool psr_exit_link_training_required; 759 }; 760 761 #endif /* DC_DP_TYPES_H */ 762
