1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
2 /* QLogic qed NIC Driver
3 * Copyright (c) 2015-2017 QLogic Corporation
4 * Copyright (c) 2019-2020 Marvell International Ltd.
5 */
6
7 #ifndef _QED_IF_H
8 #define _QED_IF_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/netdevice.h>
13 #include <linux/pci.h>
14 #include <linux/skbuff.h>
15 #include <asm/byteorder.h>
16 #include <linux/io.h>
17 #include <linux/compiler.h>
18 #include <linux/kernel.h>
19 #include <linux/list.h>
20 #include <linux/slab.h>
21 #include <linux/qed/common_hsi.h>
22 #include <linux/qed/qed_chain.h>
23 #include <linux/io-64-nonatomic-lo-hi.h>
24 #include <net/devlink.h>
25
26 enum dcbx_protocol_type {
27 DCBX_PROTOCOL_ISCSI,
28 DCBX_PROTOCOL_FCOE,
29 DCBX_PROTOCOL_ROCE,
30 DCBX_PROTOCOL_ROCE_V2,
31 DCBX_PROTOCOL_ETH,
32 DCBX_MAX_PROTOCOL_TYPE
33 };
34
35 #define QED_ROCE_PROTOCOL_INDEX (3)
36
37 #define QED_LLDP_CHASSIS_ID_STAT_LEN 4
38 #define QED_LLDP_PORT_ID_STAT_LEN 4
39 #define QED_DCBX_MAX_APP_PROTOCOL 32
40 #define QED_MAX_PFC_PRIORITIES 8
41 #define QED_DCBX_DSCP_SIZE 64
42
43 struct qed_dcbx_lldp_remote {
44 u32 peer_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
45 u32 peer_port_id[QED_LLDP_PORT_ID_STAT_LEN];
46 bool enable_rx;
47 bool enable_tx;
48 u32 tx_interval;
49 u32 max_credit;
50 };
51
52 struct qed_dcbx_lldp_local {
53 u32 local_chassis_id[QED_LLDP_CHASSIS_ID_STAT_LEN];
54 u32 local_port_id[QED_LLDP_PORT_ID_STAT_LEN];
55 };
56
57 struct qed_dcbx_app_prio {
58 u8 roce;
59 u8 roce_v2;
60 u8 fcoe;
61 u8 iscsi;
62 u8 eth;
63 };
64
65 struct qed_dbcx_pfc_params {
66 bool willing;
67 bool enabled;
68 u8 prio[QED_MAX_PFC_PRIORITIES];
69 u8 max_tc;
70 };
71
72 enum qed_dcbx_sf_ieee_type {
73 QED_DCBX_SF_IEEE_ETHTYPE,
74 QED_DCBX_SF_IEEE_TCP_PORT,
75 QED_DCBX_SF_IEEE_UDP_PORT,
76 QED_DCBX_SF_IEEE_TCP_UDP_PORT
77 };
78
79 struct qed_app_entry {
80 bool ethtype;
81 enum qed_dcbx_sf_ieee_type sf_ieee;
82 bool enabled;
83 u8 prio;
84 u16 proto_id;
85 enum dcbx_protocol_type proto_type;
86 };
87
88 struct qed_dcbx_params {
89 struct qed_app_entry app_entry[QED_DCBX_MAX_APP_PROTOCOL];
90 u16 num_app_entries;
91 bool app_willing;
92 bool app_valid;
93 bool app_error;
94 bool ets_willing;
95 bool ets_enabled;
96 bool ets_cbs;
97 bool valid;
98 u8 ets_pri_tc_tbl[QED_MAX_PFC_PRIORITIES];
99 u8 ets_tc_bw_tbl[QED_MAX_PFC_PRIORITIES];
100 u8 ets_tc_tsa_tbl[QED_MAX_PFC_PRIORITIES];
101 struct qed_dbcx_pfc_params pfc;
102 u8 max_ets_tc;
103 };
104
105 struct qed_dcbx_admin_params {
106 struct qed_dcbx_params params;
107 bool valid;
108 };
109
110 struct qed_dcbx_remote_params {
111 struct qed_dcbx_params params;
112 bool valid;
113 };
114
115 struct qed_dcbx_operational_params {
116 struct qed_dcbx_app_prio app_prio;
117 struct qed_dcbx_params params;
118 bool valid;
119 bool enabled;
120 bool ieee;
121 bool cee;
122 bool local;
123 u32 err;
124 };
125
126 struct qed_dcbx_get {
127 struct qed_dcbx_operational_params operational;
128 struct qed_dcbx_lldp_remote lldp_remote;
129 struct qed_dcbx_lldp_local lldp_local;
130 struct qed_dcbx_remote_params remote;
131 struct qed_dcbx_admin_params local;
132 };
133
134 enum qed_nvm_images {
135 QED_NVM_IMAGE_ISCSI_CFG,
136 QED_NVM_IMAGE_FCOE_CFG,
137 QED_NVM_IMAGE_MDUMP,
138 QED_NVM_IMAGE_NVM_CFG1,
139 QED_NVM_IMAGE_DEFAULT_CFG,
140 QED_NVM_IMAGE_NVM_META,
141 };
142
143 struct qed_link_eee_params {
144 u32 tx_lpi_timer;
145 #define QED_EEE_1G_ADV BIT(0)
146 #define QED_EEE_10G_ADV BIT(1)
147
148 /* Capabilities are represented using QED_EEE_*_ADV values */
149 u8 adv_caps;
150 u8 lp_adv_caps;
151 bool enable;
152 bool tx_lpi_enable;
153 };
154
155 enum qed_led_mode {
156 QED_LED_MODE_OFF,
157 QED_LED_MODE_ON,
158 QED_LED_MODE_RESTORE
159 };
160
161 struct qed_mfw_tlv_eth {
162 u16 lso_maxoff_size;
163 bool lso_maxoff_size_set;
164 u16 lso_minseg_size;
165 bool lso_minseg_size_set;
166 u8 prom_mode;
167 bool prom_mode_set;
168 u16 tx_descr_size;
169 bool tx_descr_size_set;
170 u16 rx_descr_size;
171 bool rx_descr_size_set;
172 u16 netq_count;
173 bool netq_count_set;
174 u32 tcp4_offloads;
175 bool tcp4_offloads_set;
176 u32 tcp6_offloads;
177 bool tcp6_offloads_set;
178 u16 tx_descr_qdepth;
179 bool tx_descr_qdepth_set;
180 u16 rx_descr_qdepth;
181 bool rx_descr_qdepth_set;
182 u8 iov_offload;
183 #define QED_MFW_TLV_IOV_OFFLOAD_NONE (0)
184 #define QED_MFW_TLV_IOV_OFFLOAD_MULTIQUEUE (1)
185 #define QED_MFW_TLV_IOV_OFFLOAD_VEB (2)
186 #define QED_MFW_TLV_IOV_OFFLOAD_VEPA (3)
187 bool iov_offload_set;
188 u8 txqs_empty;
189 bool txqs_empty_set;
190 u8 rxqs_empty;
191 bool rxqs_empty_set;
192 u8 num_txqs_full;
193 bool num_txqs_full_set;
194 u8 num_rxqs_full;
195 bool num_rxqs_full_set;
196 };
197
198 #define QED_MFW_TLV_TIME_SIZE 14
199 struct qed_mfw_tlv_time {
200 bool b_set;
201 u8 month;
202 u8 day;
203 u8 hour;
204 u8 min;
205 u16 msec;
206 u16 usec;
207 };
208
209 struct qed_mfw_tlv_fcoe {
210 u8 scsi_timeout;
211 bool scsi_timeout_set;
212 u32 rt_tov;
213 bool rt_tov_set;
214 u32 ra_tov;
215 bool ra_tov_set;
216 u32 ed_tov;
217 bool ed_tov_set;
218 u32 cr_tov;
219 bool cr_tov_set;
220 u8 boot_type;
221 bool boot_type_set;
222 u8 npiv_state;
223 bool npiv_state_set;
224 u32 num_npiv_ids;
225 bool num_npiv_ids_set;
226 u8 switch_name[8];
227 bool switch_name_set;
228 u16 switch_portnum;
229 bool switch_portnum_set;
230 u8 switch_portid[3];
231 bool switch_portid_set;
232 u8 vendor_name[8];
233 bool vendor_name_set;
234 u8 switch_model[8];
235 bool switch_model_set;
236 u8 switch_fw_version[8];
237 bool switch_fw_version_set;
238 u8 qos_pri;
239 bool qos_pri_set;
240 u8 port_alias[3];
241 bool port_alias_set;
242 u8 port_state;
243 #define QED_MFW_TLV_PORT_STATE_OFFLINE (0)
244 #define QED_MFW_TLV_PORT_STATE_LOOP (1)
245 #define QED_MFW_TLV_PORT_STATE_P2P (2)
246 #define QED_MFW_TLV_PORT_STATE_FABRIC (3)
247 bool port_state_set;
248 u16 fip_tx_descr_size;
249 bool fip_tx_descr_size_set;
250 u16 fip_rx_descr_size;
251 bool fip_rx_descr_size_set;
252 u16 link_failures;
253 bool link_failures_set;
254 u8 fcoe_boot_progress;
255 bool fcoe_boot_progress_set;
256 u64 rx_bcast;
257 bool rx_bcast_set;
258 u64 tx_bcast;
259 bool tx_bcast_set;
260 u16 fcoe_txq_depth;
261 bool fcoe_txq_depth_set;
262 u16 fcoe_rxq_depth;
263 bool fcoe_rxq_depth_set;
264 u64 fcoe_rx_frames;
265 bool fcoe_rx_frames_set;
266 u64 fcoe_rx_bytes;
267 bool fcoe_rx_bytes_set;
268 u64 fcoe_tx_frames;
269 bool fcoe_tx_frames_set;
270 u64 fcoe_tx_bytes;
271 bool fcoe_tx_bytes_set;
272 u16 crc_count;
273 bool crc_count_set;
274 u32 crc_err_src_fcid[5];
275 bool crc_err_src_fcid_set[5];
276 struct qed_mfw_tlv_time crc_err[5];
277 u16 losync_err;
278 bool losync_err_set;
279 u16 losig_err;
280 bool losig_err_set;
281 u16 primtive_err;
282 bool primtive_err_set;
283 u16 disparity_err;
284 bool disparity_err_set;
285 u16 code_violation_err;
286 bool code_violation_err_set;
287 u32 flogi_param[4];
288 bool flogi_param_set[4];
289 struct qed_mfw_tlv_time flogi_tstamp;
290 u32 flogi_acc_param[4];
291 bool flogi_acc_param_set[4];
292 struct qed_mfw_tlv_time flogi_acc_tstamp;
293 u32 flogi_rjt;
294 bool flogi_rjt_set;
295 struct qed_mfw_tlv_time flogi_rjt_tstamp;
296 u32 fdiscs;
297 bool fdiscs_set;
298 u8 fdisc_acc;
299 bool fdisc_acc_set;
300 u8 fdisc_rjt;
301 bool fdisc_rjt_set;
302 u8 plogi;
303 bool plogi_set;
304 u8 plogi_acc;
305 bool plogi_acc_set;
306 u8 plogi_rjt;
307 bool plogi_rjt_set;
308 u32 plogi_dst_fcid[5];
309 bool plogi_dst_fcid_set[5];
310 struct qed_mfw_tlv_time plogi_tstamp[5];
311 u32 plogi_acc_src_fcid[5];
312 bool plogi_acc_src_fcid_set[5];
313 struct qed_mfw_tlv_time plogi_acc_tstamp[5];
314 u8 tx_plogos;
315 bool tx_plogos_set;
316 u8 plogo_acc;
317 bool plogo_acc_set;
318 u8 plogo_rjt;
319 bool plogo_rjt_set;
320 u32 plogo_src_fcid[5];
321 bool plogo_src_fcid_set[5];
322 struct qed_mfw_tlv_time plogo_tstamp[5];
323 u8 rx_logos;
324 bool rx_logos_set;
325 u8 tx_accs;
326 bool tx_accs_set;
327 u8 tx_prlis;
328 bool tx_prlis_set;
329 u8 rx_accs;
330 bool rx_accs_set;
331 u8 tx_abts;
332 bool tx_abts_set;
333 u8 rx_abts_acc;
334 bool rx_abts_acc_set;
335 u8 rx_abts_rjt;
336 bool rx_abts_rjt_set;
337 u32 abts_dst_fcid[5];
338 bool abts_dst_fcid_set[5];
339 struct qed_mfw_tlv_time abts_tstamp[5];
340 u8 rx_rscn;
341 bool rx_rscn_set;
342 u32 rx_rscn_nport[4];
343 bool rx_rscn_nport_set[4];
344 u8 tx_lun_rst;
345 bool tx_lun_rst_set;
346 u8 abort_task_sets;
347 bool abort_task_sets_set;
348 u8 tx_tprlos;
349 bool tx_tprlos_set;
350 u8 tx_nos;
351 bool tx_nos_set;
352 u8 rx_nos;
353 bool rx_nos_set;
354 u8 ols;
355 bool ols_set;
356 u8 lr;
357 bool lr_set;
358 u8 lrr;
359 bool lrr_set;
360 u8 tx_lip;
361 bool tx_lip_set;
362 u8 rx_lip;
363 bool rx_lip_set;
364 u8 eofa;
365 bool eofa_set;
366 u8 eofni;
367 bool eofni_set;
368 u8 scsi_chks;
369 bool scsi_chks_set;
370 u8 scsi_cond_met;
371 bool scsi_cond_met_set;
372 u8 scsi_busy;
373 bool scsi_busy_set;
374 u8 scsi_inter;
375 bool scsi_inter_set;
376 u8 scsi_inter_cond_met;
377 bool scsi_inter_cond_met_set;
378 u8 scsi_rsv_conflicts;
379 bool scsi_rsv_conflicts_set;
380 u8 scsi_tsk_full;
381 bool scsi_tsk_full_set;
382 u8 scsi_aca_active;
383 bool scsi_aca_active_set;
384 u8 scsi_tsk_abort;
385 bool scsi_tsk_abort_set;
386 u32 scsi_rx_chk[5];
387 bool scsi_rx_chk_set[5];
388 struct qed_mfw_tlv_time scsi_chk_tstamp[5];
389 };
390
391 struct qed_mfw_tlv_iscsi {
392 u8 target_llmnr;
393 bool target_llmnr_set;
394 u8 header_digest;
395 bool header_digest_set;
396 u8 data_digest;
397 bool data_digest_set;
398 u8 auth_method;
399 #define QED_MFW_TLV_AUTH_METHOD_NONE (1)
400 #define QED_MFW_TLV_AUTH_METHOD_CHAP (2)
401 #define QED_MFW_TLV_AUTH_METHOD_MUTUAL_CHAP (3)
402 bool auth_method_set;
403 u16 boot_taget_portal;
404 bool boot_taget_portal_set;
405 u16 frame_size;
406 bool frame_size_set;
407 u16 tx_desc_size;
408 bool tx_desc_size_set;
409 u16 rx_desc_size;
410 bool rx_desc_size_set;
411 u8 boot_progress;
412 bool boot_progress_set;
413 u16 tx_desc_qdepth;
414 bool tx_desc_qdepth_set;
415 u16 rx_desc_qdepth;
416 bool rx_desc_qdepth_set;
417 u64 rx_frames;
418 bool rx_frames_set;
419 u64 rx_bytes;
420 bool rx_bytes_set;
421 u64 tx_frames;
422 bool tx_frames_set;
423 u64 tx_bytes;
424 bool tx_bytes_set;
425 };
426
427 enum qed_db_rec_width {
428 DB_REC_WIDTH_32B,
429 DB_REC_WIDTH_64B,
430 };
431
432 enum qed_db_rec_space {
433 DB_REC_KERNEL,
434 DB_REC_USER,
435 };
436
437 #define DIRECT_REG_WR(reg_addr, val) writel((u32)val, \
438 (void __iomem *)(reg_addr))
439
440 #define DIRECT_REG_RD(reg_addr) readl((void __iomem *)(reg_addr))
441
442 #define DIRECT_REG_WR64(reg_addr, val) writeq((u64)val, \
443 (void __iomem *)(reg_addr))
444
445 #define QED_COALESCE_MAX 0x1FF
446 #define QED_DEFAULT_RX_USECS 12
447 #define QED_DEFAULT_TX_USECS 48
448
449 /* forward */
450 struct qed_dev;
451
452 struct qed_eth_pf_params {
453 /* The following parameters are used during HW-init
454 * and these parameters need to be passed as arguments
455 * to update_pf_params routine invoked before slowpath start
456 */
457 u16 num_cons;
458
459 /* per-VF number of CIDs */
460 u8 num_vf_cons;
461 #define ETH_PF_PARAMS_VF_CONS_DEFAULT (32)
462
463 /* To enable arfs, previous to HW-init a positive number needs to be
464 * set [as filters require allocated searcher ILT memory].
465 * This will set the maximal number of configured steering-filters.
466 */
467 u32 num_arfs_filters;
468 };
469
470 struct qed_fcoe_pf_params {
471 /* The following parameters are used during protocol-init */
472 u64 glbl_q_params_addr;
473 u64 bdq_pbl_base_addr[2];
474
475 /* The following parameters are used during HW-init
476 * and these parameters need to be passed as arguments
477 * to update_pf_params routine invoked before slowpath start
478 */
479 u16 num_cons;
480 u16 num_tasks;
481
482 /* The following parameters are used during protocol-init */
483 u16 sq_num_pbl_pages;
484
485 u16 cq_num_entries;
486 u16 cmdq_num_entries;
487 u16 rq_buffer_log_size;
488 u16 mtu;
489 u16 dummy_icid;
490 u16 bdq_xoff_threshold[2];
491 u16 bdq_xon_threshold[2];
492 u16 rq_buffer_size;
493 u8 num_cqs; /* num of global CQs */
494 u8 log_page_size;
495 u8 gl_rq_pi;
496 u8 gl_cmd_pi;
497 u8 debug_mode;
498 u8 is_target;
499 u8 bdq_pbl_num_entries[2];
500 };
501
502 /* Most of the parameters below are described in the FW iSCSI / TCP HSI */
503 struct qed_iscsi_pf_params {
504 u64 glbl_q_params_addr;
505 u64 bdq_pbl_base_addr[3];
506 u16 cq_num_entries;
507 u16 cmdq_num_entries;
508 u32 two_msl_timer;
509 u16 tx_sws_timer;
510
511 /* The following parameters are used during HW-init
512 * and these parameters need to be passed as arguments
513 * to update_pf_params routine invoked before slowpath start
514 */
515 u16 num_cons;
516 u16 num_tasks;
517
518 /* The following parameters are used during protocol-init */
519 u16 half_way_close_timeout;
520 u16 bdq_xoff_threshold[3];
521 u16 bdq_xon_threshold[3];
522 u16 cmdq_xoff_threshold;
523 u16 cmdq_xon_threshold;
524 u16 rq_buffer_size;
525
526 u8 num_sq_pages_in_ring;
527 u8 num_r2tq_pages_in_ring;
528 u8 num_uhq_pages_in_ring;
529 u8 num_queues;
530 u8 log_page_size;
531 u8 rqe_log_size;
532 u8 max_fin_rt;
533 u8 gl_rq_pi;
534 u8 gl_cmd_pi;
535 u8 debug_mode;
536 u8 ll2_ooo_queue_id;
537
538 u8 is_target;
539 u8 is_soc_en;
540 u8 soc_num_of_blocks_log;
541 u8 bdq_pbl_num_entries[3];
542 };
543
544 struct qed_rdma_pf_params {
545 /* Supplied to QED during resource allocation (may affect the ILT and
546 * the doorbell BAR).
547 */
548 u32 min_dpis; /* number of requested DPIs */
549 u32 num_qps; /* number of requested Queue Pairs */
550 u32 num_srqs; /* number of requested SRQ */
551 u8 roce_edpm_mode; /* see QED_ROCE_EDPM_MODE_ENABLE */
552 u8 gl_pi; /* protocol index */
553
554 /* Will allocate rate limiters to be used with QPs */
555 u8 enable_dcqcn;
556 };
557
558 struct qed_pf_params {
559 struct qed_eth_pf_params eth_pf_params;
560 struct qed_fcoe_pf_params fcoe_pf_params;
561 struct qed_iscsi_pf_params iscsi_pf_params;
562 struct qed_rdma_pf_params rdma_pf_params;
563 };
564
565 enum qed_int_mode {
566 QED_INT_MODE_INTA,
567 QED_INT_MODE_MSIX,
568 QED_INT_MODE_MSI,
569 QED_INT_MODE_POLL,
570 };
571
572 struct qed_sb_info {
573 struct status_block_e4 *sb_virt;
574 dma_addr_t sb_phys;
575 u32 sb_ack; /* Last given ack */
576 u16 igu_sb_id;
577 void __iomem *igu_addr;
578 u8 flags;
579 #define QED_SB_INFO_INIT 0x1
580 #define QED_SB_INFO_SETUP 0x2
581
582 struct qed_dev *cdev;
583 };
584
585 enum qed_hw_err_type {
586 QED_HW_ERR_FAN_FAIL,
587 QED_HW_ERR_MFW_RESP_FAIL,
588 QED_HW_ERR_HW_ATTN,
589 QED_HW_ERR_DMAE_FAIL,
590 QED_HW_ERR_RAMROD_FAIL,
591 QED_HW_ERR_FW_ASSERT,
592 QED_HW_ERR_LAST,
593 };
594
595 enum qed_dev_type {
596 QED_DEV_TYPE_BB,
597 QED_DEV_TYPE_AH,
598 QED_DEV_TYPE_E5,
599 };
600
601 struct qed_dev_info {
602 unsigned long pci_mem_start;
603 unsigned long pci_mem_end;
604 unsigned int pci_irq;
605 u8 num_hwfns;
606
607 u8 hw_mac[ETH_ALEN];
608
609 /* FW version */
610 u16 fw_major;
611 u16 fw_minor;
612 u16 fw_rev;
613 u16 fw_eng;
614
615 /* MFW version */
616 u32 mfw_rev;
617 #define QED_MFW_VERSION_0_MASK 0x000000FF
618 #define QED_MFW_VERSION_0_OFFSET 0
619 #define QED_MFW_VERSION_1_MASK 0x0000FF00
620 #define QED_MFW_VERSION_1_OFFSET 8
621 #define QED_MFW_VERSION_2_MASK 0x00FF0000
622 #define QED_MFW_VERSION_2_OFFSET 16
623 #define QED_MFW_VERSION_3_MASK 0xFF000000
624 #define QED_MFW_VERSION_3_OFFSET 24
625
626 u32 flash_size;
627 bool b_arfs_capable;
628 bool b_inter_pf_switch;
629 bool tx_switching;
630 bool rdma_supported;
631 u16 mtu;
632
633 bool wol_support;
634 bool smart_an;
635
636 /* MBI version */
637 u32 mbi_version;
638 #define QED_MBI_VERSION_0_MASK 0x000000FF
639 #define QED_MBI_VERSION_0_OFFSET 0
640 #define QED_MBI_VERSION_1_MASK 0x0000FF00
641 #define QED_MBI_VERSION_1_OFFSET 8
642 #define QED_MBI_VERSION_2_MASK 0x00FF0000
643 #define QED_MBI_VERSION_2_OFFSET 16
644
645 enum qed_dev_type dev_type;
646
647 /* Output parameters for qede */
648 bool vxlan_enable;
649 bool gre_enable;
650 bool geneve_enable;
651
652 u8 abs_pf_id;
653 };
654
655 enum qed_sb_type {
656 QED_SB_TYPE_L2_QUEUE,
657 QED_SB_TYPE_CNQ,
658 QED_SB_TYPE_STORAGE,
659 };
660
661 enum qed_protocol {
662 QED_PROTOCOL_ETH,
663 QED_PROTOCOL_ISCSI,
664 QED_PROTOCOL_FCOE,
665 };
666
667 enum qed_fec_mode {
668 QED_FEC_MODE_NONE = BIT(0),
669 QED_FEC_MODE_FIRECODE = BIT(1),
670 QED_FEC_MODE_RS = BIT(2),
671 QED_FEC_MODE_AUTO = BIT(3),
672 QED_FEC_MODE_UNSUPPORTED = BIT(4),
673 };
674
675 struct qed_link_params {
676 bool link_up;
677
678 u32 override_flags;
679 #define QED_LINK_OVERRIDE_SPEED_AUTONEG BIT(0)
680 #define QED_LINK_OVERRIDE_SPEED_ADV_SPEEDS BIT(1)
681 #define QED_LINK_OVERRIDE_SPEED_FORCED_SPEED BIT(2)
682 #define QED_LINK_OVERRIDE_PAUSE_CONFIG BIT(3)
683 #define QED_LINK_OVERRIDE_LOOPBACK_MODE BIT(4)
684 #define QED_LINK_OVERRIDE_EEE_CONFIG BIT(5)
685 #define QED_LINK_OVERRIDE_FEC_CONFIG BIT(6)
686
687 bool autoneg;
688 __ETHTOOL_DECLARE_LINK_MODE_MASK(adv_speeds);
689 u32 forced_speed;
690
691 u32 pause_config;
692 #define QED_LINK_PAUSE_AUTONEG_ENABLE BIT(0)
693 #define QED_LINK_PAUSE_RX_ENABLE BIT(1)
694 #define QED_LINK_PAUSE_TX_ENABLE BIT(2)
695
696 u32 loopback_mode;
697 #define QED_LINK_LOOPBACK_NONE BIT(0)
698 #define QED_LINK_LOOPBACK_INT_PHY BIT(1)
699 #define QED_LINK_LOOPBACK_EXT_PHY BIT(2)
700 #define QED_LINK_LOOPBACK_EXT BIT(3)
701 #define QED_LINK_LOOPBACK_MAC BIT(4)
702 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_0123 BIT(5)
703 #define QED_LINK_LOOPBACK_CNIG_AH_ONLY_2301 BIT(6)
704 #define QED_LINK_LOOPBACK_PCS_AH_ONLY BIT(7)
705 #define QED_LINK_LOOPBACK_REVERSE_MAC_AH_ONLY BIT(8)
706 #define QED_LINK_LOOPBACK_INT_PHY_FEA_AH_ONLY BIT(9)
707
708 struct qed_link_eee_params eee;
709 u32 fec;
710 };
711
712 struct qed_link_output {
713 bool link_up;
714
715 __ETHTOOL_DECLARE_LINK_MODE_MASK(supported_caps);
716 __ETHTOOL_DECLARE_LINK_MODE_MASK(advertised_caps);
717 __ETHTOOL_DECLARE_LINK_MODE_MASK(lp_caps);
718
719 u32 speed; /* In Mb/s */
720 u8 duplex; /* In DUPLEX defs */
721 u8 port; /* In PORT defs */
722 bool autoneg;
723 u32 pause_config;
724
725 /* EEE - capability & param */
726 bool eee_supported;
727 bool eee_active;
728 u8 sup_caps;
729 struct qed_link_eee_params eee;
730
731 u32 sup_fec;
732 u32 active_fec;
733 };
734
735 struct qed_probe_params {
736 enum qed_protocol protocol;
737 u32 dp_module;
738 u8 dp_level;
739 bool is_vf;
740 bool recov_in_prog;
741 };
742
743 #define QED_DRV_VER_STR_SIZE 12
744 struct qed_slowpath_params {
745 u32 int_mode;
746 u8 drv_major;
747 u8 drv_minor;
748 u8 drv_rev;
749 u8 drv_eng;
750 u8 name[QED_DRV_VER_STR_SIZE];
751 };
752
753 #define ILT_PAGE_SIZE_TCFC 0x8000 /* 32KB */
754
755 struct qed_int_info {
756 struct msix_entry *msix;
757 u8 msix_cnt;
758
759 /* This should be updated by the protocol driver */
760 u8 used_cnt;
761 };
762
763 struct qed_generic_tlvs {
764 #define QED_TLV_IP_CSUM BIT(0)
765 #define QED_TLV_LSO BIT(1)
766 u16 feat_flags;
767 #define QED_TLV_MAC_COUNT 3
768 u8 mac[QED_TLV_MAC_COUNT][ETH_ALEN];
769 };
770
771 #define QED_I2C_DEV_ADDR_A0 0xA0
772 #define QED_I2C_DEV_ADDR_A2 0xA2
773
774 #define QED_NVM_SIGNATURE 0x12435687
775
776 enum qed_nvm_flash_cmd {
777 QED_NVM_FLASH_CMD_FILE_DATA = 0x2,
778 QED_NVM_FLASH_CMD_FILE_START = 0x3,
779 QED_NVM_FLASH_CMD_NVM_CHANGE = 0x4,
780 QED_NVM_FLASH_CMD_NVM_CFG_ID = 0x5,
781 QED_NVM_FLASH_CMD_NVM_MAX,
782 };
783
784 struct qed_devlink {
785 struct qed_dev *cdev;
786 struct devlink_health_reporter *fw_reporter;
787 };
788
789 struct qed_common_cb_ops {
790 void (*arfs_filter_op)(void *dev, void *fltr, u8 fw_rc);
791 void (*link_update)(void *dev, struct qed_link_output *link);
792 void (*schedule_recovery_handler)(void *dev);
793 void (*schedule_hw_err_handler)(void *dev,
794 enum qed_hw_err_type err_type);
795 void (*dcbx_aen)(void *dev, struct qed_dcbx_get *get, u32 mib_type);
796 void (*get_generic_tlv_data)(void *dev, struct qed_generic_tlvs *data);
797 void (*get_protocol_tlv_data)(void *dev, void *data);
798 void (*bw_update)(void *dev);
799 };
800
801 struct qed_selftest_ops {
802 /**
803 * @brief selftest_interrupt - Perform interrupt test
804 *
805 * @param cdev
806 *
807 * @return 0 on success, error otherwise.
808 */
809 int (*selftest_interrupt)(struct qed_dev *cdev);
810
811 /**
812 * @brief selftest_memory - Perform memory test
813 *
814 * @param cdev
815 *
816 * @return 0 on success, error otherwise.
817 */
818 int (*selftest_memory)(struct qed_dev *cdev);
819
820 /**
821 * @brief selftest_register - Perform register test
822 *
823 * @param cdev
824 *
825 * @return 0 on success, error otherwise.
826 */
827 int (*selftest_register)(struct qed_dev *cdev);
828
829 /**
830 * @brief selftest_clock - Perform clock test
831 *
832 * @param cdev
833 *
834 * @return 0 on success, error otherwise.
835 */
836 int (*selftest_clock)(struct qed_dev *cdev);
837
838 /**
839 * @brief selftest_nvram - Perform nvram test
840 *
841 * @param cdev
842 *
843 * @return 0 on success, error otherwise.
844 */
845 int (*selftest_nvram) (struct qed_dev *cdev);
846 };
847
848 struct qed_common_ops {
849 struct qed_selftest_ops *selftest;
850
851 struct qed_dev* (*probe)(struct pci_dev *dev,
852 struct qed_probe_params *params);
853
854 void (*remove)(struct qed_dev *cdev);
855
856 int (*set_power_state)(struct qed_dev *cdev, pci_power_t state);
857
858 void (*set_name) (struct qed_dev *cdev, char name[]);
859
860 /* Client drivers need to make this call before slowpath_start.
861 * PF params required for the call before slowpath_start is
862 * documented within the qed_pf_params structure definition.
863 */
864 void (*update_pf_params)(struct qed_dev *cdev,
865 struct qed_pf_params *params);
866
867 int (*slowpath_start)(struct qed_dev *cdev,
868 struct qed_slowpath_params *params);
869
870 int (*slowpath_stop)(struct qed_dev *cdev);
871
872 /* Requests to use `cnt' interrupts for fastpath.
873 * upon success, returns number of interrupts allocated for fastpath.
874 */
875 int (*set_fp_int)(struct qed_dev *cdev, u16 cnt);
876
877 /* Fills `info' with pointers required for utilizing interrupts */
878 int (*get_fp_int)(struct qed_dev *cdev, struct qed_int_info *info);
879
880 u32 (*sb_init)(struct qed_dev *cdev,
881 struct qed_sb_info *sb_info,
882 void *sb_virt_addr,
883 dma_addr_t sb_phy_addr,
884 u16 sb_id,
885 enum qed_sb_type type);
886
887 u32 (*sb_release)(struct qed_dev *cdev,
888 struct qed_sb_info *sb_info,
889 u16 sb_id,
890 enum qed_sb_type type);
891
892 void (*simd_handler_config)(struct qed_dev *cdev,
893 void *token,
894 int index,
895 void (*handler)(void *));
896
897 void (*simd_handler_clean)(struct qed_dev *cdev, int index);
898
899 int (*dbg_grc)(struct qed_dev *cdev, void *buffer, u32 *num_dumped_bytes);
900
901 int (*dbg_grc_size)(struct qed_dev *cdev);
902
903 int (*dbg_all_data)(struct qed_dev *cdev, void *buffer);
904
905 int (*dbg_all_data_size)(struct qed_dev *cdev);
906
907 int (*report_fatal_error)(struct devlink *devlink,
908 enum qed_hw_err_type err_type);
909
910 /**
911 * @brief can_link_change - can the instance change the link or not
912 *
913 * @param cdev
914 *
915 * @return true if link-change is allowed, false otherwise.
916 */
917 bool (*can_link_change)(struct qed_dev *cdev);
918
919 /**
920 * @brief set_link - set links according to params
921 *
922 * @param cdev
923 * @param params - values used to override the default link configuration
924 *
925 * @return 0 on success, error otherwise.
926 */
927 int (*set_link)(struct qed_dev *cdev,
928 struct qed_link_params *params);
929
930 /**
931 * @brief get_link - returns the current link state.
932 *
933 * @param cdev
934 * @param if_link - structure to be filled with current link configuration.
935 */
936 void (*get_link)(struct qed_dev *cdev,
937 struct qed_link_output *if_link);
938
939 /**
940 * @brief - drains chip in case Tx completions fail to arrive due to pause.
941 *
942 * @param cdev
943 */
944 int (*drain)(struct qed_dev *cdev);
945
946 /**
947 * @brief update_msglvl - update module debug level
948 *
949 * @param cdev
950 * @param dp_module
951 * @param dp_level
952 */
953 void (*update_msglvl)(struct qed_dev *cdev,
954 u32 dp_module,
955 u8 dp_level);
956
957 int (*chain_alloc)(struct qed_dev *cdev,
958 struct qed_chain *chain,
959 struct qed_chain_init_params *params);
960
961 void (*chain_free)(struct qed_dev *cdev,
962 struct qed_chain *p_chain);
963
964 /**
965 * @brief nvm_flash - Flash nvm data.
966 *
967 * @param cdev
968 * @param name - file containing the data
969 *
970 * @return 0 on success, error otherwise.
971 */
972 int (*nvm_flash)(struct qed_dev *cdev, const char *name);
973
974 /**
975 * @brief nvm_get_image - reads an entire image from nvram
976 *
977 * @param cdev
978 * @param type - type of the request nvram image
979 * @param buf - preallocated buffer to fill with the image
980 * @param len - length of the allocated buffer
981 *
982 * @return 0 on success, error otherwise
983 */
984 int (*nvm_get_image)(struct qed_dev *cdev,
985 enum qed_nvm_images type, u8 *buf, u16 len);
986
987 /**
988 * @brief set_coalesce - Configure Rx coalesce value in usec
989 *
990 * @param cdev
991 * @param rx_coal - Rx coalesce value in usec
992 * @param tx_coal - Tx coalesce value in usec
993 * @param qid - Queue index
994 * @param sb_id - Status Block Id
995 *
996 * @return 0 on success, error otherwise.
997 */
998 int (*set_coalesce)(struct qed_dev *cdev,
999 u16 rx_coal, u16 tx_coal, void *handle);
1000
1001 /**
1002 * @brief set_led - Configure LED mode
1003 *
1004 * @param cdev
1005 * @param mode - LED mode
1006 *
1007 * @return 0 on success, error otherwise.
1008 */
1009 int (*set_led)(struct qed_dev *cdev,
1010 enum qed_led_mode mode);
1011
1012 /**
1013 * @brief attn_clr_enable - Prevent attentions from being reasserted
1014 *
1015 * @param cdev
1016 * @param clr_enable
1017 */
1018 void (*attn_clr_enable)(struct qed_dev *cdev, bool clr_enable);
1019
1020 /**
1021 * @brief db_recovery_add - add doorbell information to the doorbell
1022 * recovery mechanism.
1023 *
1024 * @param cdev
1025 * @param db_addr - doorbell address
1026 * @param db_data - address of where db_data is stored
1027 * @param db_is_32b - doorbell is 32b pr 64b
1028 * @param db_is_user - doorbell recovery addresses are user or kernel space
1029 */
1030 int (*db_recovery_add)(struct qed_dev *cdev,
1031 void __iomem *db_addr,
1032 void *db_data,
1033 enum qed_db_rec_width db_width,
1034 enum qed_db_rec_space db_space);
1035
1036 /**
1037 * @brief db_recovery_del - remove doorbell information from the doorbell
1038 * recovery mechanism. db_data serves as key (db_addr is not unique).
1039 *
1040 * @param cdev
1041 * @param db_addr - doorbell address
1042 * @param db_data - address where db_data is stored. Serves as key for the
1043 * entry to delete.
1044 */
1045 int (*db_recovery_del)(struct qed_dev *cdev,
1046 void __iomem *db_addr, void *db_data);
1047
1048 /**
1049 * @brief recovery_process - Trigger a recovery process
1050 *
1051 * @param cdev
1052 *
1053 * @return 0 on success, error otherwise.
1054 */
1055 int (*recovery_process)(struct qed_dev *cdev);
1056
1057 /**
1058 * @brief recovery_prolog - Execute the prolog operations of a recovery process
1059 *
1060 * @param cdev
1061 *
1062 * @return 0 on success, error otherwise.
1063 */
1064 int (*recovery_prolog)(struct qed_dev *cdev);
1065
1066 /**
1067 * @brief update_drv_state - API to inform the change in the driver state.
1068 *
1069 * @param cdev
1070 * @param active
1071 *
1072 */
1073 int (*update_drv_state)(struct qed_dev *cdev, bool active);
1074
1075 /**
1076 * @brief update_mac - API to inform the change in the mac address
1077 *
1078 * @param cdev
1079 * @param mac
1080 *
1081 */
1082 int (*update_mac)(struct qed_dev *cdev, u8 *mac);
1083
1084 /**
1085 * @brief update_mtu - API to inform the change in the mtu
1086 *
1087 * @param cdev
1088 * @param mtu
1089 *
1090 */
1091 int (*update_mtu)(struct qed_dev *cdev, u16 mtu);
1092
1093 /**
1094 * @brief update_wol - update of changes in the WoL configuration
1095 *
1096 * @param cdev
1097 * @param enabled - true iff WoL should be enabled.
1098 */
1099 int (*update_wol) (struct qed_dev *cdev, bool enabled);
1100
1101 /**
1102 * @brief read_module_eeprom
1103 *
1104 * @param cdev
1105 * @param buf - buffer
1106 * @param dev_addr - PHY device memory region
1107 * @param offset - offset into eeprom contents to be read
1108 * @param len - buffer length, i.e., max bytes to be read
1109 */
1110 int (*read_module_eeprom)(struct qed_dev *cdev,
1111 char *buf, u8 dev_addr, u32 offset, u32 len);
1112
1113 /**
1114 * @brief get_affin_hwfn_idx
1115 *
1116 * @param cdev
1117 */
1118 u8 (*get_affin_hwfn_idx)(struct qed_dev *cdev);
1119
1120 /**
1121 * @brief read_nvm_cfg - Read NVM config attribute value.
1122 * @param cdev
1123 * @param buf - buffer
1124 * @param cmd - NVM CFG command id
1125 * @param entity_id - Entity id
1126 *
1127 */
1128 int (*read_nvm_cfg)(struct qed_dev *cdev, u8 **buf, u32 cmd,
1129 u32 entity_id);
1130 /**
1131 * @brief read_nvm_cfg - Read NVM config attribute value.
1132 * @param cdev
1133 * @param cmd - NVM CFG command id
1134 *
1135 * @return config id length, 0 on error.
1136 */
1137 int (*read_nvm_cfg_len)(struct qed_dev *cdev, u32 cmd);
1138
1139 /**
1140 * @brief set_grc_config - Configure value for grc config id.
1141 * @param cdev
1142 * @param cfg_id - grc config id
1143 * @param val - grc config value
1144 *
1145 */
1146 int (*set_grc_config)(struct qed_dev *cdev, u32 cfg_id, u32 val);
1147
1148 struct devlink* (*devlink_register)(struct qed_dev *cdev);
1149
1150 void (*devlink_unregister)(struct devlink *devlink);
1151 };
1152
1153 #define MASK_FIELD(_name, _value) \
1154 ((_value) &= (_name ## _MASK))
1155
1156 #define FIELD_VALUE(_name, _value) \
1157 ((_value & _name ## _MASK) << _name ## _SHIFT)
1158
1159 #define SET_FIELD(value, name, flag) \
1160 do { \
1161 (value) &= ~(name ## _MASK << name ## _SHIFT); \
1162 (value) |= (((u64)flag) << (name ## _SHIFT)); \
1163 } while (0)
1164
1165 #define GET_FIELD(value, name) \
1166 (((value) >> (name ## _SHIFT)) & name ## _MASK)
1167
1168 #define GET_MFW_FIELD(name, field) \
1169 (((name) & (field ## _MASK)) >> (field ## _OFFSET))
1170
1171 #define SET_MFW_FIELD(name, field, value) \
1172 do { \
1173 (name) &= ~(field ## _MASK); \
1174 (name) |= (((value) << (field ## _OFFSET)) & (field ## _MASK));\
1175 } while (0)
1176
1177 #define DB_ADDR_SHIFT(addr) ((addr) << DB_PWM_ADDR_OFFSET_SHIFT)
1178
1179 /* Debug print definitions */
1180 #define DP_ERR(cdev, fmt, ...) \
1181 do { \
1182 pr_err("[%s:%d(%s)]" fmt, \
1183 __func__, __LINE__, \
1184 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1185 ## __VA_ARGS__); \
1186 } while (0)
1187
1188 #define DP_NOTICE(cdev, fmt, ...) \
1189 do { \
1190 if (unlikely((cdev)->dp_level <= QED_LEVEL_NOTICE)) { \
1191 pr_notice("[%s:%d(%s)]" fmt, \
1192 __func__, __LINE__, \
1193 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1194 ## __VA_ARGS__); \
1195 \
1196 } \
1197 } while (0)
1198
1199 #define DP_INFO(cdev, fmt, ...) \
1200 do { \
1201 if (unlikely((cdev)->dp_level <= QED_LEVEL_INFO)) { \
1202 pr_notice("[%s:%d(%s)]" fmt, \
1203 __func__, __LINE__, \
1204 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1205 ## __VA_ARGS__); \
1206 } \
1207 } while (0)
1208
1209 #define DP_VERBOSE(cdev, module, fmt, ...) \
1210 do { \
1211 if (unlikely(((cdev)->dp_level <= QED_LEVEL_VERBOSE) && \
1212 ((cdev)->dp_module & module))) { \
1213 pr_notice("[%s:%d(%s)]" fmt, \
1214 __func__, __LINE__, \
1215 DP_NAME(cdev) ? DP_NAME(cdev) : "", \
1216 ## __VA_ARGS__); \
1217 } \
1218 } while (0)
1219
1220 enum DP_LEVEL {
1221 QED_LEVEL_VERBOSE = 0x0,
1222 QED_LEVEL_INFO = 0x1,
1223 QED_LEVEL_NOTICE = 0x2,
1224 QED_LEVEL_ERR = 0x3,
1225 };
1226
1227 #define QED_LOG_LEVEL_SHIFT (30)
1228 #define QED_LOG_VERBOSE_MASK (0x3fffffff)
1229 #define QED_LOG_INFO_MASK (0x40000000)
1230 #define QED_LOG_NOTICE_MASK (0x80000000)
1231
1232 enum DP_MODULE {
1233 QED_MSG_SPQ = 0x10000,
1234 QED_MSG_STATS = 0x20000,
1235 QED_MSG_DCB = 0x40000,
1236 QED_MSG_IOV = 0x80000,
1237 QED_MSG_SP = 0x100000,
1238 QED_MSG_STORAGE = 0x200000,
1239 QED_MSG_CXT = 0x800000,
1240 QED_MSG_LL2 = 0x1000000,
1241 QED_MSG_ILT = 0x2000000,
1242 QED_MSG_RDMA = 0x4000000,
1243 QED_MSG_DEBUG = 0x8000000,
1244 /* to be added...up to 0x8000000 */
1245 };
1246
1247 enum qed_mf_mode {
1248 QED_MF_DEFAULT,
1249 QED_MF_OVLAN,
1250 QED_MF_NPAR,
1251 };
1252
1253 struct qed_eth_stats_common {
1254 u64 no_buff_discards;
1255 u64 packet_too_big_discard;
1256 u64 ttl0_discard;
1257 u64 rx_ucast_bytes;
1258 u64 rx_mcast_bytes;
1259 u64 rx_bcast_bytes;
1260 u64 rx_ucast_pkts;
1261 u64 rx_mcast_pkts;
1262 u64 rx_bcast_pkts;
1263 u64 mftag_filter_discards;
1264 u64 mac_filter_discards;
1265 u64 gft_filter_drop;
1266 u64 tx_ucast_bytes;
1267 u64 tx_mcast_bytes;
1268 u64 tx_bcast_bytes;
1269 u64 tx_ucast_pkts;
1270 u64 tx_mcast_pkts;
1271 u64 tx_bcast_pkts;
1272 u64 tx_err_drop_pkts;
1273 u64 tpa_coalesced_pkts;
1274 u64 tpa_coalesced_events;
1275 u64 tpa_aborts_num;
1276 u64 tpa_not_coalesced_pkts;
1277 u64 tpa_coalesced_bytes;
1278
1279 /* port */
1280 u64 rx_64_byte_packets;
1281 u64 rx_65_to_127_byte_packets;
1282 u64 rx_128_to_255_byte_packets;
1283 u64 rx_256_to_511_byte_packets;
1284 u64 rx_512_to_1023_byte_packets;
1285 u64 rx_1024_to_1518_byte_packets;
1286 u64 rx_crc_errors;
1287 u64 rx_mac_crtl_frames;
1288 u64 rx_pause_frames;
1289 u64 rx_pfc_frames;
1290 u64 rx_align_errors;
1291 u64 rx_carrier_errors;
1292 u64 rx_oversize_packets;
1293 u64 rx_jabbers;
1294 u64 rx_undersize_packets;
1295 u64 rx_fragments;
1296 u64 tx_64_byte_packets;
1297 u64 tx_65_to_127_byte_packets;
1298 u64 tx_128_to_255_byte_packets;
1299 u64 tx_256_to_511_byte_packets;
1300 u64 tx_512_to_1023_byte_packets;
1301 u64 tx_1024_to_1518_byte_packets;
1302 u64 tx_pause_frames;
1303 u64 tx_pfc_frames;
1304 u64 brb_truncates;
1305 u64 brb_discards;
1306 u64 rx_mac_bytes;
1307 u64 rx_mac_uc_packets;
1308 u64 rx_mac_mc_packets;
1309 u64 rx_mac_bc_packets;
1310 u64 rx_mac_frames_ok;
1311 u64 tx_mac_bytes;
1312 u64 tx_mac_uc_packets;
1313 u64 tx_mac_mc_packets;
1314 u64 tx_mac_bc_packets;
1315 u64 tx_mac_ctrl_frames;
1316 u64 link_change_count;
1317 };
1318
1319 struct qed_eth_stats_bb {
1320 u64 rx_1519_to_1522_byte_packets;
1321 u64 rx_1519_to_2047_byte_packets;
1322 u64 rx_2048_to_4095_byte_packets;
1323 u64 rx_4096_to_9216_byte_packets;
1324 u64 rx_9217_to_16383_byte_packets;
1325 u64 tx_1519_to_2047_byte_packets;
1326 u64 tx_2048_to_4095_byte_packets;
1327 u64 tx_4096_to_9216_byte_packets;
1328 u64 tx_9217_to_16383_byte_packets;
1329 u64 tx_lpi_entry_count;
1330 u64 tx_total_collisions;
1331 };
1332
1333 struct qed_eth_stats_ah {
1334 u64 rx_1519_to_max_byte_packets;
1335 u64 tx_1519_to_max_byte_packets;
1336 };
1337
1338 struct qed_eth_stats {
1339 struct qed_eth_stats_common common;
1340
1341 union {
1342 struct qed_eth_stats_bb bb;
1343 struct qed_eth_stats_ah ah;
1344 };
1345 };
1346
1347 #define QED_SB_IDX 0x0002
1348
1349 #define RX_PI 0
1350 #define TX_PI(tc) (RX_PI + 1 + tc)
1351
1352 struct qed_sb_cnt_info {
1353 /* Original, current, and free SBs for PF */
1354 int orig;
1355 int cnt;
1356 int free_cnt;
1357
1358 /* Original, current and free SBS for child VFs */
1359 int iov_orig;
1360 int iov_cnt;
1361 int free_cnt_iov;
1362 };
1363
qed_sb_update_sb_idx(struct qed_sb_info * sb_info)1364 static inline u16 qed_sb_update_sb_idx(struct qed_sb_info *sb_info)
1365 {
1366 u32 prod = 0;
1367 u16 rc = 0;
1368
1369 prod = le32_to_cpu(sb_info->sb_virt->prod_index) &
1370 STATUS_BLOCK_E4_PROD_INDEX_MASK;
1371 if (sb_info->sb_ack != prod) {
1372 sb_info->sb_ack = prod;
1373 rc |= QED_SB_IDX;
1374 }
1375
1376 /* Let SB update */
1377 return rc;
1378 }
1379
1380 /**
1381 *
1382 * @brief This function creates an update command for interrupts that is
1383 * written to the IGU.
1384 *
1385 * @param sb_info - This is the structure allocated and
1386 * initialized per status block. Assumption is
1387 * that it was initialized using qed_sb_init
1388 * @param int_cmd - Enable/Disable/Nop
1389 * @param upd_flg - whether igu consumer should be
1390 * updated.
1391 *
1392 * @return inline void
1393 */
qed_sb_ack(struct qed_sb_info * sb_info,enum igu_int_cmd int_cmd,u8 upd_flg)1394 static inline void qed_sb_ack(struct qed_sb_info *sb_info,
1395 enum igu_int_cmd int_cmd,
1396 u8 upd_flg)
1397 {
1398 u32 igu_ack;
1399
1400 igu_ack = ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
1401 (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
1402 (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
1403 (IGU_SEG_ACCESS_REG <<
1404 IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
1405
1406 DIRECT_REG_WR(sb_info->igu_addr, igu_ack);
1407
1408 /* Both segments (interrupts & acks) are written to same place address;
1409 * Need to guarantee all commands will be received (in-order) by HW.
1410 */
1411 barrier();
1412 }
1413
__internal_ram_wr(void * p_hwfn,void __iomem * addr,int size,u32 * data)1414 static inline void __internal_ram_wr(void *p_hwfn,
1415 void __iomem *addr,
1416 int size,
1417 u32 *data)
1418
1419 {
1420 unsigned int i;
1421
1422 for (i = 0; i < size / sizeof(*data); i++)
1423 DIRECT_REG_WR(&((u32 __iomem *)addr)[i], data[i]);
1424 }
1425
internal_ram_wr(void __iomem * addr,int size,u32 * data)1426 static inline void internal_ram_wr(void __iomem *addr,
1427 int size,
1428 u32 *data)
1429 {
1430 __internal_ram_wr(NULL, addr, size, data);
1431 }
1432
1433 enum qed_rss_caps {
1434 QED_RSS_IPV4 = 0x1,
1435 QED_RSS_IPV6 = 0x2,
1436 QED_RSS_IPV4_TCP = 0x4,
1437 QED_RSS_IPV6_TCP = 0x8,
1438 QED_RSS_IPV4_UDP = 0x10,
1439 QED_RSS_IPV6_UDP = 0x20,
1440 };
1441
1442 #define QED_RSS_IND_TABLE_SIZE 128
1443 #define QED_RSS_KEY_SIZE 10 /* size in 32b chunks */
1444 #endif
1445
