1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 #ifndef __DAL_DDC_SERVICE_TYPES_H__ 26 #define __DAL_DDC_SERVICE_TYPES_H__ 27 28 #define DP_BRANCH_DEVICE_ID_1 0x0010FA 29 #define DP_BRANCH_DEVICE_ID_2 0x0022B9 30 #define DP_BRANCH_DEVICE_ID_3 0x00001A 31 #define DP_BRANCH_DEVICE_ID_4 0x0080e1 32 33 enum ddc_result { 34 DDC_RESULT_UNKNOWN = 0, 35 DDC_RESULT_SUCESSFULL, 36 DDC_RESULT_FAILED_CHANNEL_BUSY, 37 DDC_RESULT_FAILED_TIMEOUT, 38 DDC_RESULT_FAILED_PROTOCOL_ERROR, 39 DDC_RESULT_FAILED_NACK, 40 DDC_RESULT_FAILED_INCOMPLETE, 41 DDC_RESULT_FAILED_OPERATION, 42 DDC_RESULT_FAILED_INVALID_OPERATION, 43 DDC_RESULT_FAILED_BUFFER_OVERFLOW, 44 DDC_RESULT_FAILED_HPD_DISCON 45 }; 46 47 enum ddc_service_type { 48 DDC_SERVICE_TYPE_CONNECTOR, 49 DDC_SERVICE_TYPE_DISPLAY_PORT_MST, 50 }; 51 52 /** 53 * display sink capability 54 */ 55 struct display_sink_capability { 56 /* dongle type (DP converter, CV smart dongle) */ 57 enum display_dongle_type dongle_type; 58 59 /********************************************************** 60 capabilities going INTO SINK DEVICE (stream capabilities) 61 **********************************************************/ 62 /* Dongle's downstream count. */ 63 uint32_t downstrm_sink_count; 64 /* Is dongle's downstream count info field (downstrm_sink_count) 65 * valid. */ 66 bool downstrm_sink_count_valid; 67 68 /* Maximum additional audio delay in microsecond (us) */ 69 uint32_t additional_audio_delay; 70 /* Audio latency value in microsecond (us) */ 71 uint32_t audio_latency; 72 /* Interlace video latency value in microsecond (us) */ 73 uint32_t video_latency_interlace; 74 /* Progressive video latency value in microsecond (us) */ 75 uint32_t video_latency_progressive; 76 /* Dongle caps: Maximum pixel clock supported over dongle for HDMI */ 77 uint32_t max_hdmi_pixel_clock; 78 /* Dongle caps: Maximum deep color supported over dongle for HDMI */ 79 enum dc_color_depth max_hdmi_deep_color; 80 81 /************************************************************ 82 capabilities going OUT OF SOURCE DEVICE (link capabilities) 83 ************************************************************/ 84 /* support for Spread Spectrum(SS) */ 85 bool ss_supported; 86 /* DP link settings (laneCount, linkRate, Spread) */ 87 uint32_t dp_link_lane_count; 88 uint32_t dp_link_rate; 89 uint32_t dp_link_spead; 90 91 /* If dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER, 92 indicates 'Frame Sequential-to-lllFrame Pack' conversion capability.*/ 93 bool is_dp_hdmi_s3d_converter; 94 /* to check if we have queried the display capability 95 * for eDP panel already. */ 96 bool is_edp_sink_cap_valid; 97 98 enum ddc_transaction_type transaction_type; 99 enum signal_type signal; 100 }; 101 102 struct av_sync_data { 103 uint8_t av_granularity;/* DPCD 00023h */ 104 uint8_t aud_dec_lat1;/* DPCD 00024h */ 105 uint8_t aud_dec_lat2;/* DPCD 00025h */ 106 uint8_t aud_pp_lat1;/* DPCD 00026h */ 107 uint8_t aud_pp_lat2;/* DPCD 00027h */ 108 uint8_t vid_inter_lat;/* DPCD 00028h */ 109 uint8_t vid_prog_lat;/* DPCD 00029h */ 110 uint8_t aud_del_ins1;/* DPCD 0002Bh */ 111 uint8_t aud_del_ins2;/* DPCD 0002Ch */ 112 uint8_t aud_del_ins3;/* DPCD 0002Dh */ 113 }; 114 115 /*Travis*/ 116 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_2[] = "sivarT"; 117 /*Nutmeg*/ 118 static const uint8_t DP_VGA_LVDS_CONVERTER_ID_3[] = "dnomlA"; 119 /*DP to Dual link DVI converter*/ 120 static const uint8_t DP_DVI_CONVERTER_ID_4[] = "m2DVIa"; 121 122 #endif /* __DAL_DDC_SERVICE_TYPES_H__ */ 123
