1 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
2 /* Copyright 2014-2016 Freescale Semiconductor Inc.
3 * Copyright 2016-2022 NXP
4 */
5
6 #ifndef __DPAA2_ETH_H
7 #define __DPAA2_ETH_H
8
9 #include <linux/dcbnl.h>
10 #include <linux/netdevice.h>
11 #include <linux/if_vlan.h>
12 #include <linux/fsl/mc.h>
13 #include <linux/net_tstamp.h>
14 #include <net/devlink.h>
15 #include <net/xdp.h>
16
17 #include <soc/fsl/dpaa2-io.h>
18 #include <soc/fsl/dpaa2-fd.h>
19 #include "dpni.h"
20 #include "dpni-cmd.h"
21
22 #include "dpaa2-eth-trace.h"
23 #include "dpaa2-eth-debugfs.h"
24 #include "dpaa2-mac.h"
25
26 #define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
27
28 #define DPAA2_ETH_STORE_SIZE 16
29
30 /* Maximum number of scatter-gather entries in an ingress frame,
31 * considering the maximum receive frame size is 64K
32 */
33 #define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
34
35 /* Maximum acceptable MTU value. It is in direct relation with the hardware
36 * enforced Max Frame Length (currently 10k).
37 */
38 #define DPAA2_ETH_MFL (10 * 1024)
39 #define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
40 /* Convert L3 MTU to L2 MFL */
41 #define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
42
43 /* Set the taildrop threshold (in bytes) to allow the enqueue of a large
44 * enough number of jumbo frames in the Rx queues (length of the current
45 * frame is not taken into account when making the taildrop decision)
46 */
47 #define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024)
48
49 /* Maximum burst size value for Tx shaping */
50 #define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF
51
52 /* Maximum number of Tx confirmation frames to be processed
53 * in a single NAPI call
54 */
55 #define DPAA2_ETH_TXCONF_PER_NAPI 256
56
57 /* Maximum number of Tx frames to be processed in a single NAPI
58 * call when AF_XDP is running. Bind it to DPAA2_ETH_TXCONF_PER_NAPI
59 * to maximize the throughput.
60 */
61 #define DPAA2_ETH_TX_ZC_PER_NAPI DPAA2_ETH_TXCONF_PER_NAPI
62
63 /* Buffer qouta per channel. We want to keep in check number of ingress frames
64 * in flight: for small sized frames, congestion group taildrop may kick in
65 * first; for large sizes, Rx FQ taildrop threshold will ensure only a
66 * reasonable number of frames will be pending at any given time.
67 * Ingress frame drop due to buffer pool depletion should be a corner case only
68 */
69 #define DPAA2_ETH_NUM_BUFS 1280
70 #define DPAA2_ETH_REFILL_THRESH \
71 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
72
73 /* Congestion group taildrop threshold: number of frames allowed to accumulate
74 * at any moment in a group of Rx queues belonging to the same traffic class.
75 * Choose value such that we don't risk depleting the buffer pool before the
76 * taildrop kicks in
77 */
78 #define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \
79 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv))
80
81 /* Congestion group notification threshold: when this many frames accumulate
82 * on the Rx queues belonging to the same TC, the MAC is instructed to send
83 * PFC frames for that TC.
84 * When number of pending frames drops below exit threshold transmission of
85 * PFC frames is stopped.
86 */
87 #define DPAA2_ETH_CN_THRESH_ENTRY(priv) \
88 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2)
89 #define DPAA2_ETH_CN_THRESH_EXIT(priv) \
90 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4)
91
92 /* Maximum number of buffers that can be acquired/released through a single
93 * QBMan command
94 */
95 #define DPAA2_ETH_BUFS_PER_CMD 7
96
97 /* Hardware requires alignment for ingress/egress buffer addresses */
98 #define DPAA2_ETH_TX_BUF_ALIGN 64
99
100 #define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE
101 #define DPAA2_ETH_RX_BUF_TAILROOM \
102 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
103 #define DPAA2_ETH_RX_BUF_SIZE \
104 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
105
106 /* Hardware annotation area in RX/TX buffers */
107 #define DPAA2_ETH_RX_HWA_SIZE 64
108 #define DPAA2_ETH_TX_HWA_SIZE 128
109
110 /* PTP nominal frequency 1GHz */
111 #define DPAA2_PTP_CLK_PERIOD_NS 1
112
113 /* Due to a limitation in WRIOP 1.0.0, the RX buffer data must be aligned
114 * to 256B. For newer revisions, the requirement is only for 64B alignment
115 */
116 #define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
117 #define DPAA2_ETH_RX_BUF_ALIGN 64
118
119 /* The firmware allows assigning multiple buffer pools to a single DPNI -
120 * maximum 8 DPBP objects. By default, only the first DPBP (idx 0) is used for
121 * all queues. Thus, when enabling AF_XDP we must accommodate up to 9 DPBPs
122 * object: the default and 8 other distinct buffer pools, one for each queue.
123 */
124 #define DPAA2_ETH_DEFAULT_BP_IDX 0
125 #define DPAA2_ETH_MAX_BPS 9
126
127 /* We are accommodating a skb backpointer and some S/G info
128 * in the frame's software annotation. The hardware
129 * options are either 0 or 64, so we choose the latter.
130 */
131 #define DPAA2_ETH_SWA_SIZE 64
132
133 /* We store different information in the software annotation area of a Tx frame
134 * based on what type of frame it is
135 */
136 enum dpaa2_eth_swa_type {
137 DPAA2_ETH_SWA_SINGLE,
138 DPAA2_ETH_SWA_SG,
139 DPAA2_ETH_SWA_XDP,
140 DPAA2_ETH_SWA_XSK,
141 DPAA2_ETH_SWA_SW_TSO,
142 };
143
144 /* Must keep this struct smaller than DPAA2_ETH_SWA_SIZE */
145 struct dpaa2_eth_swa {
146 enum dpaa2_eth_swa_type type;
147 union {
148 struct {
149 struct sk_buff *skb;
150 int sgt_size;
151 } single;
152 struct {
153 struct sk_buff *skb;
154 struct scatterlist *scl;
155 int num_sg;
156 int sgt_size;
157 } sg;
158 struct {
159 int dma_size;
160 struct xdp_frame *xdpf;
161 } xdp;
162 struct {
163 struct xdp_buff *xdp_buff;
164 int sgt_size;
165 } xsk;
166 struct {
167 struct sk_buff *skb;
168 int num_sg;
169 int sgt_size;
170 int is_last_fd;
171 } tso;
172 };
173 };
174
175 /* Annotation valid bits in FD FRC */
176 #define DPAA2_FD_FRC_FASV 0x8000
177 #define DPAA2_FD_FRC_FAEADV 0x4000
178 #define DPAA2_FD_FRC_FAPRV 0x2000
179 #define DPAA2_FD_FRC_FAIADV 0x1000
180 #define DPAA2_FD_FRC_FASWOV 0x0800
181 #define DPAA2_FD_FRC_FAICFDV 0x0400
182
183 /* Error bits in FD CTRL */
184 #define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
185 #define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
186 FD_CTRL_SBE | \
187 FD_CTRL_FSE | \
188 FD_CTRL_FAERR)
189
190 /* Annotation bits in FD CTRL */
191 #define DPAA2_FD_CTRL_ASAL 0x00020000 /* ASAL = 128B */
192
193 /* Frame annotation status */
194 struct dpaa2_fas {
195 u8 reserved;
196 u8 ppid;
197 __le16 ifpid;
198 __le32 status;
199 };
200
201 /* Frame annotation status word is located in the first 8 bytes
202 * of the buffer's hardware annoatation area
203 */
204 #define DPAA2_FAS_OFFSET 0
205 #define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
206
207 /* Timestamp is located in the next 8 bytes of the buffer's
208 * hardware annotation area
209 */
210 #define DPAA2_TS_OFFSET 0x8
211
212 /* Frame annotation parse results */
213 struct dpaa2_fapr {
214 /* 64-bit word 1 */
215 __le32 faf_lo;
216 __le16 faf_ext;
217 __le16 nxt_hdr;
218 /* 64-bit word 2 */
219 __le64 faf_hi;
220 /* 64-bit word 3 */
221 u8 last_ethertype_offset;
222 u8 vlan_tci_offset_n;
223 u8 vlan_tci_offset_1;
224 u8 llc_snap_offset;
225 u8 eth_offset;
226 u8 ip1_pid_offset;
227 u8 shim_offset_2;
228 u8 shim_offset_1;
229 /* 64-bit word 4 */
230 u8 l5_offset;
231 u8 l4_offset;
232 u8 gre_offset;
233 u8 l3_offset_n;
234 u8 l3_offset_1;
235 u8 mpls_offset_n;
236 u8 mpls_offset_1;
237 u8 pppoe_offset;
238 /* 64-bit word 5 */
239 __le16 running_sum;
240 __le16 gross_running_sum;
241 u8 ipv6_frag_offset;
242 u8 nxt_hdr_offset;
243 u8 routing_hdr_offset_2;
244 u8 routing_hdr_offset_1;
245 /* 64-bit word 6 */
246 u8 reserved[5]; /* Soft-parsing context */
247 u8 ip_proto_offset_n;
248 u8 nxt_hdr_frag_offset;
249 u8 parse_error_code;
250 };
251
252 #define DPAA2_FAPR_OFFSET 0x10
253 #define DPAA2_FAPR_SIZE sizeof((struct dpaa2_fapr))
254
255 /* Frame annotation egress action descriptor */
256 #define DPAA2_FAEAD_OFFSET 0x58
257
258 struct dpaa2_faead {
259 __le32 conf_fqid;
260 __le32 ctrl;
261 };
262
263 #define DPAA2_FAEAD_A2V 0x20000000
264 #define DPAA2_FAEAD_A4V 0x08000000
265 #define DPAA2_FAEAD_UPDV 0x00001000
266 #define DPAA2_FAEAD_EBDDV 0x00002000
267 #define DPAA2_FAEAD_UPD 0x00000010
268
269 struct ptp_tstamp {
270 u16 sec_msb;
271 u32 sec_lsb;
272 u32 nsec;
273 };
274
ns_to_ptp_tstamp(struct ptp_tstamp * tstamp,u64 ns)275 static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns)
276 {
277 u64 sec, nsec;
278
279 sec = ns;
280 nsec = do_div(sec, 1000000000);
281
282 tstamp->sec_lsb = sec & 0xFFFFFFFF;
283 tstamp->sec_msb = (sec >> 32) & 0xFFFF;
284 tstamp->nsec = nsec;
285 }
286
287 /* Accessors for the hardware annotation fields that we use */
dpaa2_get_hwa(void * buf_addr,bool swa)288 static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
289 {
290 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
291 }
292
dpaa2_get_fas(void * buf_addr,bool swa)293 static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
294 {
295 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
296 }
297
dpaa2_get_ts(void * buf_addr,bool swa)298 static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
299 {
300 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
301 }
302
dpaa2_get_fapr(void * buf_addr,bool swa)303 static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa)
304 {
305 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET;
306 }
307
dpaa2_get_faead(void * buf_addr,bool swa)308 static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
309 {
310 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
311 }
312
313 /* Error and status bits in the frame annotation status word */
314 /* Debug frame, otherwise supposed to be discarded */
315 #define DPAA2_FAS_DISC 0x80000000
316 /* MACSEC frame */
317 #define DPAA2_FAS_MS 0x40000000
318 #define DPAA2_FAS_PTP 0x08000000
319 /* Ethernet multicast frame */
320 #define DPAA2_FAS_MC 0x04000000
321 /* Ethernet broadcast frame */
322 #define DPAA2_FAS_BC 0x02000000
323 #define DPAA2_FAS_KSE 0x00040000
324 #define DPAA2_FAS_EOFHE 0x00020000
325 #define DPAA2_FAS_MNLE 0x00010000
326 #define DPAA2_FAS_TIDE 0x00008000
327 #define DPAA2_FAS_PIEE 0x00004000
328 /* Frame length error */
329 #define DPAA2_FAS_FLE 0x00002000
330 /* Frame physical error */
331 #define DPAA2_FAS_FPE 0x00001000
332 #define DPAA2_FAS_PTE 0x00000080
333 #define DPAA2_FAS_ISP 0x00000040
334 #define DPAA2_FAS_PHE 0x00000020
335 #define DPAA2_FAS_BLE 0x00000010
336 /* L3 csum validation performed */
337 #define DPAA2_FAS_L3CV 0x00000008
338 /* L3 csum error */
339 #define DPAA2_FAS_L3CE 0x00000004
340 /* L4 csum validation performed */
341 #define DPAA2_FAS_L4CV 0x00000002
342 /* L4 csum error */
343 #define DPAA2_FAS_L4CE 0x00000001
344 /* Possible errors on the ingress path */
345 #define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
346 DPAA2_FAS_EOFHE | \
347 DPAA2_FAS_MNLE | \
348 DPAA2_FAS_TIDE | \
349 DPAA2_FAS_PIEE | \
350 DPAA2_FAS_FLE | \
351 DPAA2_FAS_FPE | \
352 DPAA2_FAS_PTE | \
353 DPAA2_FAS_ISP | \
354 DPAA2_FAS_PHE | \
355 DPAA2_FAS_BLE | \
356 DPAA2_FAS_L3CE | \
357 DPAA2_FAS_L4CE)
358
359 /* Time in milliseconds between link state updates */
360 #define DPAA2_ETH_LINK_STATE_REFRESH 1000
361
362 /* Number of times to retry a frame enqueue before giving up.
363 * Value determined empirically, in order to minimize the number
364 * of frames dropped on Tx
365 */
366 #define DPAA2_ETH_ENQUEUE_RETRIES 10
367
368 /* Number of times to retry DPIO portal operations while waiting
369 * for portal to finish executing current command and become
370 * available. We want to avoid being stuck in a while loop in case
371 * hardware becomes unresponsive, but not give up too easily if
372 * the portal really is busy for valid reasons
373 */
374 #define DPAA2_ETH_SWP_BUSY_RETRIES 1000
375
376 /* Driver statistics, other than those in struct rtnl_link_stats64.
377 * These are usually collected per-CPU and aggregated by ethtool.
378 */
379 struct dpaa2_eth_drv_stats {
380 __u64 tx_conf_frames;
381 __u64 tx_conf_bytes;
382 __u64 tx_sg_frames;
383 __u64 tx_sg_bytes;
384 __u64 tx_tso_frames;
385 __u64 tx_tso_bytes;
386 __u64 rx_sg_frames;
387 __u64 rx_sg_bytes;
388 /* Linear skbs sent as a S/G FD due to insufficient headroom */
389 __u64 tx_converted_sg_frames;
390 __u64 tx_converted_sg_bytes;
391 /* Enqueues retried due to portal busy */
392 __u64 tx_portal_busy;
393 };
394
395 /* Per-FQ statistics */
396 struct dpaa2_eth_fq_stats {
397 /* Number of frames received on this queue */
398 __u64 frames;
399 };
400
401 /* Per-channel statistics */
402 struct dpaa2_eth_ch_stats {
403 /* Volatile dequeues retried due to portal busy */
404 __u64 dequeue_portal_busy;
405 /* Pull errors */
406 __u64 pull_err;
407 /* Number of CDANs; useful to estimate avg NAPI len */
408 __u64 cdan;
409 /* XDP counters */
410 __u64 xdp_drop;
411 __u64 xdp_tx;
412 __u64 xdp_tx_err;
413 __u64 xdp_redirect;
414 /* Must be last, does not show up in ethtool stats */
415 __u64 frames;
416 __u64 frames_per_cdan;
417 __u64 bytes_per_cdan;
418 };
419
420 #define DPAA2_ETH_CH_STATS 7
421
422 /* Maximum number of queues associated with a DPNI */
423 #define DPAA2_ETH_MAX_TCS 8
424 #define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16
425 #define DPAA2_ETH_MAX_RX_QUEUES \
426 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
427 #define DPAA2_ETH_MAX_TX_QUEUES 16
428 #define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
429 #define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
430 DPAA2_ETH_MAX_TX_QUEUES + \
431 DPAA2_ETH_MAX_RX_ERR_QUEUES)
432 #define DPAA2_ETH_MAX_NETDEV_QUEUES \
433 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
434
435 #define DPAA2_ETH_MAX_DPCONS 16
436
437 enum dpaa2_eth_fq_type {
438 DPAA2_RX_FQ = 0,
439 DPAA2_TX_CONF_FQ,
440 DPAA2_RX_ERR_FQ
441 };
442
443 struct dpaa2_eth_priv;
444 struct dpaa2_eth_channel;
445 struct dpaa2_eth_fq;
446
447 struct dpaa2_eth_xdp_fds {
448 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE];
449 ssize_t num;
450 };
451
452 typedef void dpaa2_eth_consume_cb_t(struct dpaa2_eth_priv *priv,
453 struct dpaa2_eth_channel *ch,
454 const struct dpaa2_fd *fd,
455 struct dpaa2_eth_fq *fq);
456
457 struct dpaa2_eth_fq {
458 u32 fqid;
459 u32 tx_qdbin;
460 u32 tx_fqid[DPAA2_ETH_MAX_TCS];
461 u16 flowid;
462 u8 tc;
463 int target_cpu;
464 u32 dq_frames;
465 u32 dq_bytes;
466 struct dpaa2_eth_channel *channel;
467 enum dpaa2_eth_fq_type type;
468
469 dpaa2_eth_consume_cb_t *consume;
470 struct dpaa2_eth_fq_stats stats;
471
472 struct dpaa2_eth_xdp_fds xdp_redirect_fds;
473 struct dpaa2_eth_xdp_fds xdp_tx_fds;
474 };
475
476 struct dpaa2_eth_ch_xdp {
477 struct bpf_prog *prog;
478 unsigned int res;
479 };
480
481 struct dpaa2_eth_bp {
482 struct fsl_mc_device *dev;
483 int bpid;
484 };
485
486 struct dpaa2_eth_channel {
487 struct dpaa2_io_notification_ctx nctx;
488 struct fsl_mc_device *dpcon;
489 int dpcon_id;
490 int ch_id;
491 struct napi_struct napi;
492 struct dpaa2_io *dpio;
493 struct dpaa2_io_store *store;
494 struct dpaa2_eth_priv *priv;
495 int buf_count;
496 struct dpaa2_eth_ch_stats stats;
497 struct dpaa2_eth_ch_xdp xdp;
498 struct xdp_rxq_info xdp_rxq;
499 struct list_head *rx_list;
500
501 /* Buffers to be recycled back in the buffer pool */
502 u64 recycled_bufs[DPAA2_ETH_BUFS_PER_CMD];
503 int recycled_bufs_cnt;
504
505 bool xsk_zc;
506 int xsk_tx_pkts_sent;
507 struct xsk_buff_pool *xsk_pool;
508 struct dpaa2_eth_bp *bp;
509 };
510
511 struct dpaa2_eth_dist_fields {
512 u64 rxnfc_field;
513 enum net_prot cls_prot;
514 int cls_field;
515 int size;
516 u64 id;
517 };
518
519 struct dpaa2_eth_cls_rule {
520 struct ethtool_rx_flow_spec fs;
521 u8 in_use;
522 };
523
524 #define DPAA2_ETH_SGT_CACHE_SIZE 256
525 struct dpaa2_eth_sgt_cache {
526 void *buf[DPAA2_ETH_SGT_CACHE_SIZE];
527 u16 count;
528 };
529
530 struct dpaa2_eth_trap_item {
531 void *trap_ctx;
532 };
533
534 struct dpaa2_eth_trap_data {
535 struct dpaa2_eth_trap_item *trap_items_arr;
536 struct dpaa2_eth_priv *priv;
537 };
538
539 #define DPAA2_ETH_SG_ENTRIES_MAX (PAGE_SIZE / sizeof(struct scatterlist))
540
541 #define DPAA2_ETH_DEFAULT_COPYBREAK 512
542
543 #define DPAA2_ETH_ENQUEUE_MAX_FDS 256
544 struct dpaa2_eth_fds {
545 struct dpaa2_fd array[DPAA2_ETH_ENQUEUE_MAX_FDS];
546 };
547
548 /* Driver private data */
549 struct dpaa2_eth_priv {
550 struct net_device *net_dev;
551
552 u8 num_fqs;
553 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
554 int (*enqueue)(struct dpaa2_eth_priv *priv,
555 struct dpaa2_eth_fq *fq,
556 struct dpaa2_fd *fd, u8 prio,
557 u32 num_frames,
558 int *frames_enqueued);
559
560 u8 num_channels;
561 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
562 struct dpaa2_eth_sgt_cache __percpu *sgt_cache;
563 unsigned long features;
564 struct dpni_attr dpni_attrs;
565 u16 dpni_ver_major;
566 u16 dpni_ver_minor;
567 u16 tx_data_offset;
568 void __iomem *onestep_reg_base;
569 u8 ptp_correction_off;
570 void (*dpaa2_set_onestep_params_cb)(struct dpaa2_eth_priv *priv,
571 u32 offset, u8 udp);
572 u16 rx_buf_size;
573 struct iommu_domain *iommu_domain;
574
575 enum hwtstamp_tx_types tx_tstamp_type; /* Tx timestamping type */
576 bool rx_tstamp; /* Rx timestamping enabled */
577
578 /* Buffer pool management */
579 struct dpaa2_eth_bp *bp[DPAA2_ETH_MAX_BPS];
580 int num_bps;
581
582 u16 tx_qdid;
583 struct fsl_mc_io *mc_io;
584 /* Cores which have an affine DPIO/DPCON.
585 * This is the cpu set on which Rx and Tx conf frames are processed
586 */
587 struct cpumask dpio_cpumask;
588
589 /* Standard statistics */
590 struct rtnl_link_stats64 __percpu *percpu_stats;
591 /* Extra stats, in addition to the ones known by the kernel */
592 struct dpaa2_eth_drv_stats __percpu *percpu_extras;
593
594 u16 mc_token;
595 u8 rx_fqtd_enabled;
596 u8 rx_cgtd_enabled;
597
598 struct dpni_link_state link_state;
599 bool do_link_poll;
600 struct task_struct *poll_thread;
601
602 /* enabled ethtool hashing bits */
603 u64 rx_hash_fields;
604 u64 rx_cls_fields;
605 struct dpaa2_eth_cls_rule *cls_rules;
606 u8 rx_cls_enabled;
607 u8 vlan_cls_enabled;
608 u8 pfc_enabled;
609 #ifdef CONFIG_FSL_DPAA2_ETH_DCB
610 u8 dcbx_mode;
611 struct ieee_pfc pfc;
612 #endif
613 struct bpf_prog *xdp_prog;
614 #ifdef CONFIG_DEBUG_FS
615 struct dpaa2_debugfs dbg;
616 #endif
617
618 struct dpaa2_mac *mac;
619 /* Serializes changes to priv->mac */
620 struct mutex mac_lock;
621 struct workqueue_struct *dpaa2_ptp_wq;
622 struct work_struct tx_onestep_tstamp;
623 struct sk_buff_head tx_skbs;
624 /* The one-step timestamping configuration on hardware
625 * registers could only be done when no one-step
626 * timestamping frames are in flight. So we use a mutex
627 * lock here to make sure the lock is released by last
628 * one-step timestamping packet through TX confirmation
629 * queue before transmit current packet.
630 */
631 struct mutex onestep_tstamp_lock;
632 struct devlink *devlink;
633 struct dpaa2_eth_trap_data *trap_data;
634 struct devlink_port devlink_port;
635
636 u32 rx_copybreak;
637
638 struct dpaa2_eth_fds __percpu *fd;
639 };
640
641 struct dpaa2_eth_devlink_priv {
642 struct dpaa2_eth_priv *dpaa2_priv;
643 };
644
645 #define TX_TSTAMP 0x1
646 #define TX_TSTAMP_ONESTEP_SYNC 0x2
647
648 #define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
649 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
650 | RXH_L4_B_2_3)
651
652 /* default Rx hash options, set during probing */
653 #define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
654 RXH_L4_B_0_1 | RXH_L4_B_2_3)
655
656 #define dpaa2_eth_hash_enabled(priv) \
657 ((priv)->dpni_attrs.num_queues > 1)
658
659 /* Required by struct dpni_rx_tc_dist_cfg::key_cfg_iova */
660 #define DPAA2_CLASSIFIER_DMA_SIZE 256
661
662 extern const struct ethtool_ops dpaa2_ethtool_ops;
663 extern int dpaa2_phc_index;
664 extern struct ptp_qoriq *dpaa2_ptp;
665
dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv * priv,u16 ver_major,u16 ver_minor)666 static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
667 u16 ver_major, u16 ver_minor)
668 {
669 if (priv->dpni_ver_major == ver_major)
670 return priv->dpni_ver_minor - ver_minor;
671 return priv->dpni_ver_major - ver_major;
672 }
673
674 /* Minimum firmware version that supports a more flexible API
675 * for configuring the Rx flow hash key
676 */
677 #define DPNI_RX_DIST_KEY_VER_MAJOR 7
678 #define DPNI_RX_DIST_KEY_VER_MINOR 5
679
680 #define dpaa2_eth_has_legacy_dist(priv) \
681 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
682 DPNI_RX_DIST_KEY_VER_MINOR) < 0)
683
684 #define dpaa2_eth_fs_enabled(priv) \
685 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
686
687 #define dpaa2_eth_fs_mask_enabled(priv) \
688 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
689
690 #define dpaa2_eth_fs_count(priv) \
691 ((priv)->dpni_attrs.fs_entries)
692
693 #define dpaa2_eth_tc_count(priv) \
694 ((priv)->dpni_attrs.num_tcs)
695
696 /* We have exactly one {Rx, Tx conf} queue per channel */
697 #define dpaa2_eth_queue_count(priv) \
698 ((priv)->num_channels)
699
700 enum dpaa2_eth_rx_dist {
701 DPAA2_ETH_RX_DIST_HASH,
702 DPAA2_ETH_RX_DIST_CLS
703 };
704
705 /* Unique IDs for the supported Rx classification header fields */
706 #define DPAA2_ETH_DIST_ETHDST BIT(0)
707 #define DPAA2_ETH_DIST_ETHSRC BIT(1)
708 #define DPAA2_ETH_DIST_ETHTYPE BIT(2)
709 #define DPAA2_ETH_DIST_VLAN BIT(3)
710 #define DPAA2_ETH_DIST_IPSRC BIT(4)
711 #define DPAA2_ETH_DIST_IPDST BIT(5)
712 #define DPAA2_ETH_DIST_IPPROTO BIT(6)
713 #define DPAA2_ETH_DIST_L4SRC BIT(7)
714 #define DPAA2_ETH_DIST_L4DST BIT(8)
715 #define DPAA2_ETH_DIST_ALL (~0ULL)
716
717 #define DPNI_PTP_ONESTEP_VER_MAJOR 8
718 #define DPNI_PTP_ONESTEP_VER_MINOR 2
719 #define DPAA2_ETH_FEATURE_ONESTEP_CFG_DIRECT BIT(0)
720 #define DPAA2_PTP_SINGLE_STEP_ENABLE BIT(31)
721 #define DPAA2_PTP_SINGLE_STEP_CH BIT(7)
722 #define DPAA2_PTP_SINGLE_CORRECTION_OFF(v) ((v) << 8)
723
724 #define DPNI_PAUSE_VER_MAJOR 7
725 #define DPNI_PAUSE_VER_MINOR 13
726 #define dpaa2_eth_has_pause_support(priv) \
727 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \
728 DPNI_PAUSE_VER_MINOR) >= 0)
729
dpaa2_eth_tx_pause_enabled(u64 link_options)730 static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options)
731 {
732 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^
733 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE);
734 }
735
dpaa2_eth_rx_pause_enabled(u64 link_options)736 static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)
737 {
738 return !!(link_options & DPNI_LINK_OPT_PAUSE);
739 }
740
dpaa2_eth_needed_headroom(struct sk_buff * skb)741 static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)
742 {
743 unsigned int headroom = DPAA2_ETH_SWA_SIZE;
744
745 /* If we don't have an skb (e.g. XDP buffer), we only need space for
746 * the software annotation area
747 */
748 if (!skb)
749 return headroom;
750
751 /* For non-linear skbs we have no headroom requirement, as we build a
752 * SG frame with a newly allocated SGT buffer
753 */
754 if (skb_is_nonlinear(skb))
755 return 0;
756
757 /* If we have Tx timestamping, need 128B hardware annotation */
758 if (skb->cb[0])
759 headroom += DPAA2_ETH_TX_HWA_SIZE;
760
761 return headroom;
762 }
763
764 /* Extra headroom space requested to hardware, in order to make sure there's
765 * no realloc'ing in forwarding scenarios
766 */
dpaa2_eth_rx_head_room(struct dpaa2_eth_priv * priv)767 static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
768 {
769 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
770 }
771
dpaa2_eth_is_type_phy(struct dpaa2_eth_priv * priv)772 static inline bool dpaa2_eth_is_type_phy(struct dpaa2_eth_priv *priv)
773 {
774 lockdep_assert_held(&priv->mac_lock);
775
776 return dpaa2_mac_is_type_phy(priv->mac);
777 }
778
dpaa2_eth_has_mac(struct dpaa2_eth_priv * priv)779 static inline bool dpaa2_eth_has_mac(struct dpaa2_eth_priv *priv)
780 {
781 lockdep_assert_held(&priv->mac_lock);
782
783 return priv->mac ? true : false;
784 }
785
786 int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
787 int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
788 int dpaa2_eth_cls_key_size(u64 key);
789 int dpaa2_eth_cls_fld_off(int prot, int field);
790 void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
791
792 void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
793 bool tx_pause, bool pfc);
794
795 extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops;
796
797 int dpaa2_eth_dl_alloc(struct dpaa2_eth_priv *priv);
798 void dpaa2_eth_dl_free(struct dpaa2_eth_priv *priv);
799
800 void dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv);
801 void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv);
802
803 int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv);
804 void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv);
805
806 int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv);
807 void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv);
808
809 struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
810 struct dpaa2_fapr *fapr);
811
812 struct dpaa2_eth_bp *dpaa2_eth_allocate_dpbp(struct dpaa2_eth_priv *priv);
813 void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv, struct dpaa2_eth_bp *bp);
814
815 struct sk_buff *dpaa2_eth_alloc_skb(struct dpaa2_eth_priv *priv,
816 struct dpaa2_eth_channel *ch,
817 const struct dpaa2_fd *fd, u32 fd_length,
818 void *fd_vaddr);
819
820 void dpaa2_eth_receive_skb(struct dpaa2_eth_priv *priv,
821 struct dpaa2_eth_channel *ch,
822 const struct dpaa2_fd *fd, void *vaddr,
823 struct dpaa2_eth_fq *fq,
824 struct rtnl_link_stats64 *percpu_stats,
825 struct sk_buff *skb);
826
827 void dpaa2_eth_rx(struct dpaa2_eth_priv *priv,
828 struct dpaa2_eth_channel *ch,
829 const struct dpaa2_fd *fd,
830 struct dpaa2_eth_fq *fq);
831
832 struct dpaa2_eth_bp *dpaa2_eth_allocate_dpbp(struct dpaa2_eth_priv *priv);
833 void dpaa2_eth_free_dpbp(struct dpaa2_eth_priv *priv,
834 struct dpaa2_eth_bp *bp);
835
836 void *dpaa2_iova_to_virt(struct iommu_domain *domain, dma_addr_t iova_addr);
837 void dpaa2_eth_recycle_buf(struct dpaa2_eth_priv *priv,
838 struct dpaa2_eth_channel *ch,
839 dma_addr_t addr);
840
841 void dpaa2_eth_xdp_enqueue(struct dpaa2_eth_priv *priv,
842 struct dpaa2_eth_channel *ch,
843 struct dpaa2_fd *fd,
844 void *buf_start, u16 queue_id);
845
846 int dpaa2_xsk_wakeup(struct net_device *dev, u32 qid, u32 flags);
847 int dpaa2_xsk_setup_pool(struct net_device *dev, struct xsk_buff_pool *pool, u16 qid);
848
849 void dpaa2_eth_free_tx_fd(struct dpaa2_eth_priv *priv,
850 struct dpaa2_eth_channel *ch,
851 struct dpaa2_eth_fq *fq,
852 const struct dpaa2_fd *fd, bool in_napi);
853 bool dpaa2_xsk_tx(struct dpaa2_eth_priv *priv,
854 struct dpaa2_eth_channel *ch);
855
856 /* SGT (Scatter-Gather Table) cache management */
857 void *dpaa2_eth_sgt_get(struct dpaa2_eth_priv *priv);
858
859 void dpaa2_eth_sgt_recycle(struct dpaa2_eth_priv *priv, void *sgt_buf);
860
861 #endif /* __DPAA2_H */
862
