1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2006-2015, Intel Corporation.
4 *
5 * Authors: Ashok Raj <ashok.raj@intel.com>
6 * Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
7 * David Woodhouse <David.Woodhouse@intel.com>
8 */
9
10 #ifndef _INTEL_IOMMU_H_
11 #define _INTEL_IOMMU_H_
12
13 #include <linux/types.h>
14 #include <linux/iova.h>
15 #include <linux/io.h>
16 #include <linux/idr.h>
17 #include <linux/mmu_notifier.h>
18 #include <linux/list.h>
19 #include <linux/iommu.h>
20 #include <linux/io-64-nonatomic-lo-hi.h>
21 #include <linux/dmar.h>
22
23 #include <asm/cacheflush.h>
24 #include <asm/iommu.h>
25
26 /*
27 * VT-d hardware uses 4KiB page size regardless of host page size.
28 */
29 #define VTD_PAGE_SHIFT (12)
30 #define VTD_PAGE_SIZE (1UL << VTD_PAGE_SHIFT)
31 #define VTD_PAGE_MASK (((u64)-1) << VTD_PAGE_SHIFT)
32 #define VTD_PAGE_ALIGN(addr) (((addr) + VTD_PAGE_SIZE - 1) & VTD_PAGE_MASK)
33
34 #define VTD_STRIDE_SHIFT (9)
35 #define VTD_STRIDE_MASK (((u64)-1) << VTD_STRIDE_SHIFT)
36
37 #define DMA_PTE_READ (1)
38 #define DMA_PTE_WRITE (2)
39 #define DMA_PTE_LARGE_PAGE (1 << 7)
40 #define DMA_PTE_SNP (1 << 11)
41
42 #define CONTEXT_TT_MULTI_LEVEL 0
43 #define CONTEXT_TT_DEV_IOTLB 1
44 #define CONTEXT_TT_PASS_THROUGH 2
45 #define CONTEXT_PASIDE BIT_ULL(3)
46
47 /*
48 * Intel IOMMU register specification per version 1.0 public spec.
49 */
50 #define DMAR_VER_REG 0x0 /* Arch version supported by this IOMMU */
51 #define DMAR_CAP_REG 0x8 /* Hardware supported capabilities */
52 #define DMAR_ECAP_REG 0x10 /* Extended capabilities supported */
53 #define DMAR_GCMD_REG 0x18 /* Global command register */
54 #define DMAR_GSTS_REG 0x1c /* Global status register */
55 #define DMAR_RTADDR_REG 0x20 /* Root entry table */
56 #define DMAR_CCMD_REG 0x28 /* Context command reg */
57 #define DMAR_FSTS_REG 0x34 /* Fault Status register */
58 #define DMAR_FECTL_REG 0x38 /* Fault control register */
59 #define DMAR_FEDATA_REG 0x3c /* Fault event interrupt data register */
60 #define DMAR_FEADDR_REG 0x40 /* Fault event interrupt addr register */
61 #define DMAR_FEUADDR_REG 0x44 /* Upper address register */
62 #define DMAR_AFLOG_REG 0x58 /* Advanced Fault control */
63 #define DMAR_PMEN_REG 0x64 /* Enable Protected Memory Region */
64 #define DMAR_PLMBASE_REG 0x68 /* PMRR Low addr */
65 #define DMAR_PLMLIMIT_REG 0x6c /* PMRR low limit */
66 #define DMAR_PHMBASE_REG 0x70 /* pmrr high base addr */
67 #define DMAR_PHMLIMIT_REG 0x78 /* pmrr high limit */
68 #define DMAR_IQH_REG 0x80 /* Invalidation queue head register */
69 #define DMAR_IQT_REG 0x88 /* Invalidation queue tail register */
70 #define DMAR_IQ_SHIFT 4 /* Invalidation queue head/tail shift */
71 #define DMAR_IQA_REG 0x90 /* Invalidation queue addr register */
72 #define DMAR_ICS_REG 0x9c /* Invalidation complete status register */
73 #define DMAR_IRTA_REG 0xb8 /* Interrupt remapping table addr register */
74 #define DMAR_PQH_REG 0xc0 /* Page request queue head register */
75 #define DMAR_PQT_REG 0xc8 /* Page request queue tail register */
76 #define DMAR_PQA_REG 0xd0 /* Page request queue address register */
77 #define DMAR_PRS_REG 0xdc /* Page request status register */
78 #define DMAR_PECTL_REG 0xe0 /* Page request event control register */
79 #define DMAR_PEDATA_REG 0xe4 /* Page request event interrupt data register */
80 #define DMAR_PEADDR_REG 0xe8 /* Page request event interrupt addr register */
81 #define DMAR_PEUADDR_REG 0xec /* Page request event Upper address register */
82 #define DMAR_MTRRCAP_REG 0x100 /* MTRR capability register */
83 #define DMAR_MTRRDEF_REG 0x108 /* MTRR default type register */
84 #define DMAR_MTRR_FIX64K_00000_REG 0x120 /* MTRR Fixed range registers */
85 #define DMAR_MTRR_FIX16K_80000_REG 0x128
86 #define DMAR_MTRR_FIX16K_A0000_REG 0x130
87 #define DMAR_MTRR_FIX4K_C0000_REG 0x138
88 #define DMAR_MTRR_FIX4K_C8000_REG 0x140
89 #define DMAR_MTRR_FIX4K_D0000_REG 0x148
90 #define DMAR_MTRR_FIX4K_D8000_REG 0x150
91 #define DMAR_MTRR_FIX4K_E0000_REG 0x158
92 #define DMAR_MTRR_FIX4K_E8000_REG 0x160
93 #define DMAR_MTRR_FIX4K_F0000_REG 0x168
94 #define DMAR_MTRR_FIX4K_F8000_REG 0x170
95 #define DMAR_MTRR_PHYSBASE0_REG 0x180 /* MTRR Variable range registers */
96 #define DMAR_MTRR_PHYSMASK0_REG 0x188
97 #define DMAR_MTRR_PHYSBASE1_REG 0x190
98 #define DMAR_MTRR_PHYSMASK1_REG 0x198
99 #define DMAR_MTRR_PHYSBASE2_REG 0x1a0
100 #define DMAR_MTRR_PHYSMASK2_REG 0x1a8
101 #define DMAR_MTRR_PHYSBASE3_REG 0x1b0
102 #define DMAR_MTRR_PHYSMASK3_REG 0x1b8
103 #define DMAR_MTRR_PHYSBASE4_REG 0x1c0
104 #define DMAR_MTRR_PHYSMASK4_REG 0x1c8
105 #define DMAR_MTRR_PHYSBASE5_REG 0x1d0
106 #define DMAR_MTRR_PHYSMASK5_REG 0x1d8
107 #define DMAR_MTRR_PHYSBASE6_REG 0x1e0
108 #define DMAR_MTRR_PHYSMASK6_REG 0x1e8
109 #define DMAR_MTRR_PHYSBASE7_REG 0x1f0
110 #define DMAR_MTRR_PHYSMASK7_REG 0x1f8
111 #define DMAR_MTRR_PHYSBASE8_REG 0x200
112 #define DMAR_MTRR_PHYSMASK8_REG 0x208
113 #define DMAR_MTRR_PHYSBASE9_REG 0x210
114 #define DMAR_MTRR_PHYSMASK9_REG 0x218
115 #define DMAR_VCCAP_REG 0xe00 /* Virtual command capability register */
116 #define DMAR_VCMD_REG 0xe10 /* Virtual command register */
117 #define DMAR_VCRSP_REG 0xe20 /* Virtual command response register */
118
119 #define OFFSET_STRIDE (9)
120
121 #define dmar_readq(a) readq(a)
122 #define dmar_writeq(a,v) writeq(v,a)
123
124 #define DMAR_VER_MAJOR(v) (((v) & 0xf0) >> 4)
125 #define DMAR_VER_MINOR(v) ((v) & 0x0f)
126
127 /*
128 * Decoding Capability Register
129 */
130 #define cap_5lp_support(c) (((c) >> 60) & 1)
131 #define cap_pi_support(c) (((c) >> 59) & 1)
132 #define cap_fl1gp_support(c) (((c) >> 56) & 1)
133 #define cap_read_drain(c) (((c) >> 55) & 1)
134 #define cap_write_drain(c) (((c) >> 54) & 1)
135 #define cap_max_amask_val(c) (((c) >> 48) & 0x3f)
136 #define cap_num_fault_regs(c) ((((c) >> 40) & 0xff) + 1)
137 #define cap_pgsel_inv(c) (((c) >> 39) & 1)
138
139 #define cap_super_page_val(c) (((c) >> 34) & 0xf)
140 #define cap_super_offset(c) (((find_first_bit(&cap_super_page_val(c), 4)) \
141 * OFFSET_STRIDE) + 21)
142
143 #define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
144 #define cap_max_fault_reg_offset(c) \
145 (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
146
147 #define cap_zlr(c) (((c) >> 22) & 1)
148 #define cap_isoch(c) (((c) >> 23) & 1)
149 #define cap_mgaw(c) ((((c) >> 16) & 0x3f) + 1)
150 #define cap_sagaw(c) (((c) >> 8) & 0x1f)
151 #define cap_caching_mode(c) (((c) >> 7) & 1)
152 #define cap_phmr(c) (((c) >> 6) & 1)
153 #define cap_plmr(c) (((c) >> 5) & 1)
154 #define cap_rwbf(c) (((c) >> 4) & 1)
155 #define cap_afl(c) (((c) >> 3) & 1)
156 #define cap_ndoms(c) (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
157 /*
158 * Extended Capability Register
159 */
160
161 #define ecap_smpwc(e) (((e) >> 48) & 0x1)
162 #define ecap_flts(e) (((e) >> 47) & 0x1)
163 #define ecap_slts(e) (((e) >> 46) & 0x1)
164 #define ecap_smts(e) (((e) >> 43) & 0x1)
165 #define ecap_dit(e) ((e >> 41) & 0x1)
166 #define ecap_pasid(e) ((e >> 40) & 0x1)
167 #define ecap_pss(e) ((e >> 35) & 0x1f)
168 #define ecap_eafs(e) ((e >> 34) & 0x1)
169 #define ecap_nwfs(e) ((e >> 33) & 0x1)
170 #define ecap_srs(e) ((e >> 31) & 0x1)
171 #define ecap_ers(e) ((e >> 30) & 0x1)
172 #define ecap_prs(e) ((e >> 29) & 0x1)
173 #define ecap_broken_pasid(e) ((e >> 28) & 0x1)
174 #define ecap_dis(e) ((e >> 27) & 0x1)
175 #define ecap_nest(e) ((e >> 26) & 0x1)
176 #define ecap_mts(e) ((e >> 25) & 0x1)
177 #define ecap_ecs(e) ((e >> 24) & 0x1)
178 #define ecap_iotlb_offset(e) ((((e) >> 8) & 0x3ff) * 16)
179 #define ecap_max_iotlb_offset(e) (ecap_iotlb_offset(e) + 16)
180 #define ecap_coherent(e) ((e) & 0x1)
181 #define ecap_qis(e) ((e) & 0x2)
182 #define ecap_pass_through(e) ((e >> 6) & 0x1)
183 #define ecap_eim_support(e) ((e >> 4) & 0x1)
184 #define ecap_ir_support(e) ((e >> 3) & 0x1)
185 #define ecap_dev_iotlb_support(e) (((e) >> 2) & 0x1)
186 #define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
187 #define ecap_sc_support(e) ((e >> 7) & 0x1) /* Snooping Control */
188
189 /* IOTLB_REG */
190 #define DMA_TLB_FLUSH_GRANU_OFFSET 60
191 #define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
192 #define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
193 #define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
194 #define DMA_TLB_IIRG(type) ((type >> 60) & 3)
195 #define DMA_TLB_IAIG(val) (((val) >> 57) & 3)
196 #define DMA_TLB_READ_DRAIN (((u64)1) << 49)
197 #define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
198 #define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
199 #define DMA_TLB_IVT (((u64)1) << 63)
200 #define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
201 #define DMA_TLB_MAX_SIZE (0x3f)
202
203 /* INVALID_DESC */
204 #define DMA_CCMD_INVL_GRANU_OFFSET 61
205 #define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 4)
206 #define DMA_ID_TLB_DSI_FLUSH (((u64)2) << 4)
207 #define DMA_ID_TLB_PSI_FLUSH (((u64)3) << 4)
208 #define DMA_ID_TLB_READ_DRAIN (((u64)1) << 7)
209 #define DMA_ID_TLB_WRITE_DRAIN (((u64)1) << 6)
210 #define DMA_ID_TLB_DID(id) (((u64)((id & 0xffff) << 16)))
211 #define DMA_ID_TLB_IH_NONLEAF (((u64)1) << 6)
212 #define DMA_ID_TLB_ADDR(addr) (addr)
213 #define DMA_ID_TLB_ADDR_MASK(mask) (mask)
214
215 /* PMEN_REG */
216 #define DMA_PMEN_EPM (((u32)1)<<31)
217 #define DMA_PMEN_PRS (((u32)1)<<0)
218
219 /* GCMD_REG */
220 #define DMA_GCMD_TE (((u32)1) << 31)
221 #define DMA_GCMD_SRTP (((u32)1) << 30)
222 #define DMA_GCMD_SFL (((u32)1) << 29)
223 #define DMA_GCMD_EAFL (((u32)1) << 28)
224 #define DMA_GCMD_WBF (((u32)1) << 27)
225 #define DMA_GCMD_QIE (((u32)1) << 26)
226 #define DMA_GCMD_SIRTP (((u32)1) << 24)
227 #define DMA_GCMD_IRE (((u32) 1) << 25)
228 #define DMA_GCMD_CFI (((u32) 1) << 23)
229
230 /* GSTS_REG */
231 #define DMA_GSTS_TES (((u32)1) << 31)
232 #define DMA_GSTS_RTPS (((u32)1) << 30)
233 #define DMA_GSTS_FLS (((u32)1) << 29)
234 #define DMA_GSTS_AFLS (((u32)1) << 28)
235 #define DMA_GSTS_WBFS (((u32)1) << 27)
236 #define DMA_GSTS_QIES (((u32)1) << 26)
237 #define DMA_GSTS_IRTPS (((u32)1) << 24)
238 #define DMA_GSTS_IRES (((u32)1) << 25)
239 #define DMA_GSTS_CFIS (((u32)1) << 23)
240
241 /* DMA_RTADDR_REG */
242 #define DMA_RTADDR_RTT (((u64)1) << 11)
243 #define DMA_RTADDR_SMT (((u64)1) << 10)
244
245 /* CCMD_REG */
246 #define DMA_CCMD_ICC (((u64)1) << 63)
247 #define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
248 #define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
249 #define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
250 #define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
251 #define DMA_CCMD_MASK_NOBIT 0
252 #define DMA_CCMD_MASK_1BIT 1
253 #define DMA_CCMD_MASK_2BIT 2
254 #define DMA_CCMD_MASK_3BIT 3
255 #define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
256 #define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
257
258 /* FECTL_REG */
259 #define DMA_FECTL_IM (((u32)1) << 31)
260
261 /* FSTS_REG */
262 #define DMA_FSTS_PFO (1 << 0) /* Primary Fault Overflow */
263 #define DMA_FSTS_PPF (1 << 1) /* Primary Pending Fault */
264 #define DMA_FSTS_IQE (1 << 4) /* Invalidation Queue Error */
265 #define DMA_FSTS_ICE (1 << 5) /* Invalidation Completion Error */
266 #define DMA_FSTS_ITE (1 << 6) /* Invalidation Time-out Error */
267 #define DMA_FSTS_PRO (1 << 7) /* Page Request Overflow */
268 #define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
269
270 /* FRCD_REG, 32 bits access */
271 #define DMA_FRCD_F (((u32)1) << 31)
272 #define dma_frcd_type(d) ((d >> 30) & 1)
273 #define dma_frcd_fault_reason(c) (c & 0xff)
274 #define dma_frcd_source_id(c) (c & 0xffff)
275 #define dma_frcd_pasid_value(c) (((c) >> 8) & 0xfffff)
276 #define dma_frcd_pasid_present(c) (((c) >> 31) & 1)
277 /* low 64 bit */
278 #define dma_frcd_page_addr(d) (d & (((u64)-1) << PAGE_SHIFT))
279
280 /* PRS_REG */
281 #define DMA_PRS_PPR ((u32)1)
282
283 #define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
284 do { \
285 cycles_t start_time = get_cycles(); \
286 while (1) { \
287 sts = op(iommu->reg + offset); \
288 if (cond) \
289 break; \
290 if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
291 panic("DMAR hardware is malfunctioning\n"); \
292 cpu_relax(); \
293 } \
294 } while (0)
295
296 #define QI_LENGTH 256 /* queue length */
297
298 enum {
299 QI_FREE,
300 QI_IN_USE,
301 QI_DONE,
302 QI_ABORT
303 };
304
305 #define QI_CC_TYPE 0x1
306 #define QI_IOTLB_TYPE 0x2
307 #define QI_DIOTLB_TYPE 0x3
308 #define QI_IEC_TYPE 0x4
309 #define QI_IWD_TYPE 0x5
310 #define QI_EIOTLB_TYPE 0x6
311 #define QI_PC_TYPE 0x7
312 #define QI_DEIOTLB_TYPE 0x8
313 #define QI_PGRP_RESP_TYPE 0x9
314 #define QI_PSTRM_RESP_TYPE 0xa
315
316 #define QI_IEC_SELECTIVE (((u64)1) << 4)
317 #define QI_IEC_IIDEX(idx) (((u64)(idx & 0xffff) << 32))
318 #define QI_IEC_IM(m) (((u64)(m & 0x1f) << 27))
319
320 #define QI_IWD_STATUS_DATA(d) (((u64)d) << 32)
321 #define QI_IWD_STATUS_WRITE (((u64)1) << 5)
322
323 #define QI_IOTLB_DID(did) (((u64)did) << 16)
324 #define QI_IOTLB_DR(dr) (((u64)dr) << 7)
325 #define QI_IOTLB_DW(dw) (((u64)dw) << 6)
326 #define QI_IOTLB_GRAN(gran) (((u64)gran) >> (DMA_TLB_FLUSH_GRANU_OFFSET-4))
327 #define QI_IOTLB_ADDR(addr) (((u64)addr) & VTD_PAGE_MASK)
328 #define QI_IOTLB_IH(ih) (((u64)ih) << 6)
329 #define QI_IOTLB_AM(am) (((u8)am))
330
331 #define QI_CC_FM(fm) (((u64)fm) << 48)
332 #define QI_CC_SID(sid) (((u64)sid) << 32)
333 #define QI_CC_DID(did) (((u64)did) << 16)
334 #define QI_CC_GRAN(gran) (((u64)gran) >> (DMA_CCMD_INVL_GRANU_OFFSET-4))
335
336 #define QI_DEV_IOTLB_SID(sid) ((u64)((sid) & 0xffff) << 32)
337 #define QI_DEV_IOTLB_QDEP(qdep) (((qdep) & 0x1f) << 16)
338 #define QI_DEV_IOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
339 #define QI_DEV_IOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
340 ((u64)((pfsid >> 4) & 0xfff) << 52))
341 #define QI_DEV_IOTLB_SIZE 1
342 #define QI_DEV_IOTLB_MAX_INVS 32
343
344 #define QI_PC_PASID(pasid) (((u64)pasid) << 32)
345 #define QI_PC_DID(did) (((u64)did) << 16)
346 #define QI_PC_GRAN(gran) (((u64)gran) << 4)
347
348 #define QI_PC_ALL_PASIDS (QI_PC_TYPE | QI_PC_GRAN(0))
349 #define QI_PC_PASID_SEL (QI_PC_TYPE | QI_PC_GRAN(1))
350
351 #define QI_EIOTLB_ADDR(addr) ((u64)(addr) & VTD_PAGE_MASK)
352 #define QI_EIOTLB_IH(ih) (((u64)ih) << 6)
353 #define QI_EIOTLB_AM(am) (((u64)am))
354 #define QI_EIOTLB_PASID(pasid) (((u64)pasid) << 32)
355 #define QI_EIOTLB_DID(did) (((u64)did) << 16)
356 #define QI_EIOTLB_GRAN(gran) (((u64)gran) << 4)
357
358 #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK)
359 #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11)
360 #define QI_DEV_EIOTLB_GLOB(g) ((u64)g)
361 #define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32)
362 #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16)
363 #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4)
364 #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \
365 ((u64)((pfsid >> 4) & 0xfff) << 52))
366 #define QI_DEV_EIOTLB_MAX_INVS 32
367
368 /* Page group response descriptor QW0 */
369 #define QI_PGRP_PASID_P(p) (((u64)(p)) << 4)
370 #define QI_PGRP_PDP(p) (((u64)(p)) << 5)
371 #define QI_PGRP_RESP_CODE(res) (((u64)(res)) << 12)
372 #define QI_PGRP_DID(rid) (((u64)(rid)) << 16)
373 #define QI_PGRP_PASID(pasid) (((u64)(pasid)) << 32)
374
375 /* Page group response descriptor QW1 */
376 #define QI_PGRP_LPIG(x) (((u64)(x)) << 2)
377 #define QI_PGRP_IDX(idx) (((u64)(idx)) << 3)
378
379
380 #define QI_RESP_SUCCESS 0x0
381 #define QI_RESP_INVALID 0x1
382 #define QI_RESP_FAILURE 0xf
383
384 #define QI_GRAN_NONG_PASID 2
385 #define QI_GRAN_PSI_PASID 3
386
387 #define qi_shift(iommu) (DMAR_IQ_SHIFT + !!ecap_smts((iommu)->ecap))
388
389 struct qi_desc {
390 u64 qw0;
391 u64 qw1;
392 u64 qw2;
393 u64 qw3;
394 };
395
396 struct q_inval {
397 raw_spinlock_t q_lock;
398 void *desc; /* invalidation queue */
399 int *desc_status; /* desc status */
400 int free_head; /* first free entry */
401 int free_tail; /* last free entry */
402 int free_cnt;
403 };
404
405 #ifdef CONFIG_IRQ_REMAP
406 /* 1MB - maximum possible interrupt remapping table size */
407 #define INTR_REMAP_PAGE_ORDER 8
408 #define INTR_REMAP_TABLE_REG_SIZE 0xf
409 #define INTR_REMAP_TABLE_REG_SIZE_MASK 0xf
410
411 #define INTR_REMAP_TABLE_ENTRIES 65536
412
413 struct irq_domain;
414
415 struct ir_table {
416 struct irte *base;
417 unsigned long *bitmap;
418 };
419 #endif
420
421 struct iommu_flush {
422 void (*flush_context)(struct intel_iommu *iommu, u16 did, u16 sid,
423 u8 fm, u64 type);
424 void (*flush_iotlb)(struct intel_iommu *iommu, u16 did, u64 addr,
425 unsigned int size_order, u64 type);
426 };
427
428 enum {
429 SR_DMAR_FECTL_REG,
430 SR_DMAR_FEDATA_REG,
431 SR_DMAR_FEADDR_REG,
432 SR_DMAR_FEUADDR_REG,
433 MAX_SR_DMAR_REGS
434 };
435
436 #define VTD_FLAG_TRANS_PRE_ENABLED (1 << 0)
437 #define VTD_FLAG_IRQ_REMAP_PRE_ENABLED (1 << 1)
438
439 extern int intel_iommu_sm;
440
441 #define sm_supported(iommu) (intel_iommu_sm && ecap_smts((iommu)->ecap))
442 #define pasid_supported(iommu) (sm_supported(iommu) && \
443 ecap_pasid((iommu)->ecap))
444
445 struct pasid_entry;
446 struct pasid_state_entry;
447 struct page_req_dsc;
448
449 /*
450 * 0: Present
451 * 1-11: Reserved
452 * 12-63: Context Ptr (12 - (haw-1))
453 * 64-127: Reserved
454 */
455 struct root_entry {
456 u64 lo;
457 u64 hi;
458 };
459
460 /*
461 * low 64 bits:
462 * 0: present
463 * 1: fault processing disable
464 * 2-3: translation type
465 * 12-63: address space root
466 * high 64 bits:
467 * 0-2: address width
468 * 3-6: aval
469 * 8-23: domain id
470 */
471 struct context_entry {
472 u64 lo;
473 u64 hi;
474 };
475
476 struct dmar_domain {
477 int nid; /* node id */
478
479 unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
480 /* Refcount of devices per iommu */
481
482
483 u16 iommu_did[DMAR_UNITS_SUPPORTED];
484 /* Domain ids per IOMMU. Use u16 since
485 * domain ids are 16 bit wide according
486 * to VT-d spec, section 9.3 */
487 unsigned int auxd_refcnt; /* Refcount of auxiliary attaching */
488
489 bool has_iotlb_device;
490 struct list_head devices; /* all devices' list */
491 struct list_head auxd; /* link to device's auxiliary list */
492 struct iova_domain iovad; /* iova's that belong to this domain */
493
494 struct dma_pte *pgd; /* virtual address */
495 int gaw; /* max guest address width */
496
497 /* adjusted guest address width, 0 is level 2 30-bit */
498 int agaw;
499
500 int flags; /* flags to find out type of domain */
501
502 int iommu_coherency;/* indicate coherency of iommu access */
503 int iommu_snooping; /* indicate snooping control feature*/
504 int iommu_count; /* reference count of iommu */
505 int iommu_superpage;/* Level of superpages supported:
506 0 == 4KiB (no superpages), 1 == 2MiB,
507 2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
508 u64 max_addr; /* maximum mapped address */
509
510 int default_pasid; /*
511 * The default pasid used for non-SVM
512 * traffic on mediated devices.
513 */
514
515 struct iommu_domain domain; /* generic domain data structure for
516 iommu core */
517 };
518
519 struct intel_iommu {
520 void __iomem *reg; /* Pointer to hardware regs, virtual addr */
521 u64 reg_phys; /* physical address of hw register set */
522 u64 reg_size; /* size of hw register set */
523 u64 cap;
524 u64 ecap;
525 u32 gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
526 raw_spinlock_t register_lock; /* protect register handling */
527 int seq_id; /* sequence id of the iommu */
528 int agaw; /* agaw of this iommu */
529 int msagaw; /* max sagaw of this iommu */
530 unsigned int irq, pr_irq;
531 u16 segment; /* PCI segment# */
532 unsigned char name[13]; /* Device Name */
533
534 #ifdef CONFIG_INTEL_IOMMU
535 unsigned long *domain_ids; /* bitmap of domains */
536 struct dmar_domain ***domains; /* ptr to domains */
537 spinlock_t lock; /* protect context, domain ids */
538 struct root_entry *root_entry; /* virtual address */
539
540 struct iommu_flush flush;
541 #endif
542 #ifdef CONFIG_INTEL_IOMMU_SVM
543 struct page_req_dsc *prq;
544 unsigned char prq_name[16]; /* Name for PRQ interrupt */
545 #endif
546 struct q_inval *qi; /* Queued invalidation info */
547 u32 *iommu_state; /* Store iommu states between suspend and resume.*/
548
549 #ifdef CONFIG_IRQ_REMAP
550 struct ir_table *ir_table; /* Interrupt remapping info */
551 struct irq_domain *ir_domain;
552 struct irq_domain *ir_msi_domain;
553 #endif
554 struct iommu_device iommu; /* IOMMU core code handle */
555 int node;
556 u32 flags; /* Software defined flags */
557 };
558
559 /* PCI domain-device relationship */
560 struct device_domain_info {
561 struct list_head link; /* link to domain siblings */
562 struct list_head global; /* link to global list */
563 struct list_head table; /* link to pasid table */
564 struct list_head auxiliary_domains; /* auxiliary domains
565 * attached to this device
566 */
567 u8 bus; /* PCI bus number */
568 u8 devfn; /* PCI devfn number */
569 u16 pfsid; /* SRIOV physical function source ID */
570 u8 pasid_supported:3;
571 u8 pasid_enabled:1;
572 u8 pri_supported:1;
573 u8 pri_enabled:1;
574 u8 ats_supported:1;
575 u8 ats_enabled:1;
576 u8 auxd_enabled:1; /* Multiple domains per device */
577 u8 ats_qdep;
578 struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
579 struct intel_iommu *iommu; /* IOMMU used by this device */
580 struct dmar_domain *domain; /* pointer to domain */
581 struct pasid_table *pasid_table; /* pasid table */
582 };
583
__iommu_flush_cache(struct intel_iommu * iommu,void * addr,int size)584 static inline void __iommu_flush_cache(
585 struct intel_iommu *iommu, void *addr, int size)
586 {
587 if (!ecap_coherent(iommu->ecap))
588 clflush_cache_range(addr, size);
589 }
590
591 /*
592 * 0: readable
593 * 1: writable
594 * 2-6: reserved
595 * 7: super page
596 * 8-10: available
597 * 11: snoop behavior
598 * 12-63: Host physcial address
599 */
600 struct dma_pte {
601 u64 val;
602 };
603
dma_clear_pte(struct dma_pte * pte)604 static inline void dma_clear_pte(struct dma_pte *pte)
605 {
606 pte->val = 0;
607 }
608
dma_pte_addr(struct dma_pte * pte)609 static inline u64 dma_pte_addr(struct dma_pte *pte)
610 {
611 #ifdef CONFIG_64BIT
612 return pte->val & VTD_PAGE_MASK;
613 #else
614 /* Must have a full atomic 64-bit read */
615 return __cmpxchg64(&pte->val, 0ULL, 0ULL) & VTD_PAGE_MASK;
616 #endif
617 }
618
dma_pte_present(struct dma_pte * pte)619 static inline bool dma_pte_present(struct dma_pte *pte)
620 {
621 return (pte->val & 3) != 0;
622 }
623
dma_pte_superpage(struct dma_pte * pte)624 static inline bool dma_pte_superpage(struct dma_pte *pte)
625 {
626 return (pte->val & DMA_PTE_LARGE_PAGE);
627 }
628
first_pte_in_page(struct dma_pte * pte)629 static inline int first_pte_in_page(struct dma_pte *pte)
630 {
631 return !((unsigned long)pte & ~VTD_PAGE_MASK);
632 }
633
634 extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
635 extern int dmar_find_matched_atsr_unit(struct pci_dev *dev);
636
637 extern int dmar_enable_qi(struct intel_iommu *iommu);
638 extern void dmar_disable_qi(struct intel_iommu *iommu);
639 extern int dmar_reenable_qi(struct intel_iommu *iommu);
640 extern void qi_global_iec(struct intel_iommu *iommu);
641
642 extern void qi_flush_context(struct intel_iommu *iommu, u16 did, u16 sid,
643 u8 fm, u64 type);
644 extern void qi_flush_iotlb(struct intel_iommu *iommu, u16 did, u64 addr,
645 unsigned int size_order, u64 type);
646 extern void qi_flush_dev_iotlb(struct intel_iommu *iommu, u16 sid, u16 pfsid,
647 u16 qdep, u64 addr, unsigned mask);
648 extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
649
650 extern int dmar_ir_support(void);
651
652 void *alloc_pgtable_page(int node);
653 void free_pgtable_page(void *vaddr);
654 struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
655 int for_each_device_domain(int (*fn)(struct device_domain_info *info,
656 void *data), void *data);
657 void iommu_flush_write_buffer(struct intel_iommu *iommu);
658 int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct device *dev);
659
660 #ifdef CONFIG_INTEL_IOMMU_SVM
661 int intel_svm_init(struct intel_iommu *iommu);
662 extern int intel_svm_enable_prq(struct intel_iommu *iommu);
663 extern int intel_svm_finish_prq(struct intel_iommu *iommu);
664
665 struct svm_dev_ops;
666
667 struct intel_svm_dev {
668 struct list_head list;
669 struct rcu_head rcu;
670 struct device *dev;
671 struct svm_dev_ops *ops;
672 int users;
673 u16 did;
674 u16 dev_iotlb:1;
675 u16 sid, qdep;
676 };
677
678 struct intel_svm {
679 struct mmu_notifier notifier;
680 struct mm_struct *mm;
681 struct intel_iommu *iommu;
682 int flags;
683 int pasid;
684 struct list_head devs;
685 struct list_head list;
686 };
687
688 extern struct intel_iommu *intel_svm_device_to_iommu(struct device *dev);
689 #endif
690
691 #ifdef CONFIG_INTEL_IOMMU_DEBUGFS
692 void intel_iommu_debugfs_init(void);
693 #else
intel_iommu_debugfs_init(void)694 static inline void intel_iommu_debugfs_init(void) {}
695 #endif /* CONFIG_INTEL_IOMMU_DEBUGFS */
696
697 extern const struct attribute_group *intel_iommu_groups[];
698 bool context_present(struct context_entry *context);
699 struct context_entry *iommu_context_addr(struct intel_iommu *iommu, u8 bus,
700 u8 devfn, int alloc);
701
702 #ifdef CONFIG_INTEL_IOMMU
703 extern int iommu_calculate_agaw(struct intel_iommu *iommu);
704 extern int iommu_calculate_max_sagaw(struct intel_iommu *iommu);
705 extern int dmar_disabled;
706 extern int intel_iommu_enabled;
707 extern int intel_iommu_tboot_noforce;
708 #else
iommu_calculate_agaw(struct intel_iommu * iommu)709 static inline int iommu_calculate_agaw(struct intel_iommu *iommu)
710 {
711 return 0;
712 }
iommu_calculate_max_sagaw(struct intel_iommu * iommu)713 static inline int iommu_calculate_max_sagaw(struct intel_iommu *iommu)
714 {
715 return 0;
716 }
717 #define dmar_disabled (1)
718 #define intel_iommu_enabled (0)
719 #endif
720
721 #endif
722
