1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * This file contains the processor specific definitions 4 * of the TI DM644x, DM355, DM365, and DM646x. 5 * 6 * Copyright (C) 2011 Texas Instruments Incorporated 7 * Copyright (c) 2007 Deep Root Systems, LLC 8 */ 9 #ifndef __DAVINCI_H 10 #define __DAVINCI_H 11 12 #include <linux/clk.h> 13 #include <linux/videodev2.h> 14 #include <linux/davinci_emac.h> 15 #include <linux/platform_device.h> 16 #include <linux/spi/spi.h> 17 #include <linux/platform_data/davinci_asp.h> 18 #include <linux/platform_data/edma.h> 19 #include <linux/platform_data/keyscan-davinci.h> 20 21 #include "hardware.h" 22 23 #include <media/davinci/vpfe_capture.h> 24 #include <media/davinci/vpif_types.h> 25 #include <media/davinci/vpss.h> 26 #include <media/davinci/vpbe_types.h> 27 #include <media/davinci/vpbe_venc.h> 28 #include <media/davinci/vpbe.h> 29 #include <media/davinci/vpbe_osd.h> 30 31 #define DAVINCI_PLL1_BASE 0x01c40800 32 #define DAVINCI_PLL2_BASE 0x01c40c00 33 #define DAVINCI_PWR_SLEEP_CNTRL_BASE 0x01c41000 34 35 #define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000 36 #define SYSMOD_VDAC_CONFIG 0x2c 37 #define SYSMOD_VIDCLKCTL 0x38 38 #define SYSMOD_VPSS_CLKCTL 0x44 39 #define SYSMOD_VDD3P3VPWDN 0x48 40 #define SYSMOD_VSCLKDIS 0x6c 41 #define SYSMOD_PUPDCTL1 0x7c 42 43 /* VPSS CLKCTL bit definitions */ 44 #define VPSS_MUXSEL_EXTCLK_ENABLE BIT(1) 45 #define VPSS_VENCCLKEN_ENABLE BIT(3) 46 #define VPSS_DACCLKEN_ENABLE BIT(4) 47 #define VPSS_PLLC2SYSCLK5_ENABLE BIT(5) 48 49 extern void __iomem *davinci_sysmod_base; 50 #define DAVINCI_SYSMOD_VIRT(x) (davinci_sysmod_base + (x)) 51 void davinci_map_sysmod(void); 52 53 #define DAVINCI_GPIO_BASE 0x01C67000 54 int davinci_gpio_register(struct resource *res, int size, void *pdata); 55 56 #define DAVINCI_TIMER0_BASE (IO_PHYS + 0x21400) 57 #define DAVINCI_WDOG_BASE (IO_PHYS + 0x21C00) 58 59 /* DM355 base addresses */ 60 #define DM355_ASYNC_EMIF_CONTROL_BASE 0x01e10000 61 #define DM355_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 62 63 #define ASP1_TX_EVT_EN 1 64 #define ASP1_RX_EVT_EN 2 65 66 /* DM365 base addresses */ 67 #define DM365_ASYNC_EMIF_CONTROL_BASE 0x01d10000 68 #define DM365_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 69 #define DM365_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 70 71 /* DM644x base addresses */ 72 #define DM644X_ASYNC_EMIF_CONTROL_BASE 0x01e00000 73 #define DM644X_ASYNC_EMIF_DATA_CE0_BASE 0x02000000 74 #define DM644X_ASYNC_EMIF_DATA_CE1_BASE 0x04000000 75 #define DM644X_ASYNC_EMIF_DATA_CE2_BASE 0x06000000 76 #define DM644X_ASYNC_EMIF_DATA_CE3_BASE 0x08000000 77 78 /* DM646x base addresses */ 79 #define DM646X_ASYNC_EMIF_CONTROL_BASE 0x20008000 80 #define DM646X_ASYNC_EMIF_CS2_SPACE_BASE 0x42000000 81 82 int davinci_init_wdt(void); 83 84 /* DM355 function declarations */ 85 void dm355_init(void); 86 void dm355_init_time(void); 87 void dm355_init_irq(void); 88 void dm355_register_clocks(void); 89 void dm355_init_spi0(unsigned chipselect_mask, 90 const struct spi_board_info *info, unsigned len); 91 void dm355_init_asp1(u32 evt_enable); 92 int dm355_init_video(struct vpfe_config *, struct vpbe_config *); 93 int dm355_gpio_register(void); 94 95 /* DM365 function declarations */ 96 void dm365_init(void); 97 void dm365_init_irq(void); 98 void dm365_init_time(void); 99 void dm365_register_clocks(void); 100 void dm365_init_asp(void); 101 void dm365_init_vc(void); 102 void dm365_init_ks(struct davinci_ks_platform_data *pdata); 103 void dm365_init_rtc(void); 104 void dm365_init_spi0(unsigned chipselect_mask, 105 const struct spi_board_info *info, unsigned len); 106 int dm365_init_video(struct vpfe_config *, struct vpbe_config *); 107 int dm365_gpio_register(void); 108 109 /* DM644x function declarations */ 110 void dm644x_init(void); 111 void dm644x_init_irq(void); 112 void dm644x_init_devices(void); 113 void dm644x_init_time(void); 114 void dm644x_register_clocks(void); 115 void dm644x_init_asp(void); 116 int dm644x_init_video(struct vpfe_config *, struct vpbe_config *); 117 int dm644x_gpio_register(void); 118 119 /* DM646x function declarations */ 120 void dm646x_init(void); 121 void dm646x_init_irq(void); 122 void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate); 123 void dm646x_register_clocks(void); 124 void dm646x_init_mcasp0(struct snd_platform_data *pdata); 125 void dm646x_init_mcasp1(struct snd_platform_data *pdata); 126 int dm646x_init_edma(struct edma_rsv_info *rsv); 127 void dm646x_video_init(void); 128 void dm646x_setup_vpif(struct vpif_display_config *, 129 struct vpif_capture_config *); 130 int dm646x_gpio_register(void); 131 132 extern struct platform_device dm365_serial_device[]; 133 extern struct platform_device dm355_serial_device[]; 134 extern struct platform_device dm644x_serial_device[]; 135 extern struct platform_device dm646x_serial_device[]; 136 #endif /*__DAVINCI_H */ 137
