1 /*
2 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
3 * Author: Archit Taneja <archit@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __OMAP2_DISPC_REG_H
19 #define __OMAP2_DISPC_REG_H
20
21 /* DISPC common registers */
22 #define DISPC_REVISION 0x0000
23 #define DISPC_SYSCONFIG 0x0010
24 #define DISPC_SYSSTATUS 0x0014
25 #define DISPC_IRQSTATUS 0x0018
26 #define DISPC_IRQENABLE 0x001C
27 #define DISPC_CONTROL 0x0040
28 #define DISPC_CONFIG 0x0044
29 #define DISPC_CAPABLE 0x0048
30 #define DISPC_LINE_STATUS 0x005C
31 #define DISPC_LINE_NUMBER 0x0060
32 #define DISPC_GLOBAL_ALPHA 0x0074
33 #define DISPC_CONTROL2 0x0238
34 #define DISPC_CONFIG2 0x0620
35 #define DISPC_DIVISOR 0x0804
36 #define DISPC_GLOBAL_BUFFER 0x0800
37 #define DISPC_CONTROL3 0x0848
38 #define DISPC_CONFIG3 0x084C
39 #define DISPC_MSTANDBY_CTRL 0x0858
40 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
41
42 #define DISPC_GAMMA_TABLE0 0x0630
43 #define DISPC_GAMMA_TABLE1 0x0634
44 #define DISPC_GAMMA_TABLE2 0x0638
45 #define DISPC_GAMMA_TABLE3 0x0850
46
47 /* DISPC overlay registers */
48 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
49 DISPC_BA0_OFFSET(n))
50 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
51 DISPC_BA1_OFFSET(n))
52 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
53 DISPC_BA0_UV_OFFSET(n))
54 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
55 DISPC_BA1_UV_OFFSET(n))
56 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
57 DISPC_POS_OFFSET(n))
58 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
59 DISPC_SIZE_OFFSET(n))
60 #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
61 DISPC_ATTR_OFFSET(n))
62 #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
63 DISPC_ATTR2_OFFSET(n))
64 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
65 DISPC_FIFO_THRESH_OFFSET(n))
66 #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
67 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
68 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
69 DISPC_ROW_INC_OFFSET(n))
70 #define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
71 DISPC_PIX_INC_OFFSET(n))
72 #define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
73 DISPC_WINDOW_SKIP_OFFSET(n))
74 #define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
75 DISPC_TABLE_BA_OFFSET(n))
76 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
77 DISPC_FIR_OFFSET(n))
78 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
79 DISPC_FIR2_OFFSET(n))
80 #define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
81 DISPC_PIC_SIZE_OFFSET(n))
82 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
83 DISPC_ACCU0_OFFSET(n))
84 #define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
85 DISPC_ACCU1_OFFSET(n))
86 #define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
87 DISPC_ACCU2_0_OFFSET(n))
88 #define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
89 DISPC_ACCU2_1_OFFSET(n))
90 #define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
91 DISPC_FIR_COEF_H_OFFSET(n, i))
92 #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
93 DISPC_FIR_COEF_HV_OFFSET(n, i))
94 #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
95 DISPC_FIR_COEF_H2_OFFSET(n, i))
96 #define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
97 DISPC_FIR_COEF_HV2_OFFSET(n, i))
98 #define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
99 DISPC_CONV_COEF_OFFSET(n, i))
100 #define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
101 DISPC_FIR_COEF_V_OFFSET(n, i))
102 #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
103 DISPC_FIR_COEF_V2_OFFSET(n, i))
104 #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
105 DISPC_PRELOAD_OFFSET(n))
106 #define DISPC_OVL_MFLAG_THRESHOLD(n) DISPC_MFLAG_THRESHOLD_OFFSET(n)
107
108 /* DISPC up/downsampling FIR filter coefficient structure */
109 struct dispc_coef {
110 s8 hc4_vc22;
111 s8 hc3_vc2;
112 u8 hc2_vc1;
113 s8 hc1_vc0;
114 s8 hc0_vc00;
115 };
116
117 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
118
119 /* DISPC manager/channel specific registers */
DISPC_DEFAULT_COLOR(enum omap_channel channel)120 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
121 {
122 switch (channel) {
123 case OMAP_DSS_CHANNEL_LCD:
124 return 0x004C;
125 case OMAP_DSS_CHANNEL_DIGIT:
126 return 0x0050;
127 case OMAP_DSS_CHANNEL_LCD2:
128 return 0x03AC;
129 case OMAP_DSS_CHANNEL_LCD3:
130 return 0x0814;
131 default:
132 BUG();
133 return 0;
134 }
135 }
136
DISPC_TRANS_COLOR(enum omap_channel channel)137 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
138 {
139 switch (channel) {
140 case OMAP_DSS_CHANNEL_LCD:
141 return 0x0054;
142 case OMAP_DSS_CHANNEL_DIGIT:
143 return 0x0058;
144 case OMAP_DSS_CHANNEL_LCD2:
145 return 0x03B0;
146 case OMAP_DSS_CHANNEL_LCD3:
147 return 0x0818;
148 default:
149 BUG();
150 return 0;
151 }
152 }
153
DISPC_TIMING_H(enum omap_channel channel)154 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
155 {
156 switch (channel) {
157 case OMAP_DSS_CHANNEL_LCD:
158 return 0x0064;
159 case OMAP_DSS_CHANNEL_DIGIT:
160 BUG();
161 return 0;
162 case OMAP_DSS_CHANNEL_LCD2:
163 return 0x0400;
164 case OMAP_DSS_CHANNEL_LCD3:
165 return 0x0840;
166 default:
167 BUG();
168 return 0;
169 }
170 }
171
DISPC_TIMING_V(enum omap_channel channel)172 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
173 {
174 switch (channel) {
175 case OMAP_DSS_CHANNEL_LCD:
176 return 0x0068;
177 case OMAP_DSS_CHANNEL_DIGIT:
178 BUG();
179 return 0;
180 case OMAP_DSS_CHANNEL_LCD2:
181 return 0x0404;
182 case OMAP_DSS_CHANNEL_LCD3:
183 return 0x0844;
184 default:
185 BUG();
186 return 0;
187 }
188 }
189
DISPC_POL_FREQ(enum omap_channel channel)190 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
191 {
192 switch (channel) {
193 case OMAP_DSS_CHANNEL_LCD:
194 return 0x006C;
195 case OMAP_DSS_CHANNEL_DIGIT:
196 BUG();
197 return 0;
198 case OMAP_DSS_CHANNEL_LCD2:
199 return 0x0408;
200 case OMAP_DSS_CHANNEL_LCD3:
201 return 0x083C;
202 default:
203 BUG();
204 return 0;
205 }
206 }
207
DISPC_DIVISORo(enum omap_channel channel)208 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
209 {
210 switch (channel) {
211 case OMAP_DSS_CHANNEL_LCD:
212 return 0x0070;
213 case OMAP_DSS_CHANNEL_DIGIT:
214 BUG();
215 return 0;
216 case OMAP_DSS_CHANNEL_LCD2:
217 return 0x040C;
218 case OMAP_DSS_CHANNEL_LCD3:
219 return 0x0838;
220 default:
221 BUG();
222 return 0;
223 }
224 }
225
226 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
DISPC_SIZE_MGR(enum omap_channel channel)227 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
228 {
229 switch (channel) {
230 case OMAP_DSS_CHANNEL_LCD:
231 return 0x007C;
232 case OMAP_DSS_CHANNEL_DIGIT:
233 return 0x0078;
234 case OMAP_DSS_CHANNEL_LCD2:
235 return 0x03CC;
236 case OMAP_DSS_CHANNEL_LCD3:
237 return 0x0834;
238 default:
239 BUG();
240 return 0;
241 }
242 }
243
DISPC_DATA_CYCLE1(enum omap_channel channel)244 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
245 {
246 switch (channel) {
247 case OMAP_DSS_CHANNEL_LCD:
248 return 0x01D4;
249 case OMAP_DSS_CHANNEL_DIGIT:
250 BUG();
251 return 0;
252 case OMAP_DSS_CHANNEL_LCD2:
253 return 0x03C0;
254 case OMAP_DSS_CHANNEL_LCD3:
255 return 0x0828;
256 default:
257 BUG();
258 return 0;
259 }
260 }
261
DISPC_DATA_CYCLE2(enum omap_channel channel)262 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
263 {
264 switch (channel) {
265 case OMAP_DSS_CHANNEL_LCD:
266 return 0x01D8;
267 case OMAP_DSS_CHANNEL_DIGIT:
268 BUG();
269 return 0;
270 case OMAP_DSS_CHANNEL_LCD2:
271 return 0x03C4;
272 case OMAP_DSS_CHANNEL_LCD3:
273 return 0x082C;
274 default:
275 BUG();
276 return 0;
277 }
278 }
279
DISPC_DATA_CYCLE3(enum omap_channel channel)280 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
281 {
282 switch (channel) {
283 case OMAP_DSS_CHANNEL_LCD:
284 return 0x01DC;
285 case OMAP_DSS_CHANNEL_DIGIT:
286 BUG();
287 return 0;
288 case OMAP_DSS_CHANNEL_LCD2:
289 return 0x03C8;
290 case OMAP_DSS_CHANNEL_LCD3:
291 return 0x0830;
292 default:
293 BUG();
294 return 0;
295 }
296 }
297
DISPC_CPR_COEF_R(enum omap_channel channel)298 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
299 {
300 switch (channel) {
301 case OMAP_DSS_CHANNEL_LCD:
302 return 0x0220;
303 case OMAP_DSS_CHANNEL_DIGIT:
304 BUG();
305 return 0;
306 case OMAP_DSS_CHANNEL_LCD2:
307 return 0x03BC;
308 case OMAP_DSS_CHANNEL_LCD3:
309 return 0x0824;
310 default:
311 BUG();
312 return 0;
313 }
314 }
315
DISPC_CPR_COEF_G(enum omap_channel channel)316 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
317 {
318 switch (channel) {
319 case OMAP_DSS_CHANNEL_LCD:
320 return 0x0224;
321 case OMAP_DSS_CHANNEL_DIGIT:
322 BUG();
323 return 0;
324 case OMAP_DSS_CHANNEL_LCD2:
325 return 0x03B8;
326 case OMAP_DSS_CHANNEL_LCD3:
327 return 0x0820;
328 default:
329 BUG();
330 return 0;
331 }
332 }
333
DISPC_CPR_COEF_B(enum omap_channel channel)334 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
335 {
336 switch (channel) {
337 case OMAP_DSS_CHANNEL_LCD:
338 return 0x0228;
339 case OMAP_DSS_CHANNEL_DIGIT:
340 BUG();
341 return 0;
342 case OMAP_DSS_CHANNEL_LCD2:
343 return 0x03B4;
344 case OMAP_DSS_CHANNEL_LCD3:
345 return 0x081C;
346 default:
347 BUG();
348 return 0;
349 }
350 }
351
352 /* DISPC overlay register base addresses */
DISPC_OVL_BASE(enum omap_plane_id plane)353 static inline u16 DISPC_OVL_BASE(enum omap_plane_id plane)
354 {
355 switch (plane) {
356 case OMAP_DSS_GFX:
357 return 0x0080;
358 case OMAP_DSS_VIDEO1:
359 return 0x00BC;
360 case OMAP_DSS_VIDEO2:
361 return 0x014C;
362 case OMAP_DSS_VIDEO3:
363 return 0x0300;
364 case OMAP_DSS_WB:
365 return 0x0500;
366 default:
367 BUG();
368 return 0;
369 }
370 }
371
372 /* DISPC overlay register offsets */
DISPC_BA0_OFFSET(enum omap_plane_id plane)373 static inline u16 DISPC_BA0_OFFSET(enum omap_plane_id plane)
374 {
375 switch (plane) {
376 case OMAP_DSS_GFX:
377 case OMAP_DSS_VIDEO1:
378 case OMAP_DSS_VIDEO2:
379 return 0x0000;
380 case OMAP_DSS_VIDEO3:
381 case OMAP_DSS_WB:
382 return 0x0008;
383 default:
384 BUG();
385 return 0;
386 }
387 }
388
DISPC_BA1_OFFSET(enum omap_plane_id plane)389 static inline u16 DISPC_BA1_OFFSET(enum omap_plane_id plane)
390 {
391 switch (plane) {
392 case OMAP_DSS_GFX:
393 case OMAP_DSS_VIDEO1:
394 case OMAP_DSS_VIDEO2:
395 return 0x0004;
396 case OMAP_DSS_VIDEO3:
397 case OMAP_DSS_WB:
398 return 0x000C;
399 default:
400 BUG();
401 return 0;
402 }
403 }
404
DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)405 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane_id plane)
406 {
407 switch (plane) {
408 case OMAP_DSS_GFX:
409 BUG();
410 return 0;
411 case OMAP_DSS_VIDEO1:
412 return 0x0544;
413 case OMAP_DSS_VIDEO2:
414 return 0x04BC;
415 case OMAP_DSS_VIDEO3:
416 return 0x0310;
417 case OMAP_DSS_WB:
418 return 0x0118;
419 default:
420 BUG();
421 return 0;
422 }
423 }
424
DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)425 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane_id plane)
426 {
427 switch (plane) {
428 case OMAP_DSS_GFX:
429 BUG();
430 return 0;
431 case OMAP_DSS_VIDEO1:
432 return 0x0548;
433 case OMAP_DSS_VIDEO2:
434 return 0x04C0;
435 case OMAP_DSS_VIDEO3:
436 return 0x0314;
437 case OMAP_DSS_WB:
438 return 0x011C;
439 default:
440 BUG();
441 return 0;
442 }
443 }
444
DISPC_POS_OFFSET(enum omap_plane_id plane)445 static inline u16 DISPC_POS_OFFSET(enum omap_plane_id plane)
446 {
447 switch (plane) {
448 case OMAP_DSS_GFX:
449 case OMAP_DSS_VIDEO1:
450 case OMAP_DSS_VIDEO2:
451 return 0x0008;
452 case OMAP_DSS_VIDEO3:
453 return 0x009C;
454 default:
455 BUG();
456 return 0;
457 }
458 }
459
DISPC_SIZE_OFFSET(enum omap_plane_id plane)460 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane_id plane)
461 {
462 switch (plane) {
463 case OMAP_DSS_GFX:
464 case OMAP_DSS_VIDEO1:
465 case OMAP_DSS_VIDEO2:
466 return 0x000C;
467 case OMAP_DSS_VIDEO3:
468 case OMAP_DSS_WB:
469 return 0x00A8;
470 default:
471 BUG();
472 return 0;
473 }
474 }
475
DISPC_ATTR_OFFSET(enum omap_plane_id plane)476 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane_id plane)
477 {
478 switch (plane) {
479 case OMAP_DSS_GFX:
480 return 0x0020;
481 case OMAP_DSS_VIDEO1:
482 case OMAP_DSS_VIDEO2:
483 return 0x0010;
484 case OMAP_DSS_VIDEO3:
485 case OMAP_DSS_WB:
486 return 0x0070;
487 default:
488 BUG();
489 return 0;
490 }
491 }
492
DISPC_ATTR2_OFFSET(enum omap_plane_id plane)493 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane_id plane)
494 {
495 switch (plane) {
496 case OMAP_DSS_GFX:
497 BUG();
498 return 0;
499 case OMAP_DSS_VIDEO1:
500 return 0x0568;
501 case OMAP_DSS_VIDEO2:
502 return 0x04DC;
503 case OMAP_DSS_VIDEO3:
504 return 0x032C;
505 case OMAP_DSS_WB:
506 return 0x0310;
507 default:
508 BUG();
509 return 0;
510 }
511 }
512
DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)513 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane_id plane)
514 {
515 switch (plane) {
516 case OMAP_DSS_GFX:
517 return 0x0024;
518 case OMAP_DSS_VIDEO1:
519 case OMAP_DSS_VIDEO2:
520 return 0x0014;
521 case OMAP_DSS_VIDEO3:
522 case OMAP_DSS_WB:
523 return 0x008C;
524 default:
525 BUG();
526 return 0;
527 }
528 }
529
DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)530 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane_id plane)
531 {
532 switch (plane) {
533 case OMAP_DSS_GFX:
534 return 0x0028;
535 case OMAP_DSS_VIDEO1:
536 case OMAP_DSS_VIDEO2:
537 return 0x0018;
538 case OMAP_DSS_VIDEO3:
539 case OMAP_DSS_WB:
540 return 0x0088;
541 default:
542 BUG();
543 return 0;
544 }
545 }
546
DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)547 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane_id plane)
548 {
549 switch (plane) {
550 case OMAP_DSS_GFX:
551 return 0x002C;
552 case OMAP_DSS_VIDEO1:
553 case OMAP_DSS_VIDEO2:
554 return 0x001C;
555 case OMAP_DSS_VIDEO3:
556 case OMAP_DSS_WB:
557 return 0x00A4;
558 default:
559 BUG();
560 return 0;
561 }
562 }
563
DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)564 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane_id plane)
565 {
566 switch (plane) {
567 case OMAP_DSS_GFX:
568 return 0x0030;
569 case OMAP_DSS_VIDEO1:
570 case OMAP_DSS_VIDEO2:
571 return 0x0020;
572 case OMAP_DSS_VIDEO3:
573 case OMAP_DSS_WB:
574 return 0x0098;
575 default:
576 BUG();
577 return 0;
578 }
579 }
580
DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)581 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane_id plane)
582 {
583 switch (plane) {
584 case OMAP_DSS_GFX:
585 return 0x0034;
586 case OMAP_DSS_VIDEO1:
587 case OMAP_DSS_VIDEO2:
588 case OMAP_DSS_VIDEO3:
589 BUG();
590 return 0;
591 default:
592 BUG();
593 return 0;
594 }
595 }
596
DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)597 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane_id plane)
598 {
599 switch (plane) {
600 case OMAP_DSS_GFX:
601 return 0x0038;
602 case OMAP_DSS_VIDEO1:
603 case OMAP_DSS_VIDEO2:
604 case OMAP_DSS_VIDEO3:
605 BUG();
606 return 0;
607 default:
608 BUG();
609 return 0;
610 }
611 }
612
DISPC_FIR_OFFSET(enum omap_plane_id plane)613 static inline u16 DISPC_FIR_OFFSET(enum omap_plane_id plane)
614 {
615 switch (plane) {
616 case OMAP_DSS_GFX:
617 BUG();
618 return 0;
619 case OMAP_DSS_VIDEO1:
620 case OMAP_DSS_VIDEO2:
621 return 0x0024;
622 case OMAP_DSS_VIDEO3:
623 case OMAP_DSS_WB:
624 return 0x0090;
625 default:
626 BUG();
627 return 0;
628 }
629 }
630
DISPC_FIR2_OFFSET(enum omap_plane_id plane)631 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane_id plane)
632 {
633 switch (plane) {
634 case OMAP_DSS_GFX:
635 BUG();
636 return 0;
637 case OMAP_DSS_VIDEO1:
638 return 0x0580;
639 case OMAP_DSS_VIDEO2:
640 return 0x055C;
641 case OMAP_DSS_VIDEO3:
642 return 0x0424;
643 case OMAP_DSS_WB:
644 return 0x290;
645 default:
646 BUG();
647 return 0;
648 }
649 }
650
DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)651 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane_id plane)
652 {
653 switch (plane) {
654 case OMAP_DSS_GFX:
655 BUG();
656 return 0;
657 case OMAP_DSS_VIDEO1:
658 case OMAP_DSS_VIDEO2:
659 return 0x0028;
660 case OMAP_DSS_VIDEO3:
661 case OMAP_DSS_WB:
662 return 0x0094;
663 default:
664 BUG();
665 return 0;
666 }
667 }
668
669
DISPC_ACCU0_OFFSET(enum omap_plane_id plane)670 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane_id plane)
671 {
672 switch (plane) {
673 case OMAP_DSS_GFX:
674 BUG();
675 return 0;
676 case OMAP_DSS_VIDEO1:
677 case OMAP_DSS_VIDEO2:
678 return 0x002C;
679 case OMAP_DSS_VIDEO3:
680 case OMAP_DSS_WB:
681 return 0x0000;
682 default:
683 BUG();
684 return 0;
685 }
686 }
687
DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)688 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane_id plane)
689 {
690 switch (plane) {
691 case OMAP_DSS_GFX:
692 BUG();
693 return 0;
694 case OMAP_DSS_VIDEO1:
695 return 0x0584;
696 case OMAP_DSS_VIDEO2:
697 return 0x0560;
698 case OMAP_DSS_VIDEO3:
699 return 0x0428;
700 case OMAP_DSS_WB:
701 return 0x0294;
702 default:
703 BUG();
704 return 0;
705 }
706 }
707
DISPC_ACCU1_OFFSET(enum omap_plane_id plane)708 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane_id plane)
709 {
710 switch (plane) {
711 case OMAP_DSS_GFX:
712 BUG();
713 return 0;
714 case OMAP_DSS_VIDEO1:
715 case OMAP_DSS_VIDEO2:
716 return 0x0030;
717 case OMAP_DSS_VIDEO3:
718 case OMAP_DSS_WB:
719 return 0x0004;
720 default:
721 BUG();
722 return 0;
723 }
724 }
725
DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)726 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane_id plane)
727 {
728 switch (plane) {
729 case OMAP_DSS_GFX:
730 BUG();
731 return 0;
732 case OMAP_DSS_VIDEO1:
733 return 0x0588;
734 case OMAP_DSS_VIDEO2:
735 return 0x0564;
736 case OMAP_DSS_VIDEO3:
737 return 0x042C;
738 case OMAP_DSS_WB:
739 return 0x0298;
740 default:
741 BUG();
742 return 0;
743 }
744 }
745
746 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane,u16 i)747 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane_id plane, u16 i)
748 {
749 switch (plane) {
750 case OMAP_DSS_GFX:
751 BUG();
752 return 0;
753 case OMAP_DSS_VIDEO1:
754 case OMAP_DSS_VIDEO2:
755 return 0x0034 + i * 0x8;
756 case OMAP_DSS_VIDEO3:
757 case OMAP_DSS_WB:
758 return 0x0010 + i * 0x8;
759 default:
760 BUG();
761 return 0;
762 }
763 }
764
765 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane,u16 i)766 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane_id plane, u16 i)
767 {
768 switch (plane) {
769 case OMAP_DSS_GFX:
770 BUG();
771 return 0;
772 case OMAP_DSS_VIDEO1:
773 return 0x058C + i * 0x8;
774 case OMAP_DSS_VIDEO2:
775 return 0x0568 + i * 0x8;
776 case OMAP_DSS_VIDEO3:
777 return 0x0430 + i * 0x8;
778 case OMAP_DSS_WB:
779 return 0x02A0 + i * 0x8;
780 default:
781 BUG();
782 return 0;
783 }
784 }
785
786 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane,u16 i)787 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane_id plane, u16 i)
788 {
789 switch (plane) {
790 case OMAP_DSS_GFX:
791 BUG();
792 return 0;
793 case OMAP_DSS_VIDEO1:
794 case OMAP_DSS_VIDEO2:
795 return 0x0038 + i * 0x8;
796 case OMAP_DSS_VIDEO3:
797 case OMAP_DSS_WB:
798 return 0x0014 + i * 0x8;
799 default:
800 BUG();
801 return 0;
802 }
803 }
804
805 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane,u16 i)806 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane_id plane, u16 i)
807 {
808 switch (plane) {
809 case OMAP_DSS_GFX:
810 BUG();
811 return 0;
812 case OMAP_DSS_VIDEO1:
813 return 0x0590 + i * 8;
814 case OMAP_DSS_VIDEO2:
815 return 0x056C + i * 0x8;
816 case OMAP_DSS_VIDEO3:
817 return 0x0434 + i * 0x8;
818 case OMAP_DSS_WB:
819 return 0x02A4 + i * 0x8;
820 default:
821 BUG();
822 return 0;
823 }
824 }
825
826 /* coef index i = {0, 1, 2, 3, 4,} */
DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane,u16 i)827 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane_id plane, u16 i)
828 {
829 switch (plane) {
830 case OMAP_DSS_GFX:
831 BUG();
832 return 0;
833 case OMAP_DSS_VIDEO1:
834 case OMAP_DSS_VIDEO2:
835 case OMAP_DSS_VIDEO3:
836 case OMAP_DSS_WB:
837 return 0x0074 + i * 0x4;
838 default:
839 BUG();
840 return 0;
841 }
842 }
843
844 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane,u16 i)845 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane_id plane, u16 i)
846 {
847 switch (plane) {
848 case OMAP_DSS_GFX:
849 BUG();
850 return 0;
851 case OMAP_DSS_VIDEO1:
852 return 0x0124 + i * 0x4;
853 case OMAP_DSS_VIDEO2:
854 return 0x00B4 + i * 0x4;
855 case OMAP_DSS_VIDEO3:
856 case OMAP_DSS_WB:
857 return 0x0050 + i * 0x4;
858 default:
859 BUG();
860 return 0;
861 }
862 }
863
864 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane,u16 i)865 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane_id plane, u16 i)
866 {
867 switch (plane) {
868 case OMAP_DSS_GFX:
869 BUG();
870 return 0;
871 case OMAP_DSS_VIDEO1:
872 return 0x05CC + i * 0x4;
873 case OMAP_DSS_VIDEO2:
874 return 0x05A8 + i * 0x4;
875 case OMAP_DSS_VIDEO3:
876 return 0x0470 + i * 0x4;
877 case OMAP_DSS_WB:
878 return 0x02E0 + i * 0x4;
879 default:
880 BUG();
881 return 0;
882 }
883 }
884
DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)885 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane_id plane)
886 {
887 switch (plane) {
888 case OMAP_DSS_GFX:
889 return 0x01AC;
890 case OMAP_DSS_VIDEO1:
891 return 0x0174;
892 case OMAP_DSS_VIDEO2:
893 return 0x00E8;
894 case OMAP_DSS_VIDEO3:
895 return 0x00A0;
896 default:
897 BUG();
898 return 0;
899 }
900 }
901
DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)902 static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane_id plane)
903 {
904 switch (plane) {
905 case OMAP_DSS_GFX:
906 return 0x0860;
907 case OMAP_DSS_VIDEO1:
908 return 0x0864;
909 case OMAP_DSS_VIDEO2:
910 return 0x0868;
911 case OMAP_DSS_VIDEO3:
912 return 0x086c;
913 case OMAP_DSS_WB:
914 return 0x0870;
915 default:
916 BUG();
917 return 0;
918 }
919 }
920 #endif
921
