1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * (C) COPYRIGHT 2018 ARM Limited. All rights reserved.
4 * Author: James.Qian.Wang <james.qian.wang@arm.com>
5 *
6 */
7 #ifndef _D71_REG_H_
8 #define _D71_REG_H_
9
10 /* Common block registers offset */
11 #define BLK_BLOCK_INFO 0x000
12 #define BLK_PIPELINE_INFO 0x004
13 #define BLK_VALID_INPUT_ID0 0x020
14 #define BLK_OUTPUT_ID0 0x060
15 #define BLK_INPUT_ID0 0x080
16 #define BLK_IRQ_RAW_STATUS 0x0A0
17 #define BLK_IRQ_CLEAR 0x0A4
18 #define BLK_IRQ_MASK 0x0A8
19 #define BLK_IRQ_STATUS 0x0AC
20 #define BLK_STATUS 0x0B0
21 #define BLK_INFO 0x0C0
22 #define BLK_CONTROL 0x0D0
23 #define BLK_SIZE 0x0D4
24 #define BLK_IN_SIZE 0x0E0
25
26 #define BLK_P0_PTR_LOW 0x100
27 #define BLK_P0_PTR_HIGH 0x104
28 #define BLK_P0_STRIDE 0x108
29 #define BLK_P1_PTR_LOW 0x110
30 #define BLK_P1_PTR_HIGH 0x114
31 #define BLK_P1_STRIDE 0x118
32 #define BLK_P2_PTR_LOW 0x120
33 #define BLK_P2_PTR_HIGH 0x124
34
35 #define BLOCK_INFO_N_SUBBLKS(x) ((x) & 0x000F)
36 #define BLOCK_INFO_BLK_ID(x) (((x) & 0x00F0) >> 4)
37 #define BLOCK_INFO_BLK_TYPE(x) (((x) & 0xFF00) >> 8)
38 #define BLOCK_INFO_INPUT_ID(x) ((x) & 0xFFF0)
39 #define BLOCK_INFO_TYPE_ID(x) (((x) & 0x0FF0) >> 4)
40
41 #define PIPELINE_INFO_N_OUTPUTS(x) ((x) & 0x000F)
42 #define PIPELINE_INFO_N_VALID_INPUTS(x) (((x) & 0x0F00) >> 8)
43
44 /* Common block control register bits */
45 #define BLK_CTRL_EN BIT(0)
46 /* Common size macro */
47 #define HV_SIZE(h, v) (((h) & 0x1FFF) + (((v) & 0x1FFF) << 16))
48 #define HV_OFFSET(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
49 #define HV_CROP(h, v) (((h) & 0xFFF) + (((v) & 0xFFF) << 16))
50
51 /* AD_CONTROL register */
52 #define AD_CONTROL 0x160
53
54 /* AD_CONTROL register bits */
55 #define AD_AEN BIT(0)
56 #define AD_YT BIT(1)
57 #define AD_BS BIT(2)
58 #define AD_WB BIT(3)
59 #define AD_TH BIT(4)
60
61 /* Global Control Unit */
62 #define GLB_ARCH_ID 0x000
63 #define GLB_CORE_ID 0x004
64 #define GLB_CORE_INFO 0x008
65 #define GLB_IRQ_STATUS 0x010
66
67 #define GCU_CONFIG_VALID0 0x0D4
68 #define GCU_CONFIG_VALID1 0x0D8
69
70 /* GCU_CONTROL_BITS */
71 #define GCU_CONTROL_MODE(x) ((x) & 0x7)
72 #define GCU_CONTROL_SRST BIT(16)
73
74 /* GCU opmode */
75 #define INACTIVE_MODE 0
76 #define TBU_CONNECT_MODE 1
77 #define TBU_DISCONNECT_MODE 2
78 #define DO0_ACTIVE_MODE 3
79 #define DO1_ACTIVE_MODE 4
80 #define DO01_ACTIVE_MODE 5
81
82 /* GLB_IRQ_STATUS bits */
83 #define GLB_IRQ_STATUS_GCU BIT(0)
84 #define GLB_IRQ_STATUS_LPU0 BIT(8)
85 #define GLB_IRQ_STATUS_LPU1 BIT(9)
86 #define GLB_IRQ_STATUS_ATU0 BIT(10)
87 #define GLB_IRQ_STATUS_ATU1 BIT(11)
88 #define GLB_IRQ_STATUS_ATU2 BIT(12)
89 #define GLB_IRQ_STATUS_ATU3 BIT(13)
90 #define GLB_IRQ_STATUS_CU0 BIT(16)
91 #define GLB_IRQ_STATUS_CU1 BIT(17)
92 #define GLB_IRQ_STATUS_DOU0 BIT(24)
93 #define GLB_IRQ_STATUS_DOU1 BIT(25)
94
95 #define GLB_IRQ_STATUS_PIPE0 (GLB_IRQ_STATUS_LPU0 |\
96 GLB_IRQ_STATUS_ATU0 |\
97 GLB_IRQ_STATUS_ATU1 |\
98 GLB_IRQ_STATUS_CU0 |\
99 GLB_IRQ_STATUS_DOU0)
100
101 #define GLB_IRQ_STATUS_PIPE1 (GLB_IRQ_STATUS_LPU1 |\
102 GLB_IRQ_STATUS_ATU2 |\
103 GLB_IRQ_STATUS_ATU3 |\
104 GLB_IRQ_STATUS_CU1 |\
105 GLB_IRQ_STATUS_DOU1)
106
107 #define GLB_IRQ_STATUS_ATU (GLB_IRQ_STATUS_ATU0 |\
108 GLB_IRQ_STATUS_ATU1 |\
109 GLB_IRQ_STATUS_ATU2 |\
110 GLB_IRQ_STATUS_ATU3)
111
112 /* GCU_IRQ_BITS */
113 #define GCU_IRQ_CVAL0 BIT(0)
114 #define GCU_IRQ_CVAL1 BIT(1)
115 #define GCU_IRQ_MODE BIT(4)
116 #define GCU_IRQ_ERR BIT(11)
117
118 /* GCU_STATUS_BITS */
119 #define GCU_STATUS_MODE(x) ((x) & 0x7)
120 #define GCU_STATUS_MERR BIT(4)
121 #define GCU_STATUS_TCS0 BIT(8)
122 #define GCU_STATUS_TCS1 BIT(9)
123 #define GCU_STATUS_ACTIVE BIT(31)
124
125 /* GCU_CONFIG_VALIDx BITS */
126 #define GCU_CONFIG_CVAL BIT(0)
127
128 /* PERIPHERAL registers */
129 #define PERIPH_MAX_LINE_SIZE BIT(0)
130 #define PERIPH_NUM_RICH_LAYERS BIT(4)
131 #define PERIPH_SPLIT_EN BIT(8)
132 #define PERIPH_TBU_EN BIT(12)
133 #define PERIPH_AFBC_DMA_EN BIT(16)
134 #define PERIPH_CONFIGURATION_ID 0x1D4
135
136 /* LPU register */
137 #define LPU_TBU_STATUS 0x0B4
138 #define LPU_RAXI_CONTROL 0x0D0
139 #define LPU_WAXI_CONTROL 0x0D4
140 #define LPU_TBU_CONTROL 0x0D8
141
142 /* LPU_xAXI_CONTROL_BITS */
143 #define TO_RAXI_AOUTSTDCAPB(x) (x)
144 #define TO_RAXI_BOUTSTDCAPB(x) ((x) << 8)
145 #define TO_RAXI_BEN(x) ((x) << 15)
146 #define TO_xAXI_BURSTLEN(x) ((x) << 16)
147 #define TO_xAXI_AxQOS(x) ((x) << 24)
148 #define TO_xAXI_ORD(x) ((x) << 31)
149 #define TO_WAXI_OUTSTDCAPB(x) (x)
150
151 #define RAXI_AOUTSTDCAPB_MASK 0x7F
152 #define RAXI_BOUTSTDCAPB_MASK 0x7F00
153 #define RAXI_BEN_MASK BIT(15)
154 #define xAXI_BURSTLEN_MASK 0x3F0000
155 #define xAXI_AxQOS_MASK 0xF000000
156 #define xAXI_ORD_MASK BIT(31)
157 #define WAXI_OUTSTDCAPB_MASK 0x3F
158
159 /* LPU_TBU_CONTROL BITS */
160 #define TO_TBU_DOUTSTDCAPB(x) (x)
161 #define TBU_DOUTSTDCAPB_MASK 0x3F
162
163 /* LPU_IRQ_BITS */
164 #define LPU_IRQ_IBSY BIT(10)
165 #define LPU_IRQ_ERR BIT(11)
166 #define LPU_IRQ_EOW BIT(12)
167 #define LPU_IRQ_PL0 BIT(13)
168
169 /* LPU_STATUS_BITS */
170 #define LPU_STATUS_AXIED(x) ((x) & 0xF)
171 #define LPU_STATUS_AXIE BIT(4)
172 #define LPU_STATUS_AXIRP BIT(5)
173 #define LPU_STATUS_AXIWP BIT(6)
174 #define LPU_STATUS_ACE0 BIT(16)
175 #define LPU_STATUS_ACE1 BIT(17)
176 #define LPU_STATUS_ACE2 BIT(18)
177 #define LPU_STATUS_ACE3 BIT(19)
178 #define LPU_STATUS_ACTIVE BIT(31)
179
180 #define AXIEID_MASK 0xF
181 #define AXIE_MASK LPU_STATUS_AXIE
182 #define AXIRP_MASK LPU_STATUS_AXIRP
183 #define AXIWP_MASK LPU_STATUS_AXIWP
184
185 #define FROM_AXIEID(reg) ((reg) & AXIEID_MASK)
186 #define TO_AXIE(x) ((x) << 4)
187 #define FROM_AXIRP(reg) (((reg) & AXIRP_MASK) >> 5)
188 #define FROM_AXIWP(reg) (((reg) & AXIWP_MASK) >> 6)
189
190 /* LPU_TBU_STATUS_BITS */
191 #define LPU_TBU_STATUS_TCF BIT(1)
192 #define LPU_TBU_STATUS_TTNG BIT(2)
193 #define LPU_TBU_STATUS_TITR BIT(8)
194 #define LPU_TBU_STATUS_TEMR BIT(16)
195 #define LPU_TBU_STATUS_TTF BIT(31)
196
197 /* LPU_TBU_CONTROL BITS */
198 #define LPU_TBU_CTRL_TLBPEN BIT(16)
199
200 /* CROSSBAR CONTROL BITS */
201 #define CBU_INPUT_CTRL_EN BIT(0)
202 #define CBU_NUM_INPUT_IDS 5
203 #define CBU_NUM_OUTPUT_IDS 5
204
205 /* CU register */
206 #define CU_BG_COLOR 0x0DC
207 #define CU_INPUT0_SIZE 0x0E0
208 #define CU_INPUT0_OFFSET 0x0E4
209 #define CU_INPUT0_CONTROL 0x0E8
210 #define CU_INPUT1_SIZE 0x0F0
211 #define CU_INPUT1_OFFSET 0x0F4
212 #define CU_INPUT1_CONTROL 0x0F8
213 #define CU_INPUT2_SIZE 0x100
214 #define CU_INPUT2_OFFSET 0x104
215 #define CU_INPUT2_CONTROL 0x108
216 #define CU_INPUT3_SIZE 0x110
217 #define CU_INPUT3_OFFSET 0x114
218 #define CU_INPUT3_CONTROL 0x118
219 #define CU_INPUT4_SIZE 0x120
220 #define CU_INPUT4_OFFSET 0x124
221 #define CU_INPUT4_CONTROL 0x128
222
223 #define CU_PER_INPUT_REGS 4
224
225 #define CU_NUM_INPUT_IDS 5
226 #define CU_NUM_OUTPUT_IDS 1
227
228 /* CU control register bits */
229 #define CU_CTRL_COPROC BIT(0)
230
231 /* CU_IRQ_BITS */
232 #define CU_IRQ_OVR BIT(9)
233 #define CU_IRQ_ERR BIT(11)
234
235 /* CU_STATUS_BITS */
236 #define CU_STATUS_CPE BIT(0)
237 #define CU_STATUS_ZME BIT(1)
238 #define CU_STATUS_CFGE BIT(2)
239 #define CU_STATUS_ACTIVE BIT(31)
240
241 /* CU input control register bits */
242 #define CU_INPUT_CTRL_EN BIT(0)
243 #define CU_INPUT_CTRL_PAD BIT(1)
244 #define CU_INPUT_CTRL_PMUL BIT(2)
245 #define CU_INPUT_CTRL_ALPHA(x) (((x) & 0xFF) << 8)
246
247 /* DOU register */
248
249 /* DOU_IRQ_BITS */
250 #define DOU_IRQ_UND BIT(8)
251 #define DOU_IRQ_ERR BIT(11)
252 #define DOU_IRQ_PL0 BIT(13)
253 #define DOU_IRQ_PL1 BIT(14)
254
255 /* DOU_STATUS_BITS */
256 #define DOU_STATUS_DRIFTTO BIT(0)
257 #define DOU_STATUS_FRAMETO BIT(1)
258 #define DOU_STATUS_TETO BIT(2)
259 #define DOU_STATUS_CSCE BIT(8)
260 #define DOU_STATUS_ACTIVE BIT(31)
261
262 /* Layer registers */
263 #define LAYER_INFO 0x0C0
264 #define LAYER_R_CONTROL 0x0D4
265 #define LAYER_FMT 0x0D8
266 #define LAYER_LT_COEFFTAB 0x0DC
267 #define LAYER_PALPHA 0x0E4
268
269 #define LAYER_YUV_RGB_COEFF0 0x130
270
271 #define LAYER_AD_H_CROP 0x164
272 #define LAYER_AD_V_CROP 0x168
273
274 #define LAYER_RGB_RGB_COEFF0 0x170
275
276 /* L_CONTROL_BITS */
277 #define L_EN BIT(0)
278 #define L_IT BIT(4)
279 #define L_R2R BIT(5)
280 #define L_FT BIT(6)
281 #define L_ROT(x) (((x) & 3) << 8)
282 #define L_HFLIP BIT(10)
283 #define L_VFLIP BIT(11)
284 #define L_TBU_EN BIT(16)
285 #define L_A_RCACHE(x) (((x) & 0xF) << 28)
286 #define L_ROT_R0 0
287 #define L_ROT_R90 1
288 #define L_ROT_R180 2
289 #define L_ROT_R270 3
290
291 /* LAYER_R_CONTROL BITS */
292 #define LR_CHI422_BILINEAR 0
293 #define LR_CHI422_REPLICATION 1
294 #define LR_CHI420_JPEG (0 << 2)
295 #define LR_CHI420_MPEG (1 << 2)
296
297 #define L_ITSEL(x) ((x) & 0xFFF)
298 #define L_FTSEL(x) (((x) & 0xFFF) << 16)
299
300 #define LAYER_PER_PLANE_REGS 4
301
302 /* Layer_WR registers */
303 #define LAYER_WR_PROG_LINE 0x0D4
304 #define LAYER_WR_FORMAT 0x0D8
305
306 /* Layer_WR control bits */
307 #define LW_OFM BIT(4)
308 #define LW_LALPHA(x) (((x) & 0xFF) << 8)
309 #define LW_A_WCACHE(x) (((x) & 0xF) << 28)
310 #define LW_TBU_EN BIT(16)
311
312 #define AxCACHE_MASK 0xF0000000
313
314 /* Layer AXI R/W cache setting */
315 #define AxCACHE_B BIT(0) /* Bufferable */
316 #define AxCACHE_M BIT(1) /* Modifiable */
317 #define AxCACHE_RA BIT(2) /* Read-Allocate */
318 #define AxCACHE_WA BIT(3) /* Write-Allocate */
319
320 /* Layer info bits */
321 #define L_INFO_RF BIT(0)
322 #define L_INFO_CM BIT(1)
323 #define L_INFO_ABUF_SIZE(x) (((x) >> 4) & 0x7)
324
325 /* Scaler registers */
326 #define SC_COEFFTAB 0x0DC
327 #define SC_OUT_SIZE 0x0E4
328 #define SC_H_CROP 0x0E8
329 #define SC_V_CROP 0x0EC
330 #define SC_H_INIT_PH 0x0F0
331 #define SC_H_DELTA_PH 0x0F4
332 #define SC_V_INIT_PH 0x0F8
333 #define SC_V_DELTA_PH 0x0FC
334 #define SC_ENH_LIMITS 0x130
335 #define SC_ENH_COEFF0 0x134
336
337 #define SC_MAX_ENH_COEFF 9
338
339 /* SC_CTRL_BITS */
340 #define SC_CTRL_SCL BIT(0)
341 #define SC_CTRL_LS BIT(1)
342 #define SC_CTRL_AP BIT(4)
343 #define SC_CTRL_IENH BIT(8)
344 #define SC_CTRL_RGBSM BIT(16)
345 #define SC_CTRL_ASM BIT(17)
346
347 #define SC_VTSEL(vtal) ((vtal) << 16)
348
349 #define SC_NUM_INPUTS_IDS 1
350 #define SC_NUM_OUTPUTS_IDS 1
351
352 #define MG_NUM_INPUTS_IDS 2
353 #define MG_NUM_OUTPUTS_IDS 1
354
355 /* Merger registers */
356 #define MG_INPUT_ID0 BLK_INPUT_ID0
357 #define MG_INPUT_ID1 (MG_INPUT_ID0 + 4)
358 #define MG_SIZE BLK_SIZE
359
360 /* Splitter registers */
361 #define SP_OVERLAP_SIZE 0xD8
362
363 /* Backend registers */
364 #define BS_INFO 0x0C0
365 #define BS_PROG_LINE 0x0D4
366 #define BS_PREFETCH_LINE 0x0D8
367 #define BS_BG_COLOR 0x0DC
368 #define BS_ACTIVESIZE 0x0E0
369 #define BS_HINTERVALS 0x0E4
370 #define BS_VINTERVALS 0x0E8
371 #define BS_SYNC 0x0EC
372 #define BS_DRIFT_TO 0x100
373 #define BS_FRAME_TO 0x104
374 #define BS_TE_TO 0x108
375 #define BS_T0_INTERVAL 0x110
376 #define BS_T1_INTERVAL 0x114
377 #define BS_T2_INTERVAL 0x118
378 #define BS_CRC0_LOW 0x120
379 #define BS_CRC0_HIGH 0x124
380 #define BS_CRC1_LOW 0x128
381 #define BS_CRC1_HIGH 0x12C
382 #define BS_USER 0x130
383
384 /* BS control register bits */
385 #define BS_CTRL_EN BIT(0)
386 #define BS_CTRL_VM BIT(1)
387 #define BS_CTRL_BM BIT(2)
388 #define BS_CTRL_HMASK BIT(4)
389 #define BS_CTRL_VD BIT(5)
390 #define BS_CTRL_TE BIT(8)
391 #define BS_CTRL_TS BIT(9)
392 #define BS_CTRL_TM BIT(12)
393 #define BS_CTRL_DL BIT(16)
394 #define BS_CTRL_SBS BIT(17)
395 #define BS_CTRL_CRC BIT(18)
396 #define BS_CTRL_PM BIT(20)
397
398 /* BS active size/intervals */
399 #define BS_H_INTVALS(hfp, hbp) (((hfp) & 0xFFF) + (((hbp) & 0x3FF) << 16))
400 #define BS_V_INTVALS(vfp, vbp) (((vfp) & 0x3FFF) + (((vbp) & 0xFF) << 16))
401
402 /* BS_SYNC bits */
403 #define BS_SYNC_HSW(x) ((x) & 0x3FF)
404 #define BS_SYNC_HSP BIT(12)
405 #define BS_SYNC_VSW(x) (((x) & 0xFF) << 16)
406 #define BS_SYNC_VSP BIT(28)
407
408 #define BS_NUM_INPUT_IDS 0
409 #define BS_NUM_OUTPUT_IDS 0
410
411 /* Image process registers */
412 #define IPS_DEPTH 0x0D8
413 #define IPS_RGB_RGB_COEFF0 0x130
414 #define IPS_RGB_YUV_COEFF0 0x170
415
416 #define IPS_DEPTH_MARK 0xF
417
418 /* IPS control register bits */
419 #define IPS_CTRL_RGB BIT(0)
420 #define IPS_CTRL_FT BIT(4)
421 #define IPS_CTRL_YUV BIT(8)
422 #define IPS_CTRL_CHD422 BIT(9)
423 #define IPS_CTRL_CHD420 BIT(10)
424 #define IPS_CTRL_LPF BIT(11)
425 #define IPS_CTRL_DITH BIT(12)
426 #define IPS_CTRL_CLAMP BIT(16)
427 #define IPS_CTRL_SBS BIT(17)
428
429 /* IPS info register bits */
430 #define IPS_INFO_CHD420 BIT(10)
431
432 #define IPS_NUM_INPUT_IDS 2
433 #define IPS_NUM_OUTPUT_IDS 1
434
435 /* FT_COEFF block registers */
436 #define FT_COEFF0 0x80
437 #define GLB_IT_COEFF 0x80
438
439 /* GLB_SC_COEFF registers */
440 #define GLB_SC_COEFF_ADDR 0x0080
441 #define GLB_SC_COEFF_DATA 0x0084
442 #define GLB_LT_COEFF_DATA 0x0080
443
444 #define GLB_SC_COEFF_MAX_NUM 1024
445 #define GLB_LT_COEFF_NUM 65
446 /* GLB_SC_ADDR */
447 #define SC_COEFF_R_ADDR BIT(18)
448 #define SC_COEFF_G_ADDR BIT(17)
449 #define SC_COEFF_B_ADDR BIT(16)
450
451 #define SC_COEFF_DATA(x, y) (((y) & 0xFFFF) | (((x) & 0xFFFF) << 16))
452
453 enum d71_blk_type {
454 D71_BLK_TYPE_GCU = 0x00,
455 D71_BLK_TYPE_LPU = 0x01,
456 D71_BLK_TYPE_CU = 0x02,
457 D71_BLK_TYPE_DOU = 0x03,
458 D71_BLK_TYPE_AEU = 0x04,
459 D71_BLK_TYPE_GLB_LT_COEFF = 0x05,
460 D71_BLK_TYPE_GLB_SCL_COEFF = 0x06, /* SH/SV scaler coeff */
461 D71_BLK_TYPE_GLB_SC_COEFF = 0x07,
462 D71_BLK_TYPE_PERIPH = 0x08,
463 D71_BLK_TYPE_LPU_TRUSTED = 0x09,
464 D71_BLK_TYPE_AEU_TRUSTED = 0x0A,
465 D71_BLK_TYPE_LPU_LAYER = 0x10,
466 D71_BLK_TYPE_LPU_WB_LAYER = 0x11,
467 D71_BLK_TYPE_CU_SPLITTER = 0x20,
468 D71_BLK_TYPE_CU_SCALER = 0x21,
469 D71_BLK_TYPE_CU_MERGER = 0x22,
470 D71_BLK_TYPE_DOU_IPS = 0x30,
471 D71_BLK_TYPE_DOU_BS = 0x31,
472 D71_BLK_TYPE_DOU_FT_COEFF = 0x32,
473 D71_BLK_TYPE_AEU_DS = 0x40,
474 D71_BLK_TYPE_AEU_AES = 0x41,
475 D71_BLK_TYPE_RESERVED = 0xFF
476 };
477
478 /* Constant of components */
479 #define D71_MAX_PIPELINE 2
480 #define D71_PIPELINE_MAX_SCALERS 2
481 #define D71_PIPELINE_MAX_LAYERS 4
482
483 #define D71_MAX_GLB_IT_COEFF 3
484 #define D71_MAX_GLB_SCL_COEFF 4
485
486 #define D71_MAX_LAYERS_PER_LPU 4
487 #define D71_BLOCK_MAX_INPUT 9
488 #define D71_BLOCK_MAX_OUTPUT 5
489 #define D71_MAX_SC_PER_CU 2
490
491 #define D71_BLOCK_OFFSET_PERIPH 0xFE00
492 #define D71_BLOCK_SIZE 0x0200
493
494 #define D71_DEFAULT_PREPRETCH_LINE 5
495 #define D71_BUS_WIDTH_16_BYTES 16
496
497 #define D71_MIN_LINE_SIZE 64
498 #define D71_MIN_VERTICAL_SIZE 64
499 #define D71_SC_MIN_LIN_SIZE 4
500 #define D71_SC_MIN_VERTICAL_SIZE 4
501 #define D71_SC_MAX_LIN_SIZE 2048
502 #define D71_SC_MAX_VERTICAL_SIZE 4096
503
504 #define D71_SC_MAX_UPSCALING 64
505 #define D71_SC_MAX_DOWNSCALING 6
506 #define D71_SC_SPLIT_OVERLAP 8
507 #define D71_SC_ENH_SPLIT_OVERLAP 1
508
509 #define D71_MG_MIN_MERGED_SIZE 4
510 #define D71_MG_MAX_MERGED_HSIZE 4032
511 #define D71_MG_MAX_MERGED_VSIZE 4096
512
513 #define D71_PALPHA_DEF_MAP 0xFFAA5500
514 #define D71_LAYER_CONTROL_DEFAULT 0x30000000
515 #define D71_WB_LAYER_CONTROL_DEFAULT 0x3000FF00
516 #define D71_BS_CONTROL_DEFAULT 0x00000002
517
518 struct block_header {
519 u32 block_info;
520 u32 pipeline_info;
521 u32 input_ids[D71_BLOCK_MAX_INPUT];
522 u32 output_ids[D71_BLOCK_MAX_OUTPUT];
523 };
524
get_block_type(struct block_header * blk)525 static inline u32 get_block_type(struct block_header *blk)
526 {
527 return BLOCK_INFO_BLK_TYPE(blk->block_info);
528 }
529
530 #endif /* !_D71_REG_H_ */
531
