1 /* Copyright 2012-15 Advanced Micro Devices, Inc. 2 * 3 * Permission is hereby granted, free of charge, to any person obtaining a 4 * copy of this software and associated documentation files (the "Software"), 5 * to deal in the Software without restriction, including without limitation 6 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 7 * and/or sell copies of the Software, and to permit persons to whom the 8 * Software is furnished to do so, subject to the following conditions: 9 * 10 * The above copyright notice and this permission notice shall be included in 11 * all copies or substantial portions of the Software. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 17 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 18 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 19 * OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * Authors: AMD 22 * 23 */ 24 25 #ifndef __DC_CLOCK_SOURCE_DCE_H__ 26 #define __DC_CLOCK_SOURCE_DCE_H__ 27 28 #include "../inc/clock_source.h" 29 30 #define TO_DCE110_CLK_SRC(clk_src)\ 31 container_of(clk_src, struct dce110_clk_src, base) 32 33 #define CS_COMMON_REG_LIST_DCE_100_110(id) \ 34 SRI(RESYNC_CNTL, PIXCLK, id), \ 35 SRI(PLL_CNTL, BPHYC_PLL, id) 36 37 #define CS_COMMON_REG_LIST_DCE_80(id) \ 38 SRI(RESYNC_CNTL, PIXCLK, id), \ 39 SRI(PLL_CNTL, DCCG_PLL, id) 40 41 #define CS_COMMON_REG_LIST_DCE_112(id) \ 42 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) 43 44 45 #define CS_SF(reg_name, field_name, post_fix)\ 46 .field_name = reg_name ## __ ## field_name ## post_fix 47 48 #define CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh)\ 49 CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ 50 CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ 51 CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ 52 CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) 53 54 #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ 55 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 56 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) 57 58 #if defined(CONFIG_DRM_AMD_DC_DCN1_0) 59 60 #define CS_COMMON_REG_LIST_DCN1_0(index, pllid) \ 61 SRI(PIXCLK_RESYNC_CNTL, PHYPLL, pllid),\ 62 SRII(PHASE, DP_DTO, 0),\ 63 SRII(PHASE, DP_DTO, 1),\ 64 SRII(PHASE, DP_DTO, 2),\ 65 SRII(PHASE, DP_DTO, 3),\ 66 SRII(MODULO, DP_DTO, 0),\ 67 SRII(MODULO, DP_DTO, 1),\ 68 SRII(MODULO, DP_DTO, 2),\ 69 SRII(MODULO, DP_DTO, 3),\ 70 SRII(PIXEL_RATE_CNTL, OTG, 0), \ 71 SRII(PIXEL_RATE_CNTL, OTG, 1), \ 72 SRII(PIXEL_RATE_CNTL, OTG, 2), \ 73 SRII(PIXEL_RATE_CNTL, OTG, 3) 74 75 #define CS_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 76 CS_SF(DP_DTO0_PHASE, DP_DTO0_PHASE, mask_sh),\ 77 CS_SF(DP_DTO0_MODULO, DP_DTO0_MODULO, mask_sh),\ 78 CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ 79 CS_SF(OTG0_PIXEL_RATE_CNTL, DP_DTO0_ENABLE, mask_sh) 80 81 #endif 82 83 #define CS_REG_FIELD_LIST(type) \ 84 type PLL_REF_DIV_SRC; \ 85 type DCCG_DEEP_COLOR_CNTL1; \ 86 type PHYPLLA_DCCG_DEEP_COLOR_CNTL; \ 87 type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ 88 type PLL_POST_DIV_PIXCLK; \ 89 type PLL_REF_DIV; \ 90 type DP_DTO0_PHASE; \ 91 type DP_DTO0_MODULO; \ 92 type DP_DTO0_ENABLE; 93 94 struct dce110_clk_src_shift { 95 CS_REG_FIELD_LIST(uint8_t) 96 }; 97 98 struct dce110_clk_src_mask{ 99 CS_REG_FIELD_LIST(uint32_t) 100 }; 101 102 struct dce110_clk_src_regs { 103 uint32_t RESYNC_CNTL; 104 uint32_t PIXCLK_RESYNC_CNTL; 105 uint32_t PLL_CNTL; 106 107 /* below are for DTO. 108 * todo: should probably use different struct to not waste space 109 */ 110 uint32_t PHASE[MAX_PIPES]; 111 uint32_t MODULO[MAX_PIPES]; 112 uint32_t PIXEL_RATE_CNTL[MAX_PIPES]; 113 }; 114 115 struct dce110_clk_src { 116 struct clock_source base; 117 const struct dce110_clk_src_regs *regs; 118 const struct dce110_clk_src_mask *cs_mask; 119 const struct dce110_clk_src_shift *cs_shift; 120 struct dc_bios *bios; 121 122 struct spread_spectrum_data *dp_ss_params; 123 uint32_t dp_ss_params_cnt; 124 struct spread_spectrum_data *hdmi_ss_params; 125 uint32_t hdmi_ss_params_cnt; 126 struct spread_spectrum_data *dvi_ss_params; 127 uint32_t dvi_ss_params_cnt; 128 129 uint32_t ext_clk_khz; 130 uint32_t ref_freq_khz; 131 132 struct calc_pll_clock_source calc_pll; 133 struct calc_pll_clock_source calc_pll_hdmi; 134 }; 135 136 bool dce110_clk_src_construct( 137 struct dce110_clk_src *clk_src, 138 struct dc_context *ctx, 139 struct dc_bios *bios, 140 enum clock_source_id, 141 const struct dce110_clk_src_regs *regs, 142 const struct dce110_clk_src_shift *cs_shift, 143 const struct dce110_clk_src_mask *cs_mask); 144 145 #endif 146
