1 /* Freescale Integrated Flash Controller
2 *
3 * Copyright 2011 Freescale Semiconductor, Inc
4 *
5 * Author: Dipen Dudhat <dipen.dudhat@freescale.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #ifndef __ASM_FSL_IFC_H
23 #define __ASM_FSL_IFC_H
24
25 #include <linux/compiler.h>
26 #include <linux/types.h>
27 #include <linux/io.h>
28
29 #include <linux/of_platform.h>
30 #include <linux/interrupt.h>
31
32 /*
33 * The actual number of banks implemented depends on the IFC version
34 * - IFC version 1.0 implements 4 banks.
35 * - IFC version 1.1 onward implements 8 banks.
36 */
37 #define FSL_IFC_BANK_COUNT 8
38
39 #define FSL_IFC_VERSION_MASK 0x0F0F0000
40 #define FSL_IFC_VERSION_1_0_0 0x01000000
41 #define FSL_IFC_VERSION_1_1_0 0x01010000
42 #define FSL_IFC_VERSION_2_0_0 0x02000000
43
44 #define PGOFFSET_64K (64*1024)
45 #define PGOFFSET_4K (4*1024)
46
47 /*
48 * CSPR - Chip Select Property Register
49 */
50 #define CSPR_BA 0xFFFF0000
51 #define CSPR_BA_SHIFT 16
52 #define CSPR_PORT_SIZE 0x00000180
53 #define CSPR_PORT_SIZE_SHIFT 7
54 /* Port Size 8 bit */
55 #define CSPR_PORT_SIZE_8 0x00000080
56 /* Port Size 16 bit */
57 #define CSPR_PORT_SIZE_16 0x00000100
58 /* Port Size 32 bit */
59 #define CSPR_PORT_SIZE_32 0x00000180
60 /* Write Protect */
61 #define CSPR_WP 0x00000040
62 #define CSPR_WP_SHIFT 6
63 /* Machine Select */
64 #define CSPR_MSEL 0x00000006
65 #define CSPR_MSEL_SHIFT 1
66 /* NOR */
67 #define CSPR_MSEL_NOR 0x00000000
68 /* NAND */
69 #define CSPR_MSEL_NAND 0x00000002
70 /* GPCM */
71 #define CSPR_MSEL_GPCM 0x00000004
72 /* Bank Valid */
73 #define CSPR_V 0x00000001
74 #define CSPR_V_SHIFT 0
75
76 /*
77 * Address Mask Register
78 */
79 #define IFC_AMASK_MASK 0xFFFF0000
80 #define IFC_AMASK_SHIFT 16
81 #define IFC_AMASK(n) (IFC_AMASK_MASK << \
82 (__ilog2(n) - IFC_AMASK_SHIFT))
83
84 /*
85 * Chip Select Option Register IFC_NAND Machine
86 */
87 /* Enable ECC Encoder */
88 #define CSOR_NAND_ECC_ENC_EN 0x80000000
89 #define CSOR_NAND_ECC_MODE_MASK 0x30000000
90 /* 4 bit correction per 520 Byte sector */
91 #define CSOR_NAND_ECC_MODE_4 0x00000000
92 /* 8 bit correction per 528 Byte sector */
93 #define CSOR_NAND_ECC_MODE_8 0x10000000
94 /* Enable ECC Decoder */
95 #define CSOR_NAND_ECC_DEC_EN 0x04000000
96 /* Row Address Length */
97 #define CSOR_NAND_RAL_MASK 0x01800000
98 #define CSOR_NAND_RAL_SHIFT 20
99 #define CSOR_NAND_RAL_1 0x00000000
100 #define CSOR_NAND_RAL_2 0x00800000
101 #define CSOR_NAND_RAL_3 0x01000000
102 #define CSOR_NAND_RAL_4 0x01800000
103 /* Page Size 512b, 2k, 4k */
104 #define CSOR_NAND_PGS_MASK 0x00180000
105 #define CSOR_NAND_PGS_SHIFT 16
106 #define CSOR_NAND_PGS_512 0x00000000
107 #define CSOR_NAND_PGS_2K 0x00080000
108 #define CSOR_NAND_PGS_4K 0x00100000
109 #define CSOR_NAND_PGS_8K 0x00180000
110 /* Spare region Size */
111 #define CSOR_NAND_SPRZ_MASK 0x0000E000
112 #define CSOR_NAND_SPRZ_SHIFT 13
113 #define CSOR_NAND_SPRZ_16 0x00000000
114 #define CSOR_NAND_SPRZ_64 0x00002000
115 #define CSOR_NAND_SPRZ_128 0x00004000
116 #define CSOR_NAND_SPRZ_210 0x00006000
117 #define CSOR_NAND_SPRZ_218 0x00008000
118 #define CSOR_NAND_SPRZ_224 0x0000A000
119 #define CSOR_NAND_SPRZ_CSOR_EXT 0x0000C000
120 /* Pages Per Block */
121 #define CSOR_NAND_PB_MASK 0x00000700
122 #define CSOR_NAND_PB_SHIFT 8
123 #define CSOR_NAND_PB(n) ((__ilog2(n) - 5) << CSOR_NAND_PB_SHIFT)
124 /* Time for Read Enable High to Output High Impedance */
125 #define CSOR_NAND_TRHZ_MASK 0x0000001C
126 #define CSOR_NAND_TRHZ_SHIFT 2
127 #define CSOR_NAND_TRHZ_20 0x00000000
128 #define CSOR_NAND_TRHZ_40 0x00000004
129 #define CSOR_NAND_TRHZ_60 0x00000008
130 #define CSOR_NAND_TRHZ_80 0x0000000C
131 #define CSOR_NAND_TRHZ_100 0x00000010
132 /* Buffer control disable */
133 #define CSOR_NAND_BCTLD 0x00000001
134
135 /*
136 * Chip Select Option Register - NOR Flash Mode
137 */
138 /* Enable Address shift Mode */
139 #define CSOR_NOR_ADM_SHFT_MODE_EN 0x80000000
140 /* Page Read Enable from NOR device */
141 #define CSOR_NOR_PGRD_EN 0x10000000
142 /* AVD Toggle Enable during Burst Program */
143 #define CSOR_NOR_AVD_TGL_PGM_EN 0x01000000
144 /* Address Data Multiplexing Shift */
145 #define CSOR_NOR_ADM_MASK 0x0003E000
146 #define CSOR_NOR_ADM_SHIFT_SHIFT 13
147 #define CSOR_NOR_ADM_SHIFT(n) ((n) << CSOR_NOR_ADM_SHIFT_SHIFT)
148 /* Type of the NOR device hooked */
149 #define CSOR_NOR_NOR_MODE_AYSNC_NOR 0x00000000
150 #define CSOR_NOR_NOR_MODE_AVD_NOR 0x00000020
151 /* Time for Read Enable High to Output High Impedance */
152 #define CSOR_NOR_TRHZ_MASK 0x0000001C
153 #define CSOR_NOR_TRHZ_SHIFT 2
154 #define CSOR_NOR_TRHZ_20 0x00000000
155 #define CSOR_NOR_TRHZ_40 0x00000004
156 #define CSOR_NOR_TRHZ_60 0x00000008
157 #define CSOR_NOR_TRHZ_80 0x0000000C
158 #define CSOR_NOR_TRHZ_100 0x00000010
159 /* Buffer control disable */
160 #define CSOR_NOR_BCTLD 0x00000001
161
162 /*
163 * Chip Select Option Register - GPCM Mode
164 */
165 /* GPCM Mode - Normal */
166 #define CSOR_GPCM_GPMODE_NORMAL 0x00000000
167 /* GPCM Mode - GenericASIC */
168 #define CSOR_GPCM_GPMODE_ASIC 0x80000000
169 /* Parity Mode odd/even */
170 #define CSOR_GPCM_PARITY_EVEN 0x40000000
171 /* Parity Checking enable/disable */
172 #define CSOR_GPCM_PAR_EN 0x20000000
173 /* GPCM Timeout Count */
174 #define CSOR_GPCM_GPTO_MASK 0x0F000000
175 #define CSOR_GPCM_GPTO_SHIFT 24
176 #define CSOR_GPCM_GPTO(n) ((__ilog2(n) - 8) << CSOR_GPCM_GPTO_SHIFT)
177 /* GPCM External Access Termination mode for read access */
178 #define CSOR_GPCM_RGETA_EXT 0x00080000
179 /* GPCM External Access Termination mode for write access */
180 #define CSOR_GPCM_WGETA_EXT 0x00040000
181 /* Address Data Multiplexing Shift */
182 #define CSOR_GPCM_ADM_MASK 0x0003E000
183 #define CSOR_GPCM_ADM_SHIFT_SHIFT 13
184 #define CSOR_GPCM_ADM_SHIFT(n) ((n) << CSOR_GPCM_ADM_SHIFT_SHIFT)
185 /* Generic ASIC Parity error indication delay */
186 #define CSOR_GPCM_GAPERRD_MASK 0x00000180
187 #define CSOR_GPCM_GAPERRD_SHIFT 7
188 #define CSOR_GPCM_GAPERRD(n) (((n) - 1) << CSOR_GPCM_GAPERRD_SHIFT)
189 /* Time for Read Enable High to Output High Impedance */
190 #define CSOR_GPCM_TRHZ_MASK 0x0000001C
191 #define CSOR_GPCM_TRHZ_20 0x00000000
192 #define CSOR_GPCM_TRHZ_40 0x00000004
193 #define CSOR_GPCM_TRHZ_60 0x00000008
194 #define CSOR_GPCM_TRHZ_80 0x0000000C
195 #define CSOR_GPCM_TRHZ_100 0x00000010
196 /* Buffer control disable */
197 #define CSOR_GPCM_BCTLD 0x00000001
198
199 /*
200 * Ready Busy Status Register (RB_STAT)
201 */
202 /* CSn is READY */
203 #define IFC_RB_STAT_READY_CS0 0x80000000
204 #define IFC_RB_STAT_READY_CS1 0x40000000
205 #define IFC_RB_STAT_READY_CS2 0x20000000
206 #define IFC_RB_STAT_READY_CS3 0x10000000
207
208 /*
209 * General Control Register (GCR)
210 */
211 #define IFC_GCR_MASK 0x8000F800
212 /* reset all IFC hardware */
213 #define IFC_GCR_SOFT_RST_ALL 0x80000000
214 /* Turnaroud Time of external buffer */
215 #define IFC_GCR_TBCTL_TRN_TIME 0x0000F800
216 #define IFC_GCR_TBCTL_TRN_TIME_SHIFT 11
217
218 /*
219 * Common Event and Error Status Register (CM_EVTER_STAT)
220 */
221 /* Chip select error */
222 #define IFC_CM_EVTER_STAT_CSER 0x80000000
223
224 /*
225 * Common Event and Error Enable Register (CM_EVTER_EN)
226 */
227 /* Chip select error checking enable */
228 #define IFC_CM_EVTER_EN_CSEREN 0x80000000
229
230 /*
231 * Common Event and Error Interrupt Enable Register (CM_EVTER_INTR_EN)
232 */
233 /* Chip select error interrupt enable */
234 #define IFC_CM_EVTER_INTR_EN_CSERIREN 0x80000000
235
236 /*
237 * Common Transfer Error Attribute Register-0 (CM_ERATTR0)
238 */
239 /* transaction type of error Read/Write */
240 #define IFC_CM_ERATTR0_ERTYP_READ 0x80000000
241 #define IFC_CM_ERATTR0_ERAID 0x0FF00000
242 #define IFC_CM_ERATTR0_ERAID_SHIFT 20
243 #define IFC_CM_ERATTR0_ESRCID 0x0000FF00
244 #define IFC_CM_ERATTR0_ESRCID_SHIFT 8
245
246 /*
247 * Clock Control Register (CCR)
248 */
249 #define IFC_CCR_MASK 0x0F0F8800
250 /* Clock division ratio */
251 #define IFC_CCR_CLK_DIV_MASK 0x0F000000
252 #define IFC_CCR_CLK_DIV_SHIFT 24
253 #define IFC_CCR_CLK_DIV(n) ((n-1) << IFC_CCR_CLK_DIV_SHIFT)
254 /* IFC Clock Delay */
255 #define IFC_CCR_CLK_DLY_MASK 0x000F0000
256 #define IFC_CCR_CLK_DLY_SHIFT 16
257 #define IFC_CCR_CLK_DLY(n) ((n) << IFC_CCR_CLK_DLY_SHIFT)
258 /* Invert IFC clock before sending out */
259 #define IFC_CCR_INV_CLK_EN 0x00008000
260 /* Fedback IFC Clock */
261 #define IFC_CCR_FB_IFC_CLK_SEL 0x00000800
262
263 /*
264 * Clock Status Register (CSR)
265 */
266 /* Clk is stable */
267 #define IFC_CSR_CLK_STAT_STABLE 0x80000000
268
269 /*
270 * IFC_NAND Machine Specific Registers
271 */
272 /*
273 * NAND Configuration Register (NCFGR)
274 */
275 /* Auto Boot Mode */
276 #define IFC_NAND_NCFGR_BOOT 0x80000000
277 /* Addressing Mode-ROW0+n/COL0 */
278 #define IFC_NAND_NCFGR_ADDR_MODE_RC0 0x00000000
279 /* Addressing Mode-ROW0+n/COL0+n */
280 #define IFC_NAND_NCFGR_ADDR_MODE_RC1 0x00400000
281 /* Number of loop iterations of FIR sequences for multi page operations */
282 #define IFC_NAND_NCFGR_NUM_LOOP_MASK 0x0000F000
283 #define IFC_NAND_NCFGR_NUM_LOOP_SHIFT 12
284 #define IFC_NAND_NCFGR_NUM_LOOP(n) ((n) << IFC_NAND_NCFGR_NUM_LOOP_SHIFT)
285 /* Number of wait cycles */
286 #define IFC_NAND_NCFGR_NUM_WAIT_MASK 0x000000FF
287 #define IFC_NAND_NCFGR_NUM_WAIT_SHIFT 0
288
289 /*
290 * NAND Flash Command Registers (NAND_FCR0/NAND_FCR1)
291 */
292 /* General purpose FCM flash command bytes CMD0-CMD7 */
293 #define IFC_NAND_FCR0_CMD0 0xFF000000
294 #define IFC_NAND_FCR0_CMD0_SHIFT 24
295 #define IFC_NAND_FCR0_CMD1 0x00FF0000
296 #define IFC_NAND_FCR0_CMD1_SHIFT 16
297 #define IFC_NAND_FCR0_CMD2 0x0000FF00
298 #define IFC_NAND_FCR0_CMD2_SHIFT 8
299 #define IFC_NAND_FCR0_CMD3 0x000000FF
300 #define IFC_NAND_FCR0_CMD3_SHIFT 0
301 #define IFC_NAND_FCR1_CMD4 0xFF000000
302 #define IFC_NAND_FCR1_CMD4_SHIFT 24
303 #define IFC_NAND_FCR1_CMD5 0x00FF0000
304 #define IFC_NAND_FCR1_CMD5_SHIFT 16
305 #define IFC_NAND_FCR1_CMD6 0x0000FF00
306 #define IFC_NAND_FCR1_CMD6_SHIFT 8
307 #define IFC_NAND_FCR1_CMD7 0x000000FF
308 #define IFC_NAND_FCR1_CMD7_SHIFT 0
309
310 /*
311 * Flash ROW and COL Address Register (ROWn, COLn)
312 */
313 /* Main/spare region locator */
314 #define IFC_NAND_COL_MS 0x80000000
315 /* Column Address */
316 #define IFC_NAND_COL_CA_MASK 0x00000FFF
317
318 /*
319 * NAND Flash Byte Count Register (NAND_BC)
320 */
321 /* Byte Count for read/Write */
322 #define IFC_NAND_BC 0x000001FF
323
324 /*
325 * NAND Flash Instruction Registers (NAND_FIR0/NAND_FIR1/NAND_FIR2)
326 */
327 /* NAND Machine specific opcodes OP0-OP14*/
328 #define IFC_NAND_FIR0_OP0 0xFC000000
329 #define IFC_NAND_FIR0_OP0_SHIFT 26
330 #define IFC_NAND_FIR0_OP1 0x03F00000
331 #define IFC_NAND_FIR0_OP1_SHIFT 20
332 #define IFC_NAND_FIR0_OP2 0x000FC000
333 #define IFC_NAND_FIR0_OP2_SHIFT 14
334 #define IFC_NAND_FIR0_OP3 0x00003F00
335 #define IFC_NAND_FIR0_OP3_SHIFT 8
336 #define IFC_NAND_FIR0_OP4 0x000000FC
337 #define IFC_NAND_FIR0_OP4_SHIFT 2
338 #define IFC_NAND_FIR1_OP5 0xFC000000
339 #define IFC_NAND_FIR1_OP5_SHIFT 26
340 #define IFC_NAND_FIR1_OP6 0x03F00000
341 #define IFC_NAND_FIR1_OP6_SHIFT 20
342 #define IFC_NAND_FIR1_OP7 0x000FC000
343 #define IFC_NAND_FIR1_OP7_SHIFT 14
344 #define IFC_NAND_FIR1_OP8 0x00003F00
345 #define IFC_NAND_FIR1_OP8_SHIFT 8
346 #define IFC_NAND_FIR1_OP9 0x000000FC
347 #define IFC_NAND_FIR1_OP9_SHIFT 2
348 #define IFC_NAND_FIR2_OP10 0xFC000000
349 #define IFC_NAND_FIR2_OP10_SHIFT 26
350 #define IFC_NAND_FIR2_OP11 0x03F00000
351 #define IFC_NAND_FIR2_OP11_SHIFT 20
352 #define IFC_NAND_FIR2_OP12 0x000FC000
353 #define IFC_NAND_FIR2_OP12_SHIFT 14
354 #define IFC_NAND_FIR2_OP13 0x00003F00
355 #define IFC_NAND_FIR2_OP13_SHIFT 8
356 #define IFC_NAND_FIR2_OP14 0x000000FC
357 #define IFC_NAND_FIR2_OP14_SHIFT 2
358
359 /*
360 * Instruction opcodes to be programmed
361 * in FIR registers- 6bits
362 */
363 enum ifc_nand_fir_opcodes {
364 IFC_FIR_OP_NOP,
365 IFC_FIR_OP_CA0,
366 IFC_FIR_OP_CA1,
367 IFC_FIR_OP_CA2,
368 IFC_FIR_OP_CA3,
369 IFC_FIR_OP_RA0,
370 IFC_FIR_OP_RA1,
371 IFC_FIR_OP_RA2,
372 IFC_FIR_OP_RA3,
373 IFC_FIR_OP_CMD0,
374 IFC_FIR_OP_CMD1,
375 IFC_FIR_OP_CMD2,
376 IFC_FIR_OP_CMD3,
377 IFC_FIR_OP_CMD4,
378 IFC_FIR_OP_CMD5,
379 IFC_FIR_OP_CMD6,
380 IFC_FIR_OP_CMD7,
381 IFC_FIR_OP_CW0,
382 IFC_FIR_OP_CW1,
383 IFC_FIR_OP_CW2,
384 IFC_FIR_OP_CW3,
385 IFC_FIR_OP_CW4,
386 IFC_FIR_OP_CW5,
387 IFC_FIR_OP_CW6,
388 IFC_FIR_OP_CW7,
389 IFC_FIR_OP_WBCD,
390 IFC_FIR_OP_RBCD,
391 IFC_FIR_OP_BTRD,
392 IFC_FIR_OP_RDSTAT,
393 IFC_FIR_OP_NWAIT,
394 IFC_FIR_OP_WFR,
395 IFC_FIR_OP_SBRD,
396 IFC_FIR_OP_UA,
397 IFC_FIR_OP_RB,
398 };
399
400 /*
401 * NAND Chip Select Register (NAND_CSEL)
402 */
403 #define IFC_NAND_CSEL 0x0C000000
404 #define IFC_NAND_CSEL_SHIFT 26
405 #define IFC_NAND_CSEL_CS0 0x00000000
406 #define IFC_NAND_CSEL_CS1 0x04000000
407 #define IFC_NAND_CSEL_CS2 0x08000000
408 #define IFC_NAND_CSEL_CS3 0x0C000000
409
410 /*
411 * NAND Operation Sequence Start (NANDSEQ_STRT)
412 */
413 /* NAND Flash Operation Start */
414 #define IFC_NAND_SEQ_STRT_FIR_STRT 0x80000000
415 /* Automatic Erase */
416 #define IFC_NAND_SEQ_STRT_AUTO_ERS 0x00800000
417 /* Automatic Program */
418 #define IFC_NAND_SEQ_STRT_AUTO_PGM 0x00100000
419 /* Automatic Copyback */
420 #define IFC_NAND_SEQ_STRT_AUTO_CPB 0x00020000
421 /* Automatic Read Operation */
422 #define IFC_NAND_SEQ_STRT_AUTO_RD 0x00004000
423 /* Automatic Status Read */
424 #define IFC_NAND_SEQ_STRT_AUTO_STAT_RD 0x00000800
425
426 /*
427 * NAND Event and Error Status Register (NAND_EVTER_STAT)
428 */
429 /* Operation Complete */
430 #define IFC_NAND_EVTER_STAT_OPC 0x80000000
431 /* Flash Timeout Error */
432 #define IFC_NAND_EVTER_STAT_FTOER 0x08000000
433 /* Write Protect Error */
434 #define IFC_NAND_EVTER_STAT_WPER 0x04000000
435 /* ECC Error */
436 #define IFC_NAND_EVTER_STAT_ECCER 0x02000000
437 /* RCW Load Done */
438 #define IFC_NAND_EVTER_STAT_RCW_DN 0x00008000
439 /* Boot Loadr Done */
440 #define IFC_NAND_EVTER_STAT_BOOT_DN 0x00004000
441 /* Bad Block Indicator search select */
442 #define IFC_NAND_EVTER_STAT_BBI_SRCH_SE 0x00000800
443
444 /*
445 * NAND Flash Page Read Completion Event Status Register
446 * (PGRDCMPL_EVT_STAT)
447 */
448 #define PGRDCMPL_EVT_STAT_MASK 0xFFFF0000
449 /* Small Page 0-15 Done */
450 #define PGRDCMPL_EVT_STAT_SECTION_SP(n) (1 << (31 - (n)))
451 /* Large Page(2K) 0-3 Done */
452 #define PGRDCMPL_EVT_STAT_LP_2K(n) (0xF << (28 - (n)*4))
453 /* Large Page(4K) 0-1 Done */
454 #define PGRDCMPL_EVT_STAT_LP_4K(n) (0xFF << (24 - (n)*8))
455
456 /*
457 * NAND Event and Error Enable Register (NAND_EVTER_EN)
458 */
459 /* Operation complete event enable */
460 #define IFC_NAND_EVTER_EN_OPC_EN 0x80000000
461 /* Page read complete event enable */
462 #define IFC_NAND_EVTER_EN_PGRDCMPL_EN 0x20000000
463 /* Flash Timeout error enable */
464 #define IFC_NAND_EVTER_EN_FTOER_EN 0x08000000
465 /* Write Protect error enable */
466 #define IFC_NAND_EVTER_EN_WPER_EN 0x04000000
467 /* ECC error logging enable */
468 #define IFC_NAND_EVTER_EN_ECCER_EN 0x02000000
469
470 /*
471 * NAND Event and Error Interrupt Enable Register (NAND_EVTER_INTR_EN)
472 */
473 /* Enable interrupt for operation complete */
474 #define IFC_NAND_EVTER_INTR_OPCIR_EN 0x80000000
475 /* Enable interrupt for Page read complete */
476 #define IFC_NAND_EVTER_INTR_PGRDCMPLIR_EN 0x20000000
477 /* Enable interrupt for Flash timeout error */
478 #define IFC_NAND_EVTER_INTR_FTOERIR_EN 0x08000000
479 /* Enable interrupt for Write protect error */
480 #define IFC_NAND_EVTER_INTR_WPERIR_EN 0x04000000
481 /* Enable interrupt for ECC error*/
482 #define IFC_NAND_EVTER_INTR_ECCERIR_EN 0x02000000
483
484 /*
485 * NAND Transfer Error Attribute Register-0 (NAND_ERATTR0)
486 */
487 #define IFC_NAND_ERATTR0_MASK 0x0C080000
488 /* Error on CS0-3 for NAND */
489 #define IFC_NAND_ERATTR0_ERCS_CS0 0x00000000
490 #define IFC_NAND_ERATTR0_ERCS_CS1 0x04000000
491 #define IFC_NAND_ERATTR0_ERCS_CS2 0x08000000
492 #define IFC_NAND_ERATTR0_ERCS_CS3 0x0C000000
493 /* Transaction type of error Read/Write */
494 #define IFC_NAND_ERATTR0_ERTTYPE_READ 0x00080000
495
496 /*
497 * NAND Flash Status Register (NAND_FSR)
498 */
499 /* First byte of data read from read status op */
500 #define IFC_NAND_NFSR_RS0 0xFF000000
501 /* Second byte of data read from read status op */
502 #define IFC_NAND_NFSR_RS1 0x00FF0000
503
504 /*
505 * ECC Error Status Registers (ECCSTAT0-ECCSTAT3)
506 */
507 /* Number of ECC errors on sector n (n = 0-15) */
508 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_MASK 0x0F000000
509 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR0_SHIFT 24
510 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_MASK 0x000F0000
511 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR1_SHIFT 16
512 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_MASK 0x00000F00
513 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR2_SHIFT 8
514 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_MASK 0x0000000F
515 #define IFC_NAND_ECCSTAT0_ERRCNT_SECTOR3_SHIFT 0
516 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_MASK 0x0F000000
517 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR4_SHIFT 24
518 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_MASK 0x000F0000
519 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR5_SHIFT 16
520 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_MASK 0x00000F00
521 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR6_SHIFT 8
522 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_MASK 0x0000000F
523 #define IFC_NAND_ECCSTAT1_ERRCNT_SECTOR7_SHIFT 0
524 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_MASK 0x0F000000
525 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR8_SHIFT 24
526 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_MASK 0x000F0000
527 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR9_SHIFT 16
528 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_MASK 0x00000F00
529 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR10_SHIFT 8
530 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_MASK 0x0000000F
531 #define IFC_NAND_ECCSTAT2_ERRCNT_SECTOR11_SHIFT 0
532 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_MASK 0x0F000000
533 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR12_SHIFT 24
534 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_MASK 0x000F0000
535 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR13_SHIFT 16
536 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_MASK 0x00000F00
537 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR14_SHIFT 8
538 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_MASK 0x0000000F
539 #define IFC_NAND_ECCSTAT3_ERRCNT_SECTOR15_SHIFT 0
540
541 /*
542 * NAND Control Register (NANDCR)
543 */
544 #define IFC_NAND_NCR_FTOCNT_MASK 0x1E000000
545 #define IFC_NAND_NCR_FTOCNT_SHIFT 25
546 #define IFC_NAND_NCR_FTOCNT(n) ((_ilog2(n) - 8) << IFC_NAND_NCR_FTOCNT_SHIFT)
547
548 /*
549 * NAND_AUTOBOOT_TRGR
550 */
551 /* Trigger RCW load */
552 #define IFC_NAND_AUTOBOOT_TRGR_RCW_LD 0x80000000
553 /* Trigget Auto Boot */
554 #define IFC_NAND_AUTOBOOT_TRGR_BOOT_LD 0x20000000
555
556 /*
557 * NAND_MDR
558 */
559 /* 1st read data byte when opcode SBRD */
560 #define IFC_NAND_MDR_RDATA0 0xFF000000
561 /* 2nd read data byte when opcode SBRD */
562 #define IFC_NAND_MDR_RDATA1 0x00FF0000
563
564 /*
565 * NOR Machine Specific Registers
566 */
567 /*
568 * NOR Event and Error Status Register (NOR_EVTER_STAT)
569 */
570 /* NOR Command Sequence Operation Complete */
571 #define IFC_NOR_EVTER_STAT_OPC_NOR 0x80000000
572 /* Write Protect Error */
573 #define IFC_NOR_EVTER_STAT_WPER 0x04000000
574 /* Command Sequence Timeout Error */
575 #define IFC_NOR_EVTER_STAT_STOER 0x01000000
576
577 /*
578 * NOR Event and Error Enable Register (NOR_EVTER_EN)
579 */
580 /* NOR Command Seq complete event enable */
581 #define IFC_NOR_EVTER_EN_OPCEN_NOR 0x80000000
582 /* Write Protect Error Checking Enable */
583 #define IFC_NOR_EVTER_EN_WPEREN 0x04000000
584 /* Timeout Error Enable */
585 #define IFC_NOR_EVTER_EN_STOEREN 0x01000000
586
587 /*
588 * NOR Event and Error Interrupt Enable Register (NOR_EVTER_INTR_EN)
589 */
590 /* Enable interrupt for OPC complete */
591 #define IFC_NOR_EVTER_INTR_OPCEN_NOR 0x80000000
592 /* Enable interrupt for write protect error */
593 #define IFC_NOR_EVTER_INTR_WPEREN 0x04000000
594 /* Enable interrupt for timeout error */
595 #define IFC_NOR_EVTER_INTR_STOEREN 0x01000000
596
597 /*
598 * NOR Transfer Error Attribute Register-0 (NOR_ERATTR0)
599 */
600 /* Source ID for error transaction */
601 #define IFC_NOR_ERATTR0_ERSRCID 0xFF000000
602 /* AXI ID for error transation */
603 #define IFC_NOR_ERATTR0_ERAID 0x000FF000
604 /* Chip select corresponds to NOR error */
605 #define IFC_NOR_ERATTR0_ERCS_CS0 0x00000000
606 #define IFC_NOR_ERATTR0_ERCS_CS1 0x00000010
607 #define IFC_NOR_ERATTR0_ERCS_CS2 0x00000020
608 #define IFC_NOR_ERATTR0_ERCS_CS3 0x00000030
609 /* Type of transaction read/write */
610 #define IFC_NOR_ERATTR0_ERTYPE_READ 0x00000001
611
612 /*
613 * NOR Transfer Error Attribute Register-2 (NOR_ERATTR2)
614 */
615 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_EXP 0x000F0000
616 #define IFC_NOR_ERATTR2_ER_NUM_PHASE_PER 0x00000F00
617
618 /*
619 * NOR Control Register (NORCR)
620 */
621 #define IFC_NORCR_MASK 0x0F0F0000
622 /* No. of Address/Data Phase */
623 #define IFC_NORCR_NUM_PHASE_MASK 0x0F000000
624 #define IFC_NORCR_NUM_PHASE_SHIFT 24
625 #define IFC_NORCR_NUM_PHASE(n) ((n-1) << IFC_NORCR_NUM_PHASE_SHIFT)
626 /* Sequence Timeout Count */
627 #define IFC_NORCR_STOCNT_MASK 0x000F0000
628 #define IFC_NORCR_STOCNT_SHIFT 16
629 #define IFC_NORCR_STOCNT(n) ((__ilog2(n) - 8) << IFC_NORCR_STOCNT_SHIFT)
630
631 /*
632 * GPCM Machine specific registers
633 */
634 /*
635 * GPCM Event and Error Status Register (GPCM_EVTER_STAT)
636 */
637 /* Timeout error */
638 #define IFC_GPCM_EVTER_STAT_TOER 0x04000000
639 /* Parity error */
640 #define IFC_GPCM_EVTER_STAT_PER 0x01000000
641
642 /*
643 * GPCM Event and Error Enable Register (GPCM_EVTER_EN)
644 */
645 /* Timeout error enable */
646 #define IFC_GPCM_EVTER_EN_TOER_EN 0x04000000
647 /* Parity error enable */
648 #define IFC_GPCM_EVTER_EN_PER_EN 0x01000000
649
650 /*
651 * GPCM Event and Error Interrupt Enable Register (GPCM_EVTER_INTR_EN)
652 */
653 /* Enable Interrupt for timeout error */
654 #define IFC_GPCM_EEIER_TOERIR_EN 0x04000000
655 /* Enable Interrupt for Parity error */
656 #define IFC_GPCM_EEIER_PERIR_EN 0x01000000
657
658 /*
659 * GPCM Transfer Error Attribute Register-0 (GPCM_ERATTR0)
660 */
661 /* Source ID for error transaction */
662 #define IFC_GPCM_ERATTR0_ERSRCID 0xFF000000
663 /* AXI ID for error transaction */
664 #define IFC_GPCM_ERATTR0_ERAID 0x000FF000
665 /* Chip select corresponds to GPCM error */
666 #define IFC_GPCM_ERATTR0_ERCS_CS0 0x00000000
667 #define IFC_GPCM_ERATTR0_ERCS_CS1 0x00000040
668 #define IFC_GPCM_ERATTR0_ERCS_CS2 0x00000080
669 #define IFC_GPCM_ERATTR0_ERCS_CS3 0x000000C0
670 /* Type of transaction read/Write */
671 #define IFC_GPCM_ERATTR0_ERTYPE_READ 0x00000001
672
673 /*
674 * GPCM Transfer Error Attribute Register-2 (GPCM_ERATTR2)
675 */
676 /* On which beat of address/data parity error is observed */
677 #define IFC_GPCM_ERATTR2_PERR_BEAT 0x00000C00
678 /* Parity Error on byte */
679 #define IFC_GPCM_ERATTR2_PERR_BYTE 0x000000F0
680 /* Parity Error reported in addr or data phase */
681 #define IFC_GPCM_ERATTR2_PERR_DATA_PHASE 0x00000001
682
683 /*
684 * GPCM Status Register (GPCM_STAT)
685 */
686 #define IFC_GPCM_STAT_BSY 0x80000000 /* GPCM is busy */
687
688 /*
689 * IFC Controller NAND Machine registers
690 */
691 struct fsl_ifc_nand {
692 __be32 ncfgr;
693 u32 res1[0x4];
694 __be32 nand_fcr0;
695 __be32 nand_fcr1;
696 u32 res2[0x8];
697 __be32 row0;
698 u32 res3;
699 __be32 col0;
700 u32 res4;
701 __be32 row1;
702 u32 res5;
703 __be32 col1;
704 u32 res6;
705 __be32 row2;
706 u32 res7;
707 __be32 col2;
708 u32 res8;
709 __be32 row3;
710 u32 res9;
711 __be32 col3;
712 u32 res10[0x24];
713 __be32 nand_fbcr;
714 u32 res11;
715 __be32 nand_fir0;
716 __be32 nand_fir1;
717 __be32 nand_fir2;
718 u32 res12[0x10];
719 __be32 nand_csel;
720 u32 res13;
721 __be32 nandseq_strt;
722 u32 res14;
723 __be32 nand_evter_stat;
724 u32 res15;
725 __be32 pgrdcmpl_evt_stat;
726 u32 res16[0x2];
727 __be32 nand_evter_en;
728 u32 res17[0x2];
729 __be32 nand_evter_intr_en;
730 __be32 nand_vol_addr_stat;
731 u32 res18;
732 __be32 nand_erattr0;
733 __be32 nand_erattr1;
734 u32 res19[0x10];
735 __be32 nand_fsr;
736 u32 res20;
737 __be32 nand_eccstat[8];
738 u32 res21[0x1c];
739 __be32 nanndcr;
740 u32 res22[0x2];
741 __be32 nand_autoboot_trgr;
742 u32 res23;
743 __be32 nand_mdr;
744 u32 res24[0x1C];
745 __be32 nand_dll_lowcfg0;
746 __be32 nand_dll_lowcfg1;
747 u32 res25;
748 __be32 nand_dll_lowstat;
749 u32 res26[0x3c];
750 };
751
752 /*
753 * IFC controller NOR Machine registers
754 */
755 struct fsl_ifc_nor {
756 __be32 nor_evter_stat;
757 u32 res1[0x2];
758 __be32 nor_evter_en;
759 u32 res2[0x2];
760 __be32 nor_evter_intr_en;
761 u32 res3[0x2];
762 __be32 nor_erattr0;
763 __be32 nor_erattr1;
764 __be32 nor_erattr2;
765 u32 res4[0x4];
766 __be32 norcr;
767 u32 res5[0xEF];
768 };
769
770 /*
771 * IFC controller GPCM Machine registers
772 */
773 struct fsl_ifc_gpcm {
774 __be32 gpcm_evter_stat;
775 u32 res1[0x2];
776 __be32 gpcm_evter_en;
777 u32 res2[0x2];
778 __be32 gpcm_evter_intr_en;
779 u32 res3[0x2];
780 __be32 gpcm_erattr0;
781 __be32 gpcm_erattr1;
782 __be32 gpcm_erattr2;
783 __be32 gpcm_stat;
784 };
785
786 /*
787 * IFC Controller Registers
788 */
789 struct fsl_ifc_global {
790 __be32 ifc_rev;
791 u32 res1[0x2];
792 struct {
793 __be32 cspr_ext;
794 __be32 cspr;
795 u32 res2;
796 } cspr_cs[FSL_IFC_BANK_COUNT];
797 u32 res3[0xd];
798 struct {
799 __be32 amask;
800 u32 res4[0x2];
801 } amask_cs[FSL_IFC_BANK_COUNT];
802 u32 res5[0xc];
803 struct {
804 __be32 csor;
805 __be32 csor_ext;
806 u32 res6;
807 } csor_cs[FSL_IFC_BANK_COUNT];
808 u32 res7[0xc];
809 struct {
810 __be32 ftim[4];
811 u32 res8[0x8];
812 } ftim_cs[FSL_IFC_BANK_COUNT];
813 u32 res9[0x30];
814 __be32 rb_stat;
815 __be32 rb_map;
816 __be32 wb_map;
817 __be32 ifc_gcr;
818 u32 res10[0x2];
819 __be32 cm_evter_stat;
820 u32 res11[0x2];
821 __be32 cm_evter_en;
822 u32 res12[0x2];
823 __be32 cm_evter_intr_en;
824 u32 res13[0x2];
825 __be32 cm_erattr0;
826 __be32 cm_erattr1;
827 u32 res14[0x2];
828 __be32 ifc_ccr;
829 __be32 ifc_csr;
830 __be32 ddr_ccr_low;
831 };
832
833
834 struct fsl_ifc_runtime {
835 struct fsl_ifc_nand ifc_nand;
836 struct fsl_ifc_nor ifc_nor;
837 struct fsl_ifc_gpcm ifc_gpcm;
838 };
839
840 extern unsigned int convert_ifc_address(phys_addr_t addr_base);
841 extern int fsl_ifc_find(phys_addr_t addr_base);
842
843 /* overview of the fsl ifc controller */
844
845 struct fsl_ifc_ctrl {
846 /* device info */
847 struct device *dev;
848 struct fsl_ifc_global __iomem *gregs;
849 struct fsl_ifc_runtime __iomem *rregs;
850 int irq;
851 int nand_irq;
852 spinlock_t lock;
853 void *nand;
854 int version;
855 int banks;
856
857 u32 nand_stat;
858 wait_queue_head_t nand_wait;
859 bool little_endian;
860 };
861
862 extern struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev;
863
ifc_in32(void __iomem * addr)864 static inline u32 ifc_in32(void __iomem *addr)
865 {
866 u32 val;
867
868 if (fsl_ifc_ctrl_dev->little_endian)
869 val = ioread32(addr);
870 else
871 val = ioread32be(addr);
872
873 return val;
874 }
875
ifc_in16(void __iomem * addr)876 static inline u16 ifc_in16(void __iomem *addr)
877 {
878 u16 val;
879
880 if (fsl_ifc_ctrl_dev->little_endian)
881 val = ioread16(addr);
882 else
883 val = ioread16be(addr);
884
885 return val;
886 }
887
ifc_in8(void __iomem * addr)888 static inline u8 ifc_in8(void __iomem *addr)
889 {
890 return ioread8(addr);
891 }
892
ifc_out32(u32 val,void __iomem * addr)893 static inline void ifc_out32(u32 val, void __iomem *addr)
894 {
895 if (fsl_ifc_ctrl_dev->little_endian)
896 iowrite32(val, addr);
897 else
898 iowrite32be(val, addr);
899 }
900
ifc_out16(u16 val,void __iomem * addr)901 static inline void ifc_out16(u16 val, void __iomem *addr)
902 {
903 if (fsl_ifc_ctrl_dev->little_endian)
904 iowrite16(val, addr);
905 else
906 iowrite16be(val, addr);
907 }
908
ifc_out8(u8 val,void __iomem * addr)909 static inline void ifc_out8(u8 val, void __iomem *addr)
910 {
911 iowrite8(val, addr);
912 }
913
914 #endif /* __ASM_FSL_IFC_H */
915
