1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright (C) 2001 David J. Mckay (david.mckay@st.com) 4 * 5 * Definitions for the SH5 PCI hardware. 6 */ 7 #ifndef __PCI_SH5_H 8 #define __PCI_SH5_H 9 10 /* Product ID */ 11 #define PCISH5_PID 0x350d 12 13 /* vendor ID */ 14 #define PCISH5_VID 0x1054 15 16 /* Configuration types */ 17 #define ST_TYPE0 0x00 /* Configuration cycle type 0 */ 18 #define ST_TYPE1 0x01 /* Configuration cycle type 1 */ 19 20 /* VCR data */ 21 #define PCISH5_VCR_STATUS 0x00 22 #define PCISH5_VCR_VERSION 0x08 23 24 /* 25 ** ICR register offsets and bits 26 */ 27 #define PCISH5_ICR_CR 0x100 /* PCI control register values */ 28 #define CR_PBAM (1<<12) 29 #define CR_PFCS (1<<11) 30 #define CR_FTO (1<<10) 31 #define CR_PFE (1<<9) 32 #define CR_TBS (1<<8) 33 #define CR_SPUE (1<<7) 34 #define CR_BMAM (1<<6) 35 #define CR_HOST (1<<5) 36 #define CR_CLKEN (1<<4) 37 #define CR_SOCS (1<<3) 38 #define CR_IOCS (1<<2) 39 #define CR_RSTCTL (1<<1) 40 #define CR_CFINT (1<<0) 41 #define CR_LOCK_MASK 0xa5000000 42 43 #define PCISH5_ICR_INT 0x114 /* Interrupt registert values */ 44 #define INT_MADIM (1<<2) 45 46 #define PCISH5_ICR_LSR0 0X104 /* Local space register values */ 47 #define PCISH5_ICR_LSR1 0X108 /* Local space register values */ 48 #define PCISH5_ICR_LAR0 0x10c /* Local address register values */ 49 #define PCISH5_ICR_LAR1 0x110 /* Local address register values */ 50 #define PCISH5_ICR_INTM 0x118 /* Interrupt mask register values */ 51 #define PCISH5_ICR_AIR 0x11c /* Interrupt error address information register values */ 52 #define PCISH5_ICR_CIR 0x120 /* Interrupt error command information register values */ 53 #define PCISH5_ICR_AINT 0x130 /* Interrupt error arbiter interrupt register values */ 54 #define PCISH5_ICR_AINTM 0x134 /* Interrupt error arbiter interrupt mask register values */ 55 #define PCISH5_ICR_BMIR 0x138 /* Interrupt error info register of bus master values */ 56 #define PCISH5_ICR_PAR 0x1c0 /* Pio address register values */ 57 #define PCISH5_ICR_MBR 0x1c4 /* Memory space bank register values */ 58 #define PCISH5_ICR_IOBR 0x1c8 /* I/O space bank register values */ 59 #define PCISH5_ICR_PINT 0x1cc /* power management interrupt register values */ 60 #define PCISH5_ICR_PINTM 0x1d0 /* power management interrupt mask register values */ 61 #define PCISH5_ICR_MBMR 0x1d8 /* memory space bank mask register values */ 62 #define PCISH5_ICR_IOBMR 0x1dc /* I/O space bank mask register values */ 63 #define PCISH5_ICR_CSCR0 0x210 /* PCI cache snoop control register 0 */ 64 #define PCISH5_ICR_CSCR1 0x214 /* PCI cache snoop control register 1 */ 65 #define PCISH5_ICR_PDR 0x220 /* Pio data register values */ 66 67 /* These are configs space registers */ 68 #define PCISH5_ICR_CSR_VID 0x000 /* Vendor id */ 69 #define PCISH5_ICR_CSR_DID 0x002 /* Device id */ 70 #define PCISH5_ICR_CSR_CMD 0x004 /* Command register */ 71 #define PCISH5_ICR_CSR_STATUS 0x006 /* Stautus */ 72 #define PCISH5_ICR_CSR_IBAR0 0x010 /* I/O base address register */ 73 #define PCISH5_ICR_CSR_MBAR0 0x014 /* First Memory base address register */ 74 #define PCISH5_ICR_CSR_MBAR1 0x018 /* Second Memory base address register */ 75 76 /* Base address of registers */ 77 #define SH5PCI_ICR_BASE (PHYS_PCI_BLOCK + 0x00040000) 78 #define SH5PCI_IO_BASE (PHYS_PCI_BLOCK + 0x00800000) 79 /* #define SH5PCI_VCR_BASE (P2SEG_PCICB_BLOCK + P2SEG) */ 80 81 extern unsigned long pcicr_virt; 82 /* Register selection macro */ 83 #define PCISH5_ICR_REG(x) ( pcicr_virt + (PCISH5_ICR_##x)) 84 /* #define PCISH5_VCR_REG(x) ( SH5PCI_VCR_BASE (PCISH5_VCR_##x)) */ 85 86 /* Write I/O functions */ 87 #define SH5PCI_WRITE(reg,val) __raw_writel((u32)(val),PCISH5_ICR_REG(reg)) 88 #define SH5PCI_WRITE_SHORT(reg,val) __raw_writew((u16)(val),PCISH5_ICR_REG(reg)) 89 #define SH5PCI_WRITE_BYTE(reg,val) __raw_writeb((u8)(val),PCISH5_ICR_REG(reg)) 90 91 /* Read I/O functions */ 92 #define SH5PCI_READ(reg) __raw_readl(PCISH5_ICR_REG(reg)) 93 #define SH5PCI_READ_SHORT(reg) __raw_readw(PCISH5_ICR_REG(reg)) 94 #define SH5PCI_READ_BYTE(reg) __raw_readb(PCISH5_ICR_REG(reg)) 95 96 /* Set PCI config bits */ 97 #define SET_CONFIG_BITS(bus,devfn,where) ((((bus) << 16) | ((devfn) << 8) | ((where) & ~3)) | 0x80000000) 98 99 /* Set PCI command register */ 100 #define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where) 101 102 /* Size converters */ 103 #define PCISH5_MEM_SIZCONV(x) (((x / 0x40000) - 1) << 18) 104 #define PCISH5_IO_SIZCONV(x) (((x / 0x40000) - 1) << 18) 105 106 extern struct pci_ops sh5_pci_ops; 107 108 #endif /* __PCI_SH5_H */ 109
