1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_POWERPC_CPUTABLE_H
3 #define __ASM_POWERPC_CPUTABLE_H
4
5
6 #include <linux/types.h>
7 #include <uapi/asm/cputable.h>
8 #include <asm/asm-const.h>
9
10 #ifndef __ASSEMBLY__
11
12 /* This structure can grow, it's real size is used by head.S code
13 * via the mkdefs mechanism.
14 */
15 struct cpu_spec;
16
17 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
18 typedef void (*cpu_restore_t)(void);
19
20 enum powerpc_oprofile_type {
21 PPC_OPROFILE_INVALID = 0,
22 PPC_OPROFILE_RS64 = 1,
23 PPC_OPROFILE_POWER4 = 2,
24 PPC_OPROFILE_G4 = 3,
25 PPC_OPROFILE_FSL_EMB = 4,
26 PPC_OPROFILE_CELL = 5,
27 PPC_OPROFILE_PA6T = 6,
28 };
29
30 enum powerpc_pmc_type {
31 PPC_PMC_DEFAULT = 0,
32 PPC_PMC_IBM = 1,
33 PPC_PMC_PA6T = 2,
34 PPC_PMC_G4 = 3,
35 };
36
37 struct pt_regs;
38
39 extern int machine_check_generic(struct pt_regs *regs);
40 extern int machine_check_4xx(struct pt_regs *regs);
41 extern int machine_check_440A(struct pt_regs *regs);
42 extern int machine_check_e500mc(struct pt_regs *regs);
43 extern int machine_check_e500(struct pt_regs *regs);
44 extern int machine_check_e200(struct pt_regs *regs);
45 extern int machine_check_47x(struct pt_regs *regs);
46 int machine_check_8xx(struct pt_regs *regs);
47 int machine_check_83xx(struct pt_regs *regs);
48
49 extern void cpu_down_flush_e500v2(void);
50 extern void cpu_down_flush_e500mc(void);
51 extern void cpu_down_flush_e5500(void);
52 extern void cpu_down_flush_e6500(void);
53
54 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
55 struct cpu_spec {
56 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
57 unsigned int pvr_mask;
58 unsigned int pvr_value;
59
60 char *cpu_name;
61 unsigned long cpu_features; /* Kernel features */
62 unsigned int cpu_user_features; /* Userland features */
63 unsigned int cpu_user_features2; /* Userland features v2 */
64 unsigned int mmu_features; /* MMU features */
65
66 /* cache line sizes */
67 unsigned int icache_bsize;
68 unsigned int dcache_bsize;
69
70 /* flush caches inside the current cpu */
71 void (*cpu_down_flush)(void);
72
73 /* number of performance monitor counters */
74 unsigned int num_pmcs;
75 enum powerpc_pmc_type pmc_type;
76
77 /* this is called to initialize various CPU bits like L1 cache,
78 * BHT, SPD, etc... from head.S before branching to identify_machine
79 */
80 cpu_setup_t cpu_setup;
81 /* Used to restore cpu setup on secondary processors and at resume */
82 cpu_restore_t cpu_restore;
83
84 /* Used by oprofile userspace to select the right counters */
85 char *oprofile_cpu_type;
86
87 /* Processor specific oprofile operations */
88 enum powerpc_oprofile_type oprofile_type;
89
90 /* Bit locations inside the mmcra change */
91 unsigned long oprofile_mmcra_sihv;
92 unsigned long oprofile_mmcra_sipr;
93
94 /* Bits to clear during an oprofile exception */
95 unsigned long oprofile_mmcra_clear;
96
97 /* Name of processor class, for the ELF AT_PLATFORM entry */
98 char *platform;
99
100 /* Processor specific machine check handling. Return negative
101 * if the error is fatal, 1 if it was fully recovered and 0 to
102 * pass up (not CPU originated) */
103 int (*machine_check)(struct pt_regs *regs);
104
105 /*
106 * Processor specific early machine check handler which is
107 * called in real mode to handle SLB and TLB errors.
108 */
109 long (*machine_check_early)(struct pt_regs *regs);
110 };
111
112 extern struct cpu_spec *cur_cpu_spec;
113
114 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
115
116 extern void set_cur_cpu_spec(struct cpu_spec *s);
117 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
118 extern void identify_cpu_name(unsigned int pvr);
119 extern void do_feature_fixups(unsigned long value, void *fixup_start,
120 void *fixup_end);
121
122 extern const char *powerpc_base_platform;
123
124 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
125 extern void cpu_feature_keys_init(void);
126 #else
cpu_feature_keys_init(void)127 static inline void cpu_feature_keys_init(void) { }
128 #endif
129
130 #endif /* __ASSEMBLY__ */
131
132 /* CPU kernel features */
133
134 /* Definitions for features that we have on both 32-bit and 64-bit chips */
135 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
136 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000002)
137 #define CPU_FTR_DBELL ASM_CONST(0x00000004)
138 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000008)
139 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00000010)
140 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00000020)
141 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00000040)
142 #define CPU_FTR_LWSYNC ASM_CONST(0x00000080)
143 #define CPU_FTR_NOEXECUTE ASM_CONST(0x00000100)
144 #define CPU_FTR_EMB_HV ASM_CONST(0x00000200)
145
146 /* Definitions for features that only exist on 32-bit chips */
147 #ifdef CONFIG_PPC32
148 #define CPU_FTR_L2CR ASM_CONST(0x00002000)
149 #define CPU_FTR_SPEC7450 ASM_CONST(0x00004000)
150 #define CPU_FTR_TAU ASM_CONST(0x00008000)
151 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00010000)
152 #define CPU_FTR_L3CR ASM_CONST(0x00040000)
153 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00080000)
154 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00100000)
155 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00200000)
156 #define CPU_FTR_NO_DPM ASM_CONST(0x00400000)
157 #define CPU_FTR_476_DD2 ASM_CONST(0x00800000)
158 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x01000000)
159 #define CPU_FTR_NO_BTIC ASM_CONST(0x02000000)
160 #define CPU_FTR_PPC_LE ASM_CONST(0x04000000)
161 #define CPU_FTR_SPE ASM_CONST(0x10000000)
162 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x20000000)
163 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x40000000)
164
165 #else /* CONFIG_PPC32 */
166 /* Define these to 0 for the sake of tests in common code */
167 #define CPU_FTR_PPC_LE (0)
168 #define CPU_FTR_SPE (0)
169 #endif
170
171 /*
172 * Definitions for the 64-bit processor unique features;
173 * on 32-bit, make the names available but defined to be 0.
174 */
175 #ifdef __powerpc64__
176 #define LONG_ASM_CONST(x) ASM_CONST(x)
177 #else
178 #define LONG_ASM_CONST(x) 0
179 #endif
180
181 #define CPU_FTR_REAL_LE LONG_ASM_CONST(0x0000000000001000)
182 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000000002000)
183 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000000008000)
184 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000000010000)
185 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000000000020000)
186 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000000000040000)
187 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000000000080000)
188 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000000000100000)
189 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000000000200000)
190 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000000000400000)
191 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000000000800000)
192 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000000001000000)
193 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000000002000000)
194 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000000004000000)
195 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000000008000000)
196 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000000010000000)
197 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0000000020000000)
198 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0000000040000000)
199 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0000000080000000)
200 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0000000100000000)
201 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0000000200000000)
202 /* LONG_ASM_CONST(0x0000000400000000) Free */
203 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0000000800000000)
204 #define CPU_FTR_TM LONG_ASM_CONST(0x0000001000000000)
205 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0000002000000000)
206 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0000004000000000)
207 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0000008000000000)
208 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0000010000000000)
209 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x0000020000000000)
210 #define CPU_FTR_POWER9_DD2_1 LONG_ASM_CONST(0x0000080000000000)
211 #define CPU_FTR_P9_TM_HV_ASSIST LONG_ASM_CONST(0x0000100000000000)
212 #define CPU_FTR_P9_TM_XER_SO_BUG LONG_ASM_CONST(0x0000200000000000)
213 #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
214 #define CPU_FTR_P9_TIDR LONG_ASM_CONST(0x0000800000000000)
215 #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
216 #define CPU_FTR_P9_RADIX_PREFETCH_BUG LONG_ASM_CONST(0x0002000000000000)
217 #define CPU_FTR_ARCH_31 LONG_ASM_CONST(0x0004000000000000)
218 #define CPU_FTR_DAWR1 LONG_ASM_CONST(0x0008000000000000)
219
220 #ifndef __ASSEMBLY__
221
222 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
223
224 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
225
226 /* We only set the altivec features if the kernel was compiled with altivec
227 * support
228 */
229 #ifdef CONFIG_ALTIVEC
230 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
231 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
232 #else
233 #define CPU_FTR_ALTIVEC_COMP 0
234 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
235 #endif
236
237 /* We only set the VSX features if the kernel was compiled with VSX
238 * support
239 */
240 #ifdef CONFIG_VSX
241 #define CPU_FTR_VSX_COMP CPU_FTR_VSX
242 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
243 #else
244 #define CPU_FTR_VSX_COMP 0
245 #define PPC_FEATURE_HAS_VSX_COMP 0
246 #endif
247
248 /* We only set the spe features if the kernel was compiled with spe
249 * support
250 */
251 #ifdef CONFIG_SPE
252 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
253 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
254 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
255 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
256 #else
257 #define CPU_FTR_SPE_COMP 0
258 #define PPC_FEATURE_HAS_SPE_COMP 0
259 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
260 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
261 #endif
262
263 /* We only set the TM feature if the kernel was compiled with TM supprt */
264 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
265 #define CPU_FTR_TM_COMP CPU_FTR_TM
266 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
267 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
268 #else
269 #define CPU_FTR_TM_COMP 0
270 #define PPC_FEATURE2_HTM_COMP 0
271 #define PPC_FEATURE2_HTM_NOSC_COMP 0
272 #endif
273
274 /* We need to mark all pages as being coherent if we're SMP or we have a
275 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
276 * require it for PCI "streaming/prefetch" to work properly.
277 * This is also required by 52xx family.
278 */
279 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
280 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
281 || defined(CONFIG_PPC_MPC52xx)
282 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
283 #else
284 #define CPU_FTR_COMMON 0
285 #endif
286
287 /* The powersave features NAP & DOZE seems to confuse BDI when
288 debugging. So if a BDI is used, disable theses
289 */
290 #ifndef CONFIG_BDI_SWITCH
291 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
292 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
293 #else
294 #define CPU_FTR_MAYBE_CAN_DOZE 0
295 #define CPU_FTR_MAYBE_CAN_NAP 0
296 #endif
297
298 #define CPU_FTRS_603 (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
299 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE | CPU_FTR_NOEXECUTE)
300 #define CPU_FTRS_604 (CPU_FTR_COMMON | CPU_FTR_PPC_LE)
301 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
302 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
303 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
304 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
305 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
306 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
307 CPU_FTR_PPC_LE)
308 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
309 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
310 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
311 CPU_FTR_PPC_LE)
312 #define CPU_FTRS_750CL (CPU_FTRS_750)
313 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
314 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
315 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
316 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
317 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
318 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
319 CPU_FTR_ALTIVEC_COMP | \
320 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
321 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
322 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_L2CR | \
323 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
324 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
325 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
326 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
327 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
328 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
329 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
330 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
331 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
332 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
333 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
334 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
335 CPU_FTR_NEED_PAIRED_STWCX | \
336 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
337 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
338 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
339 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
340 CPU_FTR_NEED_PAIRED_STWCX | \
341 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
342 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
343 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
344 CPU_FTR_NEED_PAIRED_STWCX | \
345 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
346 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
347 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
348 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
349 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
350 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
351 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
352 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
353 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
354 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
355 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
356 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
357 CPU_FTR_NEED_PAIRED_STWCX)
358 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
359 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
360 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
361 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
362 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
363 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
364 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
365 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
366 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
367 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
368 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
369 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
370 #define CPU_FTRS_82XX (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_NOEXECUTE)
371 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
372 CPU_FTR_MAYBE_CAN_NAP)
373 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
374 CPU_FTR_MAYBE_CAN_NAP | \
375 CPU_FTR_COMMON | CPU_FTR_NOEXECUTE)
376 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
377 CPU_FTR_MAYBE_CAN_NAP | \
378 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE | CPU_FTR_NOEXECUTE)
379 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON)
380 #define CPU_FTRS_8XX (CPU_FTR_NOEXECUTE)
381 #define CPU_FTRS_40X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
382 #define CPU_FTRS_44X (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
383 #define CPU_FTRS_440x6 (CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
384 CPU_FTR_INDEXED_DCR)
385 #define CPU_FTRS_47X (CPU_FTRS_440x6)
386 #define CPU_FTRS_E200 (CPU_FTR_SPE_COMP | \
387 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
388 CPU_FTR_NOEXECUTE | \
389 CPU_FTR_DEBUG_LVL_EXC)
390 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | \
391 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
392 CPU_FTR_NOEXECUTE)
393 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | \
394 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
395 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
396 #define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \
397 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
398 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
399 /*
400 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
401 * same workaround as CPU_FTR_CELL_TB_BUG.
402 */
403 #define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \
404 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
405 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
406 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
407 #define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \
408 CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
409 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
410 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
411 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
412 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
413
414 /* 64-bit CPUs */
415 #define CPU_FTRS_PPC970 (CPU_FTR_LWSYNC | \
416 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
417 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
418 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
419 CPU_FTR_HVMODE | CPU_FTR_DABRX)
420 #define CPU_FTRS_POWER5 (CPU_FTR_LWSYNC | \
421 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
422 CPU_FTR_MMCRA | CPU_FTR_SMT | \
423 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
424 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
425 #define CPU_FTRS_POWER6 (CPU_FTR_LWSYNC | \
426 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
427 CPU_FTR_MMCRA | CPU_FTR_SMT | \
428 CPU_FTR_COHERENT_ICACHE | \
429 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
430 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
431 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
432 CPU_FTR_DABRX)
433 #define CPU_FTRS_POWER7 (CPU_FTR_LWSYNC | \
434 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
435 CPU_FTR_MMCRA | CPU_FTR_SMT | \
436 CPU_FTR_COHERENT_ICACHE | \
437 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
438 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
439 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
440 CPU_FTR_CFAR | CPU_FTR_HVMODE | \
441 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX )
442 #define CPU_FTRS_POWER8 (CPU_FTR_LWSYNC | \
443 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
444 CPU_FTR_MMCRA | CPU_FTR_SMT | \
445 CPU_FTR_COHERENT_ICACHE | \
446 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
447 CPU_FTR_DSCR | CPU_FTR_SAO | \
448 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
449 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
450 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
451 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP )
452 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
453 #define CPU_FTRS_POWER9 (CPU_FTR_LWSYNC | \
454 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
455 CPU_FTR_MMCRA | CPU_FTR_SMT | \
456 CPU_FTR_COHERENT_ICACHE | \
457 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
458 CPU_FTR_DSCR | CPU_FTR_SAO | \
459 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
460 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
461 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
462 CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | CPU_FTR_P9_TLBIE_STQ_BUG | \
463 CPU_FTR_P9_TLBIE_ERAT_BUG | CPU_FTR_P9_TIDR)
464 #define CPU_FTRS_POWER9_DD2_0 (CPU_FTRS_POWER9 | CPU_FTR_P9_RADIX_PREFETCH_BUG)
465 #define CPU_FTRS_POWER9_DD2_1 (CPU_FTRS_POWER9 | \
466 CPU_FTR_P9_RADIX_PREFETCH_BUG | \
467 CPU_FTR_POWER9_DD2_1)
468 #define CPU_FTRS_POWER9_DD2_2 (CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD2_1 | \
469 CPU_FTR_P9_TM_HV_ASSIST | \
470 CPU_FTR_P9_TM_XER_SO_BUG)
471 #define CPU_FTRS_POWER10 (CPU_FTR_LWSYNC | \
472 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
473 CPU_FTR_MMCRA | CPU_FTR_SMT | \
474 CPU_FTR_COHERENT_ICACHE | \
475 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
476 CPU_FTR_DSCR | CPU_FTR_SAO | \
477 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
478 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
479 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_ARCH_207S | \
480 CPU_FTR_ARCH_300 | CPU_FTR_ARCH_31 | \
481 CPU_FTR_DAWR | CPU_FTR_DAWR1)
482 #define CPU_FTRS_CELL (CPU_FTR_LWSYNC | \
483 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
484 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
485 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
486 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
487 #define CPU_FTRS_PA6T (CPU_FTR_LWSYNC | \
488 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
489 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
490 #define CPU_FTRS_COMPATIBLE (CPU_FTR_PPCAS_ARCH_V2)
491
492 #ifdef __powerpc64__
493 #ifdef CONFIG_PPC_BOOK3E
494 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
495 #else
496 #ifdef CONFIG_CPU_LITTLE_ENDIAN
497 #define CPU_FTRS_POSSIBLE \
498 (CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | CPU_FTRS_POWER8 | \
499 CPU_FTR_ALTIVEC_COMP | CPU_FTR_VSX_COMP | CPU_FTRS_POWER9 | \
500 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
501 #else
502 #define CPU_FTRS_POSSIBLE \
503 (CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
504 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
505 CPU_FTRS_POWER8 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
506 CPU_FTR_VSX_COMP | CPU_FTR_ALTIVEC_COMP | CPU_FTRS_POWER9 | \
507 CPU_FTRS_POWER9_DD2_1 | CPU_FTRS_POWER9_DD2_2 | CPU_FTRS_POWER10)
508 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
509 #endif
510 #else
511 enum {
512 CPU_FTRS_POSSIBLE =
513 #ifdef CONFIG_PPC_BOOK3S_32
514 CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
515 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
516 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
517 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
518 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
519 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
520 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
521 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
522 CPU_FTRS_CLASSIC32 |
523 #else
524 CPU_FTRS_GENERIC_32 |
525 #endif
526 #ifdef CONFIG_PPC_8xx
527 CPU_FTRS_8XX |
528 #endif
529 #ifdef CONFIG_40x
530 CPU_FTRS_40X |
531 #endif
532 #ifdef CONFIG_44x
533 CPU_FTRS_44X | CPU_FTRS_440x6 |
534 #endif
535 #ifdef CONFIG_PPC_47x
536 CPU_FTRS_47X | CPU_FTR_476_DD2 |
537 #endif
538 #ifdef CONFIG_E200
539 CPU_FTRS_E200 |
540 #endif
541 #ifdef CONFIG_E500
542 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
543 #endif
544 #ifdef CONFIG_PPC_E500MC
545 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
546 #endif
547 0,
548 };
549 #endif /* __powerpc64__ */
550
551 #ifdef __powerpc64__
552 #ifdef CONFIG_PPC_BOOK3E
553 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
554 #else
555
556 #ifdef CONFIG_PPC_DT_CPU_FTRS
557 #define CPU_FTRS_DT_CPU_BASE \
558 (CPU_FTR_LWSYNC | \
559 CPU_FTR_FPU_UNAVAILABLE | \
560 CPU_FTR_NODSISRALIGN | \
561 CPU_FTR_NOEXECUTE | \
562 CPU_FTR_COHERENT_ICACHE | \
563 CPU_FTR_STCX_CHECKS_ADDRESS | \
564 CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
565 CPU_FTR_DAWR | \
566 CPU_FTR_ARCH_206 | \
567 CPU_FTR_ARCH_207S)
568 #else
569 #define CPU_FTRS_DT_CPU_BASE (~0ul)
570 #endif
571
572 #ifdef CONFIG_CPU_LITTLE_ENDIAN
573 #define CPU_FTRS_ALWAYS \
574 (CPU_FTRS_POSSIBLE & ~CPU_FTR_HVMODE & CPU_FTRS_POWER7 & \
575 CPU_FTRS_POWER8E & CPU_FTRS_POWER8 & CPU_FTRS_POWER9 & \
576 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
577 #else
578 #define CPU_FTRS_ALWAYS \
579 (CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
580 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
581 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
582 ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & CPU_FTRS_POWER9 & \
583 CPU_FTRS_POWER9_DD2_1 & CPU_FTRS_DT_CPU_BASE)
584 #endif /* CONFIG_CPU_LITTLE_ENDIAN */
585 #endif
586 #else
587 enum {
588 CPU_FTRS_ALWAYS =
589 #ifdef CONFIG_PPC_BOOK3S_32
590 CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
591 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
592 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
593 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
594 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
595 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
596 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
597 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
598 CPU_FTRS_CLASSIC32 &
599 #else
600 CPU_FTRS_GENERIC_32 &
601 #endif
602 #ifdef CONFIG_PPC_8xx
603 CPU_FTRS_8XX &
604 #endif
605 #ifdef CONFIG_40x
606 CPU_FTRS_40X &
607 #endif
608 #ifdef CONFIG_44x
609 CPU_FTRS_44X & CPU_FTRS_440x6 &
610 #endif
611 #ifdef CONFIG_E200
612 CPU_FTRS_E200 &
613 #endif
614 #ifdef CONFIG_E500
615 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
616 #endif
617 #ifdef CONFIG_PPC_E500MC
618 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
619 #endif
620 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
621 CPU_FTRS_POSSIBLE,
622 };
623 #endif /* __powerpc64__ */
624
625 /*
626 * Maximum number of hw breakpoint supported on powerpc. Number of
627 * breakpoints supported by actual hw might be less than this, which
628 * is decided at run time in nr_wp_slots().
629 */
630 #define HBP_NUM_MAX 2
631
632 #endif /* !__ASSEMBLY__ */
633
634 #endif /* __ASM_POWERPC_CPUTABLE_H */
635
