1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KEEPINITRD 12 select ARCH_HAS_KCOV 13 select ARCH_HAS_MEMBARRIER_SYNC_CORE 14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 16 select ARCH_HAS_PHYS_TO_DMA 17 select ARCH_HAS_SETUP_DMA_OPS 18 select ARCH_HAS_SET_MEMORY 19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 20 select ARCH_HAS_STRICT_MODULE_RWX if MMU 21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU 22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU 23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 25 select ARCH_HAVE_CUSTOM_GPIO_H 26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE 35 select ARCH_USE_BUILTIN_BSWAP 36 select ARCH_USE_CMPXCHG_LOCKREF 37 select ARCH_USE_MEMTEST 38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 39 select ARCH_WANT_IPC_PARSE_VERSION 40 select ARCH_WANT_LD_ORPHAN_WARN 41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 42 select BUILDTIME_TABLE_SORT if MMU 43 select CLONE_BACKWARDS 44 select CPU_PM if SUSPEND || CPU_IDLE 45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 46 select DMA_DECLARE_COHERENT 47 select DMA_GLOBAL_POOL if !MMU 48 select DMA_OPS 49 select DMA_REMAP if MMU 50 select EDAC_SUPPORT 51 select EDAC_ATOMIC_SCRUB 52 select GENERIC_ALLOCATOR 53 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 54 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 55 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 56 select GENERIC_IRQ_IPI if SMP 57 select GENERIC_CPU_AUTOPROBE 58 select GENERIC_EARLY_IOREMAP 59 select GENERIC_IDLE_POLL_SETUP 60 select GENERIC_IRQ_PROBE 61 select GENERIC_IRQ_SHOW 62 select GENERIC_IRQ_SHOW_LEVEL 63 select GENERIC_LIB_DEVMEM_IS_ALLOWED 64 select GENERIC_PCI_IOMAP 65 select GENERIC_SCHED_CLOCK 66 select GENERIC_SMP_IDLE_THREAD 67 select HANDLE_DOMAIN_IRQ 68 select HARDIRQS_SW_RESEND 69 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 70 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 71 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 72 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 73 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 74 select HAVE_ARCH_MMAP_RND_BITS if MMU 75 select HAVE_ARCH_PFN_VALID 76 select HAVE_ARCH_SECCOMP 77 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 78 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 79 select HAVE_ARCH_TRACEHOOK 80 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE 81 select HAVE_ARM_SMCCC if CPU_V7 82 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 83 select HAVE_CONTEXT_TRACKING 84 select HAVE_C_RECORDMCOUNT 85 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 86 select HAVE_DMA_CONTIGUOUS if MMU 87 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 88 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 89 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 90 select HAVE_EXIT_THREAD 91 select HAVE_FAST_GUP if ARM_LPAE 92 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 93 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 94 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 95 select HAVE_FUTEX_CMPXCHG if FUTEX 96 select HAVE_GCC_PLUGINS 97 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 98 select HAVE_IRQ_TIME_ACCOUNTING 99 select HAVE_KERNEL_GZIP 100 select HAVE_KERNEL_LZ4 101 select HAVE_KERNEL_LZMA 102 select HAVE_KERNEL_LZO 103 select HAVE_KERNEL_XZ 104 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 105 select HAVE_KRETPROBES if HAVE_KPROBES 106 select HAVE_MOD_ARCH_SPECIFIC 107 select HAVE_NMI 108 select HAVE_OPTPROBES if !THUMB2_KERNEL 109 select HAVE_PERF_EVENTS 110 select HAVE_PERF_REGS 111 select HAVE_PERF_USER_STACK_DUMP 112 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 113 select HAVE_REGS_AND_STACK_ACCESS_API 114 select HAVE_RSEQ 115 select HAVE_STACKPROTECTOR 116 select HAVE_SYSCALL_TRACEPOINTS 117 select HAVE_UID16 118 select HAVE_VIRT_CPU_ACCOUNTING_GEN 119 select IRQ_FORCED_THREADING 120 select MODULES_USE_ELF_REL 121 select NEED_DMA_MAP_STATE 122 select OF_EARLY_FLATTREE if OF 123 select OLD_SIGACTION 124 select OLD_SIGSUSPEND3 125 select PCI_SYSCALL if PCI 126 select PERF_USE_VMALLOC 127 select RTC_LIB 128 select SYS_SUPPORTS_APM_EMULATION 129 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M 130 # Above selects are sorted alphabetically; please add new ones 131 # according to that. Thanks. 132 help 133 The ARM series is a line of low-power-consumption RISC chip designs 134 licensed by ARM Ltd and targeted at embedded applications and 135 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 136 manufactured, but legacy ARM-based PC hardware remains popular in 137 Europe. There is an ARM Linux project with a web page at 138 <http://www.arm.linux.org.uk/>. 139 140config ARM_HAS_SG_CHAIN 141 bool 142 143config ARM_DMA_USE_IOMMU 144 bool 145 select ARM_HAS_SG_CHAIN 146 select NEED_SG_DMA_LENGTH 147 148if ARM_DMA_USE_IOMMU 149 150config ARM_DMA_IOMMU_ALIGNMENT 151 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 152 range 4 9 153 default 8 154 help 155 DMA mapping framework by default aligns all buffers to the smallest 156 PAGE_SIZE order which is greater than or equal to the requested buffer 157 size. This works well for buffers up to a few hundreds kilobytes, but 158 for larger buffers it just a waste of address space. Drivers which has 159 relatively small addressing window (like 64Mib) might run out of 160 virtual space with just a few allocations. 161 162 With this parameter you can specify the maximum PAGE_SIZE order for 163 DMA IOMMU buffers. Larger buffers will be aligned only to this 164 specified order. The order is expressed as a power of two multiplied 165 by the PAGE_SIZE. 166 167endif 168 169config SYS_SUPPORTS_APM_EMULATION 170 bool 171 172config HAVE_TCM 173 bool 174 select GENERIC_ALLOCATOR 175 176config HAVE_PROC_CPU 177 bool 178 179config NO_IOPORT_MAP 180 bool 181 182config SBUS 183 bool 184 185config STACKTRACE_SUPPORT 186 bool 187 default y 188 189config LOCKDEP_SUPPORT 190 bool 191 default y 192 193config ARCH_HAS_ILOG2_U32 194 bool 195 196config ARCH_HAS_ILOG2_U64 197 bool 198 199config ARCH_HAS_BANDGAP 200 bool 201 202config FIX_EARLYCON_MEM 203 def_bool y if MMU 204 205config GENERIC_HWEIGHT 206 bool 207 default y 208 209config GENERIC_CALIBRATE_DELAY 210 bool 211 default y 212 213config ARCH_MAY_HAVE_PC_FDC 214 bool 215 216config ARCH_SUPPORTS_UPROBES 217 def_bool y 218 219config ARCH_HAS_DMA_SET_COHERENT_MASK 220 bool 221 222config GENERIC_ISA_DMA 223 bool 224 225config FIQ 226 bool 227 228config NEED_RET_TO_USER 229 bool 230 231config ARCH_MTD_XIP 232 bool 233 234config ARM_PATCH_PHYS_VIRT 235 bool "Patch physical to virtual translations at runtime" if EMBEDDED 236 default y 237 depends on !XIP_KERNEL && MMU 238 help 239 Patch phys-to-virt and virt-to-phys translation functions at 240 boot and module load time according to the position of the 241 kernel in system memory. 242 243 This can only be used with non-XIP MMU kernels where the base 244 of physical memory is at a 2 MiB boundary. 245 246 Only disable this option if you know that you do not require 247 this feature (eg, building a kernel for a single machine) and 248 you need to shrink the kernel to the minimal size. 249 250config NEED_MACH_IO_H 251 bool 252 help 253 Select this when mach/io.h is required to provide special 254 definitions for this platform. The need for mach/io.h should 255 be avoided when possible. 256 257config NEED_MACH_MEMORY_H 258 bool 259 help 260 Select this when mach/memory.h is required to provide special 261 definitions for this platform. The need for mach/memory.h should 262 be avoided when possible. 263 264config PHYS_OFFSET 265 hex "Physical address of main memory" if MMU 266 depends on !ARM_PATCH_PHYS_VIRT 267 default DRAM_BASE if !MMU 268 default 0x00000000 if ARCH_FOOTBRIDGE 269 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 270 default 0x20000000 if ARCH_S5PV210 271 default 0xc0000000 if ARCH_SA1100 272 help 273 Please provide the physical address corresponding to the 274 location of main memory in your system. 275 276config GENERIC_BUG 277 def_bool y 278 depends on BUG 279 280config PGTABLE_LEVELS 281 int 282 default 3 if ARM_LPAE 283 default 2 284 285menu "System Type" 286 287config MMU 288 bool "MMU-based Paged Memory Management Support" 289 default y 290 help 291 Select if you want MMU-based virtualised addressing space 292 support by paged memory management. If unsure, say 'Y'. 293 294config ARCH_MMAP_RND_BITS_MIN 295 default 8 296 297config ARCH_MMAP_RND_BITS_MAX 298 default 14 if PAGE_OFFSET=0x40000000 299 default 15 if PAGE_OFFSET=0x80000000 300 default 16 301 302# 303# The "ARM system type" choice list is ordered alphabetically by option 304# text. Please add new entries in the option alphabetic order. 305# 306choice 307 prompt "ARM system type" 308 default ARM_SINGLE_ARMV7M if !MMU 309 default ARCH_MULTIPLATFORM if MMU 310 311config ARCH_MULTIPLATFORM 312 bool "Allow multiple platforms to be selected" 313 depends on MMU 314 select ARCH_FLATMEM_ENABLE 315 select ARCH_SPARSEMEM_ENABLE 316 select ARCH_SELECT_MEMORY_MODEL 317 select ARM_HAS_SG_CHAIN 318 select ARM_PATCH_PHYS_VIRT 319 select AUTO_ZRELADDR 320 select TIMER_OF 321 select COMMON_CLK 322 select GENERIC_IRQ_MULTI_HANDLER 323 select HAVE_PCI 324 select PCI_DOMAINS_GENERIC if PCI 325 select SPARSE_IRQ 326 select USE_OF 327 328config ARM_SINGLE_ARMV7M 329 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 330 depends on !MMU 331 select ARM_NVIC 332 select AUTO_ZRELADDR 333 select TIMER_OF 334 select COMMON_CLK 335 select CPU_V7M 336 select NO_IOPORT_MAP 337 select SPARSE_IRQ 338 select USE_OF 339 340config ARCH_EP93XX 341 bool "EP93xx-based" 342 select ARCH_SPARSEMEM_ENABLE 343 select ARM_AMBA 344 imply ARM_PATCH_PHYS_VIRT 345 select ARM_VIC 346 select GENERIC_IRQ_MULTI_HANDLER 347 select AUTO_ZRELADDR 348 select CLKSRC_MMIO 349 select CPU_ARM920T 350 select GPIOLIB 351 select HAVE_LEGACY_CLK 352 help 353 This enables support for the Cirrus EP93xx series of CPUs. 354 355config ARCH_FOOTBRIDGE 356 bool "FootBridge" 357 select CPU_SA110 358 select FOOTBRIDGE 359 select NEED_MACH_IO_H if !MMU 360 select NEED_MACH_MEMORY_H 361 help 362 Support for systems based on the DC21285 companion chip 363 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 364 365config ARCH_IOP32X 366 bool "IOP32x-based" 367 depends on MMU 368 select CPU_XSCALE 369 select GPIO_IOP 370 select GPIOLIB 371 select NEED_RET_TO_USER 372 select FORCE_PCI 373 select PLAT_IOP 374 help 375 Support for Intel's 80219 and IOP32X (XScale) family of 376 processors. 377 378config ARCH_IXP4XX 379 bool "IXP4xx-based" 380 depends on MMU 381 select ARCH_HAS_DMA_SET_COHERENT_MASK 382 select ARCH_SUPPORTS_BIG_ENDIAN 383 select CPU_XSCALE 384 select DMABOUNCE if PCI 385 select GENERIC_IRQ_MULTI_HANDLER 386 select GPIO_IXP4XX 387 select GPIOLIB 388 select HAVE_PCI 389 select IXP4XX_IRQ 390 select IXP4XX_TIMER 391 # With the new PCI driver this is not needed 392 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY 393 select USB_EHCI_BIG_ENDIAN_DESC 394 select USB_EHCI_BIG_ENDIAN_MMIO 395 help 396 Support for Intel's IXP4XX (XScale) family of processors. 397 398config ARCH_DOVE 399 bool "Marvell Dove" 400 select CPU_PJ4 401 select GENERIC_IRQ_MULTI_HANDLER 402 select GPIOLIB 403 select HAVE_PCI 404 select MVEBU_MBUS 405 select PINCTRL 406 select PINCTRL_DOVE 407 select PLAT_ORION_LEGACY 408 select SPARSE_IRQ 409 select PM_GENERIC_DOMAINS if PM 410 help 411 Support for the Marvell Dove SoC 88AP510 412 413config ARCH_PXA 414 bool "PXA2xx/PXA3xx-based" 415 depends on MMU 416 select ARCH_MTD_XIP 417 select ARM_CPU_SUSPEND if PM 418 select AUTO_ZRELADDR 419 select COMMON_CLK 420 select CLKSRC_PXA 421 select CLKSRC_MMIO 422 select TIMER_OF 423 select CPU_XSCALE if !CPU_XSC3 424 select GENERIC_IRQ_MULTI_HANDLER 425 select GPIO_PXA 426 select GPIOLIB 427 select IRQ_DOMAIN 428 select PLAT_PXA 429 select SPARSE_IRQ 430 help 431 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 432 433config ARCH_RPC 434 bool "RiscPC" 435 depends on MMU 436 select ARCH_ACORN 437 select ARCH_MAY_HAVE_PC_FDC 438 select ARCH_SPARSEMEM_ENABLE 439 select ARM_HAS_SG_CHAIN 440 select CPU_SA110 441 select FIQ 442 select HAVE_PATA_PLATFORM 443 select ISA_DMA_API 444 select LEGACY_TIMER_TICK 445 select NEED_MACH_IO_H 446 select NEED_MACH_MEMORY_H 447 select NO_IOPORT_MAP 448 help 449 On the Acorn Risc-PC, Linux can support the internal IDE disk and 450 CD-ROM interface, serial and parallel port, and the floppy drive. 451 452config ARCH_SA1100 453 bool "SA1100-based" 454 select ARCH_MTD_XIP 455 select ARCH_SPARSEMEM_ENABLE 456 select CLKSRC_MMIO 457 select CLKSRC_PXA 458 select TIMER_OF if OF 459 select COMMON_CLK 460 select CPU_FREQ 461 select CPU_SA1100 462 select GENERIC_IRQ_MULTI_HANDLER 463 select GPIOLIB 464 select IRQ_DOMAIN 465 select ISA 466 select NEED_MACH_MEMORY_H 467 select SPARSE_IRQ 468 help 469 Support for StrongARM 11x0 based boards. 470 471config ARCH_S3C24XX 472 bool "Samsung S3C24XX SoCs" 473 select ATAGS 474 select CLKSRC_SAMSUNG_PWM 475 select GPIO_SAMSUNG 476 select GPIOLIB 477 select GENERIC_IRQ_MULTI_HANDLER 478 select HAVE_S3C2410_I2C if I2C 479 select HAVE_S3C_RTC if RTC_CLASS 480 select NEED_MACH_IO_H 481 select S3C2410_WATCHDOG 482 select SAMSUNG_ATAGS 483 select USE_OF 484 select WATCHDOG 485 help 486 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 487 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 488 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 489 Samsung SMDK2410 development board (and derivatives). 490 491config ARCH_OMAP1 492 bool "TI OMAP1" 493 depends on MMU 494 select ARCH_OMAP 495 select CLKSRC_MMIO 496 select GENERIC_IRQ_CHIP 497 select GENERIC_IRQ_MULTI_HANDLER 498 select GPIOLIB 499 select HAVE_LEGACY_CLK 500 select IRQ_DOMAIN 501 select NEED_MACH_IO_H if PCCARD 502 select NEED_MACH_MEMORY_H 503 select SPARSE_IRQ 504 help 505 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 506 507endchoice 508 509menu "Multiple platform selection" 510 depends on ARCH_MULTIPLATFORM 511 512comment "CPU Core family selection" 513 514config ARCH_MULTI_V4 515 bool "ARMv4 based platforms (FA526)" 516 depends on !ARCH_MULTI_V6_V7 517 select ARCH_MULTI_V4_V5 518 select CPU_FA526 519 520config ARCH_MULTI_V4T 521 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 522 depends on !ARCH_MULTI_V6_V7 523 select ARCH_MULTI_V4_V5 524 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 525 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 526 CPU_ARM925T || CPU_ARM940T) 527 528config ARCH_MULTI_V5 529 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 530 depends on !ARCH_MULTI_V6_V7 531 select ARCH_MULTI_V4_V5 532 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 533 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 534 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 535 536config ARCH_MULTI_V4_V5 537 bool 538 539config ARCH_MULTI_V6 540 bool "ARMv6 based platforms (ARM11)" 541 select ARCH_MULTI_V6_V7 542 select CPU_V6K 543 544config ARCH_MULTI_V7 545 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 546 default y 547 select ARCH_MULTI_V6_V7 548 select CPU_V7 549 select HAVE_SMP 550 551config ARCH_MULTI_V6_V7 552 bool 553 select MIGHT_HAVE_CACHE_L2X0 554 555config ARCH_MULTI_CPU_AUTO 556 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 557 select ARCH_MULTI_V5 558 559endmenu 560 561config ARCH_VIRT 562 bool "Dummy Virtual Machine" 563 depends on ARCH_MULTI_V7 564 select ARM_AMBA 565 select ARM_GIC 566 select ARM_GIC_V2M if PCI 567 select ARM_GIC_V3 568 select ARM_GIC_V3_ITS if PCI 569 select ARM_PSCI 570 select HAVE_ARM_ARCH_TIMER 571 select ARCH_SUPPORTS_BIG_ENDIAN 572 573# 574# This is sorted alphabetically by mach-* pathname. However, plat-* 575# Kconfigs may be included either alphabetically (according to the 576# plat- suffix) or along side the corresponding mach-* source. 577# 578source "arch/arm/mach-actions/Kconfig" 579 580source "arch/arm/mach-alpine/Kconfig" 581 582source "arch/arm/mach-artpec/Kconfig" 583 584source "arch/arm/mach-asm9260/Kconfig" 585 586source "arch/arm/mach-aspeed/Kconfig" 587 588source "arch/arm/mach-at91/Kconfig" 589 590source "arch/arm/mach-axxia/Kconfig" 591 592source "arch/arm/mach-bcm/Kconfig" 593 594source "arch/arm/mach-berlin/Kconfig" 595 596source "arch/arm/mach-clps711x/Kconfig" 597 598source "arch/arm/mach-cns3xxx/Kconfig" 599 600source "arch/arm/mach-davinci/Kconfig" 601 602source "arch/arm/mach-digicolor/Kconfig" 603 604source "arch/arm/mach-dove/Kconfig" 605 606source "arch/arm/mach-ep93xx/Kconfig" 607 608source "arch/arm/mach-exynos/Kconfig" 609 610source "arch/arm/mach-footbridge/Kconfig" 611 612source "arch/arm/mach-gemini/Kconfig" 613 614source "arch/arm/mach-highbank/Kconfig" 615 616source "arch/arm/mach-hisi/Kconfig" 617 618source "arch/arm/mach-imx/Kconfig" 619 620source "arch/arm/mach-integrator/Kconfig" 621 622source "arch/arm/mach-iop32x/Kconfig" 623 624source "arch/arm/mach-ixp4xx/Kconfig" 625 626source "arch/arm/mach-keystone/Kconfig" 627 628source "arch/arm/mach-lpc32xx/Kconfig" 629 630source "arch/arm/mach-mediatek/Kconfig" 631 632source "arch/arm/mach-meson/Kconfig" 633 634source "arch/arm/mach-milbeaut/Kconfig" 635 636source "arch/arm/mach-mmp/Kconfig" 637 638source "arch/arm/mach-moxart/Kconfig" 639 640source "arch/arm/mach-mstar/Kconfig" 641 642source "arch/arm/mach-mv78xx0/Kconfig" 643 644source "arch/arm/mach-mvebu/Kconfig" 645 646source "arch/arm/mach-mxs/Kconfig" 647 648source "arch/arm/mach-nomadik/Kconfig" 649 650source "arch/arm/mach-npcm/Kconfig" 651 652source "arch/arm/mach-nspire/Kconfig" 653 654source "arch/arm/plat-omap/Kconfig" 655 656source "arch/arm/mach-omap1/Kconfig" 657 658source "arch/arm/mach-omap2/Kconfig" 659 660source "arch/arm/mach-orion5x/Kconfig" 661 662source "arch/arm/mach-oxnas/Kconfig" 663 664source "arch/arm/mach-pxa/Kconfig" 665source "arch/arm/plat-pxa/Kconfig" 666 667source "arch/arm/mach-qcom/Kconfig" 668 669source "arch/arm/mach-rda/Kconfig" 670 671source "arch/arm/mach-realtek/Kconfig" 672 673source "arch/arm/mach-realview/Kconfig" 674 675source "arch/arm/mach-rockchip/Kconfig" 676 677source "arch/arm/mach-s3c/Kconfig" 678 679source "arch/arm/mach-s5pv210/Kconfig" 680 681source "arch/arm/mach-sa1100/Kconfig" 682 683source "arch/arm/mach-shmobile/Kconfig" 684 685source "arch/arm/mach-socfpga/Kconfig" 686 687source "arch/arm/mach-spear/Kconfig" 688 689source "arch/arm/mach-sti/Kconfig" 690 691source "arch/arm/mach-stm32/Kconfig" 692 693source "arch/arm/mach-sunxi/Kconfig" 694 695source "arch/arm/mach-tegra/Kconfig" 696 697source "arch/arm/mach-uniphier/Kconfig" 698 699source "arch/arm/mach-ux500/Kconfig" 700 701source "arch/arm/mach-versatile/Kconfig" 702 703source "arch/arm/mach-vexpress/Kconfig" 704 705source "arch/arm/mach-vt8500/Kconfig" 706 707source "arch/arm/mach-zynq/Kconfig" 708 709# ARMv7-M architecture 710config ARCH_LPC18XX 711 bool "NXP LPC18xx/LPC43xx" 712 depends on ARM_SINGLE_ARMV7M 713 select ARCH_HAS_RESET_CONTROLLER 714 select ARM_AMBA 715 select CLKSRC_LPC32XX 716 select PINCTRL 717 help 718 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 719 high performance microcontrollers. 720 721config ARCH_MPS2 722 bool "ARM MPS2 platform" 723 depends on ARM_SINGLE_ARMV7M 724 select ARM_AMBA 725 select CLKSRC_MPS2 726 help 727 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 728 with a range of available cores like Cortex-M3/M4/M7. 729 730 Please, note that depends which Application Note is used memory map 731 for the platform may vary, so adjustment of RAM base might be needed. 732 733# Definitions to make life easier 734config ARCH_ACORN 735 bool 736 737config PLAT_IOP 738 bool 739 740config PLAT_ORION 741 bool 742 select CLKSRC_MMIO 743 select COMMON_CLK 744 select GENERIC_IRQ_CHIP 745 select IRQ_DOMAIN 746 747config PLAT_ORION_LEGACY 748 bool 749 select PLAT_ORION 750 751config PLAT_PXA 752 bool 753 754config PLAT_VERSATILE 755 bool 756 757source "arch/arm/mm/Kconfig" 758 759config IWMMXT 760 bool "Enable iWMMXt support" 761 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 762 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 763 help 764 Enable support for iWMMXt context switching at run time if 765 running on a CPU that supports it. 766 767if !MMU 768source "arch/arm/Kconfig-nommu" 769endif 770 771config PJ4B_ERRATA_4742 772 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 773 depends on CPU_PJ4B && MACH_ARMADA_370 774 default y 775 help 776 When coming out of either a Wait for Interrupt (WFI) or a Wait for 777 Event (WFE) IDLE states, a specific timing sensitivity exists between 778 the retiring WFI/WFE instructions and the newly issued subsequent 779 instructions. This sensitivity can result in a CPU hang scenario. 780 Workaround: 781 The software must insert either a Data Synchronization Barrier (DSB) 782 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 783 instruction 784 785config ARM_ERRATA_326103 786 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 787 depends on CPU_V6 788 help 789 Executing a SWP instruction to read-only memory does not set bit 11 790 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 791 treat the access as a read, preventing a COW from occurring and 792 causing the faulting task to livelock. 793 794config ARM_ERRATA_411920 795 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 796 depends on CPU_V6 || CPU_V6K 797 help 798 Invalidation of the Instruction Cache operation can 799 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 800 It does not affect the MPCore. This option enables the ARM Ltd. 801 recommended workaround. 802 803config ARM_ERRATA_430973 804 bool "ARM errata: Stale prediction on replaced interworking branch" 805 depends on CPU_V7 806 help 807 This option enables the workaround for the 430973 Cortex-A8 808 r1p* erratum. If a code sequence containing an ARM/Thumb 809 interworking branch is replaced with another code sequence at the 810 same virtual address, whether due to self-modifying code or virtual 811 to physical address re-mapping, Cortex-A8 does not recover from the 812 stale interworking branch prediction. This results in Cortex-A8 813 executing the new code sequence in the incorrect ARM or Thumb state. 814 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 815 and also flushes the branch target cache at every context switch. 816 Note that setting specific bits in the ACTLR register may not be 817 available in non-secure mode. 818 819config ARM_ERRATA_458693 820 bool "ARM errata: Processor deadlock when a false hazard is created" 821 depends on CPU_V7 822 depends on !ARCH_MULTIPLATFORM 823 help 824 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 825 erratum. For very specific sequences of memory operations, it is 826 possible for a hazard condition intended for a cache line to instead 827 be incorrectly associated with a different cache line. This false 828 hazard might then cause a processor deadlock. The workaround enables 829 the L1 caching of the NEON accesses and disables the PLD instruction 830 in the ACTLR register. Note that setting specific bits in the ACTLR 831 register may not be available in non-secure mode. 832 833config ARM_ERRATA_460075 834 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 835 depends on CPU_V7 836 depends on !ARCH_MULTIPLATFORM 837 help 838 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 839 erratum. Any asynchronous access to the L2 cache may encounter a 840 situation in which recent store transactions to the L2 cache are lost 841 and overwritten with stale memory contents from external memory. The 842 workaround disables the write-allocate mode for the L2 cache via the 843 ACTLR register. Note that setting specific bits in the ACTLR register 844 may not be available in non-secure mode. 845 846config ARM_ERRATA_742230 847 bool "ARM errata: DMB operation may be faulty" 848 depends on CPU_V7 && SMP 849 depends on !ARCH_MULTIPLATFORM 850 help 851 This option enables the workaround for the 742230 Cortex-A9 852 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 853 between two write operations may not ensure the correct visibility 854 ordering of the two writes. This workaround sets a specific bit in 855 the diagnostic register of the Cortex-A9 which causes the DMB 856 instruction to behave as a DSB, ensuring the correct behaviour of 857 the two writes. 858 859config ARM_ERRATA_742231 860 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 861 depends on CPU_V7 && SMP 862 depends on !ARCH_MULTIPLATFORM 863 help 864 This option enables the workaround for the 742231 Cortex-A9 865 (r2p0..r2p2) erratum. Under certain conditions, specific to the 866 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 867 accessing some data located in the same cache line, may get corrupted 868 data due to bad handling of the address hazard when the line gets 869 replaced from one of the CPUs at the same time as another CPU is 870 accessing it. This workaround sets specific bits in the diagnostic 871 register of the Cortex-A9 which reduces the linefill issuing 872 capabilities of the processor. 873 874config ARM_ERRATA_643719 875 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 876 depends on CPU_V7 && SMP 877 default y 878 help 879 This option enables the workaround for the 643719 Cortex-A9 (prior to 880 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 881 register returns zero when it should return one. The workaround 882 corrects this value, ensuring cache maintenance operations which use 883 it behave as intended and avoiding data corruption. 884 885config ARM_ERRATA_720789 886 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 887 depends on CPU_V7 888 help 889 This option enables the workaround for the 720789 Cortex-A9 (prior to 890 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 891 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 892 As a consequence of this erratum, some TLB entries which should be 893 invalidated are not, resulting in an incoherency in the system page 894 tables. The workaround changes the TLB flushing routines to invalidate 895 entries regardless of the ASID. 896 897config ARM_ERRATA_743622 898 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 899 depends on CPU_V7 900 depends on !ARCH_MULTIPLATFORM 901 help 902 This option enables the workaround for the 743622 Cortex-A9 903 (r2p*) erratum. Under very rare conditions, a faulty 904 optimisation in the Cortex-A9 Store Buffer may lead to data 905 corruption. This workaround sets a specific bit in the diagnostic 906 register of the Cortex-A9 which disables the Store Buffer 907 optimisation, preventing the defect from occurring. This has no 908 visible impact on the overall performance or power consumption of the 909 processor. 910 911config ARM_ERRATA_751472 912 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 913 depends on CPU_V7 914 depends on !ARCH_MULTIPLATFORM 915 help 916 This option enables the workaround for the 751472 Cortex-A9 (prior 917 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 918 completion of a following broadcasted operation if the second 919 operation is received by a CPU before the ICIALLUIS has completed, 920 potentially leading to corrupted entries in the cache or TLB. 921 922config ARM_ERRATA_754322 923 bool "ARM errata: possible faulty MMU translations following an ASID switch" 924 depends on CPU_V7 925 help 926 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 927 r3p*) erratum. A speculative memory access may cause a page table walk 928 which starts prior to an ASID switch but completes afterwards. This 929 can populate the micro-TLB with a stale entry which may be hit with 930 the new ASID. This workaround places two dsb instructions in the mm 931 switching code so that no page table walks can cross the ASID switch. 932 933config ARM_ERRATA_754327 934 bool "ARM errata: no automatic Store Buffer drain" 935 depends on CPU_V7 && SMP 936 help 937 This option enables the workaround for the 754327 Cortex-A9 (prior to 938 r2p0) erratum. The Store Buffer does not have any automatic draining 939 mechanism and therefore a livelock may occur if an external agent 940 continuously polls a memory location waiting to observe an update. 941 This workaround defines cpu_relax() as smp_mb(), preventing correctly 942 written polling loops from denying visibility of updates to memory. 943 944config ARM_ERRATA_364296 945 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 946 depends on CPU_V6 947 help 948 This options enables the workaround for the 364296 ARM1136 949 r0p2 erratum (possible cache data corruption with 950 hit-under-miss enabled). It sets the undocumented bit 31 in 951 the auxiliary control register and the FI bit in the control 952 register, thus disabling hit-under-miss without putting the 953 processor into full low interrupt latency mode. ARM11MPCore 954 is not affected. 955 956config ARM_ERRATA_764369 957 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 958 depends on CPU_V7 && SMP 959 help 960 This option enables the workaround for erratum 764369 961 affecting Cortex-A9 MPCore with two or more processors (all 962 current revisions). Under certain timing circumstances, a data 963 cache line maintenance operation by MVA targeting an Inner 964 Shareable memory region may fail to proceed up to either the 965 Point of Coherency or to the Point of Unification of the 966 system. This workaround adds a DSB instruction before the 967 relevant cache maintenance functions and sets a specific bit 968 in the diagnostic control register of the SCU. 969 970config ARM_ERRATA_775420 971 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 972 depends on CPU_V7 973 help 974 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 975 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 976 operation aborts with MMU exception, it might cause the processor 977 to deadlock. This workaround puts DSB before executing ISB if 978 an abort may occur on cache maintenance. 979 980config ARM_ERRATA_798181 981 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 982 depends on CPU_V7 && SMP 983 help 984 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 985 adequately shooting down all use of the old entries. This 986 option enables the Linux kernel workaround for this erratum 987 which sends an IPI to the CPUs that are running the same ASID 988 as the one being invalidated. 989 990config ARM_ERRATA_773022 991 bool "ARM errata: incorrect instructions may be executed from loop buffer" 992 depends on CPU_V7 993 help 994 This option enables the workaround for the 773022 Cortex-A15 995 (up to r0p4) erratum. In certain rare sequences of code, the 996 loop buffer may deliver incorrect instructions. This 997 workaround disables the loop buffer to avoid the erratum. 998 999config ARM_ERRATA_818325_852422 1000 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1001 depends on CPU_V7 1002 help 1003 This option enables the workaround for: 1004 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1005 instruction might deadlock. Fixed in r0p1. 1006 - Cortex-A12 852422: Execution of a sequence of instructions might 1007 lead to either a data corruption or a CPU deadlock. Not fixed in 1008 any Cortex-A12 cores yet. 1009 This workaround for all both errata involves setting bit[12] of the 1010 Feature Register. This bit disables an optimisation applied to a 1011 sequence of 2 instructions that use opposing condition codes. 1012 1013config ARM_ERRATA_821420 1014 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1015 depends on CPU_V7 1016 help 1017 This option enables the workaround for the 821420 Cortex-A12 1018 (all revs) erratum. In very rare timing conditions, a sequence 1019 of VMOV to Core registers instructions, for which the second 1020 one is in the shadow of a branch or abort, can lead to a 1021 deadlock when the VMOV instructions are issued out-of-order. 1022 1023config ARM_ERRATA_825619 1024 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1025 depends on CPU_V7 1026 help 1027 This option enables the workaround for the 825619 Cortex-A12 1028 (all revs) erratum. Within rare timing constraints, executing a 1029 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1030 and Device/Strongly-Ordered loads and stores might cause deadlock 1031 1032config ARM_ERRATA_857271 1033 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1034 depends on CPU_V7 1035 help 1036 This option enables the workaround for the 857271 Cortex-A12 1037 (all revs) erratum. Under very rare timing conditions, the CPU might 1038 hang. The workaround is expected to have a < 1% performance impact. 1039 1040config ARM_ERRATA_852421 1041 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1042 depends on CPU_V7 1043 help 1044 This option enables the workaround for the 852421 Cortex-A17 1045 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1046 execution of a DMB ST instruction might fail to properly order 1047 stores from GroupA and stores from GroupB. 1048 1049config ARM_ERRATA_852423 1050 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1051 depends on CPU_V7 1052 help 1053 This option enables the workaround for: 1054 - Cortex-A17 852423: Execution of a sequence of instructions might 1055 lead to either a data corruption or a CPU deadlock. Not fixed in 1056 any Cortex-A17 cores yet. 1057 This is identical to Cortex-A12 erratum 852422. It is a separate 1058 config option from the A12 erratum due to the way errata are checked 1059 for and handled. 1060 1061config ARM_ERRATA_857272 1062 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1063 depends on CPU_V7 1064 help 1065 This option enables the workaround for the 857272 Cortex-A17 erratum. 1066 This erratum is not known to be fixed in any A17 revision. 1067 This is identical to Cortex-A12 erratum 857271. It is a separate 1068 config option from the A12 erratum due to the way errata are checked 1069 for and handled. 1070 1071endmenu 1072 1073source "arch/arm/common/Kconfig" 1074 1075menu "Bus support" 1076 1077config ISA 1078 bool 1079 help 1080 Find out whether you have ISA slots on your motherboard. ISA is the 1081 name of a bus system, i.e. the way the CPU talks to the other stuff 1082 inside your box. Other bus systems are PCI, EISA, MicroChannel 1083 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1084 newer boards don't support it. If you have ISA, say Y, otherwise N. 1085 1086# Select ISA DMA controller support 1087config ISA_DMA 1088 bool 1089 select ISA_DMA_API 1090 1091# Select ISA DMA interface 1092config ISA_DMA_API 1093 bool 1094 1095config PCI_NANOENGINE 1096 bool "BSE nanoEngine PCI support" 1097 depends on SA1100_NANOENGINE 1098 help 1099 Enable PCI on the BSE nanoEngine board. 1100 1101config ARM_ERRATA_814220 1102 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1103 depends on CPU_V7 1104 help 1105 The v7 ARM states that all cache and branch predictor maintenance 1106 operations that do not specify an address execute, relative to 1107 each other, in program order. 1108 However, because of this erratum, an L2 set/way cache maintenance 1109 operation can overtake an L1 set/way cache maintenance operation. 1110 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1111 r0p4, r0p5. 1112 1113endmenu 1114 1115menu "Kernel Features" 1116 1117config HAVE_SMP 1118 bool 1119 help 1120 This option should be selected by machines which have an SMP- 1121 capable CPU. 1122 1123 The only effect of this option is to make the SMP-related 1124 options available to the user for configuration. 1125 1126config SMP 1127 bool "Symmetric Multi-Processing" 1128 depends on CPU_V6K || CPU_V7 1129 depends on HAVE_SMP 1130 depends on MMU || ARM_MPU 1131 select IRQ_WORK 1132 help 1133 This enables support for systems with more than one CPU. If you have 1134 a system with only one CPU, say N. If you have a system with more 1135 than one CPU, say Y. 1136 1137 If you say N here, the kernel will run on uni- and multiprocessor 1138 machines, but will use only one CPU of a multiprocessor machine. If 1139 you say Y here, the kernel will run on many, but not all, 1140 uniprocessor machines. On a uniprocessor machine, the kernel 1141 will run faster if you say N here. 1142 1143 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1144 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1145 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1146 1147 If you don't know what to do here, say N. 1148 1149config SMP_ON_UP 1150 bool "Allow booting SMP kernel on uniprocessor systems" 1151 depends on SMP && !XIP_KERNEL && MMU 1152 default y 1153 help 1154 SMP kernels contain instructions which fail on non-SMP processors. 1155 Enabling this option allows the kernel to modify itself to make 1156 these instructions safe. Disabling it allows about 1K of space 1157 savings. 1158 1159 If you don't know what to do here, say Y. 1160 1161config ARM_CPU_TOPOLOGY 1162 bool "Support cpu topology definition" 1163 depends on SMP && CPU_V7 1164 default y 1165 help 1166 Support ARM cpu topology definition. The MPIDR register defines 1167 affinity between processors which is then used to describe the cpu 1168 topology of an ARM System. 1169 1170config SCHED_MC 1171 bool "Multi-core scheduler support" 1172 depends on ARM_CPU_TOPOLOGY 1173 help 1174 Multi-core scheduler support improves the CPU scheduler's decision 1175 making when dealing with multi-core CPU chips at a cost of slightly 1176 increased overhead in some places. If unsure say N here. 1177 1178config SCHED_SMT 1179 bool "SMT scheduler support" 1180 depends on ARM_CPU_TOPOLOGY 1181 help 1182 Improves the CPU scheduler's decision making when dealing with 1183 MultiThreading at a cost of slightly increased overhead in some 1184 places. If unsure say N here. 1185 1186config HAVE_ARM_SCU 1187 bool 1188 help 1189 This option enables support for the ARM snoop control unit 1190 1191config HAVE_ARM_ARCH_TIMER 1192 bool "Architected timer support" 1193 depends on CPU_V7 1194 select ARM_ARCH_TIMER 1195 help 1196 This option enables support for the ARM architected timer 1197 1198config HAVE_ARM_TWD 1199 bool 1200 help 1201 This options enables support for the ARM timer and watchdog unit 1202 1203config MCPM 1204 bool "Multi-Cluster Power Management" 1205 depends on CPU_V7 && SMP 1206 help 1207 This option provides the common power management infrastructure 1208 for (multi-)cluster based systems, such as big.LITTLE based 1209 systems. 1210 1211config MCPM_QUAD_CLUSTER 1212 bool 1213 depends on MCPM 1214 help 1215 To avoid wasting resources unnecessarily, MCPM only supports up 1216 to 2 clusters by default. 1217 Platforms with 3 or 4 clusters that use MCPM must select this 1218 option to allow the additional clusters to be managed. 1219 1220config BIG_LITTLE 1221 bool "big.LITTLE support (Experimental)" 1222 depends on CPU_V7 && SMP 1223 select MCPM 1224 help 1225 This option enables support selections for the big.LITTLE 1226 system architecture. 1227 1228config BL_SWITCHER 1229 bool "big.LITTLE switcher support" 1230 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1231 select CPU_PM 1232 help 1233 The big.LITTLE "switcher" provides the core functionality to 1234 transparently handle transition between a cluster of A15's 1235 and a cluster of A7's in a big.LITTLE system. 1236 1237config BL_SWITCHER_DUMMY_IF 1238 tristate "Simple big.LITTLE switcher user interface" 1239 depends on BL_SWITCHER && DEBUG_KERNEL 1240 help 1241 This is a simple and dummy char dev interface to control 1242 the big.LITTLE switcher core code. It is meant for 1243 debugging purposes only. 1244 1245choice 1246 prompt "Memory split" 1247 depends on MMU 1248 default VMSPLIT_3G 1249 help 1250 Select the desired split between kernel and user memory. 1251 1252 If you are not absolutely sure what you are doing, leave this 1253 option alone! 1254 1255 config VMSPLIT_3G 1256 bool "3G/1G user/kernel split" 1257 config VMSPLIT_3G_OPT 1258 depends on !ARM_LPAE 1259 bool "3G/1G user/kernel split (for full 1G low memory)" 1260 config VMSPLIT_2G 1261 bool "2G/2G user/kernel split" 1262 config VMSPLIT_1G 1263 bool "1G/3G user/kernel split" 1264endchoice 1265 1266config PAGE_OFFSET 1267 hex 1268 default PHYS_OFFSET if !MMU 1269 default 0x40000000 if VMSPLIT_1G 1270 default 0x80000000 if VMSPLIT_2G 1271 default 0xB0000000 if VMSPLIT_3G_OPT 1272 default 0xC0000000 1273 1274config KASAN_SHADOW_OFFSET 1275 hex 1276 depends on KASAN 1277 default 0x1f000000 if PAGE_OFFSET=0x40000000 1278 default 0x5f000000 if PAGE_OFFSET=0x80000000 1279 default 0x9f000000 if PAGE_OFFSET=0xC0000000 1280 default 0x8f000000 if PAGE_OFFSET=0xB0000000 1281 default 0xffffffff 1282 1283config NR_CPUS 1284 int "Maximum number of CPUs (2-32)" 1285 range 2 16 if DEBUG_KMAP_LOCAL 1286 range 2 32 if !DEBUG_KMAP_LOCAL 1287 depends on SMP 1288 default "4" 1289 help 1290 The maximum number of CPUs that the kernel can support. 1291 Up to 32 CPUs can be supported, or up to 16 if kmap_local() 1292 debugging is enabled, which uses half of the per-CPU fixmap 1293 slots as guard regions. 1294 1295config HOTPLUG_CPU 1296 bool "Support for hot-pluggable CPUs" 1297 depends on SMP 1298 select GENERIC_IRQ_MIGRATION 1299 help 1300 Say Y here to experiment with turning CPUs off and on. CPUs 1301 can be controlled through /sys/devices/system/cpu. 1302 1303config ARM_PSCI 1304 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1305 depends on HAVE_ARM_SMCCC 1306 select ARM_PSCI_FW 1307 help 1308 Say Y here if you want Linux to communicate with system firmware 1309 implementing the PSCI specification for CPU-centric power 1310 management operations described in ARM document number ARM DEN 1311 0022A ("Power State Coordination Interface System Software on 1312 ARM processors"). 1313 1314# The GPIO number here must be sorted by descending number. In case of 1315# a multiplatform kernel, we just want the highest value required by the 1316# selected platforms. 1317config ARCH_NR_GPIO 1318 int 1319 default 2048 if ARCH_INTEL_SOCFPGA 1320 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1321 ARCH_ZYNQ || ARCH_ASPEED 1322 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1323 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1324 default 416 if ARCH_SUNXI 1325 default 392 if ARCH_U8500 1326 default 352 if ARCH_VT8500 1327 default 288 if ARCH_ROCKCHIP 1328 default 264 if MACH_H4700 1329 default 0 1330 help 1331 Maximum number of GPIOs in the system. 1332 1333 If unsure, leave the default value. 1334 1335config HZ_FIXED 1336 int 1337 default 128 if SOC_AT91RM9200 1338 default 0 1339 1340choice 1341 depends on HZ_FIXED = 0 1342 prompt "Timer frequency" 1343 1344config HZ_100 1345 bool "100 Hz" 1346 1347config HZ_200 1348 bool "200 Hz" 1349 1350config HZ_250 1351 bool "250 Hz" 1352 1353config HZ_300 1354 bool "300 Hz" 1355 1356config HZ_500 1357 bool "500 Hz" 1358 1359config HZ_1000 1360 bool "1000 Hz" 1361 1362endchoice 1363 1364config HZ 1365 int 1366 default HZ_FIXED if HZ_FIXED != 0 1367 default 100 if HZ_100 1368 default 200 if HZ_200 1369 default 250 if HZ_250 1370 default 300 if HZ_300 1371 default 500 if HZ_500 1372 default 1000 1373 1374config SCHED_HRTICK 1375 def_bool HIGH_RES_TIMERS 1376 1377config THUMB2_KERNEL 1378 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1379 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1380 default y if CPU_THUMBONLY 1381 select ARM_UNWIND 1382 help 1383 By enabling this option, the kernel will be compiled in 1384 Thumb-2 mode. 1385 1386 If unsure, say N. 1387 1388config ARM_PATCH_IDIV 1389 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1390 depends on CPU_32v7 && !XIP_KERNEL 1391 default y 1392 help 1393 The ARM compiler inserts calls to __aeabi_idiv() and 1394 __aeabi_uidiv() when it needs to perform division on signed 1395 and unsigned integers. Some v7 CPUs have support for the sdiv 1396 and udiv instructions that can be used to implement those 1397 functions. 1398 1399 Enabling this option allows the kernel to modify itself to 1400 replace the first two instructions of these library functions 1401 with the sdiv or udiv plus "bx lr" instructions when the CPU 1402 it is running on supports them. Typically this will be faster 1403 and less power intensive than running the original library 1404 code to do integer division. 1405 1406config AEABI 1407 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1408 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1409 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1410 help 1411 This option allows for the kernel to be compiled using the latest 1412 ARM ABI (aka EABI). This is only useful if you are using a user 1413 space environment that is also compiled with EABI. 1414 1415 Since there are major incompatibilities between the legacy ABI and 1416 EABI, especially with regard to structure member alignment, this 1417 option also changes the kernel syscall calling convention to 1418 disambiguate both ABIs and allow for backward compatibility support 1419 (selected with CONFIG_OABI_COMPAT). 1420 1421 To use this you need GCC version 4.0.0 or later. 1422 1423config OABI_COMPAT 1424 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1425 depends on AEABI && !THUMB2_KERNEL 1426 help 1427 This option preserves the old syscall interface along with the 1428 new (ARM EABI) one. It also provides a compatibility layer to 1429 intercept syscalls that have structure arguments which layout 1430 in memory differs between the legacy ABI and the new ARM EABI 1431 (only for non "thumb" binaries). This option adds a tiny 1432 overhead to all syscalls and produces a slightly larger kernel. 1433 1434 The seccomp filter system will not be available when this is 1435 selected, since there is no way yet to sensibly distinguish 1436 between calling conventions during filtering. 1437 1438 If you know you'll be using only pure EABI user space then you 1439 can say N here. If this option is not selected and you attempt 1440 to execute a legacy ABI binary then the result will be 1441 UNPREDICTABLE (in fact it can be predicted that it won't work 1442 at all). If in doubt say N. 1443 1444config ARCH_SELECT_MEMORY_MODEL 1445 bool 1446 1447config ARCH_FLATMEM_ENABLE 1448 bool 1449 1450config ARCH_SPARSEMEM_ENABLE 1451 bool 1452 select SPARSEMEM_STATIC if SPARSEMEM 1453 1454config HIGHMEM 1455 bool "High Memory Support" 1456 depends on MMU 1457 select KMAP_LOCAL 1458 help 1459 The address space of ARM processors is only 4 Gigabytes large 1460 and it has to accommodate user address space, kernel address 1461 space as well as some memory mapped IO. That means that, if you 1462 have a large amount of physical memory and/or IO, not all of the 1463 memory can be "permanently mapped" by the kernel. The physical 1464 memory that is not permanently mapped is called "high memory". 1465 1466 Depending on the selected kernel/user memory split, minimum 1467 vmalloc space and actual amount of RAM, you may not need this 1468 option which should result in a slightly faster kernel. 1469 1470 If unsure, say n. 1471 1472config HIGHPTE 1473 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1474 depends on HIGHMEM 1475 default y 1476 help 1477 The VM uses one page of physical memory for each page table. 1478 For systems with a lot of processes, this can use a lot of 1479 precious low memory, eventually leading to low memory being 1480 consumed by page tables. Setting this option will allow 1481 user-space 2nd level page tables to reside in high memory. 1482 1483config CPU_SW_DOMAIN_PAN 1484 bool "Enable use of CPU domains to implement privileged no-access" 1485 depends on MMU && !ARM_LPAE 1486 default y 1487 help 1488 Increase kernel security by ensuring that normal kernel accesses 1489 are unable to access userspace addresses. This can help prevent 1490 use-after-free bugs becoming an exploitable privilege escalation 1491 by ensuring that magic values (such as LIST_POISON) will always 1492 fault when dereferenced. 1493 1494 CPUs with low-vector mappings use a best-efforts implementation. 1495 Their lower 1MB needs to remain accessible for the vectors, but 1496 the remainder of userspace will become appropriately inaccessible. 1497 1498config HW_PERF_EVENTS 1499 def_bool y 1500 depends on ARM_PMU 1501 1502config ARCH_WANT_GENERAL_HUGETLB 1503 def_bool y 1504 1505config ARM_MODULE_PLTS 1506 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1507 depends on MODULES 1508 default y 1509 help 1510 Allocate PLTs when loading modules so that jumps and calls whose 1511 targets are too far away for their relative offsets to be encoded 1512 in the instructions themselves can be bounced via veneers in the 1513 module's PLT. This allows modules to be allocated in the generic 1514 vmalloc area after the dedicated module memory area has been 1515 exhausted. The modules will use slightly more memory, but after 1516 rounding up to page size, the actual memory footprint is usually 1517 the same. 1518 1519 Disabling this is usually safe for small single-platform 1520 configurations. If unsure, say y. 1521 1522config FORCE_MAX_ZONEORDER 1523 int "Maximum zone order" 1524 default "12" if SOC_AM33XX 1525 default "9" if SA1111 1526 default "11" 1527 help 1528 The kernel memory allocator divides physically contiguous memory 1529 blocks into "zones", where each zone is a power of two number of 1530 pages. This option selects the largest power of two that the kernel 1531 keeps in the memory allocator. If you need to allocate very large 1532 blocks of physically contiguous memory, then you may need to 1533 increase this value. 1534 1535 This config option is actually maximum order plus one. For example, 1536 a value of 11 means that the largest free memory block is 2^10 pages. 1537 1538config ALIGNMENT_TRAP 1539 def_bool CPU_CP15_MMU 1540 select HAVE_PROC_CPU if PROC_FS 1541 help 1542 ARM processors cannot fetch/store information which is not 1543 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1544 address divisible by 4. On 32-bit ARM processors, these non-aligned 1545 fetch/store instructions will be emulated in software if you say 1546 here, which has a severe performance impact. This is necessary for 1547 correct operation of some network protocols. With an IP-only 1548 configuration it is safe to say N, otherwise say Y. 1549 1550config UACCESS_WITH_MEMCPY 1551 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1552 depends on MMU 1553 default y if CPU_FEROCEON 1554 help 1555 Implement faster copy_to_user and clear_user methods for CPU 1556 cores where a 8-word STM instruction give significantly higher 1557 memory write throughput than a sequence of individual 32bit stores. 1558 1559 A possible side effect is a slight increase in scheduling latency 1560 between threads sharing the same address space if they invoke 1561 such copy operations with large buffers. 1562 1563 However, if the CPU data cache is using a write-allocate mode, 1564 this option is unlikely to provide any performance gain. 1565 1566config PARAVIRT 1567 bool "Enable paravirtualization code" 1568 help 1569 This changes the kernel so it can modify itself when it is run 1570 under a hypervisor, potentially improving performance significantly 1571 over full virtualization. 1572 1573config PARAVIRT_TIME_ACCOUNTING 1574 bool "Paravirtual steal time accounting" 1575 select PARAVIRT 1576 help 1577 Select this option to enable fine granularity task steal time 1578 accounting. Time spent executing other tasks in parallel with 1579 the current vCPU is discounted from the vCPU power. To account for 1580 that, there can be a small performance impact. 1581 1582 If in doubt, say N here. 1583 1584config XEN_DOM0 1585 def_bool y 1586 depends on XEN 1587 1588config XEN 1589 bool "Xen guest support on ARM" 1590 depends on ARM && AEABI && OF 1591 depends on CPU_V7 && !CPU_V6 1592 depends on !GENERIC_ATOMIC64 1593 depends on MMU 1594 select ARCH_DMA_ADDR_T_64BIT 1595 select ARM_PSCI 1596 select SWIOTLB 1597 select SWIOTLB_XEN 1598 select PARAVIRT 1599 help 1600 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1601 1602config STACKPROTECTOR_PER_TASK 1603 bool "Use a unique stack canary value for each task" 1604 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1605 select GCC_PLUGIN_ARM_SSP_PER_TASK 1606 default y 1607 help 1608 Due to the fact that GCC uses an ordinary symbol reference from 1609 which to load the value of the stack canary, this value can only 1610 change at reboot time on SMP systems, and all tasks running in the 1611 kernel's address space are forced to use the same canary value for 1612 the entire duration that the system is up. 1613 1614 Enable this option to switch to a different method that uses a 1615 different canary value for each task. 1616 1617endmenu 1618 1619menu "Boot options" 1620 1621config USE_OF 1622 bool "Flattened Device Tree support" 1623 select IRQ_DOMAIN 1624 select OF 1625 help 1626 Include support for flattened device tree machine descriptions. 1627 1628config ATAGS 1629 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1630 default y 1631 help 1632 This is the traditional way of passing data to the kernel at boot 1633 time. If you are solely relying on the flattened device tree (or 1634 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1635 to remove ATAGS support from your kernel binary. If unsure, 1636 leave this to y. 1637 1638config DEPRECATED_PARAM_STRUCT 1639 bool "Provide old way to pass kernel parameters" 1640 depends on ATAGS 1641 help 1642 This was deprecated in 2001 and announced to live on for 5 years. 1643 Some old boot loaders still use this way. 1644 1645# Compressed boot loader in ROM. Yes, we really want to ask about 1646# TEXT and BSS so we preserve their values in the config files. 1647config ZBOOT_ROM_TEXT 1648 hex "Compressed ROM boot loader base address" 1649 default 0x0 1650 help 1651 The physical address at which the ROM-able zImage is to be 1652 placed in the target. Platforms which normally make use of 1653 ROM-able zImage formats normally set this to a suitable 1654 value in their defconfig file. 1655 1656 If ZBOOT_ROM is not enabled, this has no effect. 1657 1658config ZBOOT_ROM_BSS 1659 hex "Compressed ROM boot loader BSS address" 1660 default 0x0 1661 help 1662 The base address of an area of read/write memory in the target 1663 for the ROM-able zImage which must be available while the 1664 decompressor is running. It must be large enough to hold the 1665 entire decompressed kernel plus an additional 128 KiB. 1666 Platforms which normally make use of ROM-able zImage formats 1667 normally set this to a suitable value in their defconfig file. 1668 1669 If ZBOOT_ROM is not enabled, this has no effect. 1670 1671config ZBOOT_ROM 1672 bool "Compressed boot loader in ROM/flash" 1673 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1674 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1675 help 1676 Say Y here if you intend to execute your compressed kernel image 1677 (zImage) directly from ROM or flash. If unsure, say N. 1678 1679config ARM_APPENDED_DTB 1680 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1681 depends on OF 1682 help 1683 With this option, the boot code will look for a device tree binary 1684 (DTB) appended to zImage 1685 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1686 1687 This is meant as a backward compatibility convenience for those 1688 systems with a bootloader that can't be upgraded to accommodate 1689 the documented boot protocol using a device tree. 1690 1691 Beware that there is very little in terms of protection against 1692 this option being confused by leftover garbage in memory that might 1693 look like a DTB header after a reboot if no actual DTB is appended 1694 to zImage. Do not leave this option active in a production kernel 1695 if you don't intend to always append a DTB. Proper passing of the 1696 location into r2 of a bootloader provided DTB is always preferable 1697 to this option. 1698 1699config ARM_ATAG_DTB_COMPAT 1700 bool "Supplement the appended DTB with traditional ATAG information" 1701 depends on ARM_APPENDED_DTB 1702 help 1703 Some old bootloaders can't be updated to a DTB capable one, yet 1704 they provide ATAGs with memory configuration, the ramdisk address, 1705 the kernel cmdline string, etc. Such information is dynamically 1706 provided by the bootloader and can't always be stored in a static 1707 DTB. To allow a device tree enabled kernel to be used with such 1708 bootloaders, this option allows zImage to extract the information 1709 from the ATAG list and store it at run time into the appended DTB. 1710 1711choice 1712 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1713 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1714 1715config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1716 bool "Use bootloader kernel arguments if available" 1717 help 1718 Uses the command-line options passed by the boot loader instead of 1719 the device tree bootargs property. If the boot loader doesn't provide 1720 any, the device tree bootargs property will be used. 1721 1722config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1723 bool "Extend with bootloader kernel arguments" 1724 help 1725 The command-line arguments provided by the boot loader will be 1726 appended to the the device tree bootargs property. 1727 1728endchoice 1729 1730config CMDLINE 1731 string "Default kernel command string" 1732 default "" 1733 help 1734 On some architectures (e.g. CATS), there is currently no way 1735 for the boot loader to pass arguments to the kernel. For these 1736 architectures, you should supply some command-line options at build 1737 time by entering them here. As a minimum, you should specify the 1738 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1739 1740choice 1741 prompt "Kernel command line type" if CMDLINE != "" 1742 default CMDLINE_FROM_BOOTLOADER 1743 depends on ATAGS 1744 1745config CMDLINE_FROM_BOOTLOADER 1746 bool "Use bootloader kernel arguments if available" 1747 help 1748 Uses the command-line options passed by the boot loader. If 1749 the boot loader doesn't provide any, the default kernel command 1750 string provided in CMDLINE will be used. 1751 1752config CMDLINE_EXTEND 1753 bool "Extend bootloader kernel arguments" 1754 help 1755 The command-line arguments provided by the boot loader will be 1756 appended to the default kernel command string. 1757 1758config CMDLINE_FORCE 1759 bool "Always use the default kernel command string" 1760 help 1761 Always use the default kernel command string, even if the boot 1762 loader passes other arguments to the kernel. 1763 This is useful if you cannot or don't want to change the 1764 command-line options your boot loader passes to the kernel. 1765endchoice 1766 1767config XIP_KERNEL 1768 bool "Kernel Execute-In-Place from ROM" 1769 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1770 help 1771 Execute-In-Place allows the kernel to run from non-volatile storage 1772 directly addressable by the CPU, such as NOR flash. This saves RAM 1773 space since the text section of the kernel is not loaded from flash 1774 to RAM. Read-write sections, such as the data section and stack, 1775 are still copied to RAM. The XIP kernel is not compressed since 1776 it has to run directly from flash, so it will take more space to 1777 store it. The flash address used to link the kernel object files, 1778 and for storing it, is configuration dependent. Therefore, if you 1779 say Y here, you must know the proper physical address where to 1780 store the kernel image depending on your own flash memory usage. 1781 1782 Also note that the make target becomes "make xipImage" rather than 1783 "make zImage" or "make Image". The final kernel binary to put in 1784 ROM memory will be arch/arm/boot/xipImage. 1785 1786 If unsure, say N. 1787 1788config XIP_PHYS_ADDR 1789 hex "XIP Kernel Physical Location" 1790 depends on XIP_KERNEL 1791 default "0x00080000" 1792 help 1793 This is the physical address in your flash memory the kernel will 1794 be linked for and stored to. This address is dependent on your 1795 own flash usage. 1796 1797config XIP_DEFLATED_DATA 1798 bool "Store kernel .data section compressed in ROM" 1799 depends on XIP_KERNEL 1800 select ZLIB_INFLATE 1801 help 1802 Before the kernel is actually executed, its .data section has to be 1803 copied to RAM from ROM. This option allows for storing that data 1804 in compressed form and decompressed to RAM rather than merely being 1805 copied, saving some precious ROM space. A possible drawback is a 1806 slightly longer boot delay. 1807 1808config KEXEC 1809 bool "Kexec system call (EXPERIMENTAL)" 1810 depends on (!SMP || PM_SLEEP_SMP) 1811 depends on MMU 1812 select KEXEC_CORE 1813 help 1814 kexec is a system call that implements the ability to shutdown your 1815 current kernel, and to start another kernel. It is like a reboot 1816 but it is independent of the system firmware. And like a reboot 1817 you can start any kernel with it, not just Linux. 1818 1819 It is an ongoing process to be certain the hardware in a machine 1820 is properly shutdown, so do not be surprised if this code does not 1821 initially work for you. 1822 1823config ATAGS_PROC 1824 bool "Export atags in procfs" 1825 depends on ATAGS && KEXEC 1826 default y 1827 help 1828 Should the atags used to boot the kernel be exported in an "atags" 1829 file in procfs. Useful with kexec. 1830 1831config CRASH_DUMP 1832 bool "Build kdump crash kernel (EXPERIMENTAL)" 1833 help 1834 Generate crash dump after being started by kexec. This should 1835 be normally only set in special crash dump kernels which are 1836 loaded in the main kernel with kexec-tools into a specially 1837 reserved region and then later executed after a crash by 1838 kdump/kexec. The crash dump kernel must be compiled to a 1839 memory address not used by the main kernel 1840 1841 For more details see Documentation/admin-guide/kdump/kdump.rst 1842 1843config AUTO_ZRELADDR 1844 bool "Auto calculation of the decompressed kernel image address" 1845 help 1846 ZRELADDR is the physical address where the decompressed kernel 1847 image will be placed. If AUTO_ZRELADDR is selected, the address 1848 will be determined at run-time, either by masking the current IP 1849 with 0xf8000000, or, if invalid, from the DTB passed in r2. 1850 This assumes the zImage being placed in the first 128MB from 1851 start of memory. 1852 1853config EFI_STUB 1854 bool 1855 1856config EFI 1857 bool "UEFI runtime support" 1858 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1859 select UCS2_STRING 1860 select EFI_PARAMS_FROM_FDT 1861 select EFI_STUB 1862 select EFI_GENERIC_STUB 1863 select EFI_RUNTIME_WRAPPERS 1864 help 1865 This option provides support for runtime services provided 1866 by UEFI firmware (such as non-volatile variables, realtime 1867 clock, and platform reset). A UEFI stub is also provided to 1868 allow the kernel to be booted as an EFI application. This 1869 is only useful for kernels that may run on systems that have 1870 UEFI firmware. 1871 1872config DMI 1873 bool "Enable support for SMBIOS (DMI) tables" 1874 depends on EFI 1875 default y 1876 help 1877 This enables SMBIOS/DMI feature for systems. 1878 1879 This option is only useful on systems that have UEFI firmware. 1880 However, even with this option, the resultant kernel should 1881 continue to boot on existing non-UEFI platforms. 1882 1883 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1884 i.e., the the practice of identifying the platform via DMI to 1885 decide whether certain workarounds for buggy hardware and/or 1886 firmware need to be enabled. This would require the DMI subsystem 1887 to be enabled much earlier than we do on ARM, which is non-trivial. 1888 1889endmenu 1890 1891menu "CPU Power Management" 1892 1893source "drivers/cpufreq/Kconfig" 1894 1895source "drivers/cpuidle/Kconfig" 1896 1897endmenu 1898 1899menu "Floating point emulation" 1900 1901comment "At least one emulation must be selected" 1902 1903config FPE_NWFPE 1904 bool "NWFPE math emulation" 1905 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1906 help 1907 Say Y to include the NWFPE floating point emulator in the kernel. 1908 This is necessary to run most binaries. Linux does not currently 1909 support floating point hardware so you need to say Y here even if 1910 your machine has an FPA or floating point co-processor podule. 1911 1912 You may say N here if you are going to load the Acorn FPEmulator 1913 early in the bootup. 1914 1915config FPE_NWFPE_XP 1916 bool "Support extended precision" 1917 depends on FPE_NWFPE 1918 help 1919 Say Y to include 80-bit support in the kernel floating-point 1920 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1921 Note that gcc does not generate 80-bit operations by default, 1922 so in most cases this option only enlarges the size of the 1923 floating point emulator without any good reason. 1924 1925 You almost surely want to say N here. 1926 1927config FPE_FASTFPE 1928 bool "FastFPE math emulation (EXPERIMENTAL)" 1929 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1930 help 1931 Say Y here to include the FAST floating point emulator in the kernel. 1932 This is an experimental much faster emulator which now also has full 1933 precision for the mantissa. It does not support any exceptions. 1934 It is very simple, and approximately 3-6 times faster than NWFPE. 1935 1936 It should be sufficient for most programs. It may be not suitable 1937 for scientific calculations, but you have to check this for yourself. 1938 If you do not feel you need a faster FP emulation you should better 1939 choose NWFPE. 1940 1941config VFP 1942 bool "VFP-format floating point maths" 1943 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1944 help 1945 Say Y to include VFP support code in the kernel. This is needed 1946 if your hardware includes a VFP unit. 1947 1948 Please see <file:Documentation/arm/vfp/release-notes.rst> for 1949 release notes and additional status information. 1950 1951 Say N if your target does not have VFP hardware. 1952 1953config VFPv3 1954 bool 1955 depends on VFP 1956 default y if CPU_V7 1957 1958config NEON 1959 bool "Advanced SIMD (NEON) Extension support" 1960 depends on VFPv3 && CPU_V7 1961 help 1962 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 1963 Extension. 1964 1965config KERNEL_MODE_NEON 1966 bool "Support for NEON in kernel mode" 1967 depends on NEON && AEABI 1968 help 1969 Say Y to include support for NEON in kernel mode. 1970 1971endmenu 1972 1973menu "Power management options" 1974 1975source "kernel/power/Kconfig" 1976 1977config ARCH_SUSPEND_POSSIBLE 1978 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 1979 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 1980 def_bool y 1981 1982config ARM_CPU_SUSPEND 1983 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 1984 depends on ARCH_SUSPEND_POSSIBLE 1985 1986config ARCH_HIBERNATION_POSSIBLE 1987 bool 1988 depends on MMU 1989 default y if ARCH_SUSPEND_POSSIBLE 1990 1991endmenu 1992 1993if CRYPTO 1994source "arch/arm/crypto/Kconfig" 1995endif 1996 1997source "arch/arm/Kconfig.assembler" 1998
