1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_CLOCKSOURCE_DATA 6 select ARCH_DISCARD_MEMBLOCK if !HAVE_ARCH_PFN_VALID && !KEXEC 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_ELF_RANDOMIZE 10 select ARCH_HAS_FORTIFY_SOURCE 11 select ARCH_HAS_KCOV 12 select ARCH_HAS_MEMBARRIER_SYNC_CORE 13 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 14 select ARCH_HAS_PHYS_TO_DMA 15 select ARCH_HAS_SET_MEMORY 16 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 17 select ARCH_HAS_STRICT_MODULE_RWX if MMU 18 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 19 select ARCH_HAVE_CUSTOM_GPIO_H 20 select ARCH_HAS_GCOV_PROFILE_ALL 21 select ARCH_MIGHT_HAVE_PC_PARPORT 22 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 23 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 24 select ARCH_SUPPORTS_ATOMIC_RMW 25 select ARCH_USE_BUILTIN_BSWAP 26 select ARCH_USE_CMPXCHG_LOCKREF 27 select ARCH_WANT_IPC_PARSE_VERSION 28 select BUILDTIME_EXTABLE_SORT if MMU 29 select CLONE_BACKWARDS 30 select CPU_PM if (SUSPEND || CPU_IDLE) 31 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 32 select DMA_DIRECT_OPS if !MMU 33 select EDAC_SUPPORT 34 select EDAC_ATOMIC_SCRUB 35 select GENERIC_ALLOCATOR 36 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 37 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI) 38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 39 select GENERIC_CPU_AUTOPROBE 40 select GENERIC_EARLY_IOREMAP 41 select GENERIC_IDLE_POLL_SETUP 42 select GENERIC_IRQ_PROBE 43 select GENERIC_IRQ_SHOW 44 select GENERIC_IRQ_SHOW_LEVEL 45 select GENERIC_PCI_IOMAP 46 select GENERIC_SCHED_CLOCK 47 select GENERIC_SMP_IDLE_THREAD 48 select GENERIC_STRNCPY_FROM_USER 49 select GENERIC_STRNLEN_USER 50 select HANDLE_DOMAIN_IRQ 51 select HARDIRQS_SW_RESEND 52 select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) 53 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 54 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 55 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 56 select HAVE_ARCH_MMAP_RND_BITS if MMU 57 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) 58 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 59 select HAVE_ARCH_TRACEHOOK 60 select HAVE_ARM_SMCCC if CPU_V7 61 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 62 select HAVE_CONTEXT_TRACKING 63 select HAVE_C_RECORDMCOUNT 64 select HAVE_DEBUG_KMEMLEAK 65 select HAVE_DMA_CONTIGUOUS if MMU 66 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU 67 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 68 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 69 select HAVE_EXIT_THREAD 70 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) 71 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) 72 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) 73 select HAVE_GCC_PLUGINS 74 select HAVE_GENERIC_DMA_COHERENT 75 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)) 76 select HAVE_IDE if PCI || ISA || PCMCIA 77 select HAVE_IRQ_TIME_ACCOUNTING 78 select HAVE_KERNEL_GZIP 79 select HAVE_KERNEL_LZ4 80 select HAVE_KERNEL_LZMA 81 select HAVE_KERNEL_LZO 82 select HAVE_KERNEL_XZ 83 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 84 select HAVE_KRETPROBES if (HAVE_KPROBES) 85 select HAVE_MEMBLOCK 86 select HAVE_MOD_ARCH_SPECIFIC 87 select HAVE_NMI 88 select HAVE_OPROFILE if (HAVE_PERF_EVENTS) 89 select HAVE_OPTPROBES if !THUMB2_KERNEL 90 select HAVE_PERF_EVENTS 91 select HAVE_PERF_REGS 92 select HAVE_PERF_USER_STACK_DUMP 93 select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE) 94 select HAVE_REGS_AND_STACK_ACCESS_API 95 select HAVE_RSEQ 96 select HAVE_STACKPROTECTOR 97 select HAVE_SYSCALL_TRACEPOINTS 98 select HAVE_UID16 99 select HAVE_VIRT_CPU_ACCOUNTING_GEN 100 select IRQ_FORCED_THREADING 101 select MODULES_USE_ELF_REL 102 select NEED_DMA_MAP_STATE 103 select NO_BOOTMEM 104 select OF_EARLY_FLATTREE if OF 105 select OF_RESERVED_MEM if OF 106 select OLD_SIGACTION 107 select OLD_SIGSUSPEND3 108 select PERF_USE_VMALLOC 109 select REFCOUNT_FULL 110 select RTC_LIB 111 select SYS_SUPPORTS_APM_EMULATION 112 # Above selects are sorted alphabetically; please add new ones 113 # according to that. Thanks. 114 help 115 The ARM series is a line of low-power-consumption RISC chip designs 116 licensed by ARM Ltd and targeted at embedded applications and 117 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 118 manufactured, but legacy ARM-based PC hardware remains popular in 119 Europe. There is an ARM Linux project with a web page at 120 <http://www.arm.linux.org.uk/>. 121 122config ARM_HAS_SG_CHAIN 123 select ARCH_HAS_SG_CHAIN 124 bool 125 126config ARM_DMA_USE_IOMMU 127 bool 128 select ARM_HAS_SG_CHAIN 129 select NEED_SG_DMA_LENGTH 130 131if ARM_DMA_USE_IOMMU 132 133config ARM_DMA_IOMMU_ALIGNMENT 134 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 135 range 4 9 136 default 8 137 help 138 DMA mapping framework by default aligns all buffers to the smallest 139 PAGE_SIZE order which is greater than or equal to the requested buffer 140 size. This works well for buffers up to a few hundreds kilobytes, but 141 for larger buffers it just a waste of address space. Drivers which has 142 relatively small addressing window (like 64Mib) might run out of 143 virtual space with just a few allocations. 144 145 With this parameter you can specify the maximum PAGE_SIZE order for 146 DMA IOMMU buffers. Larger buffers will be aligned only to this 147 specified order. The order is expressed as a power of two multiplied 148 by the PAGE_SIZE. 149 150endif 151 152config MIGHT_HAVE_PCI 153 bool 154 155config SYS_SUPPORTS_APM_EMULATION 156 bool 157 158config HAVE_TCM 159 bool 160 select GENERIC_ALLOCATOR 161 162config HAVE_PROC_CPU 163 bool 164 165config NO_IOPORT_MAP 166 bool 167 168config EISA 169 bool 170 ---help--- 171 The Extended Industry Standard Architecture (EISA) bus was 172 developed as an open alternative to the IBM MicroChannel bus. 173 174 The EISA bus provided some of the features of the IBM MicroChannel 175 bus while maintaining backward compatibility with cards made for 176 the older ISA bus. The EISA bus saw limited use between 1988 and 177 1995 when it was made obsolete by the PCI bus. 178 179 Say Y here if you are building a kernel for an EISA-based machine. 180 181 Otherwise, say N. 182 183config SBUS 184 bool 185 186config STACKTRACE_SUPPORT 187 bool 188 default y 189 190config LOCKDEP_SUPPORT 191 bool 192 default y 193 194config TRACE_IRQFLAGS_SUPPORT 195 bool 196 default !CPU_V7M 197 198config RWSEM_XCHGADD_ALGORITHM 199 bool 200 default y 201 202config ARCH_HAS_ILOG2_U32 203 bool 204 205config ARCH_HAS_ILOG2_U64 206 bool 207 208config ARCH_HAS_BANDGAP 209 bool 210 211config FIX_EARLYCON_MEM 212 def_bool y if MMU 213 214config GENERIC_HWEIGHT 215 bool 216 default y 217 218config GENERIC_CALIBRATE_DELAY 219 bool 220 default y 221 222config ARCH_MAY_HAVE_PC_FDC 223 bool 224 225config ZONE_DMA 226 bool 227 228config ARCH_SUPPORTS_UPROBES 229 def_bool y 230 231config ARCH_HAS_DMA_SET_COHERENT_MASK 232 bool 233 234config GENERIC_ISA_DMA 235 bool 236 237config FIQ 238 bool 239 240config NEED_RET_TO_USER 241 bool 242 243config ARCH_MTD_XIP 244 bool 245 246config ARM_PATCH_PHYS_VIRT 247 bool "Patch physical to virtual translations at runtime" if EMBEDDED 248 default y 249 depends on !XIP_KERNEL && MMU 250 help 251 Patch phys-to-virt and virt-to-phys translation functions at 252 boot and module load time according to the position of the 253 kernel in system memory. 254 255 This can only be used with non-XIP MMU kernels where the base 256 of physical memory is at a 16MB boundary. 257 258 Only disable this option if you know that you do not require 259 this feature (eg, building a kernel for a single machine) and 260 you need to shrink the kernel to the minimal size. 261 262config NEED_MACH_IO_H 263 bool 264 help 265 Select this when mach/io.h is required to provide special 266 definitions for this platform. The need for mach/io.h should 267 be avoided when possible. 268 269config NEED_MACH_MEMORY_H 270 bool 271 help 272 Select this when mach/memory.h is required to provide special 273 definitions for this platform. The need for mach/memory.h should 274 be avoided when possible. 275 276config PHYS_OFFSET 277 hex "Physical address of main memory" if MMU 278 depends on !ARM_PATCH_PHYS_VIRT 279 default DRAM_BASE if !MMU 280 default 0x00000000 if ARCH_EBSA110 || \ 281 ARCH_FOOTBRIDGE || \ 282 ARCH_INTEGRATOR || \ 283 ARCH_IOP13XX || \ 284 ARCH_KS8695 || \ 285 ARCH_REALVIEW 286 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 287 default 0x20000000 if ARCH_S5PV210 288 default 0xc0000000 if ARCH_SA1100 289 help 290 Please provide the physical address corresponding to the 291 location of main memory in your system. 292 293config GENERIC_BUG 294 def_bool y 295 depends on BUG 296 297config PGTABLE_LEVELS 298 int 299 default 3 if ARM_LPAE 300 default 2 301 302menu "System Type" 303 304config MMU 305 bool "MMU-based Paged Memory Management Support" 306 default y 307 help 308 Select if you want MMU-based virtualised addressing space 309 support by paged memory management. If unsure, say 'Y'. 310 311config ARCH_MMAP_RND_BITS_MIN 312 default 8 313 314config ARCH_MMAP_RND_BITS_MAX 315 default 14 if PAGE_OFFSET=0x40000000 316 default 15 if PAGE_OFFSET=0x80000000 317 default 16 318 319# 320# The "ARM system type" choice list is ordered alphabetically by option 321# text. Please add new entries in the option alphabetic order. 322# 323choice 324 prompt "ARM system type" 325 default ARM_SINGLE_ARMV7M if !MMU 326 default ARCH_MULTIPLATFORM if MMU 327 328config ARCH_MULTIPLATFORM 329 bool "Allow multiple platforms to be selected" 330 depends on MMU 331 select ARM_HAS_SG_CHAIN 332 select ARM_PATCH_PHYS_VIRT 333 select AUTO_ZRELADDR 334 select TIMER_OF 335 select COMMON_CLK 336 select GENERIC_CLOCKEVENTS 337 select GENERIC_IRQ_MULTI_HANDLER 338 select MIGHT_HAVE_PCI 339 select PCI_DOMAINS if PCI 340 select SPARSE_IRQ 341 select USE_OF 342 343config ARM_SINGLE_ARMV7M 344 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 345 depends on !MMU 346 select ARM_NVIC 347 select AUTO_ZRELADDR 348 select TIMER_OF 349 select COMMON_CLK 350 select CPU_V7M 351 select GENERIC_CLOCKEVENTS 352 select NO_IOPORT_MAP 353 select SPARSE_IRQ 354 select USE_OF 355 356config ARCH_EBSA110 357 bool "EBSA-110" 358 select ARCH_USES_GETTIMEOFFSET 359 select CPU_SA110 360 select ISA 361 select NEED_MACH_IO_H 362 select NEED_MACH_MEMORY_H 363 select NO_IOPORT_MAP 364 help 365 This is an evaluation board for the StrongARM processor available 366 from Digital. It has limited hardware on-board, including an 367 Ethernet interface, two PCMCIA sockets, two serial ports and a 368 parallel port. 369 370config ARCH_EP93XX 371 bool "EP93xx-based" 372 select ARCH_SPARSEMEM_ENABLE 373 select ARM_AMBA 374 imply ARM_PATCH_PHYS_VIRT 375 select ARM_VIC 376 select AUTO_ZRELADDR 377 select CLKDEV_LOOKUP 378 select CLKSRC_MMIO 379 select CPU_ARM920T 380 select GENERIC_CLOCKEVENTS 381 select GPIOLIB 382 help 383 This enables support for the Cirrus EP93xx series of CPUs. 384 385config ARCH_FOOTBRIDGE 386 bool "FootBridge" 387 select CPU_SA110 388 select FOOTBRIDGE 389 select GENERIC_CLOCKEVENTS 390 select HAVE_IDE 391 select NEED_MACH_IO_H if !MMU 392 select NEED_MACH_MEMORY_H 393 help 394 Support for systems based on the DC21285 companion chip 395 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 396 397config ARCH_NETX 398 bool "Hilscher NetX based" 399 select ARM_VIC 400 select CLKSRC_MMIO 401 select CPU_ARM926T 402 select GENERIC_CLOCKEVENTS 403 help 404 This enables support for systems based on the Hilscher NetX Soc 405 406config ARCH_IOP13XX 407 bool "IOP13xx-based" 408 depends on MMU 409 select CPU_XSC3 410 select NEED_MACH_MEMORY_H 411 select NEED_RET_TO_USER 412 select PCI 413 select PLAT_IOP 414 select VMSPLIT_1G 415 select SPARSE_IRQ 416 help 417 Support for Intel's IOP13XX (XScale) family of processors. 418 419config ARCH_IOP32X 420 bool "IOP32x-based" 421 depends on MMU 422 select CPU_XSCALE 423 select GPIO_IOP 424 select GPIOLIB 425 select NEED_RET_TO_USER 426 select PCI 427 select PLAT_IOP 428 help 429 Support for Intel's 80219 and IOP32X (XScale) family of 430 processors. 431 432config ARCH_IOP33X 433 bool "IOP33x-based" 434 depends on MMU 435 select CPU_XSCALE 436 select GPIO_IOP 437 select GPIOLIB 438 select NEED_RET_TO_USER 439 select PCI 440 select PLAT_IOP 441 help 442 Support for Intel's IOP33X (XScale) family of processors. 443 444config ARCH_IXP4XX 445 bool "IXP4xx-based" 446 depends on MMU 447 select ARCH_HAS_DMA_SET_COHERENT_MASK 448 select ARCH_SUPPORTS_BIG_ENDIAN 449 select CLKSRC_MMIO 450 select CPU_XSCALE 451 select DMABOUNCE if PCI 452 select GENERIC_CLOCKEVENTS 453 select GPIOLIB 454 select MIGHT_HAVE_PCI 455 select NEED_MACH_IO_H 456 select USB_EHCI_BIG_ENDIAN_DESC 457 select USB_EHCI_BIG_ENDIAN_MMIO 458 help 459 Support for Intel's IXP4XX (XScale) family of processors. 460 461config ARCH_DOVE 462 bool "Marvell Dove" 463 select CPU_PJ4 464 select GENERIC_CLOCKEVENTS 465 select GENERIC_IRQ_MULTI_HANDLER 466 select GPIOLIB 467 select MIGHT_HAVE_PCI 468 select MVEBU_MBUS 469 select PINCTRL 470 select PINCTRL_DOVE 471 select PLAT_ORION_LEGACY 472 select SPARSE_IRQ 473 select PM_GENERIC_DOMAINS if PM 474 help 475 Support for the Marvell Dove SoC 88AP510 476 477config ARCH_KS8695 478 bool "Micrel/Kendin KS8695" 479 select CLKSRC_MMIO 480 select CPU_ARM922T 481 select GENERIC_CLOCKEVENTS 482 select GPIOLIB 483 select NEED_MACH_MEMORY_H 484 help 485 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 486 System-on-Chip devices. 487 488config ARCH_W90X900 489 bool "Nuvoton W90X900 CPU" 490 select CLKDEV_LOOKUP 491 select CLKSRC_MMIO 492 select CPU_ARM926T 493 select GENERIC_CLOCKEVENTS 494 select GPIOLIB 495 help 496 Support for Nuvoton (Winbond logic dept.) ARM9 processor, 497 At present, the w90x900 has been renamed nuc900, regarding 498 the ARM series product line, you can login the following 499 link address to know more. 500 501 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/ 502 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller> 503 504config ARCH_LPC32XX 505 bool "NXP LPC32XX" 506 select ARM_AMBA 507 select CLKDEV_LOOKUP 508 select CLKSRC_LPC32XX 509 select COMMON_CLK 510 select CPU_ARM926T 511 select GENERIC_CLOCKEVENTS 512 select GENERIC_IRQ_MULTI_HANDLER 513 select GPIOLIB 514 select SPARSE_IRQ 515 select USE_OF 516 help 517 Support for the NXP LPC32XX family of processors 518 519config ARCH_PXA 520 bool "PXA2xx/PXA3xx-based" 521 depends on MMU 522 select ARCH_MTD_XIP 523 select ARM_CPU_SUSPEND if PM 524 select AUTO_ZRELADDR 525 select COMMON_CLK 526 select CLKDEV_LOOKUP 527 select CLKSRC_PXA 528 select CLKSRC_MMIO 529 select TIMER_OF 530 select CPU_XSCALE if !CPU_XSC3 531 select GENERIC_CLOCKEVENTS 532 select GENERIC_IRQ_MULTI_HANDLER 533 select GPIO_PXA 534 select GPIOLIB 535 select HAVE_IDE 536 select IRQ_DOMAIN 537 select PLAT_PXA 538 select SPARSE_IRQ 539 help 540 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 541 542config ARCH_RPC 543 bool "RiscPC" 544 depends on MMU 545 select ARCH_ACORN 546 select ARCH_MAY_HAVE_PC_FDC 547 select ARCH_SPARSEMEM_ENABLE 548 select ARCH_USES_GETTIMEOFFSET 549 select CPU_SA110 550 select FIQ 551 select HAVE_IDE 552 select HAVE_PATA_PLATFORM 553 select ISA_DMA_API 554 select NEED_MACH_IO_H 555 select NEED_MACH_MEMORY_H 556 select NO_IOPORT_MAP 557 help 558 On the Acorn Risc-PC, Linux can support the internal IDE disk and 559 CD-ROM interface, serial and parallel port, and the floppy drive. 560 561config ARCH_SA1100 562 bool "SA1100-based" 563 select ARCH_MTD_XIP 564 select ARCH_SPARSEMEM_ENABLE 565 select CLKDEV_LOOKUP 566 select CLKSRC_MMIO 567 select CLKSRC_PXA 568 select TIMER_OF if OF 569 select CPU_FREQ 570 select CPU_SA1100 571 select GENERIC_CLOCKEVENTS 572 select GENERIC_IRQ_MULTI_HANDLER 573 select GPIOLIB 574 select HAVE_IDE 575 select IRQ_DOMAIN 576 select ISA 577 select NEED_MACH_MEMORY_H 578 select SPARSE_IRQ 579 help 580 Support for StrongARM 11x0 based boards. 581 582config ARCH_S3C24XX 583 bool "Samsung S3C24XX SoCs" 584 select ATAGS 585 select CLKDEV_LOOKUP 586 select CLKSRC_SAMSUNG_PWM 587 select GENERIC_CLOCKEVENTS 588 select GPIO_SAMSUNG 589 select GPIOLIB 590 select GENERIC_IRQ_MULTI_HANDLER 591 select HAVE_S3C2410_I2C if I2C 592 select HAVE_S3C2410_WATCHDOG if WATCHDOG 593 select HAVE_S3C_RTC if RTC_CLASS 594 select NEED_MACH_IO_H 595 select SAMSUNG_ATAGS 596 select USE_OF 597 help 598 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 599 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 600 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 601 Samsung SMDK2410 development board (and derivatives). 602 603config ARCH_DAVINCI 604 bool "TI DaVinci" 605 select ARCH_HAS_HOLES_MEMORYMODEL 606 select COMMON_CLK 607 select CPU_ARM926T 608 select GENERIC_ALLOCATOR 609 select GENERIC_CLOCKEVENTS 610 select GENERIC_IRQ_CHIP 611 select GPIOLIB 612 select HAVE_IDE 613 select PM_GENERIC_DOMAINS if PM 614 select PM_GENERIC_DOMAINS_OF if PM && OF 615 select RESET_CONTROLLER 616 select USE_OF 617 select ZONE_DMA 618 help 619 Support for TI's DaVinci platform. 620 621config ARCH_OMAP1 622 bool "TI OMAP1" 623 depends on MMU 624 select ARCH_HAS_HOLES_MEMORYMODEL 625 select ARCH_OMAP 626 select CLKDEV_LOOKUP 627 select CLKSRC_MMIO 628 select GENERIC_CLOCKEVENTS 629 select GENERIC_IRQ_CHIP 630 select GENERIC_IRQ_MULTI_HANDLER 631 select GPIOLIB 632 select HAVE_IDE 633 select IRQ_DOMAIN 634 select NEED_MACH_IO_H if PCCARD 635 select NEED_MACH_MEMORY_H 636 select SPARSE_IRQ 637 help 638 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 639 640endchoice 641 642menu "Multiple platform selection" 643 depends on ARCH_MULTIPLATFORM 644 645comment "CPU Core family selection" 646 647config ARCH_MULTI_V4 648 bool "ARMv4 based platforms (FA526)" 649 depends on !ARCH_MULTI_V6_V7 650 select ARCH_MULTI_V4_V5 651 select CPU_FA526 652 653config ARCH_MULTI_V4T 654 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 655 depends on !ARCH_MULTI_V6_V7 656 select ARCH_MULTI_V4_V5 657 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 658 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 659 CPU_ARM925T || CPU_ARM940T) 660 661config ARCH_MULTI_V5 662 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 663 depends on !ARCH_MULTI_V6_V7 664 select ARCH_MULTI_V4_V5 665 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 666 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 667 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 668 669config ARCH_MULTI_V4_V5 670 bool 671 672config ARCH_MULTI_V6 673 bool "ARMv6 based platforms (ARM11)" 674 select ARCH_MULTI_V6_V7 675 select CPU_V6K 676 677config ARCH_MULTI_V7 678 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 679 default y 680 select ARCH_MULTI_V6_V7 681 select CPU_V7 682 select HAVE_SMP 683 684config ARCH_MULTI_V6_V7 685 bool 686 select MIGHT_HAVE_CACHE_L2X0 687 688config ARCH_MULTI_CPU_AUTO 689 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 690 select ARCH_MULTI_V5 691 692endmenu 693 694config ARCH_VIRT 695 bool "Dummy Virtual Machine" 696 depends on ARCH_MULTI_V7 697 select ARM_AMBA 698 select ARM_GIC 699 select ARM_GIC_V2M if PCI 700 select ARM_GIC_V3 701 select ARM_GIC_V3_ITS if PCI 702 select ARM_PSCI 703 select HAVE_ARM_ARCH_TIMER 704 705# 706# This is sorted alphabetically by mach-* pathname. However, plat-* 707# Kconfigs may be included either alphabetically (according to the 708# plat- suffix) or along side the corresponding mach-* source. 709# 710source "arch/arm/mach-actions/Kconfig" 711 712source "arch/arm/mach-alpine/Kconfig" 713 714source "arch/arm/mach-artpec/Kconfig" 715 716source "arch/arm/mach-asm9260/Kconfig" 717 718source "arch/arm/mach-aspeed/Kconfig" 719 720source "arch/arm/mach-at91/Kconfig" 721 722source "arch/arm/mach-axxia/Kconfig" 723 724source "arch/arm/mach-bcm/Kconfig" 725 726source "arch/arm/mach-berlin/Kconfig" 727 728source "arch/arm/mach-clps711x/Kconfig" 729 730source "arch/arm/mach-cns3xxx/Kconfig" 731 732source "arch/arm/mach-davinci/Kconfig" 733 734source "arch/arm/mach-digicolor/Kconfig" 735 736source "arch/arm/mach-dove/Kconfig" 737 738source "arch/arm/mach-ep93xx/Kconfig" 739 740source "arch/arm/mach-exynos/Kconfig" 741source "arch/arm/plat-samsung/Kconfig" 742 743source "arch/arm/mach-footbridge/Kconfig" 744 745source "arch/arm/mach-gemini/Kconfig" 746 747source "arch/arm/mach-highbank/Kconfig" 748 749source "arch/arm/mach-hisi/Kconfig" 750 751source "arch/arm/mach-imx/Kconfig" 752 753source "arch/arm/mach-integrator/Kconfig" 754 755source "arch/arm/mach-iop13xx/Kconfig" 756 757source "arch/arm/mach-iop32x/Kconfig" 758 759source "arch/arm/mach-iop33x/Kconfig" 760 761source "arch/arm/mach-ixp4xx/Kconfig" 762 763source "arch/arm/mach-keystone/Kconfig" 764 765source "arch/arm/mach-ks8695/Kconfig" 766 767source "arch/arm/mach-mediatek/Kconfig" 768 769source "arch/arm/mach-meson/Kconfig" 770 771source "arch/arm/mach-mmp/Kconfig" 772 773source "arch/arm/mach-moxart/Kconfig" 774 775source "arch/arm/mach-mv78xx0/Kconfig" 776 777source "arch/arm/mach-mvebu/Kconfig" 778 779source "arch/arm/mach-mxs/Kconfig" 780 781source "arch/arm/mach-netx/Kconfig" 782 783source "arch/arm/mach-nomadik/Kconfig" 784 785source "arch/arm/mach-npcm/Kconfig" 786 787source "arch/arm/mach-nspire/Kconfig" 788 789source "arch/arm/plat-omap/Kconfig" 790 791source "arch/arm/mach-omap1/Kconfig" 792 793source "arch/arm/mach-omap2/Kconfig" 794 795source "arch/arm/mach-orion5x/Kconfig" 796 797source "arch/arm/mach-oxnas/Kconfig" 798 799source "arch/arm/mach-picoxcell/Kconfig" 800 801source "arch/arm/mach-prima2/Kconfig" 802 803source "arch/arm/mach-pxa/Kconfig" 804source "arch/arm/plat-pxa/Kconfig" 805 806source "arch/arm/mach-qcom/Kconfig" 807 808source "arch/arm/mach-realview/Kconfig" 809 810source "arch/arm/mach-rockchip/Kconfig" 811 812source "arch/arm/mach-s3c24xx/Kconfig" 813 814source "arch/arm/mach-s3c64xx/Kconfig" 815 816source "arch/arm/mach-s5pv210/Kconfig" 817 818source "arch/arm/mach-sa1100/Kconfig" 819 820source "arch/arm/mach-shmobile/Kconfig" 821 822source "arch/arm/mach-socfpga/Kconfig" 823 824source "arch/arm/mach-spear/Kconfig" 825 826source "arch/arm/mach-sti/Kconfig" 827 828source "arch/arm/mach-stm32/Kconfig" 829 830source "arch/arm/mach-sunxi/Kconfig" 831 832source "arch/arm/mach-tango/Kconfig" 833 834source "arch/arm/mach-tegra/Kconfig" 835 836source "arch/arm/mach-u300/Kconfig" 837 838source "arch/arm/mach-uniphier/Kconfig" 839 840source "arch/arm/mach-ux500/Kconfig" 841 842source "arch/arm/mach-versatile/Kconfig" 843 844source "arch/arm/mach-vexpress/Kconfig" 845source "arch/arm/plat-versatile/Kconfig" 846 847source "arch/arm/mach-vt8500/Kconfig" 848 849source "arch/arm/mach-w90x900/Kconfig" 850 851source "arch/arm/mach-zx/Kconfig" 852 853source "arch/arm/mach-zynq/Kconfig" 854 855# ARMv7-M architecture 856config ARCH_EFM32 857 bool "Energy Micro efm32" 858 depends on ARM_SINGLE_ARMV7M 859 select GPIOLIB 860 help 861 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 862 processors. 863 864config ARCH_LPC18XX 865 bool "NXP LPC18xx/LPC43xx" 866 depends on ARM_SINGLE_ARMV7M 867 select ARCH_HAS_RESET_CONTROLLER 868 select ARM_AMBA 869 select CLKSRC_LPC32XX 870 select PINCTRL 871 help 872 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 873 high performance microcontrollers. 874 875config ARCH_MPS2 876 bool "ARM MPS2 platform" 877 depends on ARM_SINGLE_ARMV7M 878 select ARM_AMBA 879 select CLKSRC_MPS2 880 help 881 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 882 with a range of available cores like Cortex-M3/M4/M7. 883 884 Please, note that depends which Application Note is used memory map 885 for the platform may vary, so adjustment of RAM base might be needed. 886 887# Definitions to make life easier 888config ARCH_ACORN 889 bool 890 891config PLAT_IOP 892 bool 893 select GENERIC_CLOCKEVENTS 894 895config PLAT_ORION 896 bool 897 select CLKSRC_MMIO 898 select COMMON_CLK 899 select GENERIC_IRQ_CHIP 900 select IRQ_DOMAIN 901 902config PLAT_ORION_LEGACY 903 bool 904 select PLAT_ORION 905 906config PLAT_PXA 907 bool 908 909config PLAT_VERSATILE 910 bool 911 912source "arch/arm/firmware/Kconfig" 913 914source arch/arm/mm/Kconfig 915 916config IWMMXT 917 bool "Enable iWMMXt support" 918 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 919 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 920 help 921 Enable support for iWMMXt context switching at run time if 922 running on a CPU that supports it. 923 924if !MMU 925source "arch/arm/Kconfig-nommu" 926endif 927 928config PJ4B_ERRATA_4742 929 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 930 depends on CPU_PJ4B && MACH_ARMADA_370 931 default y 932 help 933 When coming out of either a Wait for Interrupt (WFI) or a Wait for 934 Event (WFE) IDLE states, a specific timing sensitivity exists between 935 the retiring WFI/WFE instructions and the newly issued subsequent 936 instructions. This sensitivity can result in a CPU hang scenario. 937 Workaround: 938 The software must insert either a Data Synchronization Barrier (DSB) 939 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 940 instruction 941 942config ARM_ERRATA_326103 943 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 944 depends on CPU_V6 945 help 946 Executing a SWP instruction to read-only memory does not set bit 11 947 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 948 treat the access as a read, preventing a COW from occurring and 949 causing the faulting task to livelock. 950 951config ARM_ERRATA_411920 952 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 953 depends on CPU_V6 || CPU_V6K 954 help 955 Invalidation of the Instruction Cache operation can 956 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 957 It does not affect the MPCore. This option enables the ARM Ltd. 958 recommended workaround. 959 960config ARM_ERRATA_430973 961 bool "ARM errata: Stale prediction on replaced interworking branch" 962 depends on CPU_V7 963 help 964 This option enables the workaround for the 430973 Cortex-A8 965 r1p* erratum. If a code sequence containing an ARM/Thumb 966 interworking branch is replaced with another code sequence at the 967 same virtual address, whether due to self-modifying code or virtual 968 to physical address re-mapping, Cortex-A8 does not recover from the 969 stale interworking branch prediction. This results in Cortex-A8 970 executing the new code sequence in the incorrect ARM or Thumb state. 971 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 972 and also flushes the branch target cache at every context switch. 973 Note that setting specific bits in the ACTLR register may not be 974 available in non-secure mode. 975 976config ARM_ERRATA_458693 977 bool "ARM errata: Processor deadlock when a false hazard is created" 978 depends on CPU_V7 979 depends on !ARCH_MULTIPLATFORM 980 help 981 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 982 erratum. For very specific sequences of memory operations, it is 983 possible for a hazard condition intended for a cache line to instead 984 be incorrectly associated with a different cache line. This false 985 hazard might then cause a processor deadlock. The workaround enables 986 the L1 caching of the NEON accesses and disables the PLD instruction 987 in the ACTLR register. Note that setting specific bits in the ACTLR 988 register may not be available in non-secure mode. 989 990config ARM_ERRATA_460075 991 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 992 depends on CPU_V7 993 depends on !ARCH_MULTIPLATFORM 994 help 995 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 996 erratum. Any asynchronous access to the L2 cache may encounter a 997 situation in which recent store transactions to the L2 cache are lost 998 and overwritten with stale memory contents from external memory. The 999 workaround disables the write-allocate mode for the L2 cache via the 1000 ACTLR register. Note that setting specific bits in the ACTLR register 1001 may not be available in non-secure mode. 1002 1003config ARM_ERRATA_742230 1004 bool "ARM errata: DMB operation may be faulty" 1005 depends on CPU_V7 && SMP 1006 depends on !ARCH_MULTIPLATFORM 1007 help 1008 This option enables the workaround for the 742230 Cortex-A9 1009 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 1010 between two write operations may not ensure the correct visibility 1011 ordering of the two writes. This workaround sets a specific bit in 1012 the diagnostic register of the Cortex-A9 which causes the DMB 1013 instruction to behave as a DSB, ensuring the correct behaviour of 1014 the two writes. 1015 1016config ARM_ERRATA_742231 1017 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 1018 depends on CPU_V7 && SMP 1019 depends on !ARCH_MULTIPLATFORM 1020 help 1021 This option enables the workaround for the 742231 Cortex-A9 1022 (r2p0..r2p2) erratum. Under certain conditions, specific to the 1023 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 1024 accessing some data located in the same cache line, may get corrupted 1025 data due to bad handling of the address hazard when the line gets 1026 replaced from one of the CPUs at the same time as another CPU is 1027 accessing it. This workaround sets specific bits in the diagnostic 1028 register of the Cortex-A9 which reduces the linefill issuing 1029 capabilities of the processor. 1030 1031config ARM_ERRATA_643719 1032 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 1033 depends on CPU_V7 && SMP 1034 default y 1035 help 1036 This option enables the workaround for the 643719 Cortex-A9 (prior to 1037 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 1038 register returns zero when it should return one. The workaround 1039 corrects this value, ensuring cache maintenance operations which use 1040 it behave as intended and avoiding data corruption. 1041 1042config ARM_ERRATA_720789 1043 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 1044 depends on CPU_V7 1045 help 1046 This option enables the workaround for the 720789 Cortex-A9 (prior to 1047 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 1048 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 1049 As a consequence of this erratum, some TLB entries which should be 1050 invalidated are not, resulting in an incoherency in the system page 1051 tables. The workaround changes the TLB flushing routines to invalidate 1052 entries regardless of the ASID. 1053 1054config ARM_ERRATA_743622 1055 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 1056 depends on CPU_V7 1057 depends on !ARCH_MULTIPLATFORM 1058 help 1059 This option enables the workaround for the 743622 Cortex-A9 1060 (r2p*) erratum. Under very rare conditions, a faulty 1061 optimisation in the Cortex-A9 Store Buffer may lead to data 1062 corruption. This workaround sets a specific bit in the diagnostic 1063 register of the Cortex-A9 which disables the Store Buffer 1064 optimisation, preventing the defect from occurring. This has no 1065 visible impact on the overall performance or power consumption of the 1066 processor. 1067 1068config ARM_ERRATA_751472 1069 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 1070 depends on CPU_V7 1071 depends on !ARCH_MULTIPLATFORM 1072 help 1073 This option enables the workaround for the 751472 Cortex-A9 (prior 1074 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 1075 completion of a following broadcasted operation if the second 1076 operation is received by a CPU before the ICIALLUIS has completed, 1077 potentially leading to corrupted entries in the cache or TLB. 1078 1079config ARM_ERRATA_754322 1080 bool "ARM errata: possible faulty MMU translations following an ASID switch" 1081 depends on CPU_V7 1082 help 1083 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 1084 r3p*) erratum. A speculative memory access may cause a page table walk 1085 which starts prior to an ASID switch but completes afterwards. This 1086 can populate the micro-TLB with a stale entry which may be hit with 1087 the new ASID. This workaround places two dsb instructions in the mm 1088 switching code so that no page table walks can cross the ASID switch. 1089 1090config ARM_ERRATA_754327 1091 bool "ARM errata: no automatic Store Buffer drain" 1092 depends on CPU_V7 && SMP 1093 help 1094 This option enables the workaround for the 754327 Cortex-A9 (prior to 1095 r2p0) erratum. The Store Buffer does not have any automatic draining 1096 mechanism and therefore a livelock may occur if an external agent 1097 continuously polls a memory location waiting to observe an update. 1098 This workaround defines cpu_relax() as smp_mb(), preventing correctly 1099 written polling loops from denying visibility of updates to memory. 1100 1101config ARM_ERRATA_364296 1102 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 1103 depends on CPU_V6 1104 help 1105 This options enables the workaround for the 364296 ARM1136 1106 r0p2 erratum (possible cache data corruption with 1107 hit-under-miss enabled). It sets the undocumented bit 31 in 1108 the auxiliary control register and the FI bit in the control 1109 register, thus disabling hit-under-miss without putting the 1110 processor into full low interrupt latency mode. ARM11MPCore 1111 is not affected. 1112 1113config ARM_ERRATA_764369 1114 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1115 depends on CPU_V7 && SMP 1116 help 1117 This option enables the workaround for erratum 764369 1118 affecting Cortex-A9 MPCore with two or more processors (all 1119 current revisions). Under certain timing circumstances, a data 1120 cache line maintenance operation by MVA targeting an Inner 1121 Shareable memory region may fail to proceed up to either the 1122 Point of Coherency or to the Point of Unification of the 1123 system. This workaround adds a DSB instruction before the 1124 relevant cache maintenance functions and sets a specific bit 1125 in the diagnostic control register of the SCU. 1126 1127config ARM_ERRATA_775420 1128 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1129 depends on CPU_V7 1130 help 1131 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1132 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance 1133 operation aborts with MMU exception, it might cause the processor 1134 to deadlock. This workaround puts DSB before executing ISB if 1135 an abort may occur on cache maintenance. 1136 1137config ARM_ERRATA_798181 1138 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1139 depends on CPU_V7 && SMP 1140 help 1141 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1142 adequately shooting down all use of the old entries. This 1143 option enables the Linux kernel workaround for this erratum 1144 which sends an IPI to the CPUs that are running the same ASID 1145 as the one being invalidated. 1146 1147config ARM_ERRATA_773022 1148 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1149 depends on CPU_V7 1150 help 1151 This option enables the workaround for the 773022 Cortex-A15 1152 (up to r0p4) erratum. In certain rare sequences of code, the 1153 loop buffer may deliver incorrect instructions. This 1154 workaround disables the loop buffer to avoid the erratum. 1155 1156config ARM_ERRATA_818325_852422 1157 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1158 depends on CPU_V7 1159 help 1160 This option enables the workaround for: 1161 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1162 instruction might deadlock. Fixed in r0p1. 1163 - Cortex-A12 852422: Execution of a sequence of instructions might 1164 lead to either a data corruption or a CPU deadlock. Not fixed in 1165 any Cortex-A12 cores yet. 1166 This workaround for all both errata involves setting bit[12] of the 1167 Feature Register. This bit disables an optimisation applied to a 1168 sequence of 2 instructions that use opposing condition codes. 1169 1170config ARM_ERRATA_821420 1171 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1172 depends on CPU_V7 1173 help 1174 This option enables the workaround for the 821420 Cortex-A12 1175 (all revs) erratum. In very rare timing conditions, a sequence 1176 of VMOV to Core registers instructions, for which the second 1177 one is in the shadow of a branch or abort, can lead to a 1178 deadlock when the VMOV instructions are issued out-of-order. 1179 1180config ARM_ERRATA_825619 1181 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1182 depends on CPU_V7 1183 help 1184 This option enables the workaround for the 825619 Cortex-A12 1185 (all revs) erratum. Within rare timing constraints, executing a 1186 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1187 and Device/Strongly-Ordered loads and stores might cause deadlock 1188 1189config ARM_ERRATA_852421 1190 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1191 depends on CPU_V7 1192 help 1193 This option enables the workaround for the 852421 Cortex-A17 1194 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1195 execution of a DMB ST instruction might fail to properly order 1196 stores from GroupA and stores from GroupB. 1197 1198config ARM_ERRATA_852423 1199 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1200 depends on CPU_V7 1201 help 1202 This option enables the workaround for: 1203 - Cortex-A17 852423: Execution of a sequence of instructions might 1204 lead to either a data corruption or a CPU deadlock. Not fixed in 1205 any Cortex-A17 cores yet. 1206 This is identical to Cortex-A12 erratum 852422. It is a separate 1207 config option from the A12 erratum due to the way errata are checked 1208 for and handled. 1209 1210endmenu 1211 1212source "arch/arm/common/Kconfig" 1213 1214menu "Bus support" 1215 1216config ISA 1217 bool 1218 help 1219 Find out whether you have ISA slots on your motherboard. ISA is the 1220 name of a bus system, i.e. the way the CPU talks to the other stuff 1221 inside your box. Other bus systems are PCI, EISA, MicroChannel 1222 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1223 newer boards don't support it. If you have ISA, say Y, otherwise N. 1224 1225# Select ISA DMA controller support 1226config ISA_DMA 1227 bool 1228 select ISA_DMA_API 1229 1230# Select ISA DMA interface 1231config ISA_DMA_API 1232 bool 1233 1234config PCI 1235 bool "PCI support" if MIGHT_HAVE_PCI 1236 help 1237 Find out whether you have a PCI motherboard. PCI is the name of a 1238 bus system, i.e. the way the CPU talks to the other stuff inside 1239 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 1240 VESA. If you have PCI, say Y, otherwise N. 1241 1242config PCI_DOMAINS 1243 bool "Support for multiple PCI domains" 1244 depends on PCI 1245 help 1246 Enable PCI domains kernel management. Say Y if your machine 1247 has a PCI bus hierarchy that requires more than one PCI 1248 domain (aka segment) to be correctly managed. Say N otherwise. 1249 1250 If you don't know what to do here, say N. 1251 1252config PCI_DOMAINS_GENERIC 1253 def_bool PCI_DOMAINS 1254 1255config PCI_NANOENGINE 1256 bool "BSE nanoEngine PCI support" 1257 depends on SA1100_NANOENGINE 1258 help 1259 Enable PCI on the BSE nanoEngine board. 1260 1261config PCI_SYSCALL 1262 def_bool PCI 1263 1264config PCI_HOST_ITE8152 1265 bool 1266 depends on PCI && MACH_ARMCORE 1267 default y 1268 select DMABOUNCE 1269 1270source "drivers/pci/Kconfig" 1271 1272source "drivers/pcmcia/Kconfig" 1273 1274endmenu 1275 1276menu "Kernel Features" 1277 1278config HAVE_SMP 1279 bool 1280 help 1281 This option should be selected by machines which have an SMP- 1282 capable CPU. 1283 1284 The only effect of this option is to make the SMP-related 1285 options available to the user for configuration. 1286 1287config SMP 1288 bool "Symmetric Multi-Processing" 1289 depends on CPU_V6K || CPU_V7 1290 depends on GENERIC_CLOCKEVENTS 1291 depends on HAVE_SMP 1292 depends on MMU || ARM_MPU 1293 select IRQ_WORK 1294 help 1295 This enables support for systems with more than one CPU. If you have 1296 a system with only one CPU, say N. If you have a system with more 1297 than one CPU, say Y. 1298 1299 If you say N here, the kernel will run on uni- and multiprocessor 1300 machines, but will use only one CPU of a multiprocessor machine. If 1301 you say Y here, the kernel will run on many, but not all, 1302 uniprocessor machines. On a uniprocessor machine, the kernel 1303 will run faster if you say N here. 1304 1305 See also <file:Documentation/x86/i386/IO-APIC.txt>, 1306 <file:Documentation/lockup-watchdogs.txt> and the SMP-HOWTO available at 1307 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1308 1309 If you don't know what to do here, say N. 1310 1311config SMP_ON_UP 1312 bool "Allow booting SMP kernel on uniprocessor systems" 1313 depends on SMP && !XIP_KERNEL && MMU 1314 default y 1315 help 1316 SMP kernels contain instructions which fail on non-SMP processors. 1317 Enabling this option allows the kernel to modify itself to make 1318 these instructions safe. Disabling it allows about 1K of space 1319 savings. 1320 1321 If you don't know what to do here, say Y. 1322 1323config ARM_CPU_TOPOLOGY 1324 bool "Support cpu topology definition" 1325 depends on SMP && CPU_V7 1326 default y 1327 help 1328 Support ARM cpu topology definition. The MPIDR register defines 1329 affinity between processors which is then used to describe the cpu 1330 topology of an ARM System. 1331 1332config SCHED_MC 1333 bool "Multi-core scheduler support" 1334 depends on ARM_CPU_TOPOLOGY 1335 help 1336 Multi-core scheduler support improves the CPU scheduler's decision 1337 making when dealing with multi-core CPU chips at a cost of slightly 1338 increased overhead in some places. If unsure say N here. 1339 1340config SCHED_SMT 1341 bool "SMT scheduler support" 1342 depends on ARM_CPU_TOPOLOGY 1343 help 1344 Improves the CPU scheduler's decision making when dealing with 1345 MultiThreading at a cost of slightly increased overhead in some 1346 places. If unsure say N here. 1347 1348config HAVE_ARM_SCU 1349 bool 1350 help 1351 This option enables support for the ARM system coherency unit 1352 1353config HAVE_ARM_ARCH_TIMER 1354 bool "Architected timer support" 1355 depends on CPU_V7 1356 select ARM_ARCH_TIMER 1357 select GENERIC_CLOCKEVENTS 1358 help 1359 This option enables support for the ARM architected timer 1360 1361config HAVE_ARM_TWD 1362 bool 1363 select TIMER_OF if OF 1364 help 1365 This options enables support for the ARM timer and watchdog unit 1366 1367config MCPM 1368 bool "Multi-Cluster Power Management" 1369 depends on CPU_V7 && SMP 1370 help 1371 This option provides the common power management infrastructure 1372 for (multi-)cluster based systems, such as big.LITTLE based 1373 systems. 1374 1375config MCPM_QUAD_CLUSTER 1376 bool 1377 depends on MCPM 1378 help 1379 To avoid wasting resources unnecessarily, MCPM only supports up 1380 to 2 clusters by default. 1381 Platforms with 3 or 4 clusters that use MCPM must select this 1382 option to allow the additional clusters to be managed. 1383 1384config BIG_LITTLE 1385 bool "big.LITTLE support (Experimental)" 1386 depends on CPU_V7 && SMP 1387 select MCPM 1388 help 1389 This option enables support selections for the big.LITTLE 1390 system architecture. 1391 1392config BL_SWITCHER 1393 bool "big.LITTLE switcher support" 1394 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1395 select CPU_PM 1396 help 1397 The big.LITTLE "switcher" provides the core functionality to 1398 transparently handle transition between a cluster of A15's 1399 and a cluster of A7's in a big.LITTLE system. 1400 1401config BL_SWITCHER_DUMMY_IF 1402 tristate "Simple big.LITTLE switcher user interface" 1403 depends on BL_SWITCHER && DEBUG_KERNEL 1404 help 1405 This is a simple and dummy char dev interface to control 1406 the big.LITTLE switcher core code. It is meant for 1407 debugging purposes only. 1408 1409choice 1410 prompt "Memory split" 1411 depends on MMU 1412 default VMSPLIT_3G 1413 help 1414 Select the desired split between kernel and user memory. 1415 1416 If you are not absolutely sure what you are doing, leave this 1417 option alone! 1418 1419 config VMSPLIT_3G 1420 bool "3G/1G user/kernel split" 1421 config VMSPLIT_3G_OPT 1422 depends on !ARM_LPAE 1423 bool "3G/1G user/kernel split (for full 1G low memory)" 1424 config VMSPLIT_2G 1425 bool "2G/2G user/kernel split" 1426 config VMSPLIT_1G 1427 bool "1G/3G user/kernel split" 1428endchoice 1429 1430config PAGE_OFFSET 1431 hex 1432 default PHYS_OFFSET if !MMU 1433 default 0x40000000 if VMSPLIT_1G 1434 default 0x80000000 if VMSPLIT_2G 1435 default 0xB0000000 if VMSPLIT_3G_OPT 1436 default 0xC0000000 1437 1438config NR_CPUS 1439 int "Maximum number of CPUs (2-32)" 1440 range 2 32 1441 depends on SMP 1442 default "4" 1443 1444config HOTPLUG_CPU 1445 bool "Support for hot-pluggable CPUs" 1446 depends on SMP 1447 help 1448 Say Y here to experiment with turning CPUs off and on. CPUs 1449 can be controlled through /sys/devices/system/cpu. 1450 1451config ARM_PSCI 1452 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1453 depends on HAVE_ARM_SMCCC 1454 select ARM_PSCI_FW 1455 help 1456 Say Y here if you want Linux to communicate with system firmware 1457 implementing the PSCI specification for CPU-centric power 1458 management operations described in ARM document number ARM DEN 1459 0022A ("Power State Coordination Interface System Software on 1460 ARM processors"). 1461 1462# The GPIO number here must be sorted by descending number. In case of 1463# a multiplatform kernel, we just want the highest value required by the 1464# selected platforms. 1465config ARCH_NR_GPIO 1466 int 1467 default 2048 if ARCH_SOCFPGA 1468 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1469 ARCH_ZYNQ 1470 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1471 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1472 default 416 if ARCH_SUNXI 1473 default 392 if ARCH_U8500 1474 default 352 if ARCH_VT8500 1475 default 288 if ARCH_ROCKCHIP 1476 default 264 if MACH_H4700 1477 default 0 1478 help 1479 Maximum number of GPIOs in the system. 1480 1481 If unsure, leave the default value. 1482 1483config HZ_FIXED 1484 int 1485 default 200 if ARCH_EBSA110 1486 default 128 if SOC_AT91RM9200 1487 default 0 1488 1489choice 1490 depends on HZ_FIXED = 0 1491 prompt "Timer frequency" 1492 1493config HZ_100 1494 bool "100 Hz" 1495 1496config HZ_200 1497 bool "200 Hz" 1498 1499config HZ_250 1500 bool "250 Hz" 1501 1502config HZ_300 1503 bool "300 Hz" 1504 1505config HZ_500 1506 bool "500 Hz" 1507 1508config HZ_1000 1509 bool "1000 Hz" 1510 1511endchoice 1512 1513config HZ 1514 int 1515 default HZ_FIXED if HZ_FIXED != 0 1516 default 100 if HZ_100 1517 default 200 if HZ_200 1518 default 250 if HZ_250 1519 default 300 if HZ_300 1520 default 500 if HZ_500 1521 default 1000 1522 1523config SCHED_HRTICK 1524 def_bool HIGH_RES_TIMERS 1525 1526config THUMB2_KERNEL 1527 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1528 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1529 default y if CPU_THUMBONLY 1530 select ARM_UNWIND 1531 help 1532 By enabling this option, the kernel will be compiled in 1533 Thumb-2 mode. 1534 1535 If unsure, say N. 1536 1537config THUMB2_AVOID_R_ARM_THM_JUMP11 1538 bool "Work around buggy Thumb-2 short branch relocations in gas" 1539 depends on THUMB2_KERNEL && MODULES 1540 default y 1541 help 1542 Various binutils versions can resolve Thumb-2 branches to 1543 locally-defined, preemptible global symbols as short-range "b.n" 1544 branch instructions. 1545 1546 This is a problem, because there's no guarantee the final 1547 destination of the symbol, or any candidate locations for a 1548 trampoline, are within range of the branch. For this reason, the 1549 kernel does not support fixing up the R_ARM_THM_JUMP11 (102) 1550 relocation in modules at all, and it makes little sense to add 1551 support. 1552 1553 The symptom is that the kernel fails with an "unsupported 1554 relocation" error when loading some modules. 1555 1556 Until fixed tools are available, passing 1557 -fno-optimize-sibling-calls to gcc should prevent gcc generating 1558 code which hits this problem, at the cost of a bit of extra runtime 1559 stack usage in some cases. 1560 1561 The problem is described in more detail at: 1562 https://bugs.launchpad.net/binutils-linaro/+bug/725126 1563 1564 Only Thumb-2 kernels are affected. 1565 1566 Unless you are sure your tools don't have this problem, say Y. 1567 1568config ARM_PATCH_IDIV 1569 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1570 depends on CPU_32v7 && !XIP_KERNEL 1571 default y 1572 help 1573 The ARM compiler inserts calls to __aeabi_idiv() and 1574 __aeabi_uidiv() when it needs to perform division on signed 1575 and unsigned integers. Some v7 CPUs have support for the sdiv 1576 and udiv instructions that can be used to implement those 1577 functions. 1578 1579 Enabling this option allows the kernel to modify itself to 1580 replace the first two instructions of these library functions 1581 with the sdiv or udiv plus "bx lr" instructions when the CPU 1582 it is running on supports them. Typically this will be faster 1583 and less power intensive than running the original library 1584 code to do integer division. 1585 1586config AEABI 1587 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && !CPU_V7M && !CPU_V6 && !CPU_V6K 1588 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K 1589 help 1590 This option allows for the kernel to be compiled using the latest 1591 ARM ABI (aka EABI). This is only useful if you are using a user 1592 space environment that is also compiled with EABI. 1593 1594 Since there are major incompatibilities between the legacy ABI and 1595 EABI, especially with regard to structure member alignment, this 1596 option also changes the kernel syscall calling convention to 1597 disambiguate both ABIs and allow for backward compatibility support 1598 (selected with CONFIG_OABI_COMPAT). 1599 1600 To use this you need GCC version 4.0.0 or later. 1601 1602config OABI_COMPAT 1603 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1604 depends on AEABI && !THUMB2_KERNEL 1605 help 1606 This option preserves the old syscall interface along with the 1607 new (ARM EABI) one. It also provides a compatibility layer to 1608 intercept syscalls that have structure arguments which layout 1609 in memory differs between the legacy ABI and the new ARM EABI 1610 (only for non "thumb" binaries). This option adds a tiny 1611 overhead to all syscalls and produces a slightly larger kernel. 1612 1613 The seccomp filter system will not be available when this is 1614 selected, since there is no way yet to sensibly distinguish 1615 between calling conventions during filtering. 1616 1617 If you know you'll be using only pure EABI user space then you 1618 can say N here. If this option is not selected and you attempt 1619 to execute a legacy ABI binary then the result will be 1620 UNPREDICTABLE (in fact it can be predicted that it won't work 1621 at all). If in doubt say N. 1622 1623config ARCH_HAS_HOLES_MEMORYMODEL 1624 bool 1625 1626config ARCH_SPARSEMEM_ENABLE 1627 bool 1628 1629config ARCH_SPARSEMEM_DEFAULT 1630 def_bool ARCH_SPARSEMEM_ENABLE 1631 1632config ARCH_SELECT_MEMORY_MODEL 1633 def_bool ARCH_SPARSEMEM_ENABLE 1634 1635config HAVE_ARCH_PFN_VALID 1636 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1637 1638config HAVE_GENERIC_GUP 1639 def_bool y 1640 depends on ARM_LPAE 1641 1642config HIGHMEM 1643 bool "High Memory Support" 1644 depends on MMU 1645 help 1646 The address space of ARM processors is only 4 Gigabytes large 1647 and it has to accommodate user address space, kernel address 1648 space as well as some memory mapped IO. That means that, if you 1649 have a large amount of physical memory and/or IO, not all of the 1650 memory can be "permanently mapped" by the kernel. The physical 1651 memory that is not permanently mapped is called "high memory". 1652 1653 Depending on the selected kernel/user memory split, minimum 1654 vmalloc space and actual amount of RAM, you may not need this 1655 option which should result in a slightly faster kernel. 1656 1657 If unsure, say n. 1658 1659config HIGHPTE 1660 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1661 depends on HIGHMEM 1662 default y 1663 help 1664 The VM uses one page of physical memory for each page table. 1665 For systems with a lot of processes, this can use a lot of 1666 precious low memory, eventually leading to low memory being 1667 consumed by page tables. Setting this option will allow 1668 user-space 2nd level page tables to reside in high memory. 1669 1670config CPU_SW_DOMAIN_PAN 1671 bool "Enable use of CPU domains to implement privileged no-access" 1672 depends on MMU && !ARM_LPAE 1673 default y 1674 help 1675 Increase kernel security by ensuring that normal kernel accesses 1676 are unable to access userspace addresses. This can help prevent 1677 use-after-free bugs becoming an exploitable privilege escalation 1678 by ensuring that magic values (such as LIST_POISON) will always 1679 fault when dereferenced. 1680 1681 CPUs with low-vector mappings use a best-efforts implementation. 1682 Their lower 1MB needs to remain accessible for the vectors, but 1683 the remainder of userspace will become appropriately inaccessible. 1684 1685config HW_PERF_EVENTS 1686 def_bool y 1687 depends on ARM_PMU 1688 1689config SYS_SUPPORTS_HUGETLBFS 1690 def_bool y 1691 depends on ARM_LPAE 1692 1693config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1694 def_bool y 1695 depends on ARM_LPAE 1696 1697config ARCH_WANT_GENERAL_HUGETLB 1698 def_bool y 1699 1700config ARM_MODULE_PLTS 1701 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1702 depends on MODULES 1703 default y 1704 help 1705 Allocate PLTs when loading modules so that jumps and calls whose 1706 targets are too far away for their relative offsets to be encoded 1707 in the instructions themselves can be bounced via veneers in the 1708 module's PLT. This allows modules to be allocated in the generic 1709 vmalloc area after the dedicated module memory area has been 1710 exhausted. The modules will use slightly more memory, but after 1711 rounding up to page size, the actual memory footprint is usually 1712 the same. 1713 1714 Disabling this is usually safe for small single-platform 1715 configurations. If unsure, say y. 1716 1717config FORCE_MAX_ZONEORDER 1718 int "Maximum zone order" 1719 default "12" if SOC_AM33XX 1720 default "9" if SA1111 || ARCH_EFM32 1721 default "11" 1722 help 1723 The kernel memory allocator divides physically contiguous memory 1724 blocks into "zones", where each zone is a power of two number of 1725 pages. This option selects the largest power of two that the kernel 1726 keeps in the memory allocator. If you need to allocate very large 1727 blocks of physically contiguous memory, then you may need to 1728 increase this value. 1729 1730 This config option is actually maximum order plus one. For example, 1731 a value of 11 means that the largest free memory block is 2^10 pages. 1732 1733config ALIGNMENT_TRAP 1734 bool 1735 depends on CPU_CP15_MMU 1736 default y if !ARCH_EBSA110 1737 select HAVE_PROC_CPU if PROC_FS 1738 help 1739 ARM processors cannot fetch/store information which is not 1740 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1741 address divisible by 4. On 32-bit ARM processors, these non-aligned 1742 fetch/store instructions will be emulated in software if you say 1743 here, which has a severe performance impact. This is necessary for 1744 correct operation of some network protocols. With an IP-only 1745 configuration it is safe to say N, otherwise say Y. 1746 1747config UACCESS_WITH_MEMCPY 1748 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1749 depends on MMU 1750 default y if CPU_FEROCEON 1751 help 1752 Implement faster copy_to_user and clear_user methods for CPU 1753 cores where a 8-word STM instruction give significantly higher 1754 memory write throughput than a sequence of individual 32bit stores. 1755 1756 A possible side effect is a slight increase in scheduling latency 1757 between threads sharing the same address space if they invoke 1758 such copy operations with large buffers. 1759 1760 However, if the CPU data cache is using a write-allocate mode, 1761 this option is unlikely to provide any performance gain. 1762 1763config SECCOMP 1764 bool 1765 prompt "Enable seccomp to safely compute untrusted bytecode" 1766 ---help--- 1767 This kernel feature is useful for number crunching applications 1768 that may need to compute untrusted bytecode during their 1769 execution. By using pipes or other transports made available to 1770 the process as file descriptors supporting the read/write 1771 syscalls, it's possible to isolate those applications in 1772 their own address space using seccomp. Once seccomp is 1773 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled 1774 and the task is only allowed to execute a few safe syscalls 1775 defined by each seccomp mode. 1776 1777config PARAVIRT 1778 bool "Enable paravirtualization code" 1779 help 1780 This changes the kernel so it can modify itself when it is run 1781 under a hypervisor, potentially improving performance significantly 1782 over full virtualization. 1783 1784config PARAVIRT_TIME_ACCOUNTING 1785 bool "Paravirtual steal time accounting" 1786 select PARAVIRT 1787 default n 1788 help 1789 Select this option to enable fine granularity task steal time 1790 accounting. Time spent executing other tasks in parallel with 1791 the current vCPU is discounted from the vCPU power. To account for 1792 that, there can be a small performance impact. 1793 1794 If in doubt, say N here. 1795 1796config XEN_DOM0 1797 def_bool y 1798 depends on XEN 1799 1800config XEN 1801 bool "Xen guest support on ARM" 1802 depends on ARM && AEABI && OF 1803 depends on CPU_V7 && !CPU_V6 1804 depends on !GENERIC_ATOMIC64 1805 depends on MMU 1806 select ARCH_DMA_ADDR_T_64BIT 1807 select ARM_PSCI 1808 select SWIOTLB 1809 select SWIOTLB_XEN 1810 select PARAVIRT 1811 help 1812 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1813 1814endmenu 1815 1816menu "Boot options" 1817 1818config USE_OF 1819 bool "Flattened Device Tree support" 1820 select IRQ_DOMAIN 1821 select OF 1822 help 1823 Include support for flattened device tree machine descriptions. 1824 1825config ATAGS 1826 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1827 default y 1828 help 1829 This is the traditional way of passing data to the kernel at boot 1830 time. If you are solely relying on the flattened device tree (or 1831 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1832 to remove ATAGS support from your kernel binary. If unsure, 1833 leave this to y. 1834 1835config DEPRECATED_PARAM_STRUCT 1836 bool "Provide old way to pass kernel parameters" 1837 depends on ATAGS 1838 help 1839 This was deprecated in 2001 and announced to live on for 5 years. 1840 Some old boot loaders still use this way. 1841 1842# Compressed boot loader in ROM. Yes, we really want to ask about 1843# TEXT and BSS so we preserve their values in the config files. 1844config ZBOOT_ROM_TEXT 1845 hex "Compressed ROM boot loader base address" 1846 default "0" 1847 help 1848 The physical address at which the ROM-able zImage is to be 1849 placed in the target. Platforms which normally make use of 1850 ROM-able zImage formats normally set this to a suitable 1851 value in their defconfig file. 1852 1853 If ZBOOT_ROM is not enabled, this has no effect. 1854 1855config ZBOOT_ROM_BSS 1856 hex "Compressed ROM boot loader BSS address" 1857 default "0" 1858 help 1859 The base address of an area of read/write memory in the target 1860 for the ROM-able zImage which must be available while the 1861 decompressor is running. It must be large enough to hold the 1862 entire decompressed kernel plus an additional 128 KiB. 1863 Platforms which normally make use of ROM-able zImage formats 1864 normally set this to a suitable value in their defconfig file. 1865 1866 If ZBOOT_ROM is not enabled, this has no effect. 1867 1868config ZBOOT_ROM 1869 bool "Compressed boot loader in ROM/flash" 1870 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1871 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1872 help 1873 Say Y here if you intend to execute your compressed kernel image 1874 (zImage) directly from ROM or flash. If unsure, say N. 1875 1876config ARM_APPENDED_DTB 1877 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1878 depends on OF 1879 help 1880 With this option, the boot code will look for a device tree binary 1881 (DTB) appended to zImage 1882 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1883 1884 This is meant as a backward compatibility convenience for those 1885 systems with a bootloader that can't be upgraded to accommodate 1886 the documented boot protocol using a device tree. 1887 1888 Beware that there is very little in terms of protection against 1889 this option being confused by leftover garbage in memory that might 1890 look like a DTB header after a reboot if no actual DTB is appended 1891 to zImage. Do not leave this option active in a production kernel 1892 if you don't intend to always append a DTB. Proper passing of the 1893 location into r2 of a bootloader provided DTB is always preferable 1894 to this option. 1895 1896config ARM_ATAG_DTB_COMPAT 1897 bool "Supplement the appended DTB with traditional ATAG information" 1898 depends on ARM_APPENDED_DTB 1899 help 1900 Some old bootloaders can't be updated to a DTB capable one, yet 1901 they provide ATAGs with memory configuration, the ramdisk address, 1902 the kernel cmdline string, etc. Such information is dynamically 1903 provided by the bootloader and can't always be stored in a static 1904 DTB. To allow a device tree enabled kernel to be used with such 1905 bootloaders, this option allows zImage to extract the information 1906 from the ATAG list and store it at run time into the appended DTB. 1907 1908choice 1909 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1910 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1911 1912config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1913 bool "Use bootloader kernel arguments if available" 1914 help 1915 Uses the command-line options passed by the boot loader instead of 1916 the device tree bootargs property. If the boot loader doesn't provide 1917 any, the device tree bootargs property will be used. 1918 1919config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1920 bool "Extend with bootloader kernel arguments" 1921 help 1922 The command-line arguments provided by the boot loader will be 1923 appended to the the device tree bootargs property. 1924 1925endchoice 1926 1927config CMDLINE 1928 string "Default kernel command string" 1929 default "" 1930 help 1931 On some architectures (EBSA110 and CATS), there is currently no way 1932 for the boot loader to pass arguments to the kernel. For these 1933 architectures, you should supply some command-line options at build 1934 time by entering them here. As a minimum, you should specify the 1935 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1936 1937choice 1938 prompt "Kernel command line type" if CMDLINE != "" 1939 default CMDLINE_FROM_BOOTLOADER 1940 depends on ATAGS 1941 1942config CMDLINE_FROM_BOOTLOADER 1943 bool "Use bootloader kernel arguments if available" 1944 help 1945 Uses the command-line options passed by the boot loader. If 1946 the boot loader doesn't provide any, the default kernel command 1947 string provided in CMDLINE will be used. 1948 1949config CMDLINE_EXTEND 1950 bool "Extend bootloader kernel arguments" 1951 help 1952 The command-line arguments provided by the boot loader will be 1953 appended to the default kernel command string. 1954 1955config CMDLINE_FORCE 1956 bool "Always use the default kernel command string" 1957 help 1958 Always use the default kernel command string, even if the boot 1959 loader passes other arguments to the kernel. 1960 This is useful if you cannot or don't want to change the 1961 command-line options your boot loader passes to the kernel. 1962endchoice 1963 1964config XIP_KERNEL 1965 bool "Kernel Execute-In-Place from ROM" 1966 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1967 help 1968 Execute-In-Place allows the kernel to run from non-volatile storage 1969 directly addressable by the CPU, such as NOR flash. This saves RAM 1970 space since the text section of the kernel is not loaded from flash 1971 to RAM. Read-write sections, such as the data section and stack, 1972 are still copied to RAM. The XIP kernel is not compressed since 1973 it has to run directly from flash, so it will take more space to 1974 store it. The flash address used to link the kernel object files, 1975 and for storing it, is configuration dependent. Therefore, if you 1976 say Y here, you must know the proper physical address where to 1977 store the kernel image depending on your own flash memory usage. 1978 1979 Also note that the make target becomes "make xipImage" rather than 1980 "make zImage" or "make Image". The final kernel binary to put in 1981 ROM memory will be arch/arm/boot/xipImage. 1982 1983 If unsure, say N. 1984 1985config XIP_PHYS_ADDR 1986 hex "XIP Kernel Physical Location" 1987 depends on XIP_KERNEL 1988 default "0x00080000" 1989 help 1990 This is the physical address in your flash memory the kernel will 1991 be linked for and stored to. This address is dependent on your 1992 own flash usage. 1993 1994config XIP_DEFLATED_DATA 1995 bool "Store kernel .data section compressed in ROM" 1996 depends on XIP_KERNEL 1997 select ZLIB_INFLATE 1998 help 1999 Before the kernel is actually executed, its .data section has to be 2000 copied to RAM from ROM. This option allows for storing that data 2001 in compressed form and decompressed to RAM rather than merely being 2002 copied, saving some precious ROM space. A possible drawback is a 2003 slightly longer boot delay. 2004 2005config KEXEC 2006 bool "Kexec system call (EXPERIMENTAL)" 2007 depends on (!SMP || PM_SLEEP_SMP) 2008 depends on !CPU_V7M 2009 select KEXEC_CORE 2010 help 2011 kexec is a system call that implements the ability to shutdown your 2012 current kernel, and to start another kernel. It is like a reboot 2013 but it is independent of the system firmware. And like a reboot 2014 you can start any kernel with it, not just Linux. 2015 2016 It is an ongoing process to be certain the hardware in a machine 2017 is properly shutdown, so do not be surprised if this code does not 2018 initially work for you. 2019 2020config ATAGS_PROC 2021 bool "Export atags in procfs" 2022 depends on ATAGS && KEXEC 2023 default y 2024 help 2025 Should the atags used to boot the kernel be exported in an "atags" 2026 file in procfs. Useful with kexec. 2027 2028config CRASH_DUMP 2029 bool "Build kdump crash kernel (EXPERIMENTAL)" 2030 help 2031 Generate crash dump after being started by kexec. This should 2032 be normally only set in special crash dump kernels which are 2033 loaded in the main kernel with kexec-tools into a specially 2034 reserved region and then later executed after a crash by 2035 kdump/kexec. The crash dump kernel must be compiled to a 2036 memory address not used by the main kernel 2037 2038 For more details see Documentation/kdump/kdump.txt 2039 2040config AUTO_ZRELADDR 2041 bool "Auto calculation of the decompressed kernel image address" 2042 help 2043 ZRELADDR is the physical address where the decompressed kernel 2044 image will be placed. If AUTO_ZRELADDR is selected, the address 2045 will be determined at run-time by masking the current IP with 2046 0xf8000000. This assumes the zImage being placed in the first 128MB 2047 from start of memory. 2048 2049config EFI_STUB 2050 bool 2051 2052config EFI 2053 bool "UEFI runtime support" 2054 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 2055 select UCS2_STRING 2056 select EFI_PARAMS_FROM_FDT 2057 select EFI_STUB 2058 select EFI_ARMSTUB 2059 select EFI_RUNTIME_WRAPPERS 2060 ---help--- 2061 This option provides support for runtime services provided 2062 by UEFI firmware (such as non-volatile variables, realtime 2063 clock, and platform reset). A UEFI stub is also provided to 2064 allow the kernel to be booted as an EFI application. This 2065 is only useful for kernels that may run on systems that have 2066 UEFI firmware. 2067 2068config DMI 2069 bool "Enable support for SMBIOS (DMI) tables" 2070 depends on EFI 2071 default y 2072 help 2073 This enables SMBIOS/DMI feature for systems. 2074 2075 This option is only useful on systems that have UEFI firmware. 2076 However, even with this option, the resultant kernel should 2077 continue to boot on existing non-UEFI platforms. 2078 2079 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 2080 i.e., the the practice of identifying the platform via DMI to 2081 decide whether certain workarounds for buggy hardware and/or 2082 firmware need to be enabled. This would require the DMI subsystem 2083 to be enabled much earlier than we do on ARM, which is non-trivial. 2084 2085endmenu 2086 2087menu "CPU Power Management" 2088 2089source "drivers/cpufreq/Kconfig" 2090 2091source "drivers/cpuidle/Kconfig" 2092 2093endmenu 2094 2095menu "Floating point emulation" 2096 2097comment "At least one emulation must be selected" 2098 2099config FPE_NWFPE 2100 bool "NWFPE math emulation" 2101 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 2102 ---help--- 2103 Say Y to include the NWFPE floating point emulator in the kernel. 2104 This is necessary to run most binaries. Linux does not currently 2105 support floating point hardware so you need to say Y here even if 2106 your machine has an FPA or floating point co-processor podule. 2107 2108 You may say N here if you are going to load the Acorn FPEmulator 2109 early in the bootup. 2110 2111config FPE_NWFPE_XP 2112 bool "Support extended precision" 2113 depends on FPE_NWFPE 2114 help 2115 Say Y to include 80-bit support in the kernel floating-point 2116 emulator. Otherwise, only 32 and 64-bit support is compiled in. 2117 Note that gcc does not generate 80-bit operations by default, 2118 so in most cases this option only enlarges the size of the 2119 floating point emulator without any good reason. 2120 2121 You almost surely want to say N here. 2122 2123config FPE_FASTFPE 2124 bool "FastFPE math emulation (EXPERIMENTAL)" 2125 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 2126 ---help--- 2127 Say Y here to include the FAST floating point emulator in the kernel. 2128 This is an experimental much faster emulator which now also has full 2129 precision for the mantissa. It does not support any exceptions. 2130 It is very simple, and approximately 3-6 times faster than NWFPE. 2131 2132 It should be sufficient for most programs. It may be not suitable 2133 for scientific calculations, but you have to check this for yourself. 2134 If you do not feel you need a faster FP emulation you should better 2135 choose NWFPE. 2136 2137config VFP 2138 bool "VFP-format floating point maths" 2139 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 2140 help 2141 Say Y to include VFP support code in the kernel. This is needed 2142 if your hardware includes a VFP unit. 2143 2144 Please see <file:Documentation/arm/VFP/release-notes.txt> for 2145 release notes and additional status information. 2146 2147 Say N if your target does not have VFP hardware. 2148 2149config VFPv3 2150 bool 2151 depends on VFP 2152 default y if CPU_V7 2153 2154config NEON 2155 bool "Advanced SIMD (NEON) Extension support" 2156 depends on VFPv3 && CPU_V7 2157 help 2158 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2159 Extension. 2160 2161config KERNEL_MODE_NEON 2162 bool "Support for NEON in kernel mode" 2163 depends on NEON && AEABI 2164 help 2165 Say Y to include support for NEON in kernel mode. 2166 2167endmenu 2168 2169menu "Power management options" 2170 2171source "kernel/power/Kconfig" 2172 2173config ARCH_SUSPEND_POSSIBLE 2174 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2175 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2176 def_bool y 2177 2178config ARM_CPU_SUSPEND 2179 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2180 depends on ARCH_SUSPEND_POSSIBLE 2181 2182config ARCH_HIBERNATION_POSSIBLE 2183 bool 2184 depends on MMU 2185 default y if ARCH_SUSPEND_POSSIBLE 2186 2187endmenu 2188 2189source "drivers/firmware/Kconfig" 2190 2191if CRYPTO 2192source "arch/arm/crypto/Kconfig" 2193endif 2194 2195source "arch/arm/kvm/Kconfig" 2196
