1# SPDX-License-Identifier: GPL-2.0 2config ARM 3 bool 4 default y 5 select ARCH_32BIT_OFF_T 6 select ARCH_HAS_BINFMT_FLAT 7 select ARCH_HAS_DEBUG_VIRTUAL if MMU 8 select ARCH_HAS_DEVMEM_IS_ALLOWED 9 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE 10 select ARCH_HAS_ELF_RANDOMIZE 11 select ARCH_HAS_FORTIFY_SOURCE 12 select ARCH_HAS_KEEPINITRD 13 select ARCH_HAS_KCOV 14 select ARCH_HAS_MEMBARRIER_SYNC_CORE 15 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE 16 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE 17 select ARCH_HAS_PHYS_TO_DMA 18 select ARCH_HAS_SETUP_DMA_OPS 19 select ARCH_HAS_SET_MEMORY 20 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL 21 select ARCH_HAS_STRICT_MODULE_RWX if MMU 22 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB 23 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB 24 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU 25 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST 26 select ARCH_HAVE_CUSTOM_GPIO_H 27 select ARCH_HAS_GCOV_PROFILE_ALL 28 select ARCH_KEEP_MEMBLOCK if HAVE_ARCH_PFN_VALID || KEXEC 29 select ARCH_MIGHT_HAVE_PC_PARPORT 30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN 31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX 32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7 33 select ARCH_SUPPORTS_ATOMIC_RMW 34 select ARCH_USE_BUILTIN_BSWAP 35 select ARCH_USE_CMPXCHG_LOCKREF 36 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU 37 select ARCH_WANT_IPC_PARSE_VERSION 38 select ARCH_WANT_LD_ORPHAN_WARN 39 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK 40 select BUILDTIME_TABLE_SORT if MMU 41 select CLONE_BACKWARDS 42 select CPU_PM if SUSPEND || CPU_IDLE 43 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS 44 select DMA_DECLARE_COHERENT 45 select DMA_OPS 46 select DMA_REMAP if MMU 47 select EDAC_SUPPORT 48 select EDAC_ATOMIC_SCRUB 49 select GENERIC_ALLOCATOR 50 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY 51 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI 52 select GENERIC_CLOCKEVENTS_BROADCAST if SMP 53 select GENERIC_IRQ_IPI if SMP 54 select GENERIC_CPU_AUTOPROBE 55 select GENERIC_EARLY_IOREMAP 56 select GENERIC_IDLE_POLL_SETUP 57 select GENERIC_IRQ_PROBE 58 select GENERIC_IRQ_SHOW 59 select GENERIC_IRQ_SHOW_LEVEL 60 select GENERIC_PCI_IOMAP 61 select GENERIC_SCHED_CLOCK 62 select GENERIC_SMP_IDLE_THREAD 63 select GENERIC_STRNCPY_FROM_USER 64 select GENERIC_STRNLEN_USER 65 select HANDLE_DOMAIN_IRQ 66 select HARDIRQS_SW_RESEND 67 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT 68 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 69 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 70 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU 71 select HAVE_ARCH_MMAP_RND_BITS if MMU 72 select HAVE_ARCH_SECCOMP 73 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT 74 select HAVE_ARCH_THREAD_STRUCT_WHITELIST 75 select HAVE_ARCH_TRACEHOOK 76 select HAVE_ARM_SMCCC if CPU_V7 77 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32 78 select HAVE_CONTEXT_TRACKING 79 select HAVE_C_RECORDMCOUNT 80 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL 81 select HAVE_DMA_CONTIGUOUS if MMU 82 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU 83 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE 84 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU 85 select HAVE_EXIT_THREAD 86 select HAVE_FAST_GUP if ARM_LPAE 87 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL 88 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG 89 select HAVE_FUNCTION_TRACER if !XIP_KERNEL 90 select HAVE_GCC_PLUGINS 91 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7) 92 select HAVE_IDE if PCI || ISA || PCMCIA 93 select HAVE_IRQ_TIME_ACCOUNTING 94 select HAVE_KERNEL_GZIP 95 select HAVE_KERNEL_LZ4 96 select HAVE_KERNEL_LZMA 97 select HAVE_KERNEL_LZO 98 select HAVE_KERNEL_XZ 99 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M 100 select HAVE_KRETPROBES if HAVE_KPROBES 101 select HAVE_MOD_ARCH_SPECIFIC 102 select HAVE_NMI 103 select HAVE_OPROFILE if HAVE_PERF_EVENTS 104 select HAVE_OPTPROBES if !THUMB2_KERNEL 105 select HAVE_PERF_EVENTS 106 select HAVE_PERF_REGS 107 select HAVE_PERF_USER_STACK_DUMP 108 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE 109 select HAVE_REGS_AND_STACK_ACCESS_API 110 select HAVE_RSEQ 111 select HAVE_STACKPROTECTOR 112 select HAVE_SYSCALL_TRACEPOINTS 113 select HAVE_UID16 114 select HAVE_VIRT_CPU_ACCOUNTING_GEN 115 select IRQ_FORCED_THREADING 116 select MODULES_USE_ELF_REL 117 select NEED_DMA_MAP_STATE 118 select OF_EARLY_FLATTREE if OF 119 select OLD_SIGACTION 120 select OLD_SIGSUSPEND3 121 select PCI_SYSCALL if PCI 122 select PERF_USE_VMALLOC 123 select RTC_LIB 124 select SET_FS 125 select SYS_SUPPORTS_APM_EMULATION 126 # Above selects are sorted alphabetically; please add new ones 127 # according to that. Thanks. 128 help 129 The ARM series is a line of low-power-consumption RISC chip designs 130 licensed by ARM Ltd and targeted at embedded applications and 131 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer 132 manufactured, but legacy ARM-based PC hardware remains popular in 133 Europe. There is an ARM Linux project with a web page at 134 <http://www.arm.linux.org.uk/>. 135 136config ARM_HAS_SG_CHAIN 137 bool 138 139config ARM_DMA_USE_IOMMU 140 bool 141 select ARM_HAS_SG_CHAIN 142 select NEED_SG_DMA_LENGTH 143 144if ARM_DMA_USE_IOMMU 145 146config ARM_DMA_IOMMU_ALIGNMENT 147 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers" 148 range 4 9 149 default 8 150 help 151 DMA mapping framework by default aligns all buffers to the smallest 152 PAGE_SIZE order which is greater than or equal to the requested buffer 153 size. This works well for buffers up to a few hundreds kilobytes, but 154 for larger buffers it just a waste of address space. Drivers which has 155 relatively small addressing window (like 64Mib) might run out of 156 virtual space with just a few allocations. 157 158 With this parameter you can specify the maximum PAGE_SIZE order for 159 DMA IOMMU buffers. Larger buffers will be aligned only to this 160 specified order. The order is expressed as a power of two multiplied 161 by the PAGE_SIZE. 162 163endif 164 165config SYS_SUPPORTS_APM_EMULATION 166 bool 167 168config HAVE_TCM 169 bool 170 select GENERIC_ALLOCATOR 171 172config HAVE_PROC_CPU 173 bool 174 175config NO_IOPORT_MAP 176 bool 177 178config SBUS 179 bool 180 181config STACKTRACE_SUPPORT 182 bool 183 default y 184 185config LOCKDEP_SUPPORT 186 bool 187 default y 188 189config TRACE_IRQFLAGS_SUPPORT 190 bool 191 default !CPU_V7M 192 193config ARCH_HAS_ILOG2_U32 194 bool 195 196config ARCH_HAS_ILOG2_U64 197 bool 198 199config ARCH_HAS_BANDGAP 200 bool 201 202config FIX_EARLYCON_MEM 203 def_bool y if MMU 204 205config GENERIC_HWEIGHT 206 bool 207 default y 208 209config GENERIC_CALIBRATE_DELAY 210 bool 211 default y 212 213config ARCH_MAY_HAVE_PC_FDC 214 bool 215 216config ZONE_DMA 217 bool 218 219config ARCH_SUPPORTS_UPROBES 220 def_bool y 221 222config ARCH_HAS_DMA_SET_COHERENT_MASK 223 bool 224 225config GENERIC_ISA_DMA 226 bool 227 228config FIQ 229 bool 230 231config NEED_RET_TO_USER 232 bool 233 234config ARCH_MTD_XIP 235 bool 236 237config ARM_PATCH_PHYS_VIRT 238 bool "Patch physical to virtual translations at runtime" if EMBEDDED 239 default y 240 depends on !XIP_KERNEL && MMU 241 help 242 Patch phys-to-virt and virt-to-phys translation functions at 243 boot and module load time according to the position of the 244 kernel in system memory. 245 246 This can only be used with non-XIP MMU kernels where the base 247 of physical memory is at a 16MB boundary. 248 249 Only disable this option if you know that you do not require 250 this feature (eg, building a kernel for a single machine) and 251 you need to shrink the kernel to the minimal size. 252 253config NEED_MACH_IO_H 254 bool 255 help 256 Select this when mach/io.h is required to provide special 257 definitions for this platform. The need for mach/io.h should 258 be avoided when possible. 259 260config NEED_MACH_MEMORY_H 261 bool 262 help 263 Select this when mach/memory.h is required to provide special 264 definitions for this platform. The need for mach/memory.h should 265 be avoided when possible. 266 267config PHYS_OFFSET 268 hex "Physical address of main memory" if MMU 269 depends on !ARM_PATCH_PHYS_VIRT 270 default DRAM_BASE if !MMU 271 default 0x00000000 if ARCH_EBSA110 || \ 272 ARCH_FOOTBRIDGE 273 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC 274 default 0x20000000 if ARCH_S5PV210 275 default 0xc0000000 if ARCH_SA1100 276 help 277 Please provide the physical address corresponding to the 278 location of main memory in your system. 279 280config GENERIC_BUG 281 def_bool y 282 depends on BUG 283 284config PGTABLE_LEVELS 285 int 286 default 3 if ARM_LPAE 287 default 2 288 289menu "System Type" 290 291config MMU 292 bool "MMU-based Paged Memory Management Support" 293 default y 294 help 295 Select if you want MMU-based virtualised addressing space 296 support by paged memory management. If unsure, say 'Y'. 297 298config ARCH_MMAP_RND_BITS_MIN 299 default 8 300 301config ARCH_MMAP_RND_BITS_MAX 302 default 14 if PAGE_OFFSET=0x40000000 303 default 15 if PAGE_OFFSET=0x80000000 304 default 16 305 306# 307# The "ARM system type" choice list is ordered alphabetically by option 308# text. Please add new entries in the option alphabetic order. 309# 310choice 311 prompt "ARM system type" 312 default ARM_SINGLE_ARMV7M if !MMU 313 default ARCH_MULTIPLATFORM if MMU 314 315config ARCH_MULTIPLATFORM 316 bool "Allow multiple platforms to be selected" 317 depends on MMU 318 select ARCH_FLATMEM_ENABLE 319 select ARCH_SPARSEMEM_ENABLE 320 select ARCH_SELECT_MEMORY_MODEL 321 select ARM_HAS_SG_CHAIN 322 select ARM_PATCH_PHYS_VIRT 323 select AUTO_ZRELADDR 324 select TIMER_OF 325 select COMMON_CLK 326 select GENERIC_CLOCKEVENTS 327 select GENERIC_IRQ_MULTI_HANDLER 328 select HAVE_PCI 329 select PCI_DOMAINS_GENERIC if PCI 330 select SPARSE_IRQ 331 select USE_OF 332 333config ARM_SINGLE_ARMV7M 334 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)" 335 depends on !MMU 336 select ARM_NVIC 337 select AUTO_ZRELADDR 338 select TIMER_OF 339 select COMMON_CLK 340 select CPU_V7M 341 select GENERIC_CLOCKEVENTS 342 select NO_IOPORT_MAP 343 select SPARSE_IRQ 344 select USE_OF 345 346config ARCH_EBSA110 347 bool "EBSA-110" 348 select ARCH_USES_GETTIMEOFFSET 349 select CPU_SA110 350 select ISA 351 select NEED_MACH_IO_H 352 select NEED_MACH_MEMORY_H 353 select NO_IOPORT_MAP 354 help 355 This is an evaluation board for the StrongARM processor available 356 from Digital. It has limited hardware on-board, including an 357 Ethernet interface, two PCMCIA sockets, two serial ports and a 358 parallel port. 359 360config ARCH_EP93XX 361 bool "EP93xx-based" 362 select ARCH_SPARSEMEM_ENABLE 363 select ARM_AMBA 364 imply ARM_PATCH_PHYS_VIRT 365 select ARM_VIC 366 select AUTO_ZRELADDR 367 select CLKDEV_LOOKUP 368 select CLKSRC_MMIO 369 select CPU_ARM920T 370 select GENERIC_CLOCKEVENTS 371 select GPIOLIB 372 select HAVE_LEGACY_CLK 373 help 374 This enables support for the Cirrus EP93xx series of CPUs. 375 376config ARCH_FOOTBRIDGE 377 bool "FootBridge" 378 select CPU_SA110 379 select FOOTBRIDGE 380 select GENERIC_CLOCKEVENTS 381 select HAVE_IDE 382 select NEED_MACH_IO_H if !MMU 383 select NEED_MACH_MEMORY_H 384 help 385 Support for systems based on the DC21285 companion chip 386 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 387 388config ARCH_IOP32X 389 bool "IOP32x-based" 390 depends on MMU 391 select CPU_XSCALE 392 select GPIO_IOP 393 select GPIOLIB 394 select NEED_RET_TO_USER 395 select FORCE_PCI 396 select PLAT_IOP 397 help 398 Support for Intel's 80219 and IOP32X (XScale) family of 399 processors. 400 401config ARCH_IXP4XX 402 bool "IXP4xx-based" 403 depends on MMU 404 select ARCH_HAS_DMA_SET_COHERENT_MASK 405 select ARCH_SUPPORTS_BIG_ENDIAN 406 select CPU_XSCALE 407 select DMABOUNCE if PCI 408 select GENERIC_CLOCKEVENTS 409 select GENERIC_IRQ_MULTI_HANDLER 410 select GPIO_IXP4XX 411 select GPIOLIB 412 select HAVE_PCI 413 select IXP4XX_IRQ 414 select IXP4XX_TIMER 415 select NEED_MACH_IO_H 416 select USB_EHCI_BIG_ENDIAN_DESC 417 select USB_EHCI_BIG_ENDIAN_MMIO 418 help 419 Support for Intel's IXP4XX (XScale) family of processors. 420 421config ARCH_DOVE 422 bool "Marvell Dove" 423 select CPU_PJ4 424 select GENERIC_CLOCKEVENTS 425 select GENERIC_IRQ_MULTI_HANDLER 426 select GPIOLIB 427 select HAVE_PCI 428 select MVEBU_MBUS 429 select PINCTRL 430 select PINCTRL_DOVE 431 select PLAT_ORION_LEGACY 432 select SPARSE_IRQ 433 select PM_GENERIC_DOMAINS if PM 434 help 435 Support for the Marvell Dove SoC 88AP510 436 437config ARCH_PXA 438 bool "PXA2xx/PXA3xx-based" 439 depends on MMU 440 select ARCH_MTD_XIP 441 select ARM_CPU_SUSPEND if PM 442 select AUTO_ZRELADDR 443 select COMMON_CLK 444 select CLKSRC_PXA 445 select CLKSRC_MMIO 446 select TIMER_OF 447 select CPU_XSCALE if !CPU_XSC3 448 select GENERIC_CLOCKEVENTS 449 select GENERIC_IRQ_MULTI_HANDLER 450 select GPIO_PXA 451 select GPIOLIB 452 select HAVE_IDE 453 select IRQ_DOMAIN 454 select PLAT_PXA 455 select SPARSE_IRQ 456 help 457 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 458 459config ARCH_RPC 460 bool "RiscPC" 461 depends on MMU 462 select ARCH_ACORN 463 select ARCH_MAY_HAVE_PC_FDC 464 select ARCH_SPARSEMEM_ENABLE 465 select ARM_HAS_SG_CHAIN 466 select CPU_SA110 467 select FIQ 468 select HAVE_IDE 469 select HAVE_PATA_PLATFORM 470 select ISA_DMA_API 471 select NEED_MACH_IO_H 472 select NEED_MACH_MEMORY_H 473 select NO_IOPORT_MAP 474 help 475 On the Acorn Risc-PC, Linux can support the internal IDE disk and 476 CD-ROM interface, serial and parallel port, and the floppy drive. 477 478config ARCH_SA1100 479 bool "SA1100-based" 480 select ARCH_MTD_XIP 481 select ARCH_SPARSEMEM_ENABLE 482 select CLKSRC_MMIO 483 select CLKSRC_PXA 484 select TIMER_OF if OF 485 select COMMON_CLK 486 select CPU_FREQ 487 select CPU_SA1100 488 select GENERIC_CLOCKEVENTS 489 select GENERIC_IRQ_MULTI_HANDLER 490 select GPIOLIB 491 select HAVE_IDE 492 select IRQ_DOMAIN 493 select ISA 494 select NEED_MACH_MEMORY_H 495 select SPARSE_IRQ 496 help 497 Support for StrongARM 11x0 based boards. 498 499config ARCH_S3C24XX 500 bool "Samsung S3C24XX SoCs" 501 select ATAGS 502 select CLKSRC_SAMSUNG_PWM 503 select GENERIC_CLOCKEVENTS 504 select GPIO_SAMSUNG 505 select GPIOLIB 506 select GENERIC_IRQ_MULTI_HANDLER 507 select HAVE_S3C2410_I2C if I2C 508 select HAVE_S3C_RTC if RTC_CLASS 509 select NEED_MACH_IO_H 510 select S3C2410_WATCHDOG 511 select SAMSUNG_ATAGS 512 select USE_OF 513 select WATCHDOG 514 help 515 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 516 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST 517 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the 518 Samsung SMDK2410 development board (and derivatives). 519 520config ARCH_OMAP1 521 bool "TI OMAP1" 522 depends on MMU 523 select ARCH_HAS_HOLES_MEMORYMODEL 524 select ARCH_OMAP 525 select CLKDEV_LOOKUP 526 select CLKSRC_MMIO 527 select GENERIC_CLOCKEVENTS 528 select GENERIC_IRQ_CHIP 529 select GENERIC_IRQ_MULTI_HANDLER 530 select GPIOLIB 531 select HAVE_IDE 532 select HAVE_LEGACY_CLK 533 select IRQ_DOMAIN 534 select NEED_MACH_IO_H if PCCARD 535 select NEED_MACH_MEMORY_H 536 select SPARSE_IRQ 537 help 538 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx) 539 540endchoice 541 542menu "Multiple platform selection" 543 depends on ARCH_MULTIPLATFORM 544 545comment "CPU Core family selection" 546 547config ARCH_MULTI_V4 548 bool "ARMv4 based platforms (FA526)" 549 depends on !ARCH_MULTI_V6_V7 550 select ARCH_MULTI_V4_V5 551 select CPU_FA526 552 553config ARCH_MULTI_V4T 554 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" 555 depends on !ARCH_MULTI_V6_V7 556 select ARCH_MULTI_V4_V5 557 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ 558 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ 559 CPU_ARM925T || CPU_ARM940T) 560 561config ARCH_MULTI_V5 562 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)" 563 depends on !ARCH_MULTI_V6_V7 564 select ARCH_MULTI_V4_V5 565 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \ 566 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \ 567 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON) 568 569config ARCH_MULTI_V4_V5 570 bool 571 572config ARCH_MULTI_V6 573 bool "ARMv6 based platforms (ARM11)" 574 select ARCH_MULTI_V6_V7 575 select CPU_V6K 576 577config ARCH_MULTI_V7 578 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" 579 default y 580 select ARCH_MULTI_V6_V7 581 select CPU_V7 582 select HAVE_SMP 583 584config ARCH_MULTI_V6_V7 585 bool 586 select MIGHT_HAVE_CACHE_L2X0 587 588config ARCH_MULTI_CPU_AUTO 589 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7) 590 select ARCH_MULTI_V5 591 592endmenu 593 594config ARCH_VIRT 595 bool "Dummy Virtual Machine" 596 depends on ARCH_MULTI_V7 597 select ARM_AMBA 598 select ARM_GIC 599 select ARM_GIC_V2M if PCI 600 select ARM_GIC_V3 601 select ARM_GIC_V3_ITS if PCI 602 select ARM_PSCI 603 select HAVE_ARM_ARCH_TIMER 604 select ARCH_SUPPORTS_BIG_ENDIAN 605 606# 607# This is sorted alphabetically by mach-* pathname. However, plat-* 608# Kconfigs may be included either alphabetically (according to the 609# plat- suffix) or along side the corresponding mach-* source. 610# 611source "arch/arm/mach-actions/Kconfig" 612 613source "arch/arm/mach-alpine/Kconfig" 614 615source "arch/arm/mach-artpec/Kconfig" 616 617source "arch/arm/mach-asm9260/Kconfig" 618 619source "arch/arm/mach-aspeed/Kconfig" 620 621source "arch/arm/mach-at91/Kconfig" 622 623source "arch/arm/mach-axxia/Kconfig" 624 625source "arch/arm/mach-bcm/Kconfig" 626 627source "arch/arm/mach-berlin/Kconfig" 628 629source "arch/arm/mach-clps711x/Kconfig" 630 631source "arch/arm/mach-cns3xxx/Kconfig" 632 633source "arch/arm/mach-davinci/Kconfig" 634 635source "arch/arm/mach-digicolor/Kconfig" 636 637source "arch/arm/mach-dove/Kconfig" 638 639source "arch/arm/mach-ep93xx/Kconfig" 640 641source "arch/arm/mach-exynos/Kconfig" 642 643source "arch/arm/mach-footbridge/Kconfig" 644 645source "arch/arm/mach-gemini/Kconfig" 646 647source "arch/arm/mach-highbank/Kconfig" 648 649source "arch/arm/mach-hisi/Kconfig" 650 651source "arch/arm/mach-imx/Kconfig" 652 653source "arch/arm/mach-integrator/Kconfig" 654 655source "arch/arm/mach-iop32x/Kconfig" 656 657source "arch/arm/mach-ixp4xx/Kconfig" 658 659source "arch/arm/mach-keystone/Kconfig" 660 661source "arch/arm/mach-lpc32xx/Kconfig" 662 663source "arch/arm/mach-mediatek/Kconfig" 664 665source "arch/arm/mach-meson/Kconfig" 666 667source "arch/arm/mach-milbeaut/Kconfig" 668 669source "arch/arm/mach-mmp/Kconfig" 670 671source "arch/arm/mach-moxart/Kconfig" 672 673source "arch/arm/mach-mstar/Kconfig" 674 675source "arch/arm/mach-mv78xx0/Kconfig" 676 677source "arch/arm/mach-mvebu/Kconfig" 678 679source "arch/arm/mach-mxs/Kconfig" 680 681source "arch/arm/mach-nomadik/Kconfig" 682 683source "arch/arm/mach-npcm/Kconfig" 684 685source "arch/arm/mach-nspire/Kconfig" 686 687source "arch/arm/plat-omap/Kconfig" 688 689source "arch/arm/mach-omap1/Kconfig" 690 691source "arch/arm/mach-omap2/Kconfig" 692 693source "arch/arm/mach-orion5x/Kconfig" 694 695source "arch/arm/mach-oxnas/Kconfig" 696 697source "arch/arm/mach-picoxcell/Kconfig" 698 699source "arch/arm/mach-prima2/Kconfig" 700 701source "arch/arm/mach-pxa/Kconfig" 702source "arch/arm/plat-pxa/Kconfig" 703 704source "arch/arm/mach-qcom/Kconfig" 705 706source "arch/arm/mach-rda/Kconfig" 707 708source "arch/arm/mach-realtek/Kconfig" 709 710source "arch/arm/mach-realview/Kconfig" 711 712source "arch/arm/mach-rockchip/Kconfig" 713 714source "arch/arm/mach-s3c/Kconfig" 715 716source "arch/arm/mach-s5pv210/Kconfig" 717 718source "arch/arm/mach-sa1100/Kconfig" 719 720source "arch/arm/mach-shmobile/Kconfig" 721 722source "arch/arm/mach-socfpga/Kconfig" 723 724source "arch/arm/mach-spear/Kconfig" 725 726source "arch/arm/mach-sti/Kconfig" 727 728source "arch/arm/mach-stm32/Kconfig" 729 730source "arch/arm/mach-sunxi/Kconfig" 731 732source "arch/arm/mach-tango/Kconfig" 733 734source "arch/arm/mach-tegra/Kconfig" 735 736source "arch/arm/mach-u300/Kconfig" 737 738source "arch/arm/mach-uniphier/Kconfig" 739 740source "arch/arm/mach-ux500/Kconfig" 741 742source "arch/arm/mach-versatile/Kconfig" 743 744source "arch/arm/mach-vexpress/Kconfig" 745 746source "arch/arm/mach-vt8500/Kconfig" 747 748source "arch/arm/mach-zx/Kconfig" 749 750source "arch/arm/mach-zynq/Kconfig" 751 752# ARMv7-M architecture 753config ARCH_EFM32 754 bool "Energy Micro efm32" 755 depends on ARM_SINGLE_ARMV7M 756 select GPIOLIB 757 help 758 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko 759 processors. 760 761config ARCH_LPC18XX 762 bool "NXP LPC18xx/LPC43xx" 763 depends on ARM_SINGLE_ARMV7M 764 select ARCH_HAS_RESET_CONTROLLER 765 select ARM_AMBA 766 select CLKSRC_LPC32XX 767 select PINCTRL 768 help 769 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4 770 high performance microcontrollers. 771 772config ARCH_MPS2 773 bool "ARM MPS2 platform" 774 depends on ARM_SINGLE_ARMV7M 775 select ARM_AMBA 776 select CLKSRC_MPS2 777 help 778 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes 779 with a range of available cores like Cortex-M3/M4/M7. 780 781 Please, note that depends which Application Note is used memory map 782 for the platform may vary, so adjustment of RAM base might be needed. 783 784# Definitions to make life easier 785config ARCH_ACORN 786 bool 787 788config PLAT_IOP 789 bool 790 select GENERIC_CLOCKEVENTS 791 792config PLAT_ORION 793 bool 794 select CLKSRC_MMIO 795 select COMMON_CLK 796 select GENERIC_IRQ_CHIP 797 select IRQ_DOMAIN 798 799config PLAT_ORION_LEGACY 800 bool 801 select PLAT_ORION 802 803config PLAT_PXA 804 bool 805 806config PLAT_VERSATILE 807 bool 808 809source "arch/arm/mm/Kconfig" 810 811config IWMMXT 812 bool "Enable iWMMXt support" 813 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B 814 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B 815 help 816 Enable support for iWMMXt context switching at run time if 817 running on a CPU that supports it. 818 819if !MMU 820source "arch/arm/Kconfig-nommu" 821endif 822 823config PJ4B_ERRATA_4742 824 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation" 825 depends on CPU_PJ4B && MACH_ARMADA_370 826 default y 827 help 828 When coming out of either a Wait for Interrupt (WFI) or a Wait for 829 Event (WFE) IDLE states, a specific timing sensitivity exists between 830 the retiring WFI/WFE instructions and the newly issued subsequent 831 instructions. This sensitivity can result in a CPU hang scenario. 832 Workaround: 833 The software must insert either a Data Synchronization Barrier (DSB) 834 or Data Memory Barrier (DMB) command immediately after the WFI/WFE 835 instruction 836 837config ARM_ERRATA_326103 838 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" 839 depends on CPU_V6 840 help 841 Executing a SWP instruction to read-only memory does not set bit 11 842 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to 843 treat the access as a read, preventing a COW from occurring and 844 causing the faulting task to livelock. 845 846config ARM_ERRATA_411920 847 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" 848 depends on CPU_V6 || CPU_V6K 849 help 850 Invalidation of the Instruction Cache operation can 851 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176. 852 It does not affect the MPCore. This option enables the ARM Ltd. 853 recommended workaround. 854 855config ARM_ERRATA_430973 856 bool "ARM errata: Stale prediction on replaced interworking branch" 857 depends on CPU_V7 858 help 859 This option enables the workaround for the 430973 Cortex-A8 860 r1p* erratum. If a code sequence containing an ARM/Thumb 861 interworking branch is replaced with another code sequence at the 862 same virtual address, whether due to self-modifying code or virtual 863 to physical address re-mapping, Cortex-A8 does not recover from the 864 stale interworking branch prediction. This results in Cortex-A8 865 executing the new code sequence in the incorrect ARM or Thumb state. 866 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE 867 and also flushes the branch target cache at every context switch. 868 Note that setting specific bits in the ACTLR register may not be 869 available in non-secure mode. 870 871config ARM_ERRATA_458693 872 bool "ARM errata: Processor deadlock when a false hazard is created" 873 depends on CPU_V7 874 depends on !ARCH_MULTIPLATFORM 875 help 876 This option enables the workaround for the 458693 Cortex-A8 (r2p0) 877 erratum. For very specific sequences of memory operations, it is 878 possible for a hazard condition intended for a cache line to instead 879 be incorrectly associated with a different cache line. This false 880 hazard might then cause a processor deadlock. The workaround enables 881 the L1 caching of the NEON accesses and disables the PLD instruction 882 in the ACTLR register. Note that setting specific bits in the ACTLR 883 register may not be available in non-secure mode. 884 885config ARM_ERRATA_460075 886 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" 887 depends on CPU_V7 888 depends on !ARCH_MULTIPLATFORM 889 help 890 This option enables the workaround for the 460075 Cortex-A8 (r2p0) 891 erratum. Any asynchronous access to the L2 cache may encounter a 892 situation in which recent store transactions to the L2 cache are lost 893 and overwritten with stale memory contents from external memory. The 894 workaround disables the write-allocate mode for the L2 cache via the 895 ACTLR register. Note that setting specific bits in the ACTLR register 896 may not be available in non-secure mode. 897 898config ARM_ERRATA_742230 899 bool "ARM errata: DMB operation may be faulty" 900 depends on CPU_V7 && SMP 901 depends on !ARCH_MULTIPLATFORM 902 help 903 This option enables the workaround for the 742230 Cortex-A9 904 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction 905 between two write operations may not ensure the correct visibility 906 ordering of the two writes. This workaround sets a specific bit in 907 the diagnostic register of the Cortex-A9 which causes the DMB 908 instruction to behave as a DSB, ensuring the correct behaviour of 909 the two writes. 910 911config ARM_ERRATA_742231 912 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" 913 depends on CPU_V7 && SMP 914 depends on !ARCH_MULTIPLATFORM 915 help 916 This option enables the workaround for the 742231 Cortex-A9 917 (r2p0..r2p2) erratum. Under certain conditions, specific to the 918 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode, 919 accessing some data located in the same cache line, may get corrupted 920 data due to bad handling of the address hazard when the line gets 921 replaced from one of the CPUs at the same time as another CPU is 922 accessing it. This workaround sets specific bits in the diagnostic 923 register of the Cortex-A9 which reduces the linefill issuing 924 capabilities of the processor. 925 926config ARM_ERRATA_643719 927 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" 928 depends on CPU_V7 && SMP 929 default y 930 help 931 This option enables the workaround for the 643719 Cortex-A9 (prior to 932 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR 933 register returns zero when it should return one. The workaround 934 corrects this value, ensuring cache maintenance operations which use 935 it behave as intended and avoiding data corruption. 936 937config ARM_ERRATA_720789 938 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID" 939 depends on CPU_V7 940 help 941 This option enables the workaround for the 720789 Cortex-A9 (prior to 942 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the 943 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS. 944 As a consequence of this erratum, some TLB entries which should be 945 invalidated are not, resulting in an incoherency in the system page 946 tables. The workaround changes the TLB flushing routines to invalidate 947 entries regardless of the ASID. 948 949config ARM_ERRATA_743622 950 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption" 951 depends on CPU_V7 952 depends on !ARCH_MULTIPLATFORM 953 help 954 This option enables the workaround for the 743622 Cortex-A9 955 (r2p*) erratum. Under very rare conditions, a faulty 956 optimisation in the Cortex-A9 Store Buffer may lead to data 957 corruption. This workaround sets a specific bit in the diagnostic 958 register of the Cortex-A9 which disables the Store Buffer 959 optimisation, preventing the defect from occurring. This has no 960 visible impact on the overall performance or power consumption of the 961 processor. 962 963config ARM_ERRATA_751472 964 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" 965 depends on CPU_V7 966 depends on !ARCH_MULTIPLATFORM 967 help 968 This option enables the workaround for the 751472 Cortex-A9 (prior 969 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the 970 completion of a following broadcasted operation if the second 971 operation is received by a CPU before the ICIALLUIS has completed, 972 potentially leading to corrupted entries in the cache or TLB. 973 974config ARM_ERRATA_754322 975 bool "ARM errata: possible faulty MMU translations following an ASID switch" 976 depends on CPU_V7 977 help 978 This option enables the workaround for the 754322 Cortex-A9 (r2p*, 979 r3p*) erratum. A speculative memory access may cause a page table walk 980 which starts prior to an ASID switch but completes afterwards. This 981 can populate the micro-TLB with a stale entry which may be hit with 982 the new ASID. This workaround places two dsb instructions in the mm 983 switching code so that no page table walks can cross the ASID switch. 984 985config ARM_ERRATA_754327 986 bool "ARM errata: no automatic Store Buffer drain" 987 depends on CPU_V7 && SMP 988 help 989 This option enables the workaround for the 754327 Cortex-A9 (prior to 990 r2p0) erratum. The Store Buffer does not have any automatic draining 991 mechanism and therefore a livelock may occur if an external agent 992 continuously polls a memory location waiting to observe an update. 993 This workaround defines cpu_relax() as smp_mb(), preventing correctly 994 written polling loops from denying visibility of updates to memory. 995 996config ARM_ERRATA_364296 997 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled" 998 depends on CPU_V6 999 help 1000 This options enables the workaround for the 364296 ARM1136 1001 r0p2 erratum (possible cache data corruption with 1002 hit-under-miss enabled). It sets the undocumented bit 31 in 1003 the auxiliary control register and the FI bit in the control 1004 register, thus disabling hit-under-miss without putting the 1005 processor into full low interrupt latency mode. ARM11MPCore 1006 is not affected. 1007 1008config ARM_ERRATA_764369 1009 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed" 1010 depends on CPU_V7 && SMP 1011 help 1012 This option enables the workaround for erratum 764369 1013 affecting Cortex-A9 MPCore with two or more processors (all 1014 current revisions). Under certain timing circumstances, a data 1015 cache line maintenance operation by MVA targeting an Inner 1016 Shareable memory region may fail to proceed up to either the 1017 Point of Coherency or to the Point of Unification of the 1018 system. This workaround adds a DSB instruction before the 1019 relevant cache maintenance functions and sets a specific bit 1020 in the diagnostic control register of the SCU. 1021 1022config ARM_ERRATA_775420 1023 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock" 1024 depends on CPU_V7 1025 help 1026 This option enables the workaround for the 775420 Cortex-A9 (r2p2, 1027 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance 1028 operation aborts with MMU exception, it might cause the processor 1029 to deadlock. This workaround puts DSB before executing ISB if 1030 an abort may occur on cache maintenance. 1031 1032config ARM_ERRATA_798181 1033 bool "ARM errata: TLBI/DSB failure on Cortex-A15" 1034 depends on CPU_V7 && SMP 1035 help 1036 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not 1037 adequately shooting down all use of the old entries. This 1038 option enables the Linux kernel workaround for this erratum 1039 which sends an IPI to the CPUs that are running the same ASID 1040 as the one being invalidated. 1041 1042config ARM_ERRATA_773022 1043 bool "ARM errata: incorrect instructions may be executed from loop buffer" 1044 depends on CPU_V7 1045 help 1046 This option enables the workaround for the 773022 Cortex-A15 1047 (up to r0p4) erratum. In certain rare sequences of code, the 1048 loop buffer may deliver incorrect instructions. This 1049 workaround disables the loop buffer to avoid the erratum. 1050 1051config ARM_ERRATA_818325_852422 1052 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption" 1053 depends on CPU_V7 1054 help 1055 This option enables the workaround for: 1056 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM 1057 instruction might deadlock. Fixed in r0p1. 1058 - Cortex-A12 852422: Execution of a sequence of instructions might 1059 lead to either a data corruption or a CPU deadlock. Not fixed in 1060 any Cortex-A12 cores yet. 1061 This workaround for all both errata involves setting bit[12] of the 1062 Feature Register. This bit disables an optimisation applied to a 1063 sequence of 2 instructions that use opposing condition codes. 1064 1065config ARM_ERRATA_821420 1066 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock" 1067 depends on CPU_V7 1068 help 1069 This option enables the workaround for the 821420 Cortex-A12 1070 (all revs) erratum. In very rare timing conditions, a sequence 1071 of VMOV to Core registers instructions, for which the second 1072 one is in the shadow of a branch or abort, can lead to a 1073 deadlock when the VMOV instructions are issued out-of-order. 1074 1075config ARM_ERRATA_825619 1076 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock" 1077 depends on CPU_V7 1078 help 1079 This option enables the workaround for the 825619 Cortex-A12 1080 (all revs) erratum. Within rare timing constraints, executing a 1081 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable 1082 and Device/Strongly-Ordered loads and stores might cause deadlock 1083 1084config ARM_ERRATA_857271 1085 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions" 1086 depends on CPU_V7 1087 help 1088 This option enables the workaround for the 857271 Cortex-A12 1089 (all revs) erratum. Under very rare timing conditions, the CPU might 1090 hang. The workaround is expected to have a < 1% performance impact. 1091 1092config ARM_ERRATA_852421 1093 bool "ARM errata: A17: DMB ST might fail to create order between stores" 1094 depends on CPU_V7 1095 help 1096 This option enables the workaround for the 852421 Cortex-A17 1097 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions, 1098 execution of a DMB ST instruction might fail to properly order 1099 stores from GroupA and stores from GroupB. 1100 1101config ARM_ERRATA_852423 1102 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption" 1103 depends on CPU_V7 1104 help 1105 This option enables the workaround for: 1106 - Cortex-A17 852423: Execution of a sequence of instructions might 1107 lead to either a data corruption or a CPU deadlock. Not fixed in 1108 any Cortex-A17 cores yet. 1109 This is identical to Cortex-A12 erratum 852422. It is a separate 1110 config option from the A12 erratum due to the way errata are checked 1111 for and handled. 1112 1113config ARM_ERRATA_857272 1114 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions" 1115 depends on CPU_V7 1116 help 1117 This option enables the workaround for the 857272 Cortex-A17 erratum. 1118 This erratum is not known to be fixed in any A17 revision. 1119 This is identical to Cortex-A12 erratum 857271. It is a separate 1120 config option from the A12 erratum due to the way errata are checked 1121 for and handled. 1122 1123endmenu 1124 1125source "arch/arm/common/Kconfig" 1126 1127menu "Bus support" 1128 1129config ISA 1130 bool 1131 help 1132 Find out whether you have ISA slots on your motherboard. ISA is the 1133 name of a bus system, i.e. the way the CPU talks to the other stuff 1134 inside your box. Other bus systems are PCI, EISA, MicroChannel 1135 (MCA) or VESA. ISA is an older system, now being displaced by PCI; 1136 newer boards don't support it. If you have ISA, say Y, otherwise N. 1137 1138# Select ISA DMA controller support 1139config ISA_DMA 1140 bool 1141 select ISA_DMA_API 1142 1143# Select ISA DMA interface 1144config ISA_DMA_API 1145 bool 1146 1147config PCI_NANOENGINE 1148 bool "BSE nanoEngine PCI support" 1149 depends on SA1100_NANOENGINE 1150 help 1151 Enable PCI on the BSE nanoEngine board. 1152 1153config ARM_ERRATA_814220 1154 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" 1155 depends on CPU_V7 1156 help 1157 The v7 ARM states that all cache and branch predictor maintenance 1158 operations that do not specify an address execute, relative to 1159 each other, in program order. 1160 However, because of this erratum, an L2 set/way cache maintenance 1161 operation can overtake an L1 set/way cache maintenance operation. 1162 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3, 1163 r0p4, r0p5. 1164 1165endmenu 1166 1167menu "Kernel Features" 1168 1169config HAVE_SMP 1170 bool 1171 help 1172 This option should be selected by machines which have an SMP- 1173 capable CPU. 1174 1175 The only effect of this option is to make the SMP-related 1176 options available to the user for configuration. 1177 1178config SMP 1179 bool "Symmetric Multi-Processing" 1180 depends on CPU_V6K || CPU_V7 1181 depends on GENERIC_CLOCKEVENTS 1182 depends on HAVE_SMP 1183 depends on MMU || ARM_MPU 1184 select IRQ_WORK 1185 help 1186 This enables support for systems with more than one CPU. If you have 1187 a system with only one CPU, say N. If you have a system with more 1188 than one CPU, say Y. 1189 1190 If you say N here, the kernel will run on uni- and multiprocessor 1191 machines, but will use only one CPU of a multiprocessor machine. If 1192 you say Y here, the kernel will run on many, but not all, 1193 uniprocessor machines. On a uniprocessor machine, the kernel 1194 will run faster if you say N here. 1195 1196 See also <file:Documentation/x86/i386/IO-APIC.rst>, 1197 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at 1198 <http://tldp.org/HOWTO/SMP-HOWTO.html>. 1199 1200 If you don't know what to do here, say N. 1201 1202config SMP_ON_UP 1203 bool "Allow booting SMP kernel on uniprocessor systems" 1204 depends on SMP && !XIP_KERNEL && MMU 1205 default y 1206 help 1207 SMP kernels contain instructions which fail on non-SMP processors. 1208 Enabling this option allows the kernel to modify itself to make 1209 these instructions safe. Disabling it allows about 1K of space 1210 savings. 1211 1212 If you don't know what to do here, say Y. 1213 1214config ARM_CPU_TOPOLOGY 1215 bool "Support cpu topology definition" 1216 depends on SMP && CPU_V7 1217 default y 1218 help 1219 Support ARM cpu topology definition. The MPIDR register defines 1220 affinity between processors which is then used to describe the cpu 1221 topology of an ARM System. 1222 1223config SCHED_MC 1224 bool "Multi-core scheduler support" 1225 depends on ARM_CPU_TOPOLOGY 1226 help 1227 Multi-core scheduler support improves the CPU scheduler's decision 1228 making when dealing with multi-core CPU chips at a cost of slightly 1229 increased overhead in some places. If unsure say N here. 1230 1231config SCHED_SMT 1232 bool "SMT scheduler support" 1233 depends on ARM_CPU_TOPOLOGY 1234 help 1235 Improves the CPU scheduler's decision making when dealing with 1236 MultiThreading at a cost of slightly increased overhead in some 1237 places. If unsure say N here. 1238 1239config HAVE_ARM_SCU 1240 bool 1241 help 1242 This option enables support for the ARM snoop control unit 1243 1244config HAVE_ARM_ARCH_TIMER 1245 bool "Architected timer support" 1246 depends on CPU_V7 1247 select ARM_ARCH_TIMER 1248 help 1249 This option enables support for the ARM architected timer 1250 1251config HAVE_ARM_TWD 1252 bool 1253 help 1254 This options enables support for the ARM timer and watchdog unit 1255 1256config MCPM 1257 bool "Multi-Cluster Power Management" 1258 depends on CPU_V7 && SMP 1259 help 1260 This option provides the common power management infrastructure 1261 for (multi-)cluster based systems, such as big.LITTLE based 1262 systems. 1263 1264config MCPM_QUAD_CLUSTER 1265 bool 1266 depends on MCPM 1267 help 1268 To avoid wasting resources unnecessarily, MCPM only supports up 1269 to 2 clusters by default. 1270 Platforms with 3 or 4 clusters that use MCPM must select this 1271 option to allow the additional clusters to be managed. 1272 1273config BIG_LITTLE 1274 bool "big.LITTLE support (Experimental)" 1275 depends on CPU_V7 && SMP 1276 select MCPM 1277 help 1278 This option enables support selections for the big.LITTLE 1279 system architecture. 1280 1281config BL_SWITCHER 1282 bool "big.LITTLE switcher support" 1283 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC 1284 select CPU_PM 1285 help 1286 The big.LITTLE "switcher" provides the core functionality to 1287 transparently handle transition between a cluster of A15's 1288 and a cluster of A7's in a big.LITTLE system. 1289 1290config BL_SWITCHER_DUMMY_IF 1291 tristate "Simple big.LITTLE switcher user interface" 1292 depends on BL_SWITCHER && DEBUG_KERNEL 1293 help 1294 This is a simple and dummy char dev interface to control 1295 the big.LITTLE switcher core code. It is meant for 1296 debugging purposes only. 1297 1298choice 1299 prompt "Memory split" 1300 depends on MMU 1301 default VMSPLIT_3G 1302 help 1303 Select the desired split between kernel and user memory. 1304 1305 If you are not absolutely sure what you are doing, leave this 1306 option alone! 1307 1308 config VMSPLIT_3G 1309 bool "3G/1G user/kernel split" 1310 config VMSPLIT_3G_OPT 1311 depends on !ARM_LPAE 1312 bool "3G/1G user/kernel split (for full 1G low memory)" 1313 config VMSPLIT_2G 1314 bool "2G/2G user/kernel split" 1315 config VMSPLIT_1G 1316 bool "1G/3G user/kernel split" 1317endchoice 1318 1319config PAGE_OFFSET 1320 hex 1321 default PHYS_OFFSET if !MMU 1322 default 0x40000000 if VMSPLIT_1G 1323 default 0x80000000 if VMSPLIT_2G 1324 default 0xB0000000 if VMSPLIT_3G_OPT 1325 default 0xC0000000 1326 1327config NR_CPUS 1328 int "Maximum number of CPUs (2-32)" 1329 range 2 32 1330 depends on SMP 1331 default "4" 1332 1333config HOTPLUG_CPU 1334 bool "Support for hot-pluggable CPUs" 1335 depends on SMP 1336 select GENERIC_IRQ_MIGRATION 1337 help 1338 Say Y here to experiment with turning CPUs off and on. CPUs 1339 can be controlled through /sys/devices/system/cpu. 1340 1341config ARM_PSCI 1342 bool "Support for the ARM Power State Coordination Interface (PSCI)" 1343 depends on HAVE_ARM_SMCCC 1344 select ARM_PSCI_FW 1345 help 1346 Say Y here if you want Linux to communicate with system firmware 1347 implementing the PSCI specification for CPU-centric power 1348 management operations described in ARM document number ARM DEN 1349 0022A ("Power State Coordination Interface System Software on 1350 ARM processors"). 1351 1352# The GPIO number here must be sorted by descending number. In case of 1353# a multiplatform kernel, we just want the highest value required by the 1354# selected platforms. 1355config ARCH_NR_GPIO 1356 int 1357 default 2048 if ARCH_SOCFPGA 1358 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \ 1359 ARCH_ZYNQ || ARCH_ASPEED 1360 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \ 1361 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210 1362 default 416 if ARCH_SUNXI 1363 default 392 if ARCH_U8500 1364 default 352 if ARCH_VT8500 1365 default 288 if ARCH_ROCKCHIP 1366 default 264 if MACH_H4700 1367 default 0 1368 help 1369 Maximum number of GPIOs in the system. 1370 1371 If unsure, leave the default value. 1372 1373config HZ_FIXED 1374 int 1375 default 200 if ARCH_EBSA110 1376 default 128 if SOC_AT91RM9200 1377 default 0 1378 1379choice 1380 depends on HZ_FIXED = 0 1381 prompt "Timer frequency" 1382 1383config HZ_100 1384 bool "100 Hz" 1385 1386config HZ_200 1387 bool "200 Hz" 1388 1389config HZ_250 1390 bool "250 Hz" 1391 1392config HZ_300 1393 bool "300 Hz" 1394 1395config HZ_500 1396 bool "500 Hz" 1397 1398config HZ_1000 1399 bool "1000 Hz" 1400 1401endchoice 1402 1403config HZ 1404 int 1405 default HZ_FIXED if HZ_FIXED != 0 1406 default 100 if HZ_100 1407 default 200 if HZ_200 1408 default 250 if HZ_250 1409 default 300 if HZ_300 1410 default 500 if HZ_500 1411 default 1000 1412 1413config SCHED_HRTICK 1414 def_bool HIGH_RES_TIMERS 1415 1416config THUMB2_KERNEL 1417 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY 1418 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K 1419 default y if CPU_THUMBONLY 1420 select ARM_UNWIND 1421 help 1422 By enabling this option, the kernel will be compiled in 1423 Thumb-2 mode. 1424 1425 If unsure, say N. 1426 1427config ARM_PATCH_IDIV 1428 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()" 1429 depends on CPU_32v7 && !XIP_KERNEL 1430 default y 1431 help 1432 The ARM compiler inserts calls to __aeabi_idiv() and 1433 __aeabi_uidiv() when it needs to perform division on signed 1434 and unsigned integers. Some v7 CPUs have support for the sdiv 1435 and udiv instructions that can be used to implement those 1436 functions. 1437 1438 Enabling this option allows the kernel to modify itself to 1439 replace the first two instructions of these library functions 1440 with the sdiv or udiv plus "bx lr" instructions when the CPU 1441 it is running on supports them. Typically this will be faster 1442 and less power intensive than running the original library 1443 code to do integer division. 1444 1445config AEABI 1446 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \ 1447 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG 1448 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG 1449 help 1450 This option allows for the kernel to be compiled using the latest 1451 ARM ABI (aka EABI). This is only useful if you are using a user 1452 space environment that is also compiled with EABI. 1453 1454 Since there are major incompatibilities between the legacy ABI and 1455 EABI, especially with regard to structure member alignment, this 1456 option also changes the kernel syscall calling convention to 1457 disambiguate both ABIs and allow for backward compatibility support 1458 (selected with CONFIG_OABI_COMPAT). 1459 1460 To use this you need GCC version 4.0.0 or later. 1461 1462config OABI_COMPAT 1463 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)" 1464 depends on AEABI && !THUMB2_KERNEL 1465 help 1466 This option preserves the old syscall interface along with the 1467 new (ARM EABI) one. It also provides a compatibility layer to 1468 intercept syscalls that have structure arguments which layout 1469 in memory differs between the legacy ABI and the new ARM EABI 1470 (only for non "thumb" binaries). This option adds a tiny 1471 overhead to all syscalls and produces a slightly larger kernel. 1472 1473 The seccomp filter system will not be available when this is 1474 selected, since there is no way yet to sensibly distinguish 1475 between calling conventions during filtering. 1476 1477 If you know you'll be using only pure EABI user space then you 1478 can say N here. If this option is not selected and you attempt 1479 to execute a legacy ABI binary then the result will be 1480 UNPREDICTABLE (in fact it can be predicted that it won't work 1481 at all). If in doubt say N. 1482 1483config ARCH_HAS_HOLES_MEMORYMODEL 1484 bool 1485 1486config ARCH_SELECT_MEMORY_MODEL 1487 bool 1488 1489config ARCH_FLATMEM_ENABLE 1490 bool 1491 1492config ARCH_SPARSEMEM_ENABLE 1493 bool 1494 select SPARSEMEM_STATIC if SPARSEMEM 1495 1496config HAVE_ARCH_PFN_VALID 1497 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM 1498 1499config HIGHMEM 1500 bool "High Memory Support" 1501 depends on MMU 1502 help 1503 The address space of ARM processors is only 4 Gigabytes large 1504 and it has to accommodate user address space, kernel address 1505 space as well as some memory mapped IO. That means that, if you 1506 have a large amount of physical memory and/or IO, not all of the 1507 memory can be "permanently mapped" by the kernel. The physical 1508 memory that is not permanently mapped is called "high memory". 1509 1510 Depending on the selected kernel/user memory split, minimum 1511 vmalloc space and actual amount of RAM, you may not need this 1512 option which should result in a slightly faster kernel. 1513 1514 If unsure, say n. 1515 1516config HIGHPTE 1517 bool "Allocate 2nd-level pagetables from highmem" if EXPERT 1518 depends on HIGHMEM 1519 default y 1520 help 1521 The VM uses one page of physical memory for each page table. 1522 For systems with a lot of processes, this can use a lot of 1523 precious low memory, eventually leading to low memory being 1524 consumed by page tables. Setting this option will allow 1525 user-space 2nd level page tables to reside in high memory. 1526 1527config CPU_SW_DOMAIN_PAN 1528 bool "Enable use of CPU domains to implement privileged no-access" 1529 depends on MMU && !ARM_LPAE 1530 default y 1531 help 1532 Increase kernel security by ensuring that normal kernel accesses 1533 are unable to access userspace addresses. This can help prevent 1534 use-after-free bugs becoming an exploitable privilege escalation 1535 by ensuring that magic values (such as LIST_POISON) will always 1536 fault when dereferenced. 1537 1538 CPUs with low-vector mappings use a best-efforts implementation. 1539 Their lower 1MB needs to remain accessible for the vectors, but 1540 the remainder of userspace will become appropriately inaccessible. 1541 1542config HW_PERF_EVENTS 1543 def_bool y 1544 depends on ARM_PMU 1545 1546config SYS_SUPPORTS_HUGETLBFS 1547 def_bool y 1548 depends on ARM_LPAE 1549 1550config HAVE_ARCH_TRANSPARENT_HUGEPAGE 1551 def_bool y 1552 depends on ARM_LPAE 1553 1554config ARCH_WANT_GENERAL_HUGETLB 1555 def_bool y 1556 1557config ARM_MODULE_PLTS 1558 bool "Use PLTs to allow module memory to spill over into vmalloc area" 1559 depends on MODULES 1560 default y 1561 help 1562 Allocate PLTs when loading modules so that jumps and calls whose 1563 targets are too far away for their relative offsets to be encoded 1564 in the instructions themselves can be bounced via veneers in the 1565 module's PLT. This allows modules to be allocated in the generic 1566 vmalloc area after the dedicated module memory area has been 1567 exhausted. The modules will use slightly more memory, but after 1568 rounding up to page size, the actual memory footprint is usually 1569 the same. 1570 1571 Disabling this is usually safe for small single-platform 1572 configurations. If unsure, say y. 1573 1574config FORCE_MAX_ZONEORDER 1575 int "Maximum zone order" 1576 default "12" if SOC_AM33XX 1577 default "9" if SA1111 || ARCH_EFM32 1578 default "11" 1579 help 1580 The kernel memory allocator divides physically contiguous memory 1581 blocks into "zones", where each zone is a power of two number of 1582 pages. This option selects the largest power of two that the kernel 1583 keeps in the memory allocator. If you need to allocate very large 1584 blocks of physically contiguous memory, then you may need to 1585 increase this value. 1586 1587 This config option is actually maximum order plus one. For example, 1588 a value of 11 means that the largest free memory block is 2^10 pages. 1589 1590config ALIGNMENT_TRAP 1591 bool 1592 depends on CPU_CP15_MMU 1593 default y if !ARCH_EBSA110 1594 select HAVE_PROC_CPU if PROC_FS 1595 help 1596 ARM processors cannot fetch/store information which is not 1597 naturally aligned on the bus, i.e., a 4 byte fetch must start at an 1598 address divisible by 4. On 32-bit ARM processors, these non-aligned 1599 fetch/store instructions will be emulated in software if you say 1600 here, which has a severe performance impact. This is necessary for 1601 correct operation of some network protocols. With an IP-only 1602 configuration it is safe to say N, otherwise say Y. 1603 1604config UACCESS_WITH_MEMCPY 1605 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()" 1606 depends on MMU 1607 default y if CPU_FEROCEON 1608 help 1609 Implement faster copy_to_user and clear_user methods for CPU 1610 cores where a 8-word STM instruction give significantly higher 1611 memory write throughput than a sequence of individual 32bit stores. 1612 1613 A possible side effect is a slight increase in scheduling latency 1614 between threads sharing the same address space if they invoke 1615 such copy operations with large buffers. 1616 1617 However, if the CPU data cache is using a write-allocate mode, 1618 this option is unlikely to provide any performance gain. 1619 1620config PARAVIRT 1621 bool "Enable paravirtualization code" 1622 help 1623 This changes the kernel so it can modify itself when it is run 1624 under a hypervisor, potentially improving performance significantly 1625 over full virtualization. 1626 1627config PARAVIRT_TIME_ACCOUNTING 1628 bool "Paravirtual steal time accounting" 1629 select PARAVIRT 1630 help 1631 Select this option to enable fine granularity task steal time 1632 accounting. Time spent executing other tasks in parallel with 1633 the current vCPU is discounted from the vCPU power. To account for 1634 that, there can be a small performance impact. 1635 1636 If in doubt, say N here. 1637 1638config XEN_DOM0 1639 def_bool y 1640 depends on XEN 1641 1642config XEN 1643 bool "Xen guest support on ARM" 1644 depends on ARM && AEABI && OF 1645 depends on CPU_V7 && !CPU_V6 1646 depends on !GENERIC_ATOMIC64 1647 depends on MMU 1648 select ARCH_DMA_ADDR_T_64BIT 1649 select ARM_PSCI 1650 select SWIOTLB 1651 select SWIOTLB_XEN 1652 select PARAVIRT 1653 help 1654 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM. 1655 1656config STACKPROTECTOR_PER_TASK 1657 bool "Use a unique stack canary value for each task" 1658 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA 1659 select GCC_PLUGIN_ARM_SSP_PER_TASK 1660 default y 1661 help 1662 Due to the fact that GCC uses an ordinary symbol reference from 1663 which to load the value of the stack canary, this value can only 1664 change at reboot time on SMP systems, and all tasks running in the 1665 kernel's address space are forced to use the same canary value for 1666 the entire duration that the system is up. 1667 1668 Enable this option to switch to a different method that uses a 1669 different canary value for each task. 1670 1671endmenu 1672 1673menu "Boot options" 1674 1675config USE_OF 1676 bool "Flattened Device Tree support" 1677 select IRQ_DOMAIN 1678 select OF 1679 help 1680 Include support for flattened device tree machine descriptions. 1681 1682config ATAGS 1683 bool "Support for the traditional ATAGS boot data passing" if USE_OF 1684 default y 1685 help 1686 This is the traditional way of passing data to the kernel at boot 1687 time. If you are solely relying on the flattened device tree (or 1688 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option 1689 to remove ATAGS support from your kernel binary. If unsure, 1690 leave this to y. 1691 1692config DEPRECATED_PARAM_STRUCT 1693 bool "Provide old way to pass kernel parameters" 1694 depends on ATAGS 1695 help 1696 This was deprecated in 2001 and announced to live on for 5 years. 1697 Some old boot loaders still use this way. 1698 1699# Compressed boot loader in ROM. Yes, we really want to ask about 1700# TEXT and BSS so we preserve their values in the config files. 1701config ZBOOT_ROM_TEXT 1702 hex "Compressed ROM boot loader base address" 1703 default 0x0 1704 help 1705 The physical address at which the ROM-able zImage is to be 1706 placed in the target. Platforms which normally make use of 1707 ROM-able zImage formats normally set this to a suitable 1708 value in their defconfig file. 1709 1710 If ZBOOT_ROM is not enabled, this has no effect. 1711 1712config ZBOOT_ROM_BSS 1713 hex "Compressed ROM boot loader BSS address" 1714 default 0x0 1715 help 1716 The base address of an area of read/write memory in the target 1717 for the ROM-able zImage which must be available while the 1718 decompressor is running. It must be large enough to hold the 1719 entire decompressed kernel plus an additional 128 KiB. 1720 Platforms which normally make use of ROM-able zImage formats 1721 normally set this to a suitable value in their defconfig file. 1722 1723 If ZBOOT_ROM is not enabled, this has no effect. 1724 1725config ZBOOT_ROM 1726 bool "Compressed boot loader in ROM/flash" 1727 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS 1728 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR 1729 help 1730 Say Y here if you intend to execute your compressed kernel image 1731 (zImage) directly from ROM or flash. If unsure, say N. 1732 1733config ARM_APPENDED_DTB 1734 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1735 depends on OF 1736 help 1737 With this option, the boot code will look for a device tree binary 1738 (DTB) appended to zImage 1739 (e.g. cat zImage <filename>.dtb > zImage_w_dtb). 1740 1741 This is meant as a backward compatibility convenience for those 1742 systems with a bootloader that can't be upgraded to accommodate 1743 the documented boot protocol using a device tree. 1744 1745 Beware that there is very little in terms of protection against 1746 this option being confused by leftover garbage in memory that might 1747 look like a DTB header after a reboot if no actual DTB is appended 1748 to zImage. Do not leave this option active in a production kernel 1749 if you don't intend to always append a DTB. Proper passing of the 1750 location into r2 of a bootloader provided DTB is always preferable 1751 to this option. 1752 1753config ARM_ATAG_DTB_COMPAT 1754 bool "Supplement the appended DTB with traditional ATAG information" 1755 depends on ARM_APPENDED_DTB 1756 help 1757 Some old bootloaders can't be updated to a DTB capable one, yet 1758 they provide ATAGs with memory configuration, the ramdisk address, 1759 the kernel cmdline string, etc. Such information is dynamically 1760 provided by the bootloader and can't always be stored in a static 1761 DTB. To allow a device tree enabled kernel to be used with such 1762 bootloaders, this option allows zImage to extract the information 1763 from the ATAG list and store it at run time into the appended DTB. 1764 1765choice 1766 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT 1767 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1768 1769config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER 1770 bool "Use bootloader kernel arguments if available" 1771 help 1772 Uses the command-line options passed by the boot loader instead of 1773 the device tree bootargs property. If the boot loader doesn't provide 1774 any, the device tree bootargs property will be used. 1775 1776config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND 1777 bool "Extend with bootloader kernel arguments" 1778 help 1779 The command-line arguments provided by the boot loader will be 1780 appended to the the device tree bootargs property. 1781 1782endchoice 1783 1784config CMDLINE 1785 string "Default kernel command string" 1786 default "" 1787 help 1788 On some architectures (EBSA110 and CATS), there is currently no way 1789 for the boot loader to pass arguments to the kernel. For these 1790 architectures, you should supply some command-line options at build 1791 time by entering them here. As a minimum, you should specify the 1792 memory size and the root device (e.g., mem=64M root=/dev/nfs). 1793 1794choice 1795 prompt "Kernel command line type" if CMDLINE != "" 1796 default CMDLINE_FROM_BOOTLOADER 1797 depends on ATAGS 1798 1799config CMDLINE_FROM_BOOTLOADER 1800 bool "Use bootloader kernel arguments if available" 1801 help 1802 Uses the command-line options passed by the boot loader. If 1803 the boot loader doesn't provide any, the default kernel command 1804 string provided in CMDLINE will be used. 1805 1806config CMDLINE_EXTEND 1807 bool "Extend bootloader kernel arguments" 1808 help 1809 The command-line arguments provided by the boot loader will be 1810 appended to the default kernel command string. 1811 1812config CMDLINE_FORCE 1813 bool "Always use the default kernel command string" 1814 help 1815 Always use the default kernel command string, even if the boot 1816 loader passes other arguments to the kernel. 1817 This is useful if you cannot or don't want to change the 1818 command-line options your boot loader passes to the kernel. 1819endchoice 1820 1821config XIP_KERNEL 1822 bool "Kernel Execute-In-Place from ROM" 1823 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM 1824 help 1825 Execute-In-Place allows the kernel to run from non-volatile storage 1826 directly addressable by the CPU, such as NOR flash. This saves RAM 1827 space since the text section of the kernel is not loaded from flash 1828 to RAM. Read-write sections, such as the data section and stack, 1829 are still copied to RAM. The XIP kernel is not compressed since 1830 it has to run directly from flash, so it will take more space to 1831 store it. The flash address used to link the kernel object files, 1832 and for storing it, is configuration dependent. Therefore, if you 1833 say Y here, you must know the proper physical address where to 1834 store the kernel image depending on your own flash memory usage. 1835 1836 Also note that the make target becomes "make xipImage" rather than 1837 "make zImage" or "make Image". The final kernel binary to put in 1838 ROM memory will be arch/arm/boot/xipImage. 1839 1840 If unsure, say N. 1841 1842config XIP_PHYS_ADDR 1843 hex "XIP Kernel Physical Location" 1844 depends on XIP_KERNEL 1845 default "0x00080000" 1846 help 1847 This is the physical address in your flash memory the kernel will 1848 be linked for and stored to. This address is dependent on your 1849 own flash usage. 1850 1851config XIP_DEFLATED_DATA 1852 bool "Store kernel .data section compressed in ROM" 1853 depends on XIP_KERNEL 1854 select ZLIB_INFLATE 1855 help 1856 Before the kernel is actually executed, its .data section has to be 1857 copied to RAM from ROM. This option allows for storing that data 1858 in compressed form and decompressed to RAM rather than merely being 1859 copied, saving some precious ROM space. A possible drawback is a 1860 slightly longer boot delay. 1861 1862config KEXEC 1863 bool "Kexec system call (EXPERIMENTAL)" 1864 depends on (!SMP || PM_SLEEP_SMP) 1865 depends on MMU 1866 select KEXEC_CORE 1867 help 1868 kexec is a system call that implements the ability to shutdown your 1869 current kernel, and to start another kernel. It is like a reboot 1870 but it is independent of the system firmware. And like a reboot 1871 you can start any kernel with it, not just Linux. 1872 1873 It is an ongoing process to be certain the hardware in a machine 1874 is properly shutdown, so do not be surprised if this code does not 1875 initially work for you. 1876 1877config ATAGS_PROC 1878 bool "Export atags in procfs" 1879 depends on ATAGS && KEXEC 1880 default y 1881 help 1882 Should the atags used to boot the kernel be exported in an "atags" 1883 file in procfs. Useful with kexec. 1884 1885config CRASH_DUMP 1886 bool "Build kdump crash kernel (EXPERIMENTAL)" 1887 help 1888 Generate crash dump after being started by kexec. This should 1889 be normally only set in special crash dump kernels which are 1890 loaded in the main kernel with kexec-tools into a specially 1891 reserved region and then later executed after a crash by 1892 kdump/kexec. The crash dump kernel must be compiled to a 1893 memory address not used by the main kernel 1894 1895 For more details see Documentation/admin-guide/kdump/kdump.rst 1896 1897config AUTO_ZRELADDR 1898 bool "Auto calculation of the decompressed kernel image address" 1899 help 1900 ZRELADDR is the physical address where the decompressed kernel 1901 image will be placed. If AUTO_ZRELADDR is selected, the address 1902 will be determined at run-time by masking the current IP with 1903 0xf8000000. This assumes the zImage being placed in the first 128MB 1904 from start of memory. 1905 1906config EFI_STUB 1907 bool 1908 1909config EFI 1910 bool "UEFI runtime support" 1911 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL 1912 select UCS2_STRING 1913 select EFI_PARAMS_FROM_FDT 1914 select EFI_STUB 1915 select EFI_GENERIC_STUB 1916 select EFI_RUNTIME_WRAPPERS 1917 help 1918 This option provides support for runtime services provided 1919 by UEFI firmware (such as non-volatile variables, realtime 1920 clock, and platform reset). A UEFI stub is also provided to 1921 allow the kernel to be booted as an EFI application. This 1922 is only useful for kernels that may run on systems that have 1923 UEFI firmware. 1924 1925config DMI 1926 bool "Enable support for SMBIOS (DMI) tables" 1927 depends on EFI 1928 default y 1929 help 1930 This enables SMBIOS/DMI feature for systems. 1931 1932 This option is only useful on systems that have UEFI firmware. 1933 However, even with this option, the resultant kernel should 1934 continue to boot on existing non-UEFI platforms. 1935 1936 NOTE: This does *NOT* enable or encourage the use of DMI quirks, 1937 i.e., the the practice of identifying the platform via DMI to 1938 decide whether certain workarounds for buggy hardware and/or 1939 firmware need to be enabled. This would require the DMI subsystem 1940 to be enabled much earlier than we do on ARM, which is non-trivial. 1941 1942endmenu 1943 1944menu "CPU Power Management" 1945 1946source "drivers/cpufreq/Kconfig" 1947 1948source "drivers/cpuidle/Kconfig" 1949 1950endmenu 1951 1952menu "Floating point emulation" 1953 1954comment "At least one emulation must be selected" 1955 1956config FPE_NWFPE 1957 bool "NWFPE math emulation" 1958 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL 1959 help 1960 Say Y to include the NWFPE floating point emulator in the kernel. 1961 This is necessary to run most binaries. Linux does not currently 1962 support floating point hardware so you need to say Y here even if 1963 your machine has an FPA or floating point co-processor podule. 1964 1965 You may say N here if you are going to load the Acorn FPEmulator 1966 early in the bootup. 1967 1968config FPE_NWFPE_XP 1969 bool "Support extended precision" 1970 depends on FPE_NWFPE 1971 help 1972 Say Y to include 80-bit support in the kernel floating-point 1973 emulator. Otherwise, only 32 and 64-bit support is compiled in. 1974 Note that gcc does not generate 80-bit operations by default, 1975 so in most cases this option only enlarges the size of the 1976 floating point emulator without any good reason. 1977 1978 You almost surely want to say N here. 1979 1980config FPE_FASTFPE 1981 bool "FastFPE math emulation (EXPERIMENTAL)" 1982 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 1983 help 1984 Say Y here to include the FAST floating point emulator in the kernel. 1985 This is an experimental much faster emulator which now also has full 1986 precision for the mantissa. It does not support any exceptions. 1987 It is very simple, and approximately 3-6 times faster than NWFPE. 1988 1989 It should be sufficient for most programs. It may be not suitable 1990 for scientific calculations, but you have to check this for yourself. 1991 If you do not feel you need a faster FP emulation you should better 1992 choose NWFPE. 1993 1994config VFP 1995 bool "VFP-format floating point maths" 1996 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON 1997 help 1998 Say Y to include VFP support code in the kernel. This is needed 1999 if your hardware includes a VFP unit. 2000 2001 Please see <file:Documentation/arm/vfp/release-notes.rst> for 2002 release notes and additional status information. 2003 2004 Say N if your target does not have VFP hardware. 2005 2006config VFPv3 2007 bool 2008 depends on VFP 2009 default y if CPU_V7 2010 2011config NEON 2012 bool "Advanced SIMD (NEON) Extension support" 2013 depends on VFPv3 && CPU_V7 2014 help 2015 Say Y to include support code for NEON, the ARMv7 Advanced SIMD 2016 Extension. 2017 2018config KERNEL_MODE_NEON 2019 bool "Support for NEON in kernel mode" 2020 depends on NEON && AEABI 2021 help 2022 Say Y to include support for NEON in kernel mode. 2023 2024endmenu 2025 2026menu "Power management options" 2027 2028source "kernel/power/Kconfig" 2029 2030config ARCH_SUSPEND_POSSIBLE 2031 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2032 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2033 def_bool y 2034 2035config ARM_CPU_SUSPEND 2036 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW 2037 depends on ARCH_SUSPEND_POSSIBLE 2038 2039config ARCH_HIBERNATION_POSSIBLE 2040 bool 2041 depends on MMU 2042 default y if ARCH_SUSPEND_POSSIBLE 2043 2044endmenu 2045 2046source "drivers/firmware/Kconfig" 2047 2048if CRYPTO 2049source "arch/arm/crypto/Kconfig" 2050endif 2051 2052source "arch/arm/Kconfig.assembler" 2053
