1 /* 2 * TI CAL camera interface driver 3 * 4 * Copyright (c) 2015 Texas Instruments Inc. 5 * 6 * Benoit Parrot, <bparrot@ti.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 */ 12 13 #ifndef __TI_CAL_REGS_H 14 #define __TI_CAL_REGS_H 15 16 #define CAL_NUM_CSI2_PORTS 2 17 18 /* CAL register offsets */ 19 20 #define CAL_HL_REVISION 0x0000 21 #define CAL_HL_HWINFO 0x0004 22 #define CAL_HL_SYSCONFIG 0x0010 23 #define CAL_HL_IRQ_EOI 0x001c 24 #define CAL_HL_IRQSTATUS_RAW(m) (0x20U + ((m-1) * 0x10U)) 25 #define CAL_HL_IRQSTATUS(m) (0x24U + ((m-1) * 0x10U)) 26 #define CAL_HL_IRQENABLE_SET(m) (0x28U + ((m-1) * 0x10U)) 27 #define CAL_HL_IRQENABLE_CLR(m) (0x2cU + ((m-1) * 0x10U)) 28 #define CAL_PIX_PROC(m) (0xc0U + ((m-1) * 0x4U)) 29 #define CAL_CTRL 0x100 30 #define CAL_CTRL1 0x104 31 #define CAL_LINE_NUMBER_EVT 0x108 32 #define CAL_VPORT_CTRL1 0x120 33 #define CAL_VPORT_CTRL2 0x124 34 #define CAL_BYS_CTRL1 0x130 35 #define CAL_BYS_CTRL2 0x134 36 #define CAL_RD_DMA_CTRL 0x140 37 #define CAL_RD_DMA_PIX_ADDR 0x144 38 #define CAL_RD_DMA_PIX_OFST 0x148 39 #define CAL_RD_DMA_XSIZE 0x14c 40 #define CAL_RD_DMA_YSIZE 0x150 41 #define CAL_RD_DMA_INIT_ADDR 0x154 42 #define CAL_RD_DMA_INIT_OFST 0x168 43 #define CAL_RD_DMA_CTRL2 0x16c 44 #define CAL_WR_DMA_CTRL(m) (0x200U + ((m-1) * 0x10U)) 45 #define CAL_WR_DMA_ADDR(m) (0x204U + ((m-1) * 0x10U)) 46 #define CAL_WR_DMA_OFST(m) (0x208U + ((m-1) * 0x10U)) 47 #define CAL_WR_DMA_XSIZE(m) (0x20cU + ((m-1) * 0x10U)) 48 #define CAL_CSI2_PPI_CTRL(m) (0x300U + ((m-1) * 0x80U)) 49 #define CAL_CSI2_COMPLEXIO_CFG(m) (0x304U + ((m-1) * 0x80U)) 50 #define CAL_CSI2_COMPLEXIO_IRQSTATUS(m) (0x308U + ((m-1) * 0x80U)) 51 #define CAL_CSI2_SHORT_PACKET(m) (0x30cU + ((m-1) * 0x80U)) 52 #define CAL_CSI2_COMPLEXIO_IRQENABLE(m) (0x310U + ((m-1) * 0x80U)) 53 #define CAL_CSI2_TIMING(m) (0x314U + ((m-1) * 0x80U)) 54 #define CAL_CSI2_VC_IRQENABLE(m) (0x318U + ((m-1) * 0x80U)) 55 #define CAL_CSI2_VC_IRQSTATUS(m) (0x328U + ((m-1) * 0x80U)) 56 #define CAL_CSI2_CTX0(m) (0x330U + ((m-1) * 0x80U)) 57 #define CAL_CSI2_CTX1(m) (0x334U + ((m-1) * 0x80U)) 58 #define CAL_CSI2_CTX2(m) (0x338U + ((m-1) * 0x80U)) 59 #define CAL_CSI2_CTX3(m) (0x33cU + ((m-1) * 0x80U)) 60 #define CAL_CSI2_CTX4(m) (0x340U + ((m-1) * 0x80U)) 61 #define CAL_CSI2_CTX5(m) (0x344U + ((m-1) * 0x80U)) 62 #define CAL_CSI2_CTX6(m) (0x348U + ((m-1) * 0x80U)) 63 #define CAL_CSI2_CTX7(m) (0x34cU + ((m-1) * 0x80U)) 64 #define CAL_CSI2_STATUS0(m) (0x350U + ((m-1) * 0x80U)) 65 #define CAL_CSI2_STATUS1(m) (0x354U + ((m-1) * 0x80U)) 66 #define CAL_CSI2_STATUS2(m) (0x358U + ((m-1) * 0x80U)) 67 #define CAL_CSI2_STATUS3(m) (0x35cU + ((m-1) * 0x80U)) 68 #define CAL_CSI2_STATUS4(m) (0x360U + ((m-1) * 0x80U)) 69 #define CAL_CSI2_STATUS5(m) (0x364U + ((m-1) * 0x80U)) 70 #define CAL_CSI2_STATUS6(m) (0x368U + ((m-1) * 0x80U)) 71 #define CAL_CSI2_STATUS7(m) (0x36cU + ((m-1) * 0x80U)) 72 73 /* CAL CSI2 PHY register offsets */ 74 #define CAL_CSI2_PHY_REG0 0x000 75 #define CAL_CSI2_PHY_REG1 0x004 76 #define CAL_CSI2_PHY_REG2 0x008 77 78 /* CAL Control Module Core Camerrx Control register offsets */ 79 #define CM_CTRL_CORE_CAMERRX_CONTROL 0x000 80 81 /********************************************************************* 82 * Generic value used in various field below 83 *********************************************************************/ 84 85 #define CAL_GEN_DISABLE 0 86 #define CAL_GEN_ENABLE 1 87 #define CAL_GEN_FALSE 0 88 #define CAL_GEN_TRUE 1 89 90 /********************************************************************* 91 * Field Definition Macros 92 *********************************************************************/ 93 94 #define CAL_HL_REVISION_MINOR_MASK GENMASK(5, 0) 95 #define CAL_HL_REVISION_CUSTOM_MASK GENMASK(7, 6) 96 #define CAL_HL_REVISION_MAJOR_MASK GENMASK(10, 8) 97 #define CAL_HL_REVISION_RTL_MASK GENMASK(15, 11) 98 #define CAL_HL_REVISION_FUNC_MASK GENMASK(27, 16) 99 #define CAL_HL_REVISION_SCHEME_MASK GENMASK(31, 30) 100 #define CAL_HL_REVISION_SCHEME_H08 1 101 #define CAL_HL_REVISION_SCHEME_LEGACY 0 102 103 #define CAL_HL_HWINFO_WFIFO_MASK GENMASK(3, 0) 104 #define CAL_HL_HWINFO_RFIFO_MASK GENMASK(7, 4) 105 #define CAL_HL_HWINFO_PCTX_MASK GENMASK(12, 8) 106 #define CAL_HL_HWINFO_WCTX_MASK GENMASK(18, 13) 107 #define CAL_HL_HWINFO_VFIFO_MASK GENMASK(22, 19) 108 #define CAL_HL_HWINFO_NCPORT_MASK GENMASK(27, 23) 109 #define CAL_HL_HWINFO_NPPI_CTXS0_MASK GENMASK(29, 28) 110 #define CAL_HL_HWINFO_NPPI_CTXS1_MASK GENMASK(31, 30) 111 #define CAL_HL_HWINFO_NPPI_CONTEXTS_ZERO 0 112 #define CAL_HL_HWINFO_NPPI_CONTEXTS_FOUR 1 113 #define CAL_HL_HWINFO_NPPI_CONTEXTS_EIGHT 2 114 #define CAL_HL_HWINFO_NPPI_CONTEXTS_RESERVED 3 115 116 #define CAL_HL_SYSCONFIG_SOFTRESET_MASK BIT_MASK(0) 117 #define CAL_HL_SYSCONFIG_SOFTRESET_DONE 0x0 118 #define CAL_HL_SYSCONFIG_SOFTRESET_PENDING 0x1 119 #define CAL_HL_SYSCONFIG_SOFTRESET_NOACTION 0x0 120 #define CAL_HL_SYSCONFIG_SOFTRESET_RESET 0x1 121 #define CAL_HL_SYSCONFIG_IDLE_MASK GENMASK(3, 2) 122 #define CAL_HL_SYSCONFIG_IDLEMODE_FORCE 0 123 #define CAL_HL_SYSCONFIG_IDLEMODE_NO 1 124 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART1 2 125 #define CAL_HL_SYSCONFIG_IDLEMODE_SMART2 3 126 127 #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK BIT_MASK(0) 128 #define CAL_HL_IRQ_EOI_LINE_NUMBER_READ0 0 129 #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0 0 130 131 #define CAL_HL_IRQ_MASK(m) BIT_MASK(m-1) 132 #define CAL_HL_IRQ_NOACTION 0x0 133 #define CAL_HL_IRQ_ENABLE 0x1 134 #define CAL_HL_IRQ_CLEAR 0x1 135 #define CAL_HL_IRQ_DISABLED 0x0 136 #define CAL_HL_IRQ_ENABLED 0x1 137 #define CAL_HL_IRQ_PENDING 0x1 138 139 #define CAL_PIX_PROC_EN_MASK BIT_MASK(0) 140 #define CAL_PIX_PROC_EXTRACT_MASK GENMASK(4, 1) 141 #define CAL_PIX_PROC_EXTRACT_B6 0x0 142 #define CAL_PIX_PROC_EXTRACT_B7 0x1 143 #define CAL_PIX_PROC_EXTRACT_B8 0x2 144 #define CAL_PIX_PROC_EXTRACT_B10 0x3 145 #define CAL_PIX_PROC_EXTRACT_B10_MIPI 0x4 146 #define CAL_PIX_PROC_EXTRACT_B12 0x5 147 #define CAL_PIX_PROC_EXTRACT_B12_MIPI 0x6 148 #define CAL_PIX_PROC_EXTRACT_B14 0x7 149 #define CAL_PIX_PROC_EXTRACT_B14_MIPI 0x8 150 #define CAL_PIX_PROC_EXTRACT_B16_BE 0x9 151 #define CAL_PIX_PROC_EXTRACT_B16_LE 0xa 152 #define CAL_PIX_PROC_DPCMD_MASK GENMASK(9, 5) 153 #define CAL_PIX_PROC_DPCMD_BYPASS 0x0 154 #define CAL_PIX_PROC_DPCMD_DPCM_10_8_1 0x2 155 #define CAL_PIX_PROC_DPCMD_DPCM_12_8_1 0x8 156 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_1 0x4 157 #define CAL_PIX_PROC_DPCMD_DPCM_10_7_2 0x5 158 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_1 0x6 159 #define CAL_PIX_PROC_DPCMD_DPCM_10_6_2 0x7 160 #define CAL_PIX_PROC_DPCMD_DPCM_12_7_1 0xa 161 #define CAL_PIX_PROC_DPCMD_DPCM_12_6_1 0xc 162 #define CAL_PIX_PROC_DPCMD_DPCM_14_10 0xe 163 #define CAL_PIX_PROC_DPCMD_DPCM_14_8_1 0x10 164 #define CAL_PIX_PROC_DPCMD_DPCM_16_12_1 0x12 165 #define CAL_PIX_PROC_DPCMD_DPCM_16_10_1 0x14 166 #define CAL_PIX_PROC_DPCMD_DPCM_16_8_1 0x16 167 #define CAL_PIX_PROC_DPCME_MASK GENMASK(15, 11) 168 #define CAL_PIX_PROC_DPCME_BYPASS 0x0 169 #define CAL_PIX_PROC_DPCME_DPCM_10_8_1 0x2 170 #define CAL_PIX_PROC_DPCME_DPCM_12_8_1 0x8 171 #define CAL_PIX_PROC_DPCME_DPCM_14_10 0xe 172 #define CAL_PIX_PROC_DPCME_DPCM_14_8_1 0x10 173 #define CAL_PIX_PROC_DPCME_DPCM_16_12_1 0x12 174 #define CAL_PIX_PROC_DPCME_DPCM_16_10_1 0x14 175 #define CAL_PIX_PROC_DPCME_DPCM_16_8_1 0x16 176 #define CAL_PIX_PROC_PACK_MASK GENMASK(18, 16) 177 #define CAL_PIX_PROC_PACK_B8 0x0 178 #define CAL_PIX_PROC_PACK_B10_MIPI 0x2 179 #define CAL_PIX_PROC_PACK_B12 0x3 180 #define CAL_PIX_PROC_PACK_B12_MIPI 0x4 181 #define CAL_PIX_PROC_PACK_B16 0x5 182 #define CAL_PIX_PROC_PACK_ARGB 0x6 183 #define CAL_PIX_PROC_CPORT_MASK GENMASK(23, 19) 184 185 #define CAL_CTRL_POSTED_WRITES_MASK BIT_MASK(0) 186 #define CAL_CTRL_POSTED_WRITES_NONPOSTED 0 187 #define CAL_CTRL_POSTED_WRITES 1 188 #define CAL_CTRL_TAGCNT_MASK GENMASK(4, 1) 189 #define CAL_CTRL_BURSTSIZE_MASK GENMASK(6, 5) 190 #define CAL_CTRL_BURSTSIZE_BURST16 0x0 191 #define CAL_CTRL_BURSTSIZE_BURST32 0x1 192 #define CAL_CTRL_BURSTSIZE_BURST64 0x2 193 #define CAL_CTRL_BURSTSIZE_BURST128 0x3 194 #define CAL_CTRL_LL_FORCE_STATE_MASK GENMASK(12, 7) 195 #define CAL_CTRL_MFLAGL_MASK GENMASK(20, 13) 196 #define CAL_CTRL_PWRSCPCLK_MASK BIT_MASK(21) 197 #define CAL_CTRL_PWRSCPCLK_AUTO 0 198 #define CAL_CTRL_PWRSCPCLK_FORCE 1 199 #define CAL_CTRL_RD_DMA_STALL_MASK BIT_MASK(22) 200 #define CAL_CTRL_MFLAGH_MASK GENMASK(31, 24) 201 202 #define CAL_CTRL1_PPI_GROUPING_MASK GENMASK(1, 0) 203 #define CAL_CTRL1_PPI_GROUPING_DISABLED 0 204 #define CAL_CTRL1_PPI_GROUPING_RESERVED 1 205 #define CAL_CTRL1_PPI_GROUPING_0 2 206 #define CAL_CTRL1_PPI_GROUPING_1 3 207 #define CAL_CTRL1_INTERLEAVE01_MASK GENMASK(3, 2) 208 #define CAL_CTRL1_INTERLEAVE01_DISABLED 0 209 #define CAL_CTRL1_INTERLEAVE01_PIX1 1 210 #define CAL_CTRL1_INTERLEAVE01_PIX4 2 211 #define CAL_CTRL1_INTERLEAVE01_RESERVED 3 212 #define CAL_CTRL1_INTERLEAVE23_MASK GENMASK(5, 4) 213 #define CAL_CTRL1_INTERLEAVE23_DISABLED 0 214 #define CAL_CTRL1_INTERLEAVE23_PIX1 1 215 #define CAL_CTRL1_INTERLEAVE23_PIX4 2 216 #define CAL_CTRL1_INTERLEAVE23_RESERVED 3 217 218 #define CAL_LINE_NUMBER_EVT_CPORT_MASK GENMASK(4, 0) 219 #define CAL_LINE_NUMBER_EVT_MASK GENMASK(29, 16) 220 221 #define CAL_VPORT_CTRL1_PCLK_MASK GENMASK(16, 0) 222 #define CAL_VPORT_CTRL1_XBLK_MASK GENMASK(24, 17) 223 #define CAL_VPORT_CTRL1_YBLK_MASK GENMASK(30, 25) 224 #define CAL_VPORT_CTRL1_WIDTH_MASK BIT_MASK(31) 225 #define CAL_VPORT_CTRL1_WIDTH_ONE 0 226 #define CAL_VPORT_CTRL1_WIDTH_TWO 1 227 228 #define CAL_VPORT_CTRL2_CPORT_MASK GENMASK(4, 0) 229 #define CAL_VPORT_CTRL2_FREERUNNING_MASK BIT_MASK(15) 230 #define CAL_VPORT_CTRL2_FREERUNNING_GATED 0 231 #define CAL_VPORT_CTRL2_FREERUNNING_FREE 1 232 #define CAL_VPORT_CTRL2_FS_RESETS_MASK BIT_MASK(16) 233 #define CAL_VPORT_CTRL2_FS_RESETS_NO 0 234 #define CAL_VPORT_CTRL2_FS_RESETS_YES 1 235 #define CAL_VPORT_CTRL2_FSM_RESET_MASK BIT_MASK(17) 236 #define CAL_VPORT_CTRL2_FSM_RESET_NOEFFECT 0 237 #define CAL_VPORT_CTRL2_FSM_RESET 1 238 #define CAL_VPORT_CTRL2_RDY_THR_MASK GENMASK(31, 18) 239 240 #define CAL_BYS_CTRL1_PCLK_MASK GENMASK(16, 0) 241 #define CAL_BYS_CTRL1_XBLK_MASK GENMASK(24, 17) 242 #define CAL_BYS_CTRL1_YBLK_MASK GENMASK(30, 25) 243 #define CAL_BYS_CTRL1_BYSINEN_MASK BIT_MASK(31) 244 245 #define CAL_BYS_CTRL2_CPORTIN_MASK GENMASK(4, 0) 246 #define CAL_BYS_CTRL2_CPORTOUT_MASK GENMASK(9, 5) 247 #define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK BIT_MASK(10) 248 #define CAL_BYS_CTRL2_DUPLICATEDDATA_NO 0 249 #define CAL_BYS_CTRL2_DUPLICATEDDATA_YES 1 250 #define CAL_BYS_CTRL2_FREERUNNING_MASK BIT_MASK(11) 251 #define CAL_BYS_CTRL2_FREERUNNING_NO 0 252 #define CAL_BYS_CTRL2_FREERUNNING_YES 1 253 254 #define CAL_RD_DMA_CTRL_GO_MASK BIT_MASK(0) 255 #define CAL_RD_DMA_CTRL_GO_DIS 0 256 #define CAL_RD_DMA_CTRL_GO_EN 1 257 #define CAL_RD_DMA_CTRL_GO_IDLE 0 258 #define CAL_RD_DMA_CTRL_GO_BUSY 1 259 #define CAL_RD_DMA_CTRL_INIT_MASK BIT_MASK(1) 260 #define CAL_RD_DMA_CTRL_BW_LIMITER_MASK GENMASK(10, 2) 261 #define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK GENMASK(14, 11) 262 #define CAL_RD_DMA_CTRL_PCLK_MASK GENMASK(31, 15) 263 264 #define CAL_RD_DMA_PIX_ADDR_MASK GENMASK(31, 3) 265 266 #define CAL_RD_DMA_PIX_OFST_MASK GENMASK(31, 4) 267 268 #define CAL_RD_DMA_XSIZE_MASK GENMASK(31, 19) 269 270 #define CAL_RD_DMA_YSIZE_MASK GENMASK(29, 16) 271 272 #define CAL_RD_DMA_INIT_ADDR_MASK GENMASK(31, 3) 273 274 #define CAL_RD_DMA_INIT_OFST_MASK GENMASK(31, 3) 275 276 #define CAL_RD_DMA_CTRL2_CIRC_MODE_MASK GENMASK(2, 0) 277 #define CAL_RD_DMA_CTRL2_CIRC_MODE_DIS 0 278 #define CAL_RD_DMA_CTRL2_CIRC_MODE_ONE 1 279 #define CAL_RD_DMA_CTRL2_CIRC_MODE_FOUR 2 280 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTEEN 3 281 #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTYFOUR 4 282 #define CAL_RD_DMA_CTRL2_CIRC_MODE_RESERVED 5 283 #define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK BIT_MASK(3) 284 #define CAL_RD_DMA_CTRL2_PATTERN_MASK GENMASK(5, 4) 285 #define CAL_RD_DMA_CTRL2_PATTERN_LINEAR 0 286 #define CAL_RD_DMA_CTRL2_PATTERN_YUV420 1 287 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP2 2 288 #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP4 3 289 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK BIT_MASK(6) 290 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_FREERUNNING 0 291 #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_WAITFORBYSOUT 1 292 #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK GENMASK(29, 16) 293 294 #define CAL_WR_DMA_CTRL_MODE_MASK GENMASK(2, 0) 295 #define CAL_WR_DMA_CTRL_MODE_DIS 0 296 #define CAL_WR_DMA_CTRL_MODE_SHD 1 297 #define CAL_WR_DMA_CTRL_MODE_CNT 2 298 #define CAL_WR_DMA_CTRL_MODE_CNT_INIT 3 299 #define CAL_WR_DMA_CTRL_MODE_CONST 4 300 #define CAL_WR_DMA_CTRL_MODE_RESERVED 5 301 #define CAL_WR_DMA_CTRL_PATTERN_MASK GENMASK(4, 3) 302 #define CAL_WR_DMA_CTRL_PATTERN_LINEAR 0 303 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP2 2 304 #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP4 3 305 #define CAL_WR_DMA_CTRL_PATTERN_RESERVED 1 306 #define CAL_WR_DMA_CTRL_ICM_PSTART_MASK BIT_MASK(5) 307 #define CAL_WR_DMA_CTRL_DTAG_MASK GENMASK(8, 6) 308 #define CAL_WR_DMA_CTRL_DTAG_ATT_HDR 0 309 #define CAL_WR_DMA_CTRL_DTAG_ATT_DAT 1 310 #define CAL_WR_DMA_CTRL_DTAG 2 311 #define CAL_WR_DMA_CTRL_DTAG_PIX_HDR 3 312 #define CAL_WR_DMA_CTRL_DTAG_PIX_DAT 4 313 #define CAL_WR_DMA_CTRL_DTAG_D5 5 314 #define CAL_WR_DMA_CTRL_DTAG_D6 6 315 #define CAL_WR_DMA_CTRL_DTAG_D7 7 316 #define CAL_WR_DMA_CTRL_CPORT_MASK GENMASK(13, 9) 317 #define CAL_WR_DMA_CTRL_STALL_RD_MASK BIT_MASK(14) 318 #define CAL_WR_DMA_CTRL_YSIZE_MASK GENMASK(31, 18) 319 320 #define CAL_WR_DMA_ADDR_MASK GENMASK(31, 4) 321 322 #define CAL_WR_DMA_OFST_MASK GENMASK(18, 4) 323 #define CAL_WR_DMA_OFST_CIRC_MODE_MASK GENMASK(23, 22) 324 #define CAL_WR_DMA_OFST_CIRC_MODE_ONE 1 325 #define CAL_WR_DMA_OFST_CIRC_MODE_FOUR 2 326 #define CAL_WR_DMA_OFST_CIRC_MODE_SIXTYFOUR 3 327 #define CAL_WR_DMA_OFST_CIRC_MODE_DISABLED 0 328 #define CAL_WR_DMA_OFST_CIRC_SIZE_MASK GENMASK(31, 24) 329 330 #define CAL_WR_DMA_XSIZE_XSKIP_MASK GENMASK(15, 3) 331 #define CAL_WR_DMA_XSIZE_MASK GENMASK(31, 19) 332 333 #define CAL_CSI2_PPI_CTRL_IF_EN_MASK BIT_MASK(0) 334 #define CAL_CSI2_PPI_CTRL_ECC_EN_MASK BIT_MASK(2) 335 #define CAL_CSI2_PPI_CTRL_FRAME_MASK BIT_MASK(3) 336 #define CAL_CSI2_PPI_CTRL_FRAME_IMMEDIATE 0 337 #define CAL_CSI2_PPI_CTRL_FRAME 1 338 339 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK GENMASK(2, 0) 340 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_5 5 341 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_4 4 342 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_3 3 343 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_2 2 344 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_1 1 345 #define CAL_CSI2_COMPLEXIO_CFG_POSITION_NOT_USED 0 346 #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK BIT_MASK(3) 347 #define CAL_CSI2_COMPLEXIO_CFG_POL_PLUSMINUS 0 348 #define CAL_CSI2_COMPLEXIO_CFG_POL_MINUSPLUS 1 349 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK GENMASK(6, 4) 350 #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK BIT_MASK(7) 351 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK GENMASK(10, 8) 352 #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK BIT_MASK(11) 353 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK GENMASK(14, 12) 354 #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK BIT_MASK(15) 355 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK GENMASK(18, 16) 356 #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK BIT_MASK(19) 357 #define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK BIT_MASK(24) 358 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK GENMASK(26, 25) 359 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF 0 360 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON 1 361 #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ULP 2 362 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK GENMASK(28, 27) 363 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF 0 364 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON 1 365 #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ULP 2 366 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK BIT_MASK(29) 367 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED 1 368 #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING 0 369 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK BIT_MASK(30) 370 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL 0 371 #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL 1 372 373 #define CAL_CSI2_SHORT_PACKET_MASK GENMASK(23, 0) 374 375 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK BIT_MASK(0) 376 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK BIT_MASK(1) 377 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK BIT_MASK(2) 378 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK BIT_MASK(3) 379 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK BIT_MASK(4) 380 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK BIT_MASK(5) 381 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK BIT_MASK(6) 382 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK BIT_MASK(7) 383 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK BIT_MASK(8) 384 #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK BIT_MASK(9) 385 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK BIT_MASK(10) 386 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK BIT_MASK(11) 387 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK BIT_MASK(12) 388 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK BIT_MASK(13) 389 #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK BIT_MASK(14) 390 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK BIT_MASK(15) 391 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK BIT_MASK(16) 392 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK BIT_MASK(17) 393 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK BIT_MASK(18) 394 #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK BIT_MASK(19) 395 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK BIT_MASK(20) 396 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK BIT_MASK(21) 397 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK BIT_MASK(22) 398 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK BIT_MASK(23) 399 #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK BIT_MASK(24) 400 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK BIT_MASK(25) 401 #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK BIT_MASK(26) 402 #define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK BIT_MASK(27) 403 #define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK BIT_MASK(28) 404 #define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK BIT_MASK(30) 405 406 #define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK GENMASK(12, 0) 407 #define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK BIT_MASK(13) 408 #define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK BIT_MASK(14) 409 #define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK BIT_MASK(15) 410 411 #define CAL_CSI2_VC_IRQ_FS_IRQ_0_MASK BIT_MASK(0) 412 #define CAL_CSI2_VC_IRQ_FE_IRQ_0_MASK BIT_MASK(1) 413 #define CAL_CSI2_VC_IRQ_LS_IRQ_0_MASK BIT_MASK(2) 414 #define CAL_CSI2_VC_IRQ_LE_IRQ_0_MASK BIT_MASK(3) 415 #define CAL_CSI2_VC_IRQ_CS_IRQ_0_MASK BIT_MASK(4) 416 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_0_MASK BIT_MASK(5) 417 #define CAL_CSI2_VC_IRQ_FS_IRQ_1_MASK BIT_MASK(8) 418 #define CAL_CSI2_VC_IRQ_FE_IRQ_1_MASK BIT_MASK(9) 419 #define CAL_CSI2_VC_IRQ_LS_IRQ_1_MASK BIT_MASK(10) 420 #define CAL_CSI2_VC_IRQ_LE_IRQ_1_MASK BIT_MASK(11) 421 #define CAL_CSI2_VC_IRQ_CS_IRQ_1_MASK BIT_MASK(12) 422 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_1_MASK BIT_MASK(13) 423 #define CAL_CSI2_VC_IRQ_FS_IRQ_2_MASK BIT_MASK(16) 424 #define CAL_CSI2_VC_IRQ_FE_IRQ_2_MASK BIT_MASK(17) 425 #define CAL_CSI2_VC_IRQ_LS_IRQ_2_MASK BIT_MASK(18) 426 #define CAL_CSI2_VC_IRQ_LE_IRQ_2_MASK BIT_MASK(19) 427 #define CAL_CSI2_VC_IRQ_CS_IRQ_2_MASK BIT_MASK(20) 428 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_2_MASK BIT_MASK(21) 429 #define CAL_CSI2_VC_IRQ_FS_IRQ_3_MASK BIT_MASK(24) 430 #define CAL_CSI2_VC_IRQ_FE_IRQ_3_MASK BIT_MASK(25) 431 #define CAL_CSI2_VC_IRQ_LS_IRQ_3_MASK BIT_MASK(26) 432 #define CAL_CSI2_VC_IRQ_LE_IRQ_3_MASK BIT_MASK(27) 433 #define CAL_CSI2_VC_IRQ_CS_IRQ_3_MASK BIT_MASK(28) 434 #define CAL_CSI2_VC_IRQ_ECC_CORRECTION0_IRQ_3_MASK BIT_MASK(29) 435 436 #define CAL_CSI2_CTX_DT_MASK GENMASK(5, 0) 437 #define CAL_CSI2_CTX_VC_MASK GENMASK(7, 6) 438 #define CAL_CSI2_CTX_CPORT_MASK GENMASK(12, 8) 439 #define CAL_CSI2_CTX_ATT_MASK BIT_MASK(13) 440 #define CAL_CSI2_CTX_ATT_PIX 0 441 #define CAL_CSI2_CTX_ATT 1 442 #define CAL_CSI2_CTX_PACK_MODE_MASK BIT_MASK(14) 443 #define CAL_CSI2_CTX_PACK_MODE_LINE 0 444 #define CAL_CSI2_CTX_PACK_MODE_FRAME 1 445 #define CAL_CSI2_CTX_LINES_MASK GENMASK(29, 16) 446 447 #define CAL_CSI2_STATUS_FRAME_MASK GENMASK(15, 0) 448 449 #define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK GENMASK(7, 0) 450 #define CAL_CSI2_PHY_REG0_THS_TERM_MASK GENMASK(15, 8) 451 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK BIT_MASK(24) 452 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE 1 453 #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_ENABLE 0 454 455 #define CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK GENMASK(7, 0) 456 #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK GENMASK(9, 8) 457 #define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK GENMASK(17, 10) 458 #define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK GENMASK(24, 18) 459 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK BIT_MASK(25) 460 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_ERROR 1 461 #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_SUCCESS 0 462 #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK GENMASK(29, 28) 463 464 #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK GENMASK(23, 0) 465 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK GENMASK(25, 24) 466 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK GENMASK(27, 26) 467 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK GENMASK(29, 28) 468 #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK GENMASK(31, 30) 469 470 #define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK BIT_MASK(0) 471 #define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK GENMASK(2, 1) 472 #define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK GENMASK(4, 3) 473 #define CM_CAMERRX_CTRL_CSI1_MODE_MASK BIT_MASK(5) 474 #define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK BIT_MASK(10) 475 #define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK GENMASK(12, 11) 476 #define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK GENMASK(16, 13) 477 #define CM_CAMERRX_CTRL_CSI0_MODE_MASK BIT_MASK(17) 478 479 #endif 480