1 /* 2 * sound/soc/omap/mcbsp.h 3 * 4 * OMAP Multi-Channel Buffered Serial Port 5 * 6 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com> 7 * Peter Ujfalusi <peter.ujfalusi@ti.com> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 22 * 23 */ 24 #ifndef __ASOC_MCBSP_H 25 #define __ASOC_MCBSP_H 26 27 #ifdef CONFIG_ARCH_OMAP1 28 #define mcbsp_omap1() 1 29 #else 30 #define mcbsp_omap1() 0 31 #endif 32 33 #include <sound/dmaengine_pcm.h> 34 35 /* McBSP register numbers. Register address offset = num * reg_step */ 36 enum { 37 /* Common registers */ 38 OMAP_MCBSP_REG_SPCR2 = 4, 39 OMAP_MCBSP_REG_SPCR1, 40 OMAP_MCBSP_REG_RCR2, 41 OMAP_MCBSP_REG_RCR1, 42 OMAP_MCBSP_REG_XCR2, 43 OMAP_MCBSP_REG_XCR1, 44 OMAP_MCBSP_REG_SRGR2, 45 OMAP_MCBSP_REG_SRGR1, 46 OMAP_MCBSP_REG_MCR2, 47 OMAP_MCBSP_REG_MCR1, 48 OMAP_MCBSP_REG_RCERA, 49 OMAP_MCBSP_REG_RCERB, 50 OMAP_MCBSP_REG_XCERA, 51 OMAP_MCBSP_REG_XCERB, 52 OMAP_MCBSP_REG_PCR0, 53 OMAP_MCBSP_REG_RCERC, 54 OMAP_MCBSP_REG_RCERD, 55 OMAP_MCBSP_REG_XCERC, 56 OMAP_MCBSP_REG_XCERD, 57 OMAP_MCBSP_REG_RCERE, 58 OMAP_MCBSP_REG_RCERF, 59 OMAP_MCBSP_REG_XCERE, 60 OMAP_MCBSP_REG_XCERF, 61 OMAP_MCBSP_REG_RCERG, 62 OMAP_MCBSP_REG_RCERH, 63 OMAP_MCBSP_REG_XCERG, 64 OMAP_MCBSP_REG_XCERH, 65 66 /* OMAP1-OMAP2420 registers */ 67 OMAP_MCBSP_REG_DRR2 = 0, 68 OMAP_MCBSP_REG_DRR1, 69 OMAP_MCBSP_REG_DXR2, 70 OMAP_MCBSP_REG_DXR1, 71 72 /* OMAP2430 and onwards */ 73 OMAP_MCBSP_REG_DRR = 0, 74 OMAP_MCBSP_REG_DXR = 2, 75 OMAP_MCBSP_REG_SYSCON = 35, 76 OMAP_MCBSP_REG_THRSH2, 77 OMAP_MCBSP_REG_THRSH1, 78 OMAP_MCBSP_REG_IRQST = 40, 79 OMAP_MCBSP_REG_IRQEN, 80 OMAP_MCBSP_REG_WAKEUPEN, 81 OMAP_MCBSP_REG_XCCR, 82 OMAP_MCBSP_REG_RCCR, 83 OMAP_MCBSP_REG_XBUFFSTAT, 84 OMAP_MCBSP_REG_RBUFFSTAT, 85 OMAP_MCBSP_REG_SSELCR, 86 }; 87 88 /* OMAP3 sidetone control registers */ 89 #define OMAP_ST_REG_REV 0x00 90 #define OMAP_ST_REG_SYSCONFIG 0x10 91 #define OMAP_ST_REG_IRQSTATUS 0x18 92 #define OMAP_ST_REG_IRQENABLE 0x1C 93 #define OMAP_ST_REG_SGAINCR 0x24 94 #define OMAP_ST_REG_SFIRCR 0x28 95 #define OMAP_ST_REG_SSELCR 0x2C 96 97 /************************** McBSP SPCR1 bit definitions ***********************/ 98 #define RRST BIT(0) 99 #define RRDY BIT(1) 100 #define RFULL BIT(2) 101 #define RSYNC_ERR BIT(3) 102 #define RINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ 103 #define ABIS BIT(6) 104 #define DXENA BIT(7) 105 #define CLKSTP(value) (((value) & 0x3) << 11) /* bits 11:12 */ 106 #define RJUST(value) (((value) & 0x3) << 13) /* bits 13:14 */ 107 #define ALB BIT(15) 108 #define DLB BIT(15) 109 110 /************************** McBSP SPCR2 bit definitions ***********************/ 111 #define XRST BIT(0) 112 #define XRDY BIT(1) 113 #define XEMPTY BIT(2) 114 #define XSYNC_ERR BIT(3) 115 #define XINTM(value) (((value) & 0x3) << 4) /* bits 4:5 */ 116 #define GRST BIT(6) 117 #define FRST BIT(7) 118 #define SOFT BIT(8) 119 #define FREE BIT(9) 120 121 /************************** McBSP PCR bit definitions *************************/ 122 #define CLKRP BIT(0) 123 #define CLKXP BIT(1) 124 #define FSRP BIT(2) 125 #define FSXP BIT(3) 126 #define DR_STAT BIT(4) 127 #define DX_STAT BIT(5) 128 #define CLKS_STAT BIT(6) 129 #define SCLKME BIT(7) 130 #define CLKRM BIT(8) 131 #define CLKXM BIT(9) 132 #define FSRM BIT(10) 133 #define FSXM BIT(11) 134 #define RIOEN BIT(12) 135 #define XIOEN BIT(13) 136 #define IDLE_EN BIT(14) 137 138 /************************** McBSP RCR1 bit definitions ************************/ 139 #define RWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ 140 #define RFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ 141 142 /************************** McBSP XCR1 bit definitions ************************/ 143 #define XWDLEN1(value) (((value) & 0x7) << 5) /* Bits 5:7 */ 144 #define XFRLEN1(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ 145 146 /*************************** McBSP RCR2 bit definitions ***********************/ 147 #define RDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ 148 #define RFIG BIT(2) 149 #define RCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ 150 #define RWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ 151 #define RFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ 152 #define RPHASE BIT(15) 153 154 /*************************** McBSP XCR2 bit definitions ***********************/ 155 #define XDATDLY(value) ((value) & 0x3) /* Bits 0:1 */ 156 #define XFIG BIT(2) 157 #define XCOMPAND(value) (((value) & 0x3) << 3) /* Bits 3:4 */ 158 #define XWDLEN2(value) (((value) & 0x7) << 5) /* Bits 5:7 */ 159 #define XFRLEN2(value) (((value) & 0x7f) << 8) /* Bits 8:14 */ 160 #define XPHASE BIT(15) 161 162 /************************* McBSP SRGR1 bit definitions ************************/ 163 #define CLKGDV(value) ((value) & 0x7f) /* Bits 0:7 */ 164 #define FWID(value) (((value) & 0xff) << 8) /* Bits 8:15 */ 165 166 /************************* McBSP SRGR2 bit definitions ************************/ 167 #define FPER(value) ((value) & 0x0fff) /* Bits 0:11 */ 168 #define FSGM BIT(12) 169 #define CLKSM BIT(13) 170 #define CLKSP BIT(14) 171 #define GSYNC BIT(15) 172 173 /************************* McBSP MCR1 bit definitions *************************/ 174 #define RMCM BIT(0) 175 #define RCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ 176 #define RPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ 177 #define RPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ 178 179 /************************* McBSP MCR2 bit definitions *************************/ 180 #define XMCM(value) ((value) & 0x3) /* Bits 0:1 */ 181 #define XCBLK(value) (((value) & 0x7) << 2) /* Bits 2:4 */ 182 #define XPABLK(value) (((value) & 0x3) << 5) /* Bits 5:6 */ 183 #define XPBBLK(value) (((value) & 0x3) << 7) /* Bits 7:8 */ 184 185 /*********************** McBSP XCCR bit definitions *************************/ 186 #define XDISABLE BIT(0) 187 #define XDMAEN BIT(3) 188 #define DILB BIT(5) 189 #define XFULL_CYCLE BIT(11) 190 #define DXENDLY(value) (((value) & 0x3) << 12) /* Bits 12:13 */ 191 #define PPCONNECT BIT(14) 192 #define EXTCLKGATE BIT(15) 193 194 /********************** McBSP RCCR bit definitions *************************/ 195 #define RDISABLE BIT(0) 196 #define RDMAEN BIT(3) 197 #define RFULL_CYCLE BIT(11) 198 199 /********************** McBSP SYSCONFIG bit definitions ********************/ 200 #define SOFTRST BIT(1) 201 #define ENAWAKEUP BIT(2) 202 #define SIDLEMODE(value) (((value) & 0x3) << 3) 203 #define CLOCKACTIVITY(value) (((value) & 0x3) << 8) 204 205 /********************** McBSP SSELCR bit definitions ***********************/ 206 #define SIDETONEEN BIT(10) 207 208 /********************** McBSP Sidetone SYSCONFIG bit definitions ***********/ 209 #define ST_AUTOIDLE BIT(0) 210 211 /********************** McBSP Sidetone SGAINCR bit definitions *************/ 212 #define ST_CH0GAIN(value) ((value) & 0xffff) /* Bits 0:15 */ 213 #define ST_CH1GAIN(value) (((value) & 0xffff) << 16) /* Bits 16:31 */ 214 215 /********************** McBSP Sidetone SFIRCR bit definitions **************/ 216 #define ST_FIRCOEFF(value) ((value) & 0xffff) /* Bits 0:15 */ 217 218 /********************** McBSP Sidetone SSELCR bit definitions **************/ 219 #define ST_SIDETONEEN BIT(0) 220 #define ST_COEFFWREN BIT(1) 221 #define ST_COEFFWRDONE BIT(2) 222 223 /********************** McBSP DMA operating modes **************************/ 224 #define MCBSP_DMA_MODE_ELEMENT 0 225 #define MCBSP_DMA_MODE_THRESHOLD 1 226 227 /********************** McBSP WAKEUPEN/IRQST/IRQEN bit definitions *********/ 228 #define RSYNCERREN BIT(0) 229 #define RFSREN BIT(1) 230 #define REOFEN BIT(2) 231 #define RRDYEN BIT(3) 232 #define RUNDFLEN BIT(4) 233 #define ROVFLEN BIT(5) 234 #define XSYNCERREN BIT(7) 235 #define XFSXEN BIT(8) 236 #define XEOFEN BIT(9) 237 #define XRDYEN BIT(10) 238 #define XUNDFLEN BIT(11) 239 #define XOVFLEN BIT(12) 240 #define XEMPTYEOFEN BIT(14) 241 242 /* Clock signal muxing options */ 243 #define CLKR_SRC_CLKR 0 /* CLKR signal is from the CLKR pin */ 244 #define CLKR_SRC_CLKX 1 /* CLKR signal is from the CLKX pin */ 245 #define FSR_SRC_FSR 2 /* FSR signal is from the FSR pin */ 246 #define FSR_SRC_FSX 3 /* FSR signal is from the FSX pin */ 247 248 /* McBSP functional clock sources */ 249 #define MCBSP_CLKS_PRCM_SRC 0 250 #define MCBSP_CLKS_PAD_SRC 1 251 252 /* we don't do multichannel for now */ 253 struct omap_mcbsp_reg_cfg { 254 u16 spcr2; 255 u16 spcr1; 256 u16 rcr2; 257 u16 rcr1; 258 u16 xcr2; 259 u16 xcr1; 260 u16 srgr2; 261 u16 srgr1; 262 u16 mcr2; 263 u16 mcr1; 264 u16 pcr0; 265 u16 rcerc; 266 u16 rcerd; 267 u16 xcerc; 268 u16 xcerd; 269 u16 rcere; 270 u16 rcerf; 271 u16 xcere; 272 u16 xcerf; 273 u16 rcerg; 274 u16 rcerh; 275 u16 xcerg; 276 u16 xcerh; 277 u16 xccr; 278 u16 rccr; 279 }; 280 281 struct omap_mcbsp_st_data { 282 void __iomem *io_base_st; 283 struct clk *mcbsp_iclk; 284 bool running; 285 bool enabled; 286 s16 taps[128]; /* Sidetone filter coefficients */ 287 int nr_taps; /* Number of filter coefficients in use */ 288 s16 ch0gain; 289 s16 ch1gain; 290 }; 291 292 struct omap_mcbsp { 293 struct device *dev; 294 struct clk *fclk; 295 spinlock_t lock; 296 unsigned long phys_base; 297 unsigned long phys_dma_base; 298 void __iomem *io_base; 299 u8 id; 300 /* 301 * Flags indicating is the bus already activated and configured by 302 * another substream 303 */ 304 int active; 305 int configured; 306 u8 free; 307 308 int irq; 309 int rx_irq; 310 int tx_irq; 311 312 /* Protect the field .free, while checking if the mcbsp is in use */ 313 struct omap_mcbsp_platform_data *pdata; 314 struct omap_mcbsp_st_data *st_data; 315 struct omap_mcbsp_reg_cfg cfg_regs; 316 struct snd_dmaengine_dai_dma_data dma_data[2]; 317 unsigned int dma_req[2]; 318 int dma_op_mode; 319 u16 max_tx_thres; 320 u16 max_rx_thres; 321 void *reg_cache; 322 int reg_cache_size; 323 324 unsigned int fmt; 325 unsigned int in_freq; 326 unsigned int latency[2]; 327 int clk_div; 328 int wlen; 329 330 struct pm_qos_request pm_qos_req; 331 }; 332 333 void omap_mcbsp_config(struct omap_mcbsp *mcbsp, 334 const struct omap_mcbsp_reg_cfg *config); 335 void omap_mcbsp_set_tx_threshold(struct omap_mcbsp *mcbsp, u16 threshold); 336 void omap_mcbsp_set_rx_threshold(struct omap_mcbsp *mcbsp, u16 threshold); 337 u16 omap_mcbsp_get_tx_delay(struct omap_mcbsp *mcbsp); 338 u16 omap_mcbsp_get_rx_delay(struct omap_mcbsp *mcbsp); 339 int omap_mcbsp_get_dma_op_mode(struct omap_mcbsp *mcbsp); 340 int omap_mcbsp_request(struct omap_mcbsp *mcbsp); 341 void omap_mcbsp_free(struct omap_mcbsp *mcbsp); 342 void omap_mcbsp_start(struct omap_mcbsp *mcbsp, int tx, int rx); 343 void omap_mcbsp_stop(struct omap_mcbsp *mcbsp, int tx, int rx); 344 345 /* McBSP functional clock source changing function */ 346 int omap2_mcbsp_set_clks_src(struct omap_mcbsp *mcbsp, u8 fck_src_id); 347 348 /* Sidetone specific API */ 349 int omap_st_set_chgain(struct omap_mcbsp *mcbsp, int channel, s16 chgain); 350 int omap_st_get_chgain(struct omap_mcbsp *mcbsp, int channel, s16 *chgain); 351 int omap_st_enable(struct omap_mcbsp *mcbsp); 352 int omap_st_disable(struct omap_mcbsp *mcbsp); 353 int omap_st_is_enabled(struct omap_mcbsp *mcbsp); 354 355 int omap_mcbsp_init(struct platform_device *pdev); 356 void omap_mcbsp_cleanup(struct omap_mcbsp *mcbsp); 357 358 #endif /* __ASOC_MCBSP_H */ 359
