1 /* SPDX-License-Identifier: GPL-2.0 */
2 // Copyright (c) 2017 Cadence
3 // Cadence PCIe controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
5
6 #ifndef _PCIE_CADENCE_H
7 #define _PCIE_CADENCE_H
8
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
11 #include <linux/phy/phy.h>
12
13 /* Parameters for the waiting for link up routine */
14 #define LINK_WAIT_MAX_RETRIES 10
15 #define LINK_WAIT_USLEEP_MIN 90000
16 #define LINK_WAIT_USLEEP_MAX 100000
17
18 /*
19 * Local Management Registers
20 */
21 #define CDNS_PCIE_LM_BASE 0x00100000
22
23 /* Vendor ID Register */
24 #define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044)
25 #define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0)
26 #define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0
27 #define CDNS_PCIE_LM_ID_VENDOR(vid) \
28 (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK)
29 #define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16)
30 #define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16
31 #define CDNS_PCIE_LM_ID_SUBSYS(sub) \
32 (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK)
33
34 /* Root Port Requestor ID Register */
35 #define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228)
36 #define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0)
37 #define CDNS_PCIE_LM_RP_RID_SHIFT 0
38 #define CDNS_PCIE_LM_RP_RID_(rid) \
39 (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK)
40
41 /* Endpoint Bus and Device Number Register */
42 #define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c)
43 #define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0)
44 #define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0
45 #define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8)
46 #define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8
47
48 /* Endpoint Function f BAR b Configuration Registers */
49 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \
50 (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008)
51 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \
52 (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008)
53 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \
54 (GENMASK(4, 0) << ((b) * 8))
55 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \
56 (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b))
57 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \
58 (GENMASK(7, 5) << ((b) * 8))
59 #define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \
60 (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b))
61
62 /* Endpoint Function Configuration Register */
63 #define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0)
64
65 /* Root Complex BAR Configuration Register */
66 #define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300)
67 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0)
68 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \
69 (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK)
70 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6)
71 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \
72 (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK)
73 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9)
74 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \
75 (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK)
76 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14)
77 #define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \
78 (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK)
79 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17)
80 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0
81 #define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18)
82 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19)
83 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0
84 #define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20)
85 #define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31)
86
87 /* BAR control values applicable to both Endpoint Function and Root Complex */
88 #define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0
89 #define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1
90 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4
91 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5
92 #define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6
93 #define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7
94
95 #define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
96 (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6))
97 #define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
98 (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6))
99 #define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
100 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6))
101 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
102 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6))
103 #define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
104 (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6))
105 #define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
106 (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6))
107 #define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
108 (((aperture) - 2) << ((bar) * 8))
109
110 /*
111 * Endpoint Function Registers (PCI configuration space for endpoint functions)
112 */
113 #define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
114
115 #define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90
116 #define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0
117
118 /*
119 * Root Port Registers (PCI configuration space for the root port function)
120 */
121 #define CDNS_PCIE_RP_BASE 0x00200000
122
123
124 /*
125 * Address Translation Registers
126 */
127 #define CDNS_PCIE_AT_BASE 0x00400000
128
129 /* Region r Outbound AXI to PCIe Address Translation Register 0 */
130 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
131 (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
132 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0)
133 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \
134 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK)
135 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
136 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
137 (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK)
138 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
139 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
140 (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
141
142 /* Region r Outbound AXI to PCIe Address Translation Register 1 */
143 #define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
144 (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
145
146 /* Region r Outbound PCIe Descriptor Register 0 */
147 #define CDNS_PCIE_AT_OB_REGION_DESC0(r) \
148 (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
149 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0)
150 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2
151 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6
152 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa
153 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb
154 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc
155 #define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd
156 /* Bit 23 MUST be set in RC mode. */
157 #define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
158 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
159 #define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
160 (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
161
162 /* Region r Outbound PCIe Descriptor Register 1 */
163 #define CDNS_PCIE_AT_OB_REGION_DESC1(r) \
164 (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
165 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0)
166 #define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \
167 ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK)
168
169 /* Region r AXI Region Base Address Register 0 */
170 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
171 (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
172 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0)
173 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \
174 (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK)
175
176 /* Region r AXI Region Base Address Register 1 */
177 #define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
178 (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
179
180 /* Root Port BAR Inbound PCIe to AXI Address Translation Register */
181 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \
182 (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008)
183 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0)
184 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \
185 (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK)
186 #define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \
187 (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008)
188
189 /* AXI link down register */
190 #define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824)
191
192 enum cdns_pcie_rp_bar {
193 RP_BAR_UNDEFINED = -1,
194 RP_BAR0,
195 RP_BAR1,
196 RP_NO_BAR
197 };
198
199 #define CDNS_PCIE_RP_MAX_IB 0x3
200
201 struct cdns_pcie_rp_ib_bar {
202 u64 size;
203 bool free;
204 };
205
206 /* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register */
207 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
208 (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
209 #define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
210 (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
211
212 /* Normal/Vendor specific message access: offset inside some outbound region */
213 #define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5)
214 #define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \
215 (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK)
216 #define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8)
217 #define CDNS_PCIE_NORMAL_MSG_CODE(code) \
218 (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK)
219 #define CDNS_PCIE_MSG_NO_DATA BIT(16)
220
221 struct cdns_pcie;
222
223 enum cdns_pcie_msg_code {
224 MSG_CODE_ASSERT_INTA = 0x20,
225 MSG_CODE_ASSERT_INTB = 0x21,
226 MSG_CODE_ASSERT_INTC = 0x22,
227 MSG_CODE_ASSERT_INTD = 0x23,
228 MSG_CODE_DEASSERT_INTA = 0x24,
229 MSG_CODE_DEASSERT_INTB = 0x25,
230 MSG_CODE_DEASSERT_INTC = 0x26,
231 MSG_CODE_DEASSERT_INTD = 0x27,
232 };
233
234 enum cdns_pcie_msg_routing {
235 /* Route to Root Complex */
236 MSG_ROUTING_TO_RC,
237
238 /* Use Address Routing */
239 MSG_ROUTING_BY_ADDR,
240
241 /* Use ID Routing */
242 MSG_ROUTING_BY_ID,
243
244 /* Route as Broadcast Message from Root Complex */
245 MSG_ROUTING_BCAST,
246
247 /* Local message; terminate at receiver (INTx messages) */
248 MSG_ROUTING_LOCAL,
249
250 /* Gather & route to Root Complex (PME_TO_Ack message) */
251 MSG_ROUTING_GATHER,
252 };
253
254 struct cdns_pcie_ops {
255 int (*start_link)(struct cdns_pcie *pcie);
256 void (*stop_link)(struct cdns_pcie *pcie);
257 bool (*link_up)(struct cdns_pcie *pcie);
258 u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr);
259 };
260
261 /**
262 * struct cdns_pcie - private data for Cadence PCIe controller drivers
263 * @reg_base: IO mapped register base
264 * @mem_res: start/end offsets in the physical system memory to map PCI accesses
265 * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoint.
266 * @bus: In Root Complex mode, the bus number
267 * @ops: Platform specific ops to control various inputs from Cadence PCIe
268 * wrapper
269 */
270 struct cdns_pcie {
271 void __iomem *reg_base;
272 struct resource *mem_res;
273 struct device *dev;
274 bool is_rc;
275 int phy_count;
276 struct phy **phy;
277 struct device_link **link;
278 const struct cdns_pcie_ops *ops;
279 };
280
281 /**
282 * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
283 * @pcie: Cadence PCIe controller
284 * @dev: pointer to PCIe device
285 * @cfg_res: start/end offsets in the physical system memory to map PCI
286 * configuration space accesses
287 * @cfg_base: IO mapped window to access the PCI configuration space of a
288 * single function at a time
289 * @vendor_id: PCI vendor ID
290 * @device_id: PCI device ID
291 * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or
292 * available
293 */
294 struct cdns_pcie_rc {
295 struct cdns_pcie pcie;
296 struct resource *cfg_res;
297 void __iomem *cfg_base;
298 u32 vendor_id;
299 u32 device_id;
300 bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB];
301 };
302
303 /**
304 * struct cdns_pcie_epf - Structure to hold info about endpoint function
305 * @epf_bar: reference to the pci_epf_bar for the six Base Address Registers
306 */
307 struct cdns_pcie_epf {
308 struct pci_epf_bar *epf_bar[PCI_STD_NUM_BARS];
309 };
310
311 /**
312 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
313 * @pcie: Cadence PCIe controller
314 * @max_regions: maximum number of regions supported by hardware
315 * @ob_region_map: bitmask of mapped outbound regions
316 * @ob_addr: base addresses in the AXI bus where the outbound regions start
317 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
318 * dedicated outbound regions is mapped.
319 * @irq_cpu_addr: base address in the CPU space where a write access triggers
320 * the sending of a memory write (MSI) / normal message (legacy
321 * IRQ) TLP through the PCIe bus.
322 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
323 * dedicated outbound region.
324 * @irq_pci_fn: the latest PCI function that has updated the mapping of
325 * the MSI/legacy IRQ dedicated outbound region.
326 * @irq_pending: bitmask of asserted legacy IRQs.
327 * @lock: spin lock to disable interrupts while modifying PCIe controller
328 * registers fields (RMW) accessible by both remote RC and EP to
329 * minimize time between read and write
330 * @epf: Structure to hold info about endpoint function
331 */
332 struct cdns_pcie_ep {
333 struct cdns_pcie pcie;
334 u32 max_regions;
335 unsigned long ob_region_map;
336 phys_addr_t *ob_addr;
337 phys_addr_t irq_phys_addr;
338 void __iomem *irq_cpu_addr;
339 u64 irq_pci_addr;
340 u8 irq_pci_fn;
341 u8 irq_pending;
342 /* protect writing to PCI_STATUS while raising legacy interrupts */
343 spinlock_t lock;
344 struct cdns_pcie_epf *epf;
345 };
346
347
348 /* Register access */
cdns_pcie_writel(struct cdns_pcie * pcie,u32 reg,u32 value)349 static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value)
350 {
351 writel(value, pcie->reg_base + reg);
352 }
353
cdns_pcie_readl(struct cdns_pcie * pcie,u32 reg)354 static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg)
355 {
356 return readl(pcie->reg_base + reg);
357 }
358
cdns_pcie_read_sz(void __iomem * addr,int size)359 static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size)
360 {
361 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
362 unsigned int offset = (unsigned long)addr & 0x3;
363 u32 val = readl(aligned_addr);
364
365 if (!IS_ALIGNED((uintptr_t)addr, size)) {
366 pr_warn("Address %p and size %d are not aligned\n", addr, size);
367 return 0;
368 }
369
370 if (size > 2)
371 return val;
372
373 return (val >> (8 * offset)) & ((1 << (size * 8)) - 1);
374 }
375
cdns_pcie_write_sz(void __iomem * addr,int size,u32 value)376 static inline void cdns_pcie_write_sz(void __iomem *addr, int size, u32 value)
377 {
378 void __iomem *aligned_addr = PTR_ALIGN_DOWN(addr, 0x4);
379 unsigned int offset = (unsigned long)addr & 0x3;
380 u32 mask;
381 u32 val;
382
383 if (!IS_ALIGNED((uintptr_t)addr, size)) {
384 pr_warn("Address %p and size %d are not aligned\n", addr, size);
385 return;
386 }
387
388 if (size > 2) {
389 writel(value, addr);
390 return;
391 }
392
393 mask = ~(((1 << (size * 8)) - 1) << (offset * 8));
394 val = readl(aligned_addr) & mask;
395 val |= value << (offset * 8);
396 writel(val, aligned_addr);
397 }
398
399 /* Root Port register access */
cdns_pcie_rp_writeb(struct cdns_pcie * pcie,u32 reg,u8 value)400 static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie,
401 u32 reg, u8 value)
402 {
403 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
404
405 cdns_pcie_write_sz(addr, 0x1, value);
406 }
407
cdns_pcie_rp_writew(struct cdns_pcie * pcie,u32 reg,u16 value)408 static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie,
409 u32 reg, u16 value)
410 {
411 void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg;
412
413 cdns_pcie_write_sz(addr, 0x2, value);
414 }
415
416 /* Endpoint Function register access */
cdns_pcie_ep_fn_writeb(struct cdns_pcie * pcie,u8 fn,u32 reg,u8 value)417 static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn,
418 u32 reg, u8 value)
419 {
420 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
421
422 cdns_pcie_write_sz(addr, 0x1, value);
423 }
424
cdns_pcie_ep_fn_writew(struct cdns_pcie * pcie,u8 fn,u32 reg,u16 value)425 static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn,
426 u32 reg, u16 value)
427 {
428 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
429
430 cdns_pcie_write_sz(addr, 0x2, value);
431 }
432
cdns_pcie_ep_fn_writel(struct cdns_pcie * pcie,u8 fn,u32 reg,u32 value)433 static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn,
434 u32 reg, u32 value)
435 {
436 writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
437 }
438
cdns_pcie_ep_fn_readw(struct cdns_pcie * pcie,u8 fn,u32 reg)439 static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg)
440 {
441 void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg;
442
443 return cdns_pcie_read_sz(addr, 0x2);
444 }
445
cdns_pcie_ep_fn_readl(struct cdns_pcie * pcie,u8 fn,u32 reg)446 static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg)
447 {
448 return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
449 }
450
cdns_pcie_start_link(struct cdns_pcie * pcie)451 static inline int cdns_pcie_start_link(struct cdns_pcie *pcie)
452 {
453 if (pcie->ops->start_link)
454 return pcie->ops->start_link(pcie);
455
456 return 0;
457 }
458
cdns_pcie_stop_link(struct cdns_pcie * pcie)459 static inline void cdns_pcie_stop_link(struct cdns_pcie *pcie)
460 {
461 if (pcie->ops->stop_link)
462 pcie->ops->stop_link(pcie);
463 }
464
cdns_pcie_link_up(struct cdns_pcie * pcie)465 static inline bool cdns_pcie_link_up(struct cdns_pcie *pcie)
466 {
467 if (pcie->ops->link_up)
468 return pcie->ops->link_up(pcie);
469
470 return true;
471 }
472
473 #ifdef CONFIG_PCIE_CADENCE_HOST
474 int cdns_pcie_host_setup(struct cdns_pcie_rc *rc);
475 void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
476 int where);
477 #else
cdns_pcie_host_setup(struct cdns_pcie_rc * rc)478 static inline int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
479 {
480 return 0;
481 }
482
cdns_pci_map_bus(struct pci_bus * bus,unsigned int devfn,int where)483 static inline void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn,
484 int where)
485 {
486 return NULL;
487 }
488 #endif
489
490 #ifdef CONFIG_PCIE_CADENCE_EP
491 int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep);
492 #else
cdns_pcie_ep_setup(struct cdns_pcie_ep * ep)493 static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep)
494 {
495 return 0;
496 }
497 #endif
498 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn,
499 u32 r, bool is_io,
500 u64 cpu_addr, u64 pci_addr, size_t size);
501
502 void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie,
503 u8 busnr, u8 fn,
504 u32 r, u64 cpu_addr);
505
506 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r);
507 void cdns_pcie_disable_phy(struct cdns_pcie *pcie);
508 int cdns_pcie_enable_phy(struct cdns_pcie *pcie);
509 int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie);
510 extern const struct dev_pm_ops cdns_pcie_pm_ops;
511
512 #endif /* _PCIE_CADENCE_H */
513
