1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /****************************************************************************** 3 * 4 * Copyright(c) 2016 Realtek Corporation. 5 * 6 * Contact Information: 7 * wlanfae <wlanfae@realtek.com> 8 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 9 * Hsinchu 300, Taiwan. 10 * 11 * Larry Finger <Larry.Finger@lwfinger.net> 12 * 13 *****************************************************************************/ 14 #ifndef __RTL_WLAN_BITDEF_H__ 15 #define __RTL_WLAN_BITDEF_H__ 16 17 /*-------------------------Modification Log----------------------------------- 18 * Base on MAC_Register.doc SVN391 19 *-------------------------Modification Log----------------------------------- 20 */ 21 22 /*--------------------------Include File--------------------------------------*/ 23 /*--------------------------Include File--------------------------------------*/ 24 25 /* 3 ============Programming guide Start===================== */ 26 /* 27 * 1. For all bit define, it should be prefixed by "BIT_" 28 * 2. For all bit mask, it should be prefixed by "BIT_MASK_" 29 * 3. For all bit shift, it should be prefixed by "BIT_SHIFT_" 30 * 4. For other case, prefix is not needed 31 * 32 * Example: 33 * #define BIT_SHIFT_MAX_TXDMA 16 34 * #define BIT_MASK_MAX_TXDMA 0x7 35 * #define BIT_MAX_TXDMA(x) \ 36 * (((x) & BIT_MASK_MAX_TXDMA) << BIT_SHIFT_MAX_TXDMA) 37 * #define BIT_GET_MAX_TXDMA(x) \ 38 * (((x) >> BIT_SHIFT_MAX_TXDMA) & BIT_MASK_MAX_TXDMA) 39 * 40 */ 41 /* 3 ============Programming guide End===================== */ 42 43 #define CPU_OPT_WIDTH 0x1F 44 45 #define BIT_SHIFT_WATCH_DOG_RECORD_V1 10 46 #define BIT_MASK_WATCH_DOG_RECORD_V1 0x3fff 47 #define BIT_WATCH_DOG_RECORD_V1(x) \ 48 (((x) & BIT_MASK_WATCH_DOG_RECORD_V1) << BIT_SHIFT_WATCH_DOG_RECORD_V1) 49 #define BIT_GET_WATCH_DOG_RECORD_V1(x) \ 50 (((x) >> BIT_SHIFT_WATCH_DOG_RECORD_V1) & BIT_MASK_WATCH_DOG_RECORD_V1) 51 52 #define BIT_R_IO_TIMEOUT_FLAG_V1 BIT(9) 53 54 #define BIT_ISO_MD2PP BIT(0) 55 56 #define BIT_SHIFT_R_WMAC_IPV6_MYIPAD 0 57 #define BIT_MASK_R_WMAC_IPV6_MYIPAD 0xffffffffffffffffffffffffffffffffL 58 #define BIT_R_WMAC_IPV6_MYIPAD(x) \ 59 (((x) & BIT_MASK_R_WMAC_IPV6_MYIPAD) << BIT_SHIFT_R_WMAC_IPV6_MYIPAD) 60 #define BIT_GET_R_WMAC_IPV6_MYIPAD(x) \ 61 (((x) >> BIT_SHIFT_R_WMAC_IPV6_MYIPAD) & BIT_MASK_R_WMAC_IPV6_MYIPAD) 62 63 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 64 65 #define BIT_SHIFT_SDIO_INT_TIMEOUT 16 66 #define BIT_MASK_SDIO_INT_TIMEOUT 0xffff 67 #define BIT_SDIO_INT_TIMEOUT(x) \ 68 (((x) & BIT_MASK_SDIO_INT_TIMEOUT) << BIT_SHIFT_SDIO_INT_TIMEOUT) 69 #define BIT_GET_SDIO_INT_TIMEOUT(x) \ 70 (((x) >> BIT_SHIFT_SDIO_INT_TIMEOUT) & BIT_MASK_SDIO_INT_TIMEOUT) 71 72 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 73 74 #define BIT_PWC_EV12V BIT(15) 75 76 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 77 78 #define BIT_IO_ERR_STATUS BIT(15) 79 80 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 81 82 #define BIT_PWC_EV25V BIT(14) 83 84 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 85 86 #define BIT_PA33V_EN BIT(13) 87 #define BIT_PA12V_EN BIT(12) 88 89 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 90 91 #define BIT_UA33V_EN BIT(11) 92 #define BIT_UA12V_EN BIT(10) 93 94 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 95 96 #define BIT_ISO_RFDIO BIT(9) 97 98 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 99 100 #define BIT_REPLY_ERRCRC_IN_DATA BIT(9) 101 102 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 103 104 #define BIT_ISO_EB2CORE BIT(8) 105 106 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 107 108 #define BIT_EN_CMD53_OVERLAP BIT(8) 109 110 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 111 112 #define BIT_ISO_DIOE BIT(7) 113 114 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 115 116 #define BIT_REPLY_ERR_IN_R5 BIT(7) 117 118 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 119 120 #define BIT_ISO_WLPON2PP BIT(6) 121 122 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 123 124 #define BIT_R18A_EN BIT(6) 125 126 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 127 128 #define BIT_ISO_IP2MAC_WA2PP BIT(5) 129 130 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 131 132 #define BIT_INIT_CMD_EN BIT(5) 133 134 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 135 136 #define BIT_ISO_PD2CORE BIT(4) 137 138 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 139 140 #define BIT_ISO_PA2PCIE BIT(3) 141 142 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 143 144 #define BIT_ISO_UD2CORE BIT(2) 145 146 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 147 148 #define BIT_EN_RXDMA_MASK_INT BIT(2) 149 150 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 151 152 #define BIT_ISO_UA2USB BIT(1) 153 154 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 155 156 #define BIT_EN_MASK_TIMER BIT(1) 157 158 /* 2 REG_SYS_ISO_CTRL (Offset 0x0000) */ 159 160 #define BIT_ISO_WD2PP BIT(0) 161 162 /* 2 REG_SDIO_TX_CTRL (Offset 0x10250000) */ 163 164 #define BIT_CMD_ERR_STOP_INT_EN BIT(0) 165 166 /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 167 168 #define BIT_FEN_MREGEN BIT(15) 169 #define BIT_FEN_HWPDN BIT(14) 170 171 /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 172 173 #define BIT_EN_25_1 BIT(13) 174 175 /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 176 177 #define BIT_FEN_ELDR BIT(12) 178 #define BIT_FEN_DCORE BIT(11) 179 #define BIT_FEN_CPUEN BIT(10) 180 #define BIT_FEN_DIOE BIT(9) 181 #define BIT_FEN_PCIED BIT(8) 182 #define BIT_FEN_PPLL BIT(7) 183 #define BIT_FEN_PCIEA BIT(6) 184 #define BIT_FEN_DIO_PCIE BIT(5) 185 #define BIT_FEN_USBD BIT(4) 186 #define BIT_FEN_UPLL BIT(3) 187 #define BIT_FEN_USBA BIT(2) 188 189 /* 2 REG_SYS_FUNC_EN (Offset 0x0002) */ 190 191 #define BIT_FEN_BB_GLB_RSTN BIT(1) 192 #define BIT_FEN_BBRSTB BIT(0) 193 194 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 195 196 #define BIT_SOP_EABM BIT(31) 197 198 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 199 200 #define BIT_SOP_ACKF BIT(30) 201 #define BIT_SOP_ERCK BIT(29) 202 203 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 204 205 #define BIT_SOP_ESWR BIT(28) 206 207 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 208 209 #define BIT_SOP_PWMM BIT(27) 210 211 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 212 213 #define BIT_SOP_EECK BIT(26) 214 215 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 216 217 #define BIT_SOP_EXTL BIT(24) 218 219 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 220 221 #define BIT_SYM_OP_RING_12M BIT(22) 222 223 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 224 225 #define BIT_ROP_SWPR BIT(21) 226 227 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 228 229 #define BIT_DIS_HW_LPLDM BIT(20) 230 231 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 232 233 #define BIT_OPT_SWRST_WLMCU BIT(19) 234 #define BIT_RDY_SYSPWR BIT(17) 235 236 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 237 238 #define BIT_EN_WLON BIT(16) 239 240 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 241 242 #define BIT_APDM_HPDN BIT(15) 243 244 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 245 246 #define BIT_AFSM_PCIE_SUS_EN BIT(12) 247 248 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 249 250 #define BIT_AFSM_WLSUS_EN BIT(11) 251 252 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 253 254 #define BIT_APFM_SWLPS BIT(10) 255 256 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 257 258 #define BIT_APFM_OFFMAC BIT(9) 259 #define BIT_APFN_ONMAC BIT(8) 260 261 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 262 263 #define BIT_CHIP_PDN_EN BIT(7) 264 265 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 266 267 #define BIT_RDY_MACDIS BIT(6) 268 269 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 270 271 #define BIT_RING_CLK_12M_EN BIT(4) 272 273 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 274 275 #define BIT_PFM_WOWL BIT(3) 276 277 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 278 279 #define BIT_PFM_LDKP BIT(2) 280 281 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 282 283 #define BIT_WL_HCI_ALD BIT(1) 284 285 /* 2 REG_SYS_PW_CTRL (Offset 0x0004) */ 286 287 #define BIT_PFM_LDALL BIT(0) 288 289 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 290 291 #define BIT_LDO_DUMMY BIT(15) 292 293 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 294 295 #define BIT_CPU_CLK_EN BIT(14) 296 297 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 298 299 #define BIT_SYMREG_CLK_EN BIT(13) 300 301 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 302 303 #define BIT_HCI_CLK_EN BIT(12) 304 305 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 306 307 #define BIT_MAC_CLK_EN BIT(11) 308 #define BIT_SEC_CLK_EN BIT(10) 309 310 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 311 312 #define BIT_PHY_SSC_RSTB BIT(9) 313 #define BIT_EXT_32K_EN BIT(8) 314 315 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 316 317 #define BIT_WL_CLK_TEST BIT(7) 318 #define BIT_OP_SPS_PWM_EN BIT(6) 319 320 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 321 322 #define BIT_LOADER_CLK_EN BIT(5) 323 #define BIT_MACSLP BIT(4) 324 #define BIT_WAKEPAD_EN BIT(3) 325 #define BIT_ROMD16V_EN BIT(2) 326 327 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 328 329 #define BIT_CKANA12M_EN BIT(1) 330 331 /* 2 REG_SYS_CLK_CTRL (Offset 0x0008) */ 332 333 #define BIT_CNTD16V_EN BIT(0) 334 335 /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ 336 337 #define BIT_SHIFT_VPDIDX 8 338 #define BIT_MASK_VPDIDX 0xff 339 #define BIT_VPDIDX(x) (((x) & BIT_MASK_VPDIDX) << BIT_SHIFT_VPDIDX) 340 #define BIT_GET_VPDIDX(x) (((x) >> BIT_SHIFT_VPDIDX) & BIT_MASK_VPDIDX) 341 342 #define BIT_SHIFT_EEM1_0 6 343 #define BIT_MASK_EEM1_0 0x3 344 #define BIT_EEM1_0(x) (((x) & BIT_MASK_EEM1_0) << BIT_SHIFT_EEM1_0) 345 #define BIT_GET_EEM1_0(x) (((x) >> BIT_SHIFT_EEM1_0) & BIT_MASK_EEM1_0) 346 347 #define BIT_AUTOLOAD_SUS BIT(5) 348 349 /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ 350 351 #define BIT_EERPOMSEL BIT(4) 352 353 /* 2 REG_SYS_EEPROM_CTRL (Offset 0x000A) */ 354 355 #define BIT_EECS_V1 BIT(3) 356 #define BIT_EESK_V1 BIT(2) 357 #define BIT_EEDI_V1 BIT(1) 358 #define BIT_EEDO_V1 BIT(0) 359 360 /* 2 REG_EE_VPD (Offset 0x000C) */ 361 362 #define BIT_SHIFT_VPD_DATA 0 363 #define BIT_MASK_VPD_DATA 0xffffffffL 364 #define BIT_VPD_DATA(x) (((x) & BIT_MASK_VPD_DATA) << BIT_SHIFT_VPD_DATA) 365 #define BIT_GET_VPD_DATA(x) (((x) >> BIT_SHIFT_VPD_DATA) & BIT_MASK_VPD_DATA) 366 367 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 368 369 #define BIT_C2_L_BIT0 BIT(31) 370 371 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 372 373 #define BIT_SHIFT_C1_L 29 374 #define BIT_MASK_C1_L 0x3 375 #define BIT_C1_L(x) (((x) & BIT_MASK_C1_L) << BIT_SHIFT_C1_L) 376 #define BIT_GET_C1_L(x) (((x) >> BIT_SHIFT_C1_L) & BIT_MASK_C1_L) 377 378 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 379 380 #define BIT_SHIFT_REG_FREQ_L 25 381 #define BIT_MASK_REG_FREQ_L 0x7 382 #define BIT_REG_FREQ_L(x) (((x) & BIT_MASK_REG_FREQ_L) << BIT_SHIFT_REG_FREQ_L) 383 #define BIT_GET_REG_FREQ_L(x) \ 384 (((x) >> BIT_SHIFT_REG_FREQ_L) & BIT_MASK_REG_FREQ_L) 385 386 #define BIT_REG_EN_DUTY BIT(24) 387 388 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 389 390 #define BIT_SHIFT_REG_MODE 22 391 #define BIT_MASK_REG_MODE 0x3 392 #define BIT_REG_MODE(x) (((x) & BIT_MASK_REG_MODE) << BIT_SHIFT_REG_MODE) 393 #define BIT_GET_REG_MODE(x) (((x) >> BIT_SHIFT_REG_MODE) & BIT_MASK_REG_MODE) 394 395 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 396 397 #define BIT_REG_EN_SP BIT(21) 398 #define BIT_REG_AUTO_L BIT(20) 399 400 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 401 402 #define BIT_SW18_SELD_BIT0 BIT(19) 403 404 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 405 406 #define BIT_SW18_POWOCP BIT(18) 407 408 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 409 410 #define BIT_SHIFT_OCP_L1 15 411 #define BIT_MASK_OCP_L1 0x7 412 #define BIT_OCP_L1(x) (((x) & BIT_MASK_OCP_L1) << BIT_SHIFT_OCP_L1) 413 #define BIT_GET_OCP_L1(x) (((x) >> BIT_SHIFT_OCP_L1) & BIT_MASK_OCP_L1) 414 415 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 416 417 #define BIT_SHIFT_CF_L 13 418 #define BIT_MASK_CF_L 0x3 419 #define BIT_CF_L(x) (((x) & BIT_MASK_CF_L) << BIT_SHIFT_CF_L) 420 #define BIT_GET_CF_L(x) (((x) >> BIT_SHIFT_CF_L) & BIT_MASK_CF_L) 421 422 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 423 424 #define BIT_SW18_FPWM BIT(11) 425 426 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 427 428 #define BIT_SW18_SWEN BIT(9) 429 #define BIT_SW18_LDEN BIT(8) 430 #define BIT_MAC_ID_EN BIT(7) 431 432 /* 2 REG_SYS_SWR_CTRL1 (Offset 0x0010) */ 433 434 #define BIT_AFE_BGEN BIT(0) 435 436 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 437 438 #define BIT_POW_ZCD_L BIT(31) 439 440 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 441 442 #define BIT_SDIO_CRCERR_MSK BIT(31) 443 444 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 445 446 #define BIT_AUTOZCD_L BIT(30) 447 #define BIT_SDIO_HSISR3_IND_MSK BIT(30) 448 #define BIT_SDIO_HSISR2_IND_MSK BIT(29) 449 450 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 451 452 #define BIT_SHIFT_REG_DELAY 28 453 #define BIT_MASK_REG_DELAY 0x3 454 #define BIT_REG_DELAY(x) (((x) & BIT_MASK_REG_DELAY) << BIT_SHIFT_REG_DELAY) 455 #define BIT_GET_REG_DELAY(x) (((x) >> BIT_SHIFT_REG_DELAY) & BIT_MASK_REG_DELAY) 456 457 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 458 459 #define BIT_SDIO_HEISR_IND_MSK BIT(28) 460 461 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 462 463 #define BIT_SDIO_CTWEND_MSK BIT(27) 464 #define BIT_SDIO_ATIMEND_E_MSK BIT(26) 465 466 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 467 468 #define BIT_SDIIO_ATIMEND_MSK BIT(25) 469 470 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 471 472 #define BIT_SDIO_OCPINT_MSK BIT(24) 473 474 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 475 476 #define BIT_SHIFT_V15ADJ_L1_V1 24 477 #define BIT_MASK_V15ADJ_L1_V1 0x7 478 #define BIT_V15ADJ_L1_V1(x) \ 479 (((x) & BIT_MASK_V15ADJ_L1_V1) << BIT_SHIFT_V15ADJ_L1_V1) 480 #define BIT_GET_V15ADJ_L1_V1(x) \ 481 (((x) >> BIT_SHIFT_V15ADJ_L1_V1) & BIT_MASK_V15ADJ_L1_V1) 482 483 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 484 485 #define BIT_SDIO_PSTIMEOUT_MSK BIT(23) 486 487 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 488 489 #define BIT_SDIO_GTINT4_MSK BIT(22) 490 491 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 492 493 #define BIT_SDIO_GTINT3_MSK BIT(21) 494 495 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 496 497 #define BIT_SDIO_HSISR_IND_MSK BIT(20) 498 499 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 500 501 #define BIT_SHIFT_VOL_L1_V1 20 502 #define BIT_MASK_VOL_L1_V1 0xf 503 #define BIT_VOL_L1_V1(x) (((x) & BIT_MASK_VOL_L1_V1) << BIT_SHIFT_VOL_L1_V1) 504 #define BIT_GET_VOL_L1_V1(x) (((x) >> BIT_SHIFT_VOL_L1_V1) & BIT_MASK_VOL_L1_V1) 505 506 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 507 508 #define BIT_SDIO_CPWM2_MSK BIT(19) 509 510 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 511 512 #define BIT_SDIO_CPWM1_MSK BIT(18) 513 514 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 515 516 #define BIT_SDIO_C2HCMD_INT_MSK BIT(17) 517 518 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 519 520 #define BIT_SHIFT_IN_L1_V1 17 521 #define BIT_MASK_IN_L1_V1 0x7 522 #define BIT_IN_L1_V1(x) (((x) & BIT_MASK_IN_L1_V1) << BIT_SHIFT_IN_L1_V1) 523 #define BIT_GET_IN_L1_V1(x) (((x) >> BIT_SHIFT_IN_L1_V1) & BIT_MASK_IN_L1_V1) 524 525 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 526 527 #define BIT_SDIO_BCNERLY_INT_MSK BIT(16) 528 529 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 530 531 #define BIT_SHIFT_TBOX_L1 15 532 #define BIT_MASK_TBOX_L1 0x3 533 #define BIT_TBOX_L1(x) (((x) & BIT_MASK_TBOX_L1) << BIT_SHIFT_TBOX_L1) 534 #define BIT_GET_TBOX_L1(x) (((x) >> BIT_SHIFT_TBOX_L1) & BIT_MASK_TBOX_L1) 535 536 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 537 538 #define BIT_SW18_SEL BIT(13) 539 540 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 541 542 #define BIT_SW18_SD BIT(10) 543 544 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 545 546 #define BIT_SDIO_TXBCNERR_MSK BIT(7) 547 548 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 549 550 #define BIT_SHIFT_R3_L 7 551 #define BIT_MASK_R3_L 0x3 552 #define BIT_R3_L(x) (((x) & BIT_MASK_R3_L) << BIT_SHIFT_R3_L) 553 #define BIT_GET_R3_L(x) (((x) >> BIT_SHIFT_R3_L) & BIT_MASK_R3_L) 554 555 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 556 557 #define BIT_SDIO_TXBCNOK_MSK BIT(6) 558 559 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 560 561 #define BIT_SHIFT_SW18_R2 5 562 #define BIT_MASK_SW18_R2 0x3 563 #define BIT_SW18_R2(x) (((x) & BIT_MASK_SW18_R2) << BIT_SHIFT_SW18_R2) 564 #define BIT_GET_SW18_R2(x) (((x) >> BIT_SHIFT_SW18_R2) & BIT_MASK_SW18_R2) 565 566 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 567 568 #define BIT_SDIO_RXFOVW_MSK BIT(5) 569 #define BIT_SDIO_TXFOVW_MSK BIT(4) 570 571 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 572 573 #define BIT_SHIFT_SW18_R1 3 574 #define BIT_MASK_SW18_R1 0x3 575 #define BIT_SW18_R1(x) (((x) & BIT_MASK_SW18_R1) << BIT_SHIFT_SW18_R1) 576 #define BIT_GET_SW18_R1(x) (((x) >> BIT_SHIFT_SW18_R1) & BIT_MASK_SW18_R1) 577 578 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 579 580 #define BIT_SDIO_RXERR_MSK BIT(3) 581 #define BIT_SDIO_TXERR_MSK BIT(2) 582 583 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 584 585 #define BIT_SDIO_AVAL_MSK BIT(1) 586 587 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 588 589 #define BIT_SHIFT_C3_L_C3 1 590 #define BIT_MASK_C3_L_C3 0x3 591 #define BIT_C3_L_C3(x) (((x) & BIT_MASK_C3_L_C3) << BIT_SHIFT_C3_L_C3) 592 #define BIT_GET_C3_L_C3(x) (((x) >> BIT_SHIFT_C3_L_C3) & BIT_MASK_C3_L_C3) 593 594 /* 2 REG_SDIO_HIMR (Offset 0x10250014) */ 595 596 #define BIT_RX_REQUEST_MSK BIT(0) 597 598 /* 2 REG_SYS_SWR_CTRL2 (Offset 0x0014) */ 599 600 #define BIT_C2_L_BIT1 BIT(0) 601 602 /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ 603 604 #define BIT_SPS18_OCP_DIS BIT(31) 605 606 /* 2 REG_SDIO_HISR (Offset 0x10250018) */ 607 608 #define BIT_SDIO_CRCERR BIT(31) 609 610 /* 2 REG_SDIO_HISR (Offset 0x10250018) */ 611 612 #define BIT_SDIO_HSISR3_IND BIT(30) 613 #define BIT_SDIO_HSISR2_IND BIT(29) 614 #define BIT_SDIO_HEISR_IND BIT(28) 615 616 /* 2 REG_SDIO_HISR (Offset 0x10250018) */ 617 618 #define BIT_SDIO_CTWEND BIT(27) 619 #define BIT_SDIO_ATIMEND_E BIT(26) 620 #define BIT_SDIO_ATIMEND BIT(25) 621 #define BIT_SDIO_OCPINT BIT(24) 622 #define BIT_SDIO_PSTIMEOUT BIT(23) 623 #define BIT_SDIO_GTINT4 BIT(22) 624 #define BIT_SDIO_GTINT3 BIT(21) 625 #define BIT_SDIO_HSISR_IND BIT(20) 626 #define BIT_SDIO_CPWM2 BIT(19) 627 #define BIT_SDIO_CPWM1 BIT(18) 628 #define BIT_SDIO_C2HCMD_INT BIT(17) 629 630 /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ 631 632 #define BIT_SHIFT_SPS18_OCP_TH 16 633 #define BIT_MASK_SPS18_OCP_TH 0x7fff 634 #define BIT_SPS18_OCP_TH(x) \ 635 (((x) & BIT_MASK_SPS18_OCP_TH) << BIT_SHIFT_SPS18_OCP_TH) 636 #define BIT_GET_SPS18_OCP_TH(x) \ 637 (((x) >> BIT_SHIFT_SPS18_OCP_TH) & BIT_MASK_SPS18_OCP_TH) 638 639 /* 2 REG_SDIO_HISR (Offset 0x10250018) */ 640 641 #define BIT_SDIO_BCNERLY_INT BIT(16) 642 #define BIT_SDIO_TXBCNERR BIT(7) 643 #define BIT_SDIO_TXBCNOK BIT(6) 644 #define BIT_SDIO_RXFOVW BIT(5) 645 #define BIT_SDIO_TXFOVW BIT(4) 646 #define BIT_SDIO_RXERR BIT(3) 647 #define BIT_SDIO_TXERR BIT(2) 648 #define BIT_SDIO_AVAL BIT(1) 649 650 /* 2 REG_SYS_SWR_CTRL3 (Offset 0x0018) */ 651 652 #define BIT_SHIFT_OCP_WINDOW 0 653 #define BIT_MASK_OCP_WINDOW 0xffff 654 #define BIT_OCP_WINDOW(x) (((x) & BIT_MASK_OCP_WINDOW) << BIT_SHIFT_OCP_WINDOW) 655 #define BIT_GET_OCP_WINDOW(x) \ 656 (((x) >> BIT_SHIFT_OCP_WINDOW) & BIT_MASK_OCP_WINDOW) 657 658 /* 2 REG_SDIO_HISR (Offset 0x10250018) */ 659 660 #define BIT_RX_REQUEST BIT(0) 661 662 /* 2 REG_RSV_CTRL (Offset 0x001C) */ 663 664 #define BIT_HREG_DBG BIT(23) 665 666 /* 2 REG_RSV_CTRL (Offset 0x001C) */ 667 668 #define BIT_WLMCUIOIF BIT(8) 669 670 /* 2 REG_RSV_CTRL (Offset 0x001C) */ 671 672 #define BIT_LOCK_ALL_EN BIT(7) 673 674 /* 2 REG_RSV_CTRL (Offset 0x001C) */ 675 676 #define BIT_R_DIS_PRST BIT(6) 677 678 /* 2 REG_RSV_CTRL (Offset 0x001C) */ 679 680 #define BIT_WLOCK_1C_B6 BIT(5) 681 682 /* 2 REG_RSV_CTRL (Offset 0x001C) */ 683 684 #define BIT_WLOCK_40 BIT(4) 685 #define BIT_WLOCK_08 BIT(3) 686 #define BIT_WLOCK_04 BIT(2) 687 #define BIT_WLOCK_00 BIT(1) 688 #define BIT_WLOCK_ALL BIT(0) 689 690 /* 2 REG_SDIO_RX_REQ_LEN (Offset 0x1025001C) */ 691 692 #define BIT_SHIFT_RX_REQ_LEN_V1 0 693 #define BIT_MASK_RX_REQ_LEN_V1 0x3ffff 694 #define BIT_RX_REQ_LEN_V1(x) \ 695 (((x) & BIT_MASK_RX_REQ_LEN_V1) << BIT_SHIFT_RX_REQ_LEN_V1) 696 #define BIT_GET_RX_REQ_LEN_V1(x) \ 697 (((x) >> BIT_SHIFT_RX_REQ_LEN_V1) & BIT_MASK_RX_REQ_LEN_V1) 698 699 /* 2 REG_RF_CTRL (Offset 0x001F) */ 700 701 #define BIT_RF_SDMRSTB BIT(2) 702 703 /* 2 REG_RF_CTRL (Offset 0x001F) */ 704 705 #define BIT_RF_RSTB BIT(1) 706 707 /* 2 REG_RF_CTRL (Offset 0x001F) */ 708 709 #define BIT_RF_EN BIT(0) 710 711 /* 2 REG_SDIO_FREE_TXPG_SEQ_V1 (Offset 0x1025001F) */ 712 713 #define BIT_SHIFT_FREE_TXPG_SEQ 0 714 #define BIT_MASK_FREE_TXPG_SEQ 0xff 715 #define BIT_FREE_TXPG_SEQ(x) \ 716 (((x) & BIT_MASK_FREE_TXPG_SEQ) << BIT_SHIFT_FREE_TXPG_SEQ) 717 #define BIT_GET_FREE_TXPG_SEQ(x) \ 718 (((x) >> BIT_SHIFT_FREE_TXPG_SEQ) & BIT_MASK_FREE_TXPG_SEQ) 719 720 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 721 722 #define BIT_SHIFT_LPLDH12_RSV 29 723 #define BIT_MASK_LPLDH12_RSV 0x7 724 #define BIT_LPLDH12_RSV(x) \ 725 (((x) & BIT_MASK_LPLDH12_RSV) << BIT_SHIFT_LPLDH12_RSV) 726 #define BIT_GET_LPLDH12_RSV(x) \ 727 (((x) >> BIT_SHIFT_LPLDH12_RSV) & BIT_MASK_LPLDH12_RSV) 728 729 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 730 731 #define BIT_LPLDH12_SLP BIT(28) 732 733 #define BIT_SHIFT_LPLDH12_VADJ 24 734 #define BIT_MASK_LPLDH12_VADJ 0xf 735 #define BIT_LPLDH12_VADJ(x) \ 736 (((x) & BIT_MASK_LPLDH12_VADJ) << BIT_SHIFT_LPLDH12_VADJ) 737 #define BIT_GET_LPLDH12_VADJ(x) \ 738 (((x) >> BIT_SHIFT_LPLDH12_VADJ) & BIT_MASK_LPLDH12_VADJ) 739 740 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 741 742 #define BIT_LDH12_EN BIT(16) 743 744 /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ 745 746 #define BIT_SHIFT_MID_FREEPG_V1 16 747 #define BIT_MASK_MID_FREEPG_V1 0xfff 748 #define BIT_MID_FREEPG_V1(x) \ 749 (((x) & BIT_MASK_MID_FREEPG_V1) << BIT_SHIFT_MID_FREEPG_V1) 750 #define BIT_GET_MID_FREEPG_V1(x) \ 751 (((x) >> BIT_SHIFT_MID_FREEPG_V1) & BIT_MASK_MID_FREEPG_V1) 752 753 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 754 755 #define BIT_WLBBOFF_BIG_PWC_EN BIT(14) 756 #define BIT_WLBBOFF_SMALL_PWC_EN BIT(13) 757 #define BIT_WLMACOFF_BIG_PWC_EN BIT(12) 758 #define BIT_WLPON_PWC_EN BIT(11) 759 760 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 761 762 #define BIT_POW_REGU_P1 BIT(10) 763 764 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 765 766 #define BIT_LDOV12W_EN BIT(8) 767 768 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 769 770 #define BIT_EX_XTAL_DRV_DIGI BIT(7) 771 #define BIT_EX_XTAL_DRV_USB BIT(6) 772 #define BIT_EX_XTAL_DRV_AFE BIT(5) 773 774 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 775 776 #define BIT_EX_XTAL_DRV_RF2 BIT(4) 777 778 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 779 780 #define BIT_EX_XTAL_DRV_RF1 BIT(3) 781 #define BIT_POW_REGU_P0 BIT(2) 782 783 /* 2 REG_AFE_LDO_CTRL (Offset 0x0020) */ 784 785 #define BIT_POW_PLL_LDO BIT(0) 786 787 /* 2 REG_SDIO_FREE_TXPG (Offset 0x10250020) */ 788 789 #define BIT_SHIFT_HIQ_FREEPG_V1 0 790 #define BIT_MASK_HIQ_FREEPG_V1 0xfff 791 #define BIT_HIQ_FREEPG_V1(x) \ 792 (((x) & BIT_MASK_HIQ_FREEPG_V1) << BIT_SHIFT_HIQ_FREEPG_V1) 793 #define BIT_GET_HIQ_FREEPG_V1(x) \ 794 (((x) >> BIT_SHIFT_HIQ_FREEPG_V1) & BIT_MASK_HIQ_FREEPG_V1) 795 796 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 797 798 #define BIT_AGPIO_GPE BIT(31) 799 800 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 801 802 #define BIT_SHIFT_XTAL_CAP_XI 25 803 #define BIT_MASK_XTAL_CAP_XI 0x3f 804 #define BIT_XTAL_CAP_XI(x) \ 805 (((x) & BIT_MASK_XTAL_CAP_XI) << BIT_SHIFT_XTAL_CAP_XI) 806 #define BIT_GET_XTAL_CAP_XI(x) \ 807 (((x) >> BIT_SHIFT_XTAL_CAP_XI) & BIT_MASK_XTAL_CAP_XI) 808 809 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 810 811 #define BIT_SHIFT_XTAL_DRV_DIGI 23 812 #define BIT_MASK_XTAL_DRV_DIGI 0x3 813 #define BIT_XTAL_DRV_DIGI(x) \ 814 (((x) & BIT_MASK_XTAL_DRV_DIGI) << BIT_SHIFT_XTAL_DRV_DIGI) 815 #define BIT_GET_XTAL_DRV_DIGI(x) \ 816 (((x) >> BIT_SHIFT_XTAL_DRV_DIGI) & BIT_MASK_XTAL_DRV_DIGI) 817 818 #define BIT_XTAL_DRV_USB_BIT1 BIT(22) 819 820 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 821 822 #define BIT_SHIFT_MAC_CLK_SEL 20 823 #define BIT_MASK_MAC_CLK_SEL 0x3 824 #define BIT_MAC_CLK_SEL(x) \ 825 (((x) & BIT_MASK_MAC_CLK_SEL) << BIT_SHIFT_MAC_CLK_SEL) 826 #define BIT_GET_MAC_CLK_SEL(x) \ 827 (((x) >> BIT_SHIFT_MAC_CLK_SEL) & BIT_MASK_MAC_CLK_SEL) 828 829 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 830 831 #define BIT_XTAL_DRV_USB_BIT0 BIT(19) 832 833 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 834 835 #define BIT_SHIFT_XTAL_DRV_AFE 17 836 #define BIT_MASK_XTAL_DRV_AFE 0x3 837 #define BIT_XTAL_DRV_AFE(x) \ 838 (((x) & BIT_MASK_XTAL_DRV_AFE) << BIT_SHIFT_XTAL_DRV_AFE) 839 #define BIT_GET_XTAL_DRV_AFE(x) \ 840 (((x) >> BIT_SHIFT_XTAL_DRV_AFE) & BIT_MASK_XTAL_DRV_AFE) 841 842 /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ 843 844 #define BIT_SHIFT_PUB_FREEPG_V1 16 845 #define BIT_MASK_PUB_FREEPG_V1 0xfff 846 #define BIT_PUB_FREEPG_V1(x) \ 847 (((x) & BIT_MASK_PUB_FREEPG_V1) << BIT_SHIFT_PUB_FREEPG_V1) 848 #define BIT_GET_PUB_FREEPG_V1(x) \ 849 (((x) >> BIT_SHIFT_PUB_FREEPG_V1) & BIT_MASK_PUB_FREEPG_V1) 850 851 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 852 853 #define BIT_SHIFT_XTAL_DRV_RF2 15 854 #define BIT_MASK_XTAL_DRV_RF2 0x3 855 #define BIT_XTAL_DRV_RF2(x) \ 856 (((x) & BIT_MASK_XTAL_DRV_RF2) << BIT_SHIFT_XTAL_DRV_RF2) 857 #define BIT_GET_XTAL_DRV_RF2(x) \ 858 (((x) >> BIT_SHIFT_XTAL_DRV_RF2) & BIT_MASK_XTAL_DRV_RF2) 859 860 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 861 862 #define BIT_SHIFT_XTAL_DRV_RF1 13 863 #define BIT_MASK_XTAL_DRV_RF1 0x3 864 #define BIT_XTAL_DRV_RF1(x) \ 865 (((x) & BIT_MASK_XTAL_DRV_RF1) << BIT_SHIFT_XTAL_DRV_RF1) 866 #define BIT_GET_XTAL_DRV_RF1(x) \ 867 (((x) >> BIT_SHIFT_XTAL_DRV_RF1) & BIT_MASK_XTAL_DRV_RF1) 868 869 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 870 871 #define BIT_XTAL_DELAY_DIGI BIT(12) 872 873 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 874 875 #define BIT_XTAL_DELAY_USB BIT(11) 876 #define BIT_XTAL_DELAY_AFE BIT(10) 877 878 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 879 880 #define BIT_SHIFT_XTAL_LDO_VREF 7 881 #define BIT_MASK_XTAL_LDO_VREF 0x7 882 #define BIT_XTAL_LDO_VREF(x) \ 883 (((x) & BIT_MASK_XTAL_LDO_VREF) << BIT_SHIFT_XTAL_LDO_VREF) 884 #define BIT_GET_XTAL_LDO_VREF(x) \ 885 (((x) >> BIT_SHIFT_XTAL_LDO_VREF) & BIT_MASK_XTAL_LDO_VREF) 886 887 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 888 889 #define BIT_XTAL_XQSEL_RF BIT(6) 890 #define BIT_XTAL_XQSEL BIT(5) 891 892 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 893 894 #define BIT_SHIFT_XTAL_GMN_V2 3 895 #define BIT_MASK_XTAL_GMN_V2 0x3 896 #define BIT_XTAL_GMN_V2(x) \ 897 (((x) & BIT_MASK_XTAL_GMN_V2) << BIT_SHIFT_XTAL_GMN_V2) 898 #define BIT_GET_XTAL_GMN_V2(x) \ 899 (((x) >> BIT_SHIFT_XTAL_GMN_V2) & BIT_MASK_XTAL_GMN_V2) 900 901 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 902 903 #define BIT_SHIFT_XTAL_GMP_V2 1 904 #define BIT_MASK_XTAL_GMP_V2 0x3 905 #define BIT_XTAL_GMP_V2(x) \ 906 (((x) & BIT_MASK_XTAL_GMP_V2) << BIT_SHIFT_XTAL_GMP_V2) 907 #define BIT_GET_XTAL_GMP_V2(x) \ 908 (((x) >> BIT_SHIFT_XTAL_GMP_V2) & BIT_MASK_XTAL_GMP_V2) 909 910 /* 2 REG_AFE_CTRL1 (Offset 0x0024) */ 911 912 #define BIT_XTAL_EN BIT(0) 913 914 /* 2 REG_SDIO_FREE_TXPG2 (Offset 0x10250024) */ 915 916 #define BIT_SHIFT_LOW_FREEPG_V1 0 917 #define BIT_MASK_LOW_FREEPG_V1 0xfff 918 #define BIT_LOW_FREEPG_V1(x) \ 919 (((x) & BIT_MASK_LOW_FREEPG_V1) << BIT_SHIFT_LOW_FREEPG_V1) 920 #define BIT_GET_LOW_FREEPG_V1(x) \ 921 (((x) >> BIT_SHIFT_LOW_FREEPG_V1) & BIT_MASK_LOW_FREEPG_V1) 922 923 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 924 925 #define BIT_SHIFT_REG_C3_V4 30 926 #define BIT_MASK_REG_C3_V4 0x3 927 #define BIT_REG_C3_V4(x) (((x) & BIT_MASK_REG_C3_V4) << BIT_SHIFT_REG_C3_V4) 928 #define BIT_GET_REG_C3_V4(x) (((x) >> BIT_SHIFT_REG_C3_V4) & BIT_MASK_REG_C3_V4) 929 930 #define BIT_REG_CP_BIT1 BIT(29) 931 932 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 933 934 #define BIT_SHIFT_REG_RS_V4 26 935 #define BIT_MASK_REG_RS_V4 0x7 936 #define BIT_REG_RS_V4(x) (((x) & BIT_MASK_REG_RS_V4) << BIT_SHIFT_REG_RS_V4) 937 #define BIT_GET_REG_RS_V4(x) (((x) >> BIT_SHIFT_REG_RS_V4) & BIT_MASK_REG_RS_V4) 938 939 /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ 940 941 #define BIT_SHIFT_NOAC_OQT_FREEPG_V1 24 942 #define BIT_MASK_NOAC_OQT_FREEPG_V1 0xff 943 #define BIT_NOAC_OQT_FREEPG_V1(x) \ 944 (((x) & BIT_MASK_NOAC_OQT_FREEPG_V1) << BIT_SHIFT_NOAC_OQT_FREEPG_V1) 945 #define BIT_GET_NOAC_OQT_FREEPG_V1(x) \ 946 (((x) >> BIT_SHIFT_NOAC_OQT_FREEPG_V1) & BIT_MASK_NOAC_OQT_FREEPG_V1) 947 948 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 949 950 #define BIT_SHIFT_REG__CS 24 951 #define BIT_MASK_REG__CS 0x3 952 #define BIT_REG__CS(x) (((x) & BIT_MASK_REG__CS) << BIT_SHIFT_REG__CS) 953 #define BIT_GET_REG__CS(x) (((x) >> BIT_SHIFT_REG__CS) & BIT_MASK_REG__CS) 954 955 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 956 957 #define BIT_SHIFT_REG_CP_OFFSET 21 958 #define BIT_MASK_REG_CP_OFFSET 0x7 959 #define BIT_REG_CP_OFFSET(x) \ 960 (((x) & BIT_MASK_REG_CP_OFFSET) << BIT_SHIFT_REG_CP_OFFSET) 961 #define BIT_GET_REG_CP_OFFSET(x) \ 962 (((x) >> BIT_SHIFT_REG_CP_OFFSET) & BIT_MASK_REG_CP_OFFSET) 963 964 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 965 966 #define BIT_SHIFT_CP_BIAS 18 967 #define BIT_MASK_CP_BIAS 0x7 968 #define BIT_CP_BIAS(x) (((x) & BIT_MASK_CP_BIAS) << BIT_SHIFT_CP_BIAS) 969 #define BIT_GET_CP_BIAS(x) (((x) >> BIT_SHIFT_CP_BIAS) & BIT_MASK_CP_BIAS) 970 971 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 972 973 #define BIT_REG_IDOUBLE_V2 BIT(17) 974 975 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 976 977 #define BIT_EN_SYN BIT(16) 978 979 #define BIT_SHIFT_AC_OQT_FREEPG_V1 16 980 #define BIT_MASK_AC_OQT_FREEPG_V1 0xff 981 #define BIT_AC_OQT_FREEPG_V1(x) \ 982 (((x) & BIT_MASK_AC_OQT_FREEPG_V1) << BIT_SHIFT_AC_OQT_FREEPG_V1) 983 #define BIT_GET_AC_OQT_FREEPG_V1(x) \ 984 (((x) >> BIT_SHIFT_AC_OQT_FREEPG_V1) & BIT_MASK_AC_OQT_FREEPG_V1) 985 986 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 987 988 #define BIT_SHIFT_MCCO 14 989 #define BIT_MASK_MCCO 0x3 990 #define BIT_MCCO(x) (((x) & BIT_MASK_MCCO) << BIT_SHIFT_MCCO) 991 #define BIT_GET_MCCO(x) (((x) >> BIT_SHIFT_MCCO) & BIT_MASK_MCCO) 992 993 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 994 995 #define BIT_SHIFT_REG_LDO_SEL 12 996 #define BIT_MASK_REG_LDO_SEL 0x3 997 #define BIT_REG_LDO_SEL(x) \ 998 (((x) & BIT_MASK_REG_LDO_SEL) << BIT_SHIFT_REG_LDO_SEL) 999 #define BIT_GET_REG_LDO_SEL(x) \ 1000 (((x) >> BIT_SHIFT_REG_LDO_SEL) & BIT_MASK_REG_LDO_SEL) 1001 1002 #define BIT_REG_KVCO_V2 BIT(10) 1003 1004 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1005 1006 #define BIT_AGPIO_GPO BIT(9) 1007 1008 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1009 1010 #define BIT_SHIFT_AGPIO_DRV 7 1011 #define BIT_MASK_AGPIO_DRV 0x3 1012 #define BIT_AGPIO_DRV(x) (((x) & BIT_MASK_AGPIO_DRV) << BIT_SHIFT_AGPIO_DRV) 1013 #define BIT_GET_AGPIO_DRV(x) (((x) >> BIT_SHIFT_AGPIO_DRV) & BIT_MASK_AGPIO_DRV) 1014 1015 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1016 1017 #define BIT_SHIFT_XTAL_CAP_XO 1 1018 #define BIT_MASK_XTAL_CAP_XO 0x3f 1019 #define BIT_XTAL_CAP_XO(x) \ 1020 (((x) & BIT_MASK_XTAL_CAP_XO) << BIT_SHIFT_XTAL_CAP_XO) 1021 #define BIT_GET_XTAL_CAP_XO(x) \ 1022 (((x) >> BIT_SHIFT_XTAL_CAP_XO) & BIT_MASK_XTAL_CAP_XO) 1023 1024 /* 2 REG_AFE_CTRL2 (Offset 0x0028) */ 1025 1026 #define BIT_POW_PLL BIT(0) 1027 1028 /* 2 REG_SDIO_OQT_FREE_TXPG_V1 (Offset 0x10250028) */ 1029 1030 #define BIT_SHIFT_EXQ_FREEPG_V1 0 1031 #define BIT_MASK_EXQ_FREEPG_V1 0xfff 1032 #define BIT_EXQ_FREEPG_V1(x) \ 1033 (((x) & BIT_MASK_EXQ_FREEPG_V1) << BIT_SHIFT_EXQ_FREEPG_V1) 1034 #define BIT_GET_EXQ_FREEPG_V1(x) \ 1035 (((x) >> BIT_SHIFT_EXQ_FREEPG_V1) & BIT_MASK_EXQ_FREEPG_V1) 1036 1037 /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1038 1039 #define BIT_SHIFT_PS 7 1040 #define BIT_MASK_PS 0x7 1041 #define BIT_PS(x) (((x) & BIT_MASK_PS) << BIT_SHIFT_PS) 1042 #define BIT_GET_PS(x) (((x) >> BIT_SHIFT_PS) & BIT_MASK_PS) 1043 1044 /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1045 1046 #define BIT_PSEN BIT(6) 1047 #define BIT_DOGENB BIT(5) 1048 1049 /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1050 1051 #define BIT_REG_MBIAS BIT(4) 1052 1053 /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1054 1055 #define BIT_SHIFT_REG_R3_V4 1 1056 #define BIT_MASK_REG_R3_V4 0x7 1057 #define BIT_REG_R3_V4(x) (((x) & BIT_MASK_REG_R3_V4) << BIT_SHIFT_REG_R3_V4) 1058 #define BIT_GET_REG_R3_V4(x) (((x) >> BIT_SHIFT_REG_R3_V4) & BIT_MASK_REG_R3_V4) 1059 1060 /* 2 REG_AFE_CTRL3 (Offset 0x002C) */ 1061 1062 #define BIT_REG_CP_BIT0 BIT(0) 1063 1064 /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1065 1066 #define BIT_EF_FLAG BIT(31) 1067 1068 #define BIT_SHIFT_EF_PGPD 28 1069 #define BIT_MASK_EF_PGPD 0x7 1070 #define BIT_EF_PGPD(x) (((x) & BIT_MASK_EF_PGPD) << BIT_SHIFT_EF_PGPD) 1071 #define BIT_GET_EF_PGPD(x) (((x) >> BIT_SHIFT_EF_PGPD) & BIT_MASK_EF_PGPD) 1072 1073 #define BIT_SHIFT_EF_RDT 24 1074 #define BIT_MASK_EF_RDT 0xf 1075 #define BIT_EF_RDT(x) (((x) & BIT_MASK_EF_RDT) << BIT_SHIFT_EF_RDT) 1076 #define BIT_GET_EF_RDT(x) (((x) >> BIT_SHIFT_EF_RDT) & BIT_MASK_EF_RDT) 1077 1078 #define BIT_SHIFT_EF_PGTS 20 1079 #define BIT_MASK_EF_PGTS 0xf 1080 #define BIT_EF_PGTS(x) (((x) & BIT_MASK_EF_PGTS) << BIT_SHIFT_EF_PGTS) 1081 #define BIT_GET_EF_PGTS(x) (((x) >> BIT_SHIFT_EF_PGTS) & BIT_MASK_EF_PGTS) 1082 1083 /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1084 1085 #define BIT_EF_PDWN BIT(19) 1086 1087 /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1088 1089 #define BIT_EF_ALDEN BIT(18) 1090 1091 /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ 1092 1093 #define BIT_SHIFT_HTSFR1 16 1094 #define BIT_MASK_HTSFR1 0xffff 1095 #define BIT_HTSFR1(x) (((x) & BIT_MASK_HTSFR1) << BIT_SHIFT_HTSFR1) 1096 #define BIT_GET_HTSFR1(x) (((x) >> BIT_SHIFT_HTSFR1) & BIT_MASK_HTSFR1) 1097 1098 /* 2 REG_EFUSE_CTRL (Offset 0x0030) */ 1099 1100 #define BIT_SHIFT_EF_ADDR 8 1101 #define BIT_MASK_EF_ADDR 0x3ff 1102 #define BIT_EF_ADDR(x) (((x) & BIT_MASK_EF_ADDR) << BIT_SHIFT_EF_ADDR) 1103 #define BIT_GET_EF_ADDR(x) (((x) >> BIT_SHIFT_EF_ADDR) & BIT_MASK_EF_ADDR) 1104 1105 #define BIT_SHIFT_EF_DATA 0 1106 #define BIT_MASK_EF_DATA 0xff 1107 #define BIT_EF_DATA(x) (((x) & BIT_MASK_EF_DATA) << BIT_SHIFT_EF_DATA) 1108 #define BIT_GET_EF_DATA(x) (((x) >> BIT_SHIFT_EF_DATA) & BIT_MASK_EF_DATA) 1109 1110 /* 2 REG_SDIO_HTSFR_INFO (Offset 0x10250030) */ 1111 1112 #define BIT_SHIFT_HTSFR0 0 1113 #define BIT_MASK_HTSFR0 0xffff 1114 #define BIT_HTSFR0(x) (((x) & BIT_MASK_HTSFR0) << BIT_SHIFT_HTSFR0) 1115 #define BIT_GET_HTSFR0(x) (((x) >> BIT_SHIFT_HTSFR0) & BIT_MASK_HTSFR0) 1116 1117 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1118 1119 #define BIT_LDOE25_EN BIT(31) 1120 1121 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1122 1123 #define BIT_SHIFT_LDOE25_V12ADJ_L 27 1124 #define BIT_MASK_LDOE25_V12ADJ_L 0xf 1125 #define BIT_LDOE25_V12ADJ_L(x) \ 1126 (((x) & BIT_MASK_LDOE25_V12ADJ_L) << BIT_SHIFT_LDOE25_V12ADJ_L) 1127 #define BIT_GET_LDOE25_V12ADJ_L(x) \ 1128 (((x) >> BIT_SHIFT_LDOE25_V12ADJ_L) & BIT_MASK_LDOE25_V12ADJ_L) 1129 1130 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1131 1132 #define BIT_EF_CRES_SEL BIT(26) 1133 1134 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1135 1136 #define BIT_SHIFT_EF_SCAN_START_V1 16 1137 #define BIT_MASK_EF_SCAN_START_V1 0x3ff 1138 #define BIT_EF_SCAN_START_V1(x) \ 1139 (((x) & BIT_MASK_EF_SCAN_START_V1) << BIT_SHIFT_EF_SCAN_START_V1) 1140 #define BIT_GET_EF_SCAN_START_V1(x) \ 1141 (((x) >> BIT_SHIFT_EF_SCAN_START_V1) & BIT_MASK_EF_SCAN_START_V1) 1142 1143 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1144 1145 #define BIT_SHIFT_EF_SCAN_END 12 1146 #define BIT_MASK_EF_SCAN_END 0xf 1147 #define BIT_EF_SCAN_END(x) \ 1148 (((x) & BIT_MASK_EF_SCAN_END) << BIT_SHIFT_EF_SCAN_END) 1149 #define BIT_GET_EF_SCAN_END(x) \ 1150 (((x) >> BIT_SHIFT_EF_SCAN_END) & BIT_MASK_EF_SCAN_END) 1151 1152 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1153 1154 #define BIT_EF_PD_DIS BIT(11) 1155 1156 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1157 1158 #define BIT_SHIFT_EF_CELL_SEL 8 1159 #define BIT_MASK_EF_CELL_SEL 0x3 1160 #define BIT_EF_CELL_SEL(x) \ 1161 (((x) & BIT_MASK_EF_CELL_SEL) << BIT_SHIFT_EF_CELL_SEL) 1162 #define BIT_GET_EF_CELL_SEL(x) \ 1163 (((x) >> BIT_SHIFT_EF_CELL_SEL) & BIT_MASK_EF_CELL_SEL) 1164 1165 /* 2 REG_LDO_EFUSE_CTRL (Offset 0x0034) */ 1166 1167 #define BIT_EF_TRPT BIT(7) 1168 1169 #define BIT_SHIFT_EF_TTHD 0 1170 #define BIT_MASK_EF_TTHD 0x7f 1171 #define BIT_EF_TTHD(x) (((x) & BIT_MASK_EF_TTHD) << BIT_SHIFT_EF_TTHD) 1172 #define BIT_GET_EF_TTHD(x) (((x) >> BIT_SHIFT_EF_TTHD) & BIT_MASK_EF_TTHD) 1173 1174 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1175 1176 #define BIT_SHIFT_DBG_SEL_V1 16 1177 #define BIT_MASK_DBG_SEL_V1 0xff 1178 #define BIT_DBG_SEL_V1(x) (((x) & BIT_MASK_DBG_SEL_V1) << BIT_SHIFT_DBG_SEL_V1) 1179 #define BIT_GET_DBG_SEL_V1(x) \ 1180 (((x) >> BIT_SHIFT_DBG_SEL_V1) & BIT_MASK_DBG_SEL_V1) 1181 1182 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1183 1184 #define BIT_SHIFT_DBG_SEL_BYTE 14 1185 #define BIT_MASK_DBG_SEL_BYTE 0x3 1186 #define BIT_DBG_SEL_BYTE(x) \ 1187 (((x) & BIT_MASK_DBG_SEL_BYTE) << BIT_SHIFT_DBG_SEL_BYTE) 1188 #define BIT_GET_DBG_SEL_BYTE(x) \ 1189 (((x) >> BIT_SHIFT_DBG_SEL_BYTE) & BIT_MASK_DBG_SEL_BYTE) 1190 1191 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1192 1193 #define BIT_SHIFT_STD_L1_V1 12 1194 #define BIT_MASK_STD_L1_V1 0x3 1195 #define BIT_STD_L1_V1(x) (((x) & BIT_MASK_STD_L1_V1) << BIT_SHIFT_STD_L1_V1) 1196 #define BIT_GET_STD_L1_V1(x) (((x) >> BIT_SHIFT_STD_L1_V1) & BIT_MASK_STD_L1_V1) 1197 1198 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1199 1200 #define BIT_SYSON_DBG_PAD_E2 BIT(11) 1201 1202 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1203 1204 #define BIT_SYSON_LED_PAD_E2 BIT(10) 1205 1206 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1207 1208 #define BIT_SYSON_GPEE_PAD_E2 BIT(9) 1209 1210 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1211 1212 #define BIT_SYSON_PCI_PAD_E2 BIT(8) 1213 1214 #define BIT_SHIFT_MATCH_CNT 8 1215 #define BIT_MASK_MATCH_CNT 0xff 1216 #define BIT_MATCH_CNT(x) (((x) & BIT_MASK_MATCH_CNT) << BIT_SHIFT_MATCH_CNT) 1217 #define BIT_GET_MATCH_CNT(x) (((x) >> BIT_SHIFT_MATCH_CNT) & BIT_MASK_MATCH_CNT) 1218 1219 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1220 1221 #define BIT_AUTO_SW_LDO_VOL_EN BIT(7) 1222 1223 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1224 1225 #define BIT_SHIFT_SYSON_SPS0WWV_WT 4 1226 #define BIT_MASK_SYSON_SPS0WWV_WT 0x3 1227 #define BIT_SYSON_SPS0WWV_WT(x) \ 1228 (((x) & BIT_MASK_SYSON_SPS0WWV_WT) << BIT_SHIFT_SYSON_SPS0WWV_WT) 1229 #define BIT_GET_SYSON_SPS0WWV_WT(x) \ 1230 (((x) >> BIT_SHIFT_SYSON_SPS0WWV_WT) & BIT_MASK_SYSON_SPS0WWV_WT) 1231 1232 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1233 1234 #define BIT_SHIFT_SYSON_SPS0LDO_WT 2 1235 #define BIT_MASK_SYSON_SPS0LDO_WT 0x3 1236 #define BIT_SYSON_SPS0LDO_WT(x) \ 1237 (((x) & BIT_MASK_SYSON_SPS0LDO_WT) << BIT_SHIFT_SYSON_SPS0LDO_WT) 1238 #define BIT_GET_SYSON_SPS0LDO_WT(x) \ 1239 (((x) >> BIT_SHIFT_SYSON_SPS0LDO_WT) & BIT_MASK_SYSON_SPS0LDO_WT) 1240 1241 /* 2 REG_PWR_OPTION_CTRL (Offset 0x0038) */ 1242 1243 #define BIT_SHIFT_SYSON_RCLK_SCALE 0 1244 #define BIT_MASK_SYSON_RCLK_SCALE 0x3 1245 #define BIT_SYSON_RCLK_SCALE(x) \ 1246 (((x) & BIT_MASK_SYSON_RCLK_SCALE) << BIT_SHIFT_SYSON_RCLK_SCALE) 1247 #define BIT_GET_SYSON_RCLK_SCALE(x) \ 1248 (((x) >> BIT_SHIFT_SYSON_RCLK_SCALE) & BIT_MASK_SYSON_RCLK_SCALE) 1249 1250 /* 2 REG_SDIO_HCPWM1_V2 (Offset 0x10250038) */ 1251 1252 #define BIT_SYS_CLK BIT(0) 1253 1254 /* 2 REG_CAL_TIMER (Offset 0x003C) */ 1255 1256 #define BIT_SHIFT_CAL_SCAL 0 1257 #define BIT_MASK_CAL_SCAL 0xff 1258 #define BIT_CAL_SCAL(x) (((x) & BIT_MASK_CAL_SCAL) << BIT_SHIFT_CAL_SCAL) 1259 #define BIT_GET_CAL_SCAL(x) (((x) >> BIT_SHIFT_CAL_SCAL) & BIT_MASK_CAL_SCAL) 1260 1261 /* 2 REG_ACLK_MON (Offset 0x003E) */ 1262 1263 #define BIT_SHIFT_RCLK_MON 5 1264 #define BIT_MASK_RCLK_MON 0x7ff 1265 #define BIT_RCLK_MON(x) (((x) & BIT_MASK_RCLK_MON) << BIT_SHIFT_RCLK_MON) 1266 #define BIT_GET_RCLK_MON(x) (((x) >> BIT_SHIFT_RCLK_MON) & BIT_MASK_RCLK_MON) 1267 1268 #define BIT_CAL_EN BIT(4) 1269 1270 #define BIT_SHIFT_DPSTU 2 1271 #define BIT_MASK_DPSTU 0x3 1272 #define BIT_DPSTU(x) (((x) & BIT_MASK_DPSTU) << BIT_SHIFT_DPSTU) 1273 #define BIT_GET_DPSTU(x) (((x) >> BIT_SHIFT_DPSTU) & BIT_MASK_DPSTU) 1274 1275 #define BIT_SUS_16X BIT(1) 1276 1277 /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1278 1279 #define BIT_INDIRECT_REG_RDY BIT(20) 1280 1281 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1282 1283 #define BIT_FSPI_EN BIT(19) 1284 1285 /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1286 1287 #define BIT_INDIRECT_REG_R BIT(19) 1288 1289 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1290 1291 #define BIT_WL_RTS_EXT_32K_SEL BIT(18) 1292 1293 /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1294 1295 #define BIT_INDIRECT_REG_W BIT(18) 1296 1297 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1298 1299 #define BIT_WLGP_SPI_EN BIT(16) 1300 1301 /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1302 1303 #define BIT_SHIFT_INDIRECT_REG_SIZE 16 1304 #define BIT_MASK_INDIRECT_REG_SIZE 0x3 1305 #define BIT_INDIRECT_REG_SIZE(x) \ 1306 (((x) & BIT_MASK_INDIRECT_REG_SIZE) << BIT_SHIFT_INDIRECT_REG_SIZE) 1307 #define BIT_GET_INDIRECT_REG_SIZE(x) \ 1308 (((x) >> BIT_SHIFT_INDIRECT_REG_SIZE) & BIT_MASK_INDIRECT_REG_SIZE) 1309 1310 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1311 1312 #define BIT_SIC_LBK BIT(15) 1313 #define BIT_ENHTP BIT(14) 1314 1315 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1316 1317 #define BIT_ENSIC BIT(12) 1318 #define BIT_SIC_SWRST BIT(11) 1319 1320 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1321 1322 #define BIT_PO_WIFI_PTA_PINS BIT(10) 1323 1324 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1325 1326 #define BIT_PO_BT_PTA_PINS BIT(9) 1327 1328 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1329 1330 #define BIT_ENUART BIT(8) 1331 1332 #define BIT_SHIFT_BTMODE 6 1333 #define BIT_MASK_BTMODE 0x3 1334 #define BIT_BTMODE(x) (((x) & BIT_MASK_BTMODE) << BIT_SHIFT_BTMODE) 1335 #define BIT_GET_BTMODE(x) (((x) >> BIT_SHIFT_BTMODE) & BIT_MASK_BTMODE) 1336 1337 #define BIT_ENBT BIT(5) 1338 #define BIT_EROM_EN BIT(4) 1339 1340 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1341 1342 #define BIT_WLRFE_6_7_EN BIT(3) 1343 1344 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1345 1346 #define BIT_WLRFE_4_5_EN BIT(2) 1347 1348 /* 2 REG_GPIO_MUXCFG (Offset 0x0040) */ 1349 1350 #define BIT_SHIFT_GPIOSEL 0 1351 #define BIT_MASK_GPIOSEL 0x3 1352 #define BIT_GPIOSEL(x) (((x) & BIT_MASK_GPIOSEL) << BIT_SHIFT_GPIOSEL) 1353 #define BIT_GET_GPIOSEL(x) (((x) >> BIT_SHIFT_GPIOSEL) & BIT_MASK_GPIOSEL) 1354 1355 /* 2 REG_SDIO_INDIRECT_REG_CFG (Offset 0x10250040) */ 1356 1357 #define BIT_SHIFT_INDIRECT_REG_ADDR 0 1358 #define BIT_MASK_INDIRECT_REG_ADDR 0xffff 1359 #define BIT_INDIRECT_REG_ADDR(x) \ 1360 (((x) & BIT_MASK_INDIRECT_REG_ADDR) << BIT_SHIFT_INDIRECT_REG_ADDR) 1361 #define BIT_GET_INDIRECT_REG_ADDR(x) \ 1362 (((x) >> BIT_SHIFT_INDIRECT_REG_ADDR) & BIT_MASK_INDIRECT_REG_ADDR) 1363 1364 /* 2 REG_GPIO_PIN_CTRL (Offset 0x0044) */ 1365 1366 #define BIT_SHIFT_GPIO_MOD_7_TO_0 24 1367 #define BIT_MASK_GPIO_MOD_7_TO_0 0xff 1368 #define BIT_GPIO_MOD_7_TO_0(x) \ 1369 (((x) & BIT_MASK_GPIO_MOD_7_TO_0) << BIT_SHIFT_GPIO_MOD_7_TO_0) 1370 #define BIT_GET_GPIO_MOD_7_TO_0(x) \ 1371 (((x) >> BIT_SHIFT_GPIO_MOD_7_TO_0) & BIT_MASK_GPIO_MOD_7_TO_0) 1372 1373 #define BIT_SHIFT_GPIO_IO_SEL_7_TO_0 16 1374 #define BIT_MASK_GPIO_IO_SEL_7_TO_0 0xff 1375 #define BIT_GPIO_IO_SEL_7_TO_0(x) \ 1376 (((x) & BIT_MASK_GPIO_IO_SEL_7_TO_0) << BIT_SHIFT_GPIO_IO_SEL_7_TO_0) 1377 #define BIT_GET_GPIO_IO_SEL_7_TO_0(x) \ 1378 (((x) >> BIT_SHIFT_GPIO_IO_SEL_7_TO_0) & BIT_MASK_GPIO_IO_SEL_7_TO_0) 1379 1380 #define BIT_SHIFT_GPIO_OUT_7_TO_0 8 1381 #define BIT_MASK_GPIO_OUT_7_TO_0 0xff 1382 #define BIT_GPIO_OUT_7_TO_0(x) \ 1383 (((x) & BIT_MASK_GPIO_OUT_7_TO_0) << BIT_SHIFT_GPIO_OUT_7_TO_0) 1384 #define BIT_GET_GPIO_OUT_7_TO_0(x) \ 1385 (((x) >> BIT_SHIFT_GPIO_OUT_7_TO_0) & BIT_MASK_GPIO_OUT_7_TO_0) 1386 1387 #define BIT_SHIFT_GPIO_IN_7_TO_0 0 1388 #define BIT_MASK_GPIO_IN_7_TO_0 0xff 1389 #define BIT_GPIO_IN_7_TO_0(x) \ 1390 (((x) & BIT_MASK_GPIO_IN_7_TO_0) << BIT_SHIFT_GPIO_IN_7_TO_0) 1391 #define BIT_GET_GPIO_IN_7_TO_0(x) \ 1392 (((x) >> BIT_SHIFT_GPIO_IN_7_TO_0) & BIT_MASK_GPIO_IN_7_TO_0) 1393 1394 /* 2 REG_SDIO_INDIRECT_REG_DATA (Offset 0x10250044) */ 1395 1396 #define BIT_SHIFT_INDIRECT_REG_DATA 0 1397 #define BIT_MASK_INDIRECT_REG_DATA 0xffffffffL 1398 #define BIT_INDIRECT_REG_DATA(x) \ 1399 (((x) & BIT_MASK_INDIRECT_REG_DATA) << BIT_SHIFT_INDIRECT_REG_DATA) 1400 #define BIT_GET_INDIRECT_REG_DATA(x) \ 1401 (((x) >> BIT_SHIFT_INDIRECT_REG_DATA) & BIT_MASK_INDIRECT_REG_DATA) 1402 1403 /* 2 REG_GPIO_INTM (Offset 0x0048) */ 1404 1405 #define BIT_SHIFT_MUXDBG_SEL 30 1406 #define BIT_MASK_MUXDBG_SEL 0x3 1407 #define BIT_MUXDBG_SEL(x) (((x) & BIT_MASK_MUXDBG_SEL) << BIT_SHIFT_MUXDBG_SEL) 1408 #define BIT_GET_MUXDBG_SEL(x) \ 1409 (((x) >> BIT_SHIFT_MUXDBG_SEL) & BIT_MASK_MUXDBG_SEL) 1410 1411 /* 2 REG_GPIO_INTM (Offset 0x0048) */ 1412 1413 #define BIT_EXTWOL_SEL BIT(17) 1414 1415 /* 2 REG_GPIO_INTM (Offset 0x0048) */ 1416 1417 #define BIT_EXTWOL_EN BIT(16) 1418 1419 /* 2 REG_GPIO_INTM (Offset 0x0048) */ 1420 1421 #define BIT_GPIOF_INT_MD BIT(15) 1422 #define BIT_GPIOE_INT_MD BIT(14) 1423 #define BIT_GPIOD_INT_MD BIT(13) 1424 #define BIT_GPIOC_INT_MD BIT(12) 1425 #define BIT_GPIOB_INT_MD BIT(11) 1426 #define BIT_GPIOA_INT_MD BIT(10) 1427 #define BIT_GPIO9_INT_MD BIT(9) 1428 #define BIT_GPIO8_INT_MD BIT(8) 1429 #define BIT_GPIO7_INT_MD BIT(7) 1430 #define BIT_GPIO6_INT_MD BIT(6) 1431 #define BIT_GPIO5_INT_MD BIT(5) 1432 #define BIT_GPIO4_INT_MD BIT(4) 1433 #define BIT_GPIO3_INT_MD BIT(3) 1434 #define BIT_GPIO2_INT_MD BIT(2) 1435 #define BIT_GPIO1_INT_MD BIT(1) 1436 #define BIT_GPIO0_INT_MD BIT(0) 1437 1438 /* 2 REG_LED_CFG (Offset 0x004C) */ 1439 1440 #define BIT_GPIO3_WL_CTRL_EN BIT(27) 1441 1442 /* 2 REG_LED_CFG (Offset 0x004C) */ 1443 1444 #define BIT_LNAON_SEL_EN BIT(26) 1445 1446 /* 2 REG_LED_CFG (Offset 0x004C) */ 1447 1448 #define BIT_PAPE_SEL_EN BIT(25) 1449 1450 /* 2 REG_LED_CFG (Offset 0x004C) */ 1451 1452 #define BIT_DPDT_WLBT_SEL BIT(24) 1453 1454 /* 2 REG_LED_CFG (Offset 0x004C) */ 1455 1456 #define BIT_DPDT_SEL_EN BIT(23) 1457 1458 /* 2 REG_LED_CFG (Offset 0x004C) */ 1459 1460 #define BIT_GPIO13_14_WL_CTRL_EN BIT(22) 1461 1462 /* 2 REG_LED_CFG (Offset 0x004C) */ 1463 1464 #define BIT_LED2DIS BIT(21) 1465 1466 /* 2 REG_LED_CFG (Offset 0x004C) */ 1467 1468 #define BIT_LED2PL BIT(20) 1469 #define BIT_LED2SV BIT(19) 1470 1471 #define BIT_SHIFT_LED2CM 16 1472 #define BIT_MASK_LED2CM 0x7 1473 #define BIT_LED2CM(x) (((x) & BIT_MASK_LED2CM) << BIT_SHIFT_LED2CM) 1474 #define BIT_GET_LED2CM(x) (((x) >> BIT_SHIFT_LED2CM) & BIT_MASK_LED2CM) 1475 1476 #define BIT_LED1DIS BIT(15) 1477 #define BIT_LED1PL BIT(12) 1478 #define BIT_LED1SV BIT(11) 1479 1480 #define BIT_SHIFT_LED1CM 8 1481 #define BIT_MASK_LED1CM 0x7 1482 #define BIT_LED1CM(x) (((x) & BIT_MASK_LED1CM) << BIT_SHIFT_LED1CM) 1483 #define BIT_GET_LED1CM(x) (((x) >> BIT_SHIFT_LED1CM) & BIT_MASK_LED1CM) 1484 1485 #define BIT_LED0DIS BIT(7) 1486 1487 /* 2 REG_LED_CFG (Offset 0x004C) */ 1488 1489 #define BIT_SHIFT_AFE_LDO_SWR_CHECK 5 1490 #define BIT_MASK_AFE_LDO_SWR_CHECK 0x3 1491 #define BIT_AFE_LDO_SWR_CHECK(x) \ 1492 (((x) & BIT_MASK_AFE_LDO_SWR_CHECK) << BIT_SHIFT_AFE_LDO_SWR_CHECK) 1493 #define BIT_GET_AFE_LDO_SWR_CHECK(x) \ 1494 (((x) >> BIT_SHIFT_AFE_LDO_SWR_CHECK) & BIT_MASK_AFE_LDO_SWR_CHECK) 1495 1496 /* 2 REG_LED_CFG (Offset 0x004C) */ 1497 1498 #define BIT_LED0PL BIT(4) 1499 #define BIT_LED0SV BIT(3) 1500 1501 #define BIT_SHIFT_LED0CM 0 1502 #define BIT_MASK_LED0CM 0x7 1503 #define BIT_LED0CM(x) (((x) & BIT_MASK_LED0CM) << BIT_SHIFT_LED0CM) 1504 #define BIT_GET_LED0CM(x) (((x) >> BIT_SHIFT_LED0CM) & BIT_MASK_LED0CM) 1505 1506 /* 2 REG_FSIMR (Offset 0x0050) */ 1507 1508 #define BIT_FS_PDNINT_EN BIT(31) 1509 1510 /* 2 REG_FSIMR (Offset 0x0050) */ 1511 1512 #define BIT_NFC_INT_PAD_EN BIT(30) 1513 1514 /* 2 REG_FSIMR (Offset 0x0050) */ 1515 1516 #define BIT_FS_SPS_OCP_INT_EN BIT(29) 1517 1518 /* 2 REG_FSIMR (Offset 0x0050) */ 1519 1520 #define BIT_FS_PWMERR_INT_EN BIT(28) 1521 1522 /* 2 REG_FSIMR (Offset 0x0050) */ 1523 1524 #define BIT_FS_GPIOF_INT_EN BIT(27) 1525 #define BIT_FS_GPIOE_INT_EN BIT(26) 1526 #define BIT_FS_GPIOD_INT_EN BIT(25) 1527 #define BIT_FS_GPIOC_INT_EN BIT(24) 1528 1529 /* 2 REG_FSIMR (Offset 0x0050) */ 1530 1531 #define BIT_FS_GPIOB_INT_EN BIT(23) 1532 1533 /* 2 REG_FSIMR (Offset 0x0050) */ 1534 1535 #define BIT_FS_GPIOA_INT_EN BIT(22) 1536 1537 /* 2 REG_FSIMR (Offset 0x0050) */ 1538 1539 #define BIT_FS_GPIO9_INT_EN BIT(21) 1540 1541 /* 2 REG_FSIMR (Offset 0x0050) */ 1542 1543 #define BIT_FS_GPIO8_INT_EN BIT(20) 1544 1545 /* 2 REG_FSIMR (Offset 0x0050) */ 1546 1547 #define BIT_FS_GPIO7_INT_EN BIT(19) 1548 1549 /* 2 REG_FSIMR (Offset 0x0050) */ 1550 1551 #define BIT_FS_GPIO6_INT_EN BIT(18) 1552 1553 /* 2 REG_FSIMR (Offset 0x0050) */ 1554 1555 #define BIT_FS_GPIO5_INT_EN BIT(17) 1556 1557 /* 2 REG_FSIMR (Offset 0x0050) */ 1558 1559 #define BIT_FS_GPIO4_INT_EN BIT(16) 1560 1561 /* 2 REG_FSIMR (Offset 0x0050) */ 1562 1563 #define BIT_FS_GPIO3_INT_EN BIT(15) 1564 1565 /* 2 REG_FSIMR (Offset 0x0050) */ 1566 1567 #define BIT_FS_GPIO2_INT_EN BIT(14) 1568 1569 /* 2 REG_FSIMR (Offset 0x0050) */ 1570 1571 #define BIT_FS_GPIO1_INT_EN BIT(13) 1572 1573 /* 2 REG_FSIMR (Offset 0x0050) */ 1574 1575 #define BIT_FS_GPIO0_INT_EN BIT(12) 1576 1577 /* 2 REG_FSIMR (Offset 0x0050) */ 1578 1579 #define BIT_FS_HCI_SUS_EN BIT(11) 1580 1581 /* 2 REG_FSIMR (Offset 0x0050) */ 1582 1583 #define BIT_FS_HCI_RES_EN BIT(10) 1584 1585 /* 2 REG_FSIMR (Offset 0x0050) */ 1586 1587 #define BIT_FS_HCI_RESET_EN BIT(9) 1588 1589 /* 2 REG_FSIMR (Offset 0x0050) */ 1590 1591 #define BIT_FS_BTON_STS_UPDATE_MSK_EN BIT(7) 1592 1593 /* 2 REG_FSIMR (Offset 0x0050) */ 1594 1595 #define BIT_ACT2RECOVERY_INT_EN_V1 BIT(6) 1596 1597 /* 2 REG_FSIMR (Offset 0x0050) */ 1598 1599 #define BIT_GEN1GEN2_SWITCH BIT(5) 1600 1601 /* 2 REG_FSIMR (Offset 0x0050) */ 1602 1603 #define BIT_HCI_TXDMA_REQ_HIMR BIT(4) 1604 1605 /* 2 REG_FSIMR (Offset 0x0050) */ 1606 1607 #define BIT_FS_32K_LEAVE_SETTING_MAK BIT(3) 1608 1609 /* 2 REG_FSIMR (Offset 0x0050) */ 1610 1611 #define BIT_FS_32K_ENTER_SETTING_MAK BIT(2) 1612 1613 /* 2 REG_FSIMR (Offset 0x0050) */ 1614 1615 #define BIT_FS_USB_LPMRSM_MSK BIT(1) 1616 1617 /* 2 REG_FSIMR (Offset 0x0050) */ 1618 1619 #define BIT_FS_USB_LPMINT_MSK BIT(0) 1620 1621 /* 2 REG_FSISR (Offset 0x0054) */ 1622 1623 #define BIT_FS_PDNINT BIT(31) 1624 1625 /* 2 REG_FSISR (Offset 0x0054) */ 1626 1627 #define BIT_FS_SPS_OCP_INT BIT(29) 1628 1629 /* 2 REG_FSISR (Offset 0x0054) */ 1630 1631 #define BIT_FS_PWMERR_INT BIT(28) 1632 1633 /* 2 REG_FSISR (Offset 0x0054) */ 1634 1635 #define BIT_FS_GPIOF_INT BIT(27) 1636 #define BIT_FS_GPIOE_INT BIT(26) 1637 #define BIT_FS_GPIOD_INT BIT(25) 1638 #define BIT_FS_GPIOC_INT BIT(24) 1639 1640 /* 2 REG_FSISR (Offset 0x0054) */ 1641 1642 #define BIT_FS_GPIOB_INT BIT(23) 1643 1644 /* 2 REG_FSISR (Offset 0x0054) */ 1645 1646 #define BIT_FS_GPIOA_INT BIT(22) 1647 1648 /* 2 REG_FSISR (Offset 0x0054) */ 1649 1650 #define BIT_FS_GPIO9_INT BIT(21) 1651 1652 /* 2 REG_FSISR (Offset 0x0054) */ 1653 1654 #define BIT_FS_GPIO8_INT BIT(20) 1655 1656 /* 2 REG_FSISR (Offset 0x0054) */ 1657 1658 #define BIT_FS_GPIO7_INT BIT(19) 1659 1660 /* 2 REG_FSISR (Offset 0x0054) */ 1661 1662 #define BIT_FS_GPIO6_INT BIT(18) 1663 1664 /* 2 REG_FSISR (Offset 0x0054) */ 1665 1666 #define BIT_FS_GPIO5_INT BIT(17) 1667 1668 /* 2 REG_FSISR (Offset 0x0054) */ 1669 1670 #define BIT_FS_GPIO4_INT BIT(16) 1671 1672 /* 2 REG_FSISR (Offset 0x0054) */ 1673 1674 #define BIT_FS_GPIO3_INT BIT(15) 1675 1676 /* 2 REG_FSISR (Offset 0x0054) */ 1677 1678 #define BIT_FS_GPIO2_INT BIT(14) 1679 1680 /* 2 REG_FSISR (Offset 0x0054) */ 1681 1682 #define BIT_FS_GPIO1_INT BIT(13) 1683 1684 /* 2 REG_FSISR (Offset 0x0054) */ 1685 1686 #define BIT_FS_GPIO0_INT BIT(12) 1687 1688 /* 2 REG_FSISR (Offset 0x0054) */ 1689 1690 #define BIT_FS_HCI_SUS_INT BIT(11) 1691 1692 /* 2 REG_FSISR (Offset 0x0054) */ 1693 1694 #define BIT_FS_HCI_RES_INT BIT(10) 1695 1696 /* 2 REG_FSISR (Offset 0x0054) */ 1697 1698 #define BIT_FS_HCI_RESET_INT BIT(9) 1699 1700 /* 2 REG_FSISR (Offset 0x0054) */ 1701 1702 #define BIT_ACT2RECOVERY BIT(6) 1703 1704 /* 2 REG_FSISR (Offset 0x0054) */ 1705 1706 #define BIT_HCI_TXDMA_REQ_HISR BIT(4) 1707 1708 /* 2 REG_FSISR (Offset 0x0054) */ 1709 1710 #define BIT_FS_32K_LEAVE_SETTING_INT BIT(3) 1711 1712 /* 2 REG_FSISR (Offset 0x0054) */ 1713 1714 #define BIT_FS_32K_ENTER_SETTING_INT BIT(2) 1715 1716 /* 2 REG_FSISR (Offset 0x0054) */ 1717 1718 #define BIT_FS_USB_LPMRSM_INT BIT(1) 1719 1720 /* 2 REG_FSISR (Offset 0x0054) */ 1721 1722 #define BIT_FS_USB_LPMINT_INT BIT(0) 1723 1724 /* 2 REG_HSIMR (Offset 0x0058) */ 1725 1726 #define BIT_GPIOF_INT_EN BIT(31) 1727 #define BIT_GPIOE_INT_EN BIT(30) 1728 #define BIT_GPIOD_INT_EN BIT(29) 1729 #define BIT_GPIOC_INT_EN BIT(28) 1730 #define BIT_GPIOB_INT_EN BIT(27) 1731 #define BIT_GPIOA_INT_EN BIT(26) 1732 #define BIT_GPIO9_INT_EN BIT(25) 1733 #define BIT_GPIO8_INT_EN BIT(24) 1734 #define BIT_GPIO7_INT_EN BIT(23) 1735 #define BIT_GPIO6_INT_EN BIT(22) 1736 #define BIT_GPIO5_INT_EN BIT(21) 1737 #define BIT_GPIO4_INT_EN BIT(20) 1738 #define BIT_GPIO3_INT_EN BIT(19) 1739 1740 /* 2 REG_HSIMR (Offset 0x0058) */ 1741 1742 #define BIT_GPIO1_INT_EN BIT(17) 1743 #define BIT_GPIO0_INT_EN BIT(16) 1744 1745 /* 2 REG_HSIMR (Offset 0x0058) */ 1746 1747 #define BIT_GPIO2_INT_EN_V1 BIT(16) 1748 1749 /* 2 REG_HSIMR (Offset 0x0058) */ 1750 1751 #define BIT_PDNINT_EN BIT(7) 1752 1753 /* 2 REG_HSIMR (Offset 0x0058) */ 1754 1755 #define BIT_RON_INT_EN BIT(6) 1756 1757 /* 2 REG_HSIMR (Offset 0x0058) */ 1758 1759 #define BIT_SPS_OCP_INT_EN BIT(5) 1760 1761 /* 2 REG_HSIMR (Offset 0x0058) */ 1762 1763 #define BIT_GPIO15_0_INT_EN BIT(0) 1764 1765 /* 2 REG_HSISR (Offset 0x005C) */ 1766 1767 #define BIT_GPIOF_INT BIT(31) 1768 #define BIT_GPIOE_INT BIT(30) 1769 #define BIT_GPIOD_INT BIT(29) 1770 #define BIT_GPIOC_INT BIT(28) 1771 #define BIT_GPIOB_INT BIT(27) 1772 #define BIT_GPIOA_INT BIT(26) 1773 #define BIT_GPIO9_INT BIT(25) 1774 #define BIT_GPIO8_INT BIT(24) 1775 #define BIT_GPIO7_INT BIT(23) 1776 1777 /* 2 REG_HSISR (Offset 0x005C) */ 1778 1779 #define BIT_GPIO6_INT BIT(22) 1780 #define BIT_GPIO5_INT BIT(21) 1781 #define BIT_GPIO4_INT BIT(20) 1782 #define BIT_GPIO3_INT BIT(19) 1783 1784 /* 2 REG_HSISR (Offset 0x005C) */ 1785 1786 #define BIT_GPIO1_INT BIT(17) 1787 #define BIT_GPIO0_INT BIT(16) 1788 1789 /* 2 REG_HSISR (Offset 0x005C) */ 1790 1791 #define BIT_GPIO2_INT_V1 BIT(16) 1792 1793 /* 2 REG_HSISR (Offset 0x005C) */ 1794 1795 #define BIT_PDNINT BIT(7) 1796 1797 /* 2 REG_HSISR (Offset 0x005C) */ 1798 1799 #define BIT_RON_INT BIT(6) 1800 1801 /* 2 REG_HSISR (Offset 0x005C) */ 1802 1803 #define BIT_SPS_OCP_INT BIT(5) 1804 1805 /* 2 REG_HSISR (Offset 0x005C) */ 1806 1807 #define BIT_GPIO15_0_INT BIT(0) 1808 #define BIT_MCUFWDL_EN BIT(0) 1809 1810 /* 2 REG_GPIO_EXT_CTRL (Offset 0x0060) */ 1811 1812 #define BIT_SHIFT_GPIO_MOD_15_TO_8 24 1813 #define BIT_MASK_GPIO_MOD_15_TO_8 0xff 1814 #define BIT_GPIO_MOD_15_TO_8(x) \ 1815 (((x) & BIT_MASK_GPIO_MOD_15_TO_8) << BIT_SHIFT_GPIO_MOD_15_TO_8) 1816 #define BIT_GET_GPIO_MOD_15_TO_8(x) \ 1817 (((x) >> BIT_SHIFT_GPIO_MOD_15_TO_8) & BIT_MASK_GPIO_MOD_15_TO_8) 1818 1819 #define BIT_SHIFT_GPIO_IO_SEL_15_TO_8 16 1820 #define BIT_MASK_GPIO_IO_SEL_15_TO_8 0xff 1821 #define BIT_GPIO_IO_SEL_15_TO_8(x) \ 1822 (((x) & BIT_MASK_GPIO_IO_SEL_15_TO_8) << BIT_SHIFT_GPIO_IO_SEL_15_TO_8) 1823 #define BIT_GET_GPIO_IO_SEL_15_TO_8(x) \ 1824 (((x) >> BIT_SHIFT_GPIO_IO_SEL_15_TO_8) & BIT_MASK_GPIO_IO_SEL_15_TO_8) 1825 1826 #define BIT_SHIFT_GPIO_OUT_15_TO_8 8 1827 #define BIT_MASK_GPIO_OUT_15_TO_8 0xff 1828 #define BIT_GPIO_OUT_15_TO_8(x) \ 1829 (((x) & BIT_MASK_GPIO_OUT_15_TO_8) << BIT_SHIFT_GPIO_OUT_15_TO_8) 1830 #define BIT_GET_GPIO_OUT_15_TO_8(x) \ 1831 (((x) >> BIT_SHIFT_GPIO_OUT_15_TO_8) & BIT_MASK_GPIO_OUT_15_TO_8) 1832 1833 #define BIT_SHIFT_GPIO_IN_15_TO_8 0 1834 #define BIT_MASK_GPIO_IN_15_TO_8 0xff 1835 #define BIT_GPIO_IN_15_TO_8(x) \ 1836 (((x) & BIT_MASK_GPIO_IN_15_TO_8) << BIT_SHIFT_GPIO_IN_15_TO_8) 1837 #define BIT_GET_GPIO_IN_15_TO_8(x) \ 1838 (((x) >> BIT_SHIFT_GPIO_IN_15_TO_8) & BIT_MASK_GPIO_IN_15_TO_8) 1839 1840 /* 2 REG_SDIO_H2C (Offset 0x10250060) */ 1841 1842 #define BIT_SHIFT_SDIO_H2C_MSG 0 1843 #define BIT_MASK_SDIO_H2C_MSG 0xffffffffL 1844 #define BIT_SDIO_H2C_MSG(x) \ 1845 (((x) & BIT_MASK_SDIO_H2C_MSG) << BIT_SHIFT_SDIO_H2C_MSG) 1846 #define BIT_GET_SDIO_H2C_MSG(x) \ 1847 (((x) >> BIT_SHIFT_SDIO_H2C_MSG) & BIT_MASK_SDIO_H2C_MSG) 1848 1849 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1850 1851 #define BIT_PAPE_WLBT_SEL BIT(29) 1852 #define BIT_LNAON_WLBT_SEL BIT(28) 1853 1854 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1855 1856 #define BIT_BTGP_GPG3_FEN BIT(26) 1857 #define BIT_BTGP_GPG2_FEN BIT(25) 1858 1859 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1860 1861 #define BIT_BTGP_JTAG_EN BIT(24) 1862 1863 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1864 1865 #define BIT_XTAL_CLK_EXTARNAL_EN BIT(23) 1866 1867 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1868 1869 #define BIT_BTGP_UART0_EN BIT(22) 1870 1871 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1872 1873 #define BIT_BTGP_UART1_EN BIT(21) 1874 1875 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1876 1877 #define BIT_BTGP_SPI_EN BIT(20) 1878 1879 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1880 1881 #define BIT_BTGP_GPIO_E2 BIT(19) 1882 1883 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1884 1885 #define BIT_BTGP_GPIO_EN BIT(18) 1886 1887 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1888 1889 #define BIT_SHIFT_BTGP_GPIO_SL 16 1890 #define BIT_MASK_BTGP_GPIO_SL 0x3 1891 #define BIT_BTGP_GPIO_SL(x) \ 1892 (((x) & BIT_MASK_BTGP_GPIO_SL) << BIT_SHIFT_BTGP_GPIO_SL) 1893 #define BIT_GET_BTGP_GPIO_SL(x) \ 1894 (((x) >> BIT_SHIFT_BTGP_GPIO_SL) & BIT_MASK_BTGP_GPIO_SL) 1895 1896 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1897 1898 #define BIT_PAD_SDIO_SR BIT(14) 1899 1900 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1901 1902 #define BIT_GPIO14_OUTPUT_PL BIT(13) 1903 1904 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1905 1906 #define BIT_HOST_WAKE_PAD_PULL_EN BIT(12) 1907 1908 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1909 1910 #define BIT_HOST_WAKE_PAD_SL BIT(11) 1911 1912 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1913 1914 #define BIT_PAD_LNAON_SR BIT(10) 1915 1916 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1917 1918 #define BIT_PAD_LNAON_E2 BIT(9) 1919 1920 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1921 1922 #define BIT_SW_LNAON_G_SEL_DATA BIT(8) 1923 1924 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1925 1926 #define BIT_SW_LNAON_A_SEL_DATA BIT(7) 1927 1928 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1929 1930 #define BIT_PAD_PAPE_SR BIT(6) 1931 1932 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1933 1934 #define BIT_PAD_PAPE_E2 BIT(5) 1935 1936 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1937 1938 #define BIT_SW_PAPE_G_SEL_DATA BIT(4) 1939 1940 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1941 1942 #define BIT_SW_PAPE_A_SEL_DATA BIT(3) 1943 1944 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1945 1946 #define BIT_PAD_DPDT_SR BIT(2) 1947 1948 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1949 1950 #define BIT_PAD_DPDT_PAD_E2 BIT(1) 1951 1952 /* 2 REG_PAD_CTRL1 (Offset 0x0064) */ 1953 1954 #define BIT_SW_DPDT_SEL_DATA BIT(0) 1955 1956 /* 2 REG_SDIO_C2H (Offset 0x10250064) */ 1957 1958 #define BIT_SHIFT_SDIO_C2H_MSG 0 1959 #define BIT_MASK_SDIO_C2H_MSG 0xffffffffL 1960 #define BIT_SDIO_C2H_MSG(x) \ 1961 (((x) & BIT_MASK_SDIO_C2H_MSG) << BIT_SHIFT_SDIO_C2H_MSG) 1962 #define BIT_GET_SDIO_C2H_MSG(x) \ 1963 (((x) >> BIT_SHIFT_SDIO_C2H_MSG) & BIT_MASK_SDIO_C2H_MSG) 1964 1965 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1966 1967 #define BIT_ISO_BD2PP BIT(31) 1968 #define BIT_LDOV12B_EN BIT(30) 1969 #define BIT_CKEN_BTGPS BIT(29) 1970 #define BIT_FEN_BTGPS BIT(28) 1971 1972 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1973 1974 #define BIT_MULRW BIT(27) 1975 1976 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1977 1978 #define BIT_BTCPU_BOOTSEL BIT(27) 1979 #define BIT_SPI_SPEEDUP BIT(26) 1980 1981 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1982 1983 #define BIT_DEVWAKE_PAD_TYPE_SEL BIT(24) 1984 #define BIT_CLKREQ_PAD_TYPE_SEL BIT(23) 1985 1986 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1987 1988 #define BIT_EN_CPL_TIMEOUT_PS BIT(22) 1989 1990 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1991 1992 #define BIT_ISO_BTPON2PP BIT(22) 1993 1994 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1995 1996 #define BIT_REG_TXDMA_FAIL_PS BIT(21) 1997 1998 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 1999 2000 #define BIT_EN_HWENTR_L1 BIT(19) 2001 2002 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2003 2004 #define BIT_BT_HWROF_EN BIT(19) 2005 2006 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2007 2008 #define BIT_EN_ADV_CLKGATE BIT(18) 2009 2010 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2011 2012 #define BIT_BT_FUNC_EN BIT(18) 2013 2014 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2015 2016 #define BIT_BT_HWPDN_SL BIT(17) 2017 2018 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2019 2020 #define BIT_BT_DISN_EN BIT(16) 2021 2022 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2023 2024 #define BIT_BT_PDN_PULL_EN BIT(15) 2025 2026 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2027 2028 #define BIT_WL_PDN_PULL_EN BIT(14) 2029 #define BIT_EXTERNAL_REQUEST_PL BIT(13) 2030 2031 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2032 2033 #define BIT_GPIO0_2_3_PULL_LOW_EN BIT(12) 2034 2035 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2036 2037 #define BIT_ISO_BA2PP BIT(11) 2038 #define BIT_BT_AFE_LDO_EN BIT(10) 2039 2040 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2041 2042 #define BIT_BT_AFE_PLL_EN BIT(9) 2043 2044 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2045 2046 #define BIT_BT_DIG_CLK_EN BIT(8) 2047 2048 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2049 2050 #define BIT_WL_DRV_EXIST_IDX BIT(5) 2051 2052 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2053 2054 #define BIT_DOP_EHPAD BIT(4) 2055 2056 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2057 2058 #define BIT_WL_HWROF_EN BIT(3) 2059 2060 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2061 2062 #define BIT_WL_FUNC_EN BIT(2) 2063 2064 /* 2 REG_WL_BT_PWR_CTRL (Offset 0x0068) */ 2065 2066 #define BIT_WL_HWPDN_SL BIT(1) 2067 #define BIT_WL_HWPDN_EN BIT(0) 2068 2069 /* 2 REG_SDM_DEBUG (Offset 0x006C) */ 2070 2071 #define BIT_SHIFT_WLCLK_PHASE 0 2072 #define BIT_MASK_WLCLK_PHASE 0x1f 2073 #define BIT_WLCLK_PHASE(x) \ 2074 (((x) & BIT_MASK_WLCLK_PHASE) << BIT_SHIFT_WLCLK_PHASE) 2075 #define BIT_GET_WLCLK_PHASE(x) \ 2076 (((x) >> BIT_SHIFT_WLCLK_PHASE) & BIT_MASK_WLCLK_PHASE) 2077 2078 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2079 2080 #define BIT_DBG_GNT_WL_BT BIT(27) 2081 2082 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2083 2084 #define BIT_LTE_MUX_CTRL_PATH BIT(26) 2085 2086 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2087 2088 #define BIT_LTE_COEX_UART BIT(25) 2089 2090 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2091 2092 #define BIT_3W_LTE_WL_GPIO BIT(24) 2093 2094 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2095 2096 #define BIT_SDIO_INT_POLARITY BIT(19) 2097 #define BIT_SDIO_INT BIT(18) 2098 2099 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2100 2101 #define BIT_SDIO_OFF_EN BIT(17) 2102 2103 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2104 2105 #define BIT_SDIO_ON_EN BIT(16) 2106 2107 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2108 2109 #define BIT_PCIE_WAIT_TIMEOUT_EVENT BIT(10) 2110 #define BIT_PCIE_WAIT_TIME BIT(9) 2111 2112 /* 2 REG_SYS_SDIO_CTRL (Offset 0x0070) */ 2113 2114 #define BIT_MPCIE_REFCLK_XTAL_SEL BIT(8) 2115 2116 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2117 2118 #define BIT_SHIFT_TSFT_SEL 29 2119 #define BIT_MASK_TSFT_SEL 0x7 2120 #define BIT_TSFT_SEL(x) (((x) & BIT_MASK_TSFT_SEL) << BIT_SHIFT_TSFT_SEL) 2121 #define BIT_GET_TSFT_SEL(x) (((x) >> BIT_SHIFT_TSFT_SEL) & BIT_MASK_TSFT_SEL) 2122 2123 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2124 2125 #define BIT_SHIFT_RPWM 24 2126 #define BIT_MASK_RPWM 0xff 2127 #define BIT_RPWM(x) (((x) & BIT_MASK_RPWM) << BIT_SHIFT_RPWM) 2128 #define BIT_GET_RPWM(x) (((x) >> BIT_SHIFT_RPWM) & BIT_MASK_RPWM) 2129 2130 #define BIT_ROM_DLEN BIT(19) 2131 2132 #define BIT_SHIFT_ROM_PGE 16 2133 #define BIT_MASK_ROM_PGE 0x7 2134 #define BIT_ROM_PGE(x) (((x) & BIT_MASK_ROM_PGE) << BIT_SHIFT_ROM_PGE) 2135 #define BIT_GET_ROM_PGE(x) (((x) >> BIT_SHIFT_ROM_PGE) & BIT_MASK_ROM_PGE) 2136 2137 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2138 2139 #define BIT_USB_HOST_PWR_OFF_EN BIT(12) 2140 2141 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2142 2143 #define BIT_SYM_LPS_BLOCK_EN BIT(11) 2144 2145 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2146 2147 #define BIT_USB_LPM_ACT_EN BIT(10) 2148 2149 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2150 2151 #define BIT_USB_LPM_NY BIT(9) 2152 2153 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2154 2155 #define BIT_USB_SUS_DIS BIT(8) 2156 2157 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2158 2159 #define BIT_SHIFT_SDIO_PAD_E 5 2160 #define BIT_MASK_SDIO_PAD_E 0x7 2161 #define BIT_SDIO_PAD_E(x) (((x) & BIT_MASK_SDIO_PAD_E) << BIT_SHIFT_SDIO_PAD_E) 2162 #define BIT_GET_SDIO_PAD_E(x) \ 2163 (((x) >> BIT_SHIFT_SDIO_PAD_E) & BIT_MASK_SDIO_PAD_E) 2164 2165 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2166 2167 #define BIT_USB_LPPLL_EN BIT(4) 2168 2169 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2170 2171 #define BIT_ROP_SW15 BIT(2) 2172 2173 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2174 2175 #define BIT_PCI_CKRDY_OPT BIT(1) 2176 2177 /* 2 REG_HCI_OPT_CTRL (Offset 0x0074) */ 2178 2179 #define BIT_PCI_VAUX_EN BIT(0) 2180 2181 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2182 2183 #define BIT_ZCD_HW_AUTO_EN BIT(27) 2184 #define BIT_ZCD_REGSEL BIT(26) 2185 2186 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2187 2188 #define BIT_SHIFT_AUTO_ZCD_IN_CODE 21 2189 #define BIT_MASK_AUTO_ZCD_IN_CODE 0x1f 2190 #define BIT_AUTO_ZCD_IN_CODE(x) \ 2191 (((x) & BIT_MASK_AUTO_ZCD_IN_CODE) << BIT_SHIFT_AUTO_ZCD_IN_CODE) 2192 #define BIT_GET_AUTO_ZCD_IN_CODE(x) \ 2193 (((x) >> BIT_SHIFT_AUTO_ZCD_IN_CODE) & BIT_MASK_AUTO_ZCD_IN_CODE) 2194 2195 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2196 2197 #define BIT_SHIFT_ZCD_CODE_IN_L 16 2198 #define BIT_MASK_ZCD_CODE_IN_L 0x1f 2199 #define BIT_ZCD_CODE_IN_L(x) \ 2200 (((x) & BIT_MASK_ZCD_CODE_IN_L) << BIT_SHIFT_ZCD_CODE_IN_L) 2201 #define BIT_GET_ZCD_CODE_IN_L(x) \ 2202 (((x) >> BIT_SHIFT_ZCD_CODE_IN_L) & BIT_MASK_ZCD_CODE_IN_L) 2203 2204 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2205 2206 #define BIT_SHIFT_LDO_HV5_DUMMY 14 2207 #define BIT_MASK_LDO_HV5_DUMMY 0x3 2208 #define BIT_LDO_HV5_DUMMY(x) \ 2209 (((x) & BIT_MASK_LDO_HV5_DUMMY) << BIT_SHIFT_LDO_HV5_DUMMY) 2210 #define BIT_GET_LDO_HV5_DUMMY(x) \ 2211 (((x) >> BIT_SHIFT_LDO_HV5_DUMMY) & BIT_MASK_LDO_HV5_DUMMY) 2212 2213 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2214 2215 #define BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1 12 2216 #define BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1 0x3 2217 #define BIT_REG_VTUNE33_BIT0_TO_BIT1(x) \ 2218 (((x) & BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) \ 2219 << BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) 2220 #define BIT_GET_REG_VTUNE33_BIT0_TO_BIT1(x) \ 2221 (((x) >> BIT_SHIFT_REG_VTUNE33_BIT0_TO_BIT1) & \ 2222 BIT_MASK_REG_VTUNE33_BIT0_TO_BIT1) 2223 2224 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2225 2226 #define BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1 10 2227 #define BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1 0x3 2228 #define BIT_REG_STANDBY33_BIT0_TO_BIT1(x) \ 2229 (((x) & BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) \ 2230 << BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) 2231 #define BIT_GET_REG_STANDBY33_BIT0_TO_BIT1(x) \ 2232 (((x) >> BIT_SHIFT_REG_STANDBY33_BIT0_TO_BIT1) & \ 2233 BIT_MASK_REG_STANDBY33_BIT0_TO_BIT1) 2234 2235 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2236 2237 #define BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1 8 2238 #define BIT_MASK_REG_LOAD33_BIT0_TO_BIT1 0x3 2239 #define BIT_REG_LOAD33_BIT0_TO_BIT1(x) \ 2240 (((x) & BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) \ 2241 << BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) 2242 #define BIT_GET_REG_LOAD33_BIT0_TO_BIT1(x) \ 2243 (((x) >> BIT_SHIFT_REG_LOAD33_BIT0_TO_BIT1) & \ 2244 BIT_MASK_REG_LOAD33_BIT0_TO_BIT1) 2245 2246 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2247 2248 #define BIT_REG_BYPASS_L BIT(7) 2249 2250 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2251 2252 #define BIT_REG_LDOF_L BIT(6) 2253 2254 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2255 2256 #define BIT_REG_TYPE_L_V1 BIT(5) 2257 2258 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2259 2260 #define BIT_ARENB_L BIT(3) 2261 2262 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2263 2264 #define BIT_SHIFT_CFC_L 1 2265 #define BIT_MASK_CFC_L 0x3 2266 #define BIT_CFC_L(x) (((x) & BIT_MASK_CFC_L) << BIT_SHIFT_CFC_L) 2267 #define BIT_GET_CFC_L(x) (((x) >> BIT_SHIFT_CFC_L) & BIT_MASK_CFC_L) 2268 2269 /* 2 REG_LDO_SWR_CTRL (Offset 0x007C) */ 2270 2271 #define BIT_REG_OCPS_L_V1 BIT(0) 2272 2273 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2274 2275 #define BIT_ANA_PORT_EN BIT(22) 2276 #define BIT_MAC_PORT_EN BIT(21) 2277 #define BIT_BOOT_FSPI_EN BIT(20) 2278 #define BIT_FW_INIT_RDY BIT(15) 2279 #define BIT_FW_DW_RDY BIT(14) 2280 2281 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2282 2283 #define BIT_SHIFT_CPU_CLK_SEL 12 2284 #define BIT_MASK_CPU_CLK_SEL 0x3 2285 #define BIT_CPU_CLK_SEL(x) \ 2286 (((x) & BIT_MASK_CPU_CLK_SEL) << BIT_SHIFT_CPU_CLK_SEL) 2287 #define BIT_GET_CPU_CLK_SEL(x) \ 2288 (((x) >> BIT_SHIFT_CPU_CLK_SEL) & BIT_MASK_CPU_CLK_SEL) 2289 2290 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2291 2292 #define BIT_CCLK_CHG_MASK BIT(11) 2293 2294 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2295 2296 #define BIT_EMEM__TXBUF_CHKSUM_OK BIT(10) 2297 2298 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2299 2300 #define BIT_EMEM_TXBUF_DW_RDY BIT(9) 2301 2302 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2303 2304 #define BIT_EMEM_CHKSUM_OK BIT(8) 2305 #define BIT_EMEM_DW_OK BIT(7) 2306 #define BIT_TOGGLING BIT(7) 2307 #define BIT_DMEM_CHKSUM_OK BIT(6) 2308 #define BIT_ACK BIT(6) 2309 2310 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2311 2312 #define BIT_DMEM_DW_OK BIT(5) 2313 2314 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2315 2316 #define BIT_IMEM_CHKSUM_OK BIT(4) 2317 2318 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2319 2320 #define BIT_IMEM_DW_OK BIT(3) 2321 2322 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2323 2324 #define BIT_IMEM_BOOT_LOAD_CHKSUM_OK BIT(2) 2325 2326 /* 2 REG_MCUFW_CTRL (Offset 0x0080) */ 2327 2328 #define BIT_IMEM_BOOT_LOAD_DW_OK BIT(1) 2329 2330 /* 2 REG_SDIO_HRPWM1 (Offset 0x10250080) */ 2331 2332 #define BIT_32K_PERMISSION BIT(0) 2333 2334 /* 2 REG_MCU_TST_CFG (Offset 0x0084) */ 2335 2336 #define BIT_SHIFT_LBKTST 0 2337 #define BIT_MASK_LBKTST 0xffff 2338 #define BIT_LBKTST(x) (((x) & BIT_MASK_LBKTST) << BIT_SHIFT_LBKTST) 2339 #define BIT_GET_LBKTST(x) (((x) >> BIT_SHIFT_LBKTST) & BIT_MASK_LBKTST) 2340 2341 /* 2 REG_SDIO_BUS_CTRL (Offset 0x10250085) */ 2342 2343 #define BIT_PAD_CLK_XHGE_EN BIT(3) 2344 #define BIT_INTER_CLK_EN BIT(2) 2345 #define BIT_EN_RPT_TXCRC BIT(1) 2346 #define BIT_DIS_RXDMA_STS BIT(0) 2347 2348 /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ 2349 2350 #define BIT_INTR_CTRL BIT(4) 2351 #define BIT_SDIO_VOLTAGE BIT(3) 2352 #define BIT_BYPASS_INIT BIT(2) 2353 2354 /* 2 REG_SDIO_HSUS_CTRL (Offset 0x10250086) */ 2355 2356 #define BIT_HCI_RESUME_RDY BIT(1) 2357 #define BIT_HCI_SUS_REQ BIT(0) 2358 2359 /* 2 REG_HMEBOX_E0_E1 (Offset 0x0088) */ 2360 2361 #define BIT_SHIFT_HOST_MSG_E1 16 2362 #define BIT_MASK_HOST_MSG_E1 0xffff 2363 #define BIT_HOST_MSG_E1(x) \ 2364 (((x) & BIT_MASK_HOST_MSG_E1) << BIT_SHIFT_HOST_MSG_E1) 2365 #define BIT_GET_HOST_MSG_E1(x) \ 2366 (((x) >> BIT_SHIFT_HOST_MSG_E1) & BIT_MASK_HOST_MSG_E1) 2367 2368 #define BIT_SHIFT_HOST_MSG_E0 0 2369 #define BIT_MASK_HOST_MSG_E0 0xffff 2370 #define BIT_HOST_MSG_E0(x) \ 2371 (((x) & BIT_MASK_HOST_MSG_E0) << BIT_SHIFT_HOST_MSG_E0) 2372 #define BIT_GET_HOST_MSG_E0(x) \ 2373 (((x) >> BIT_SHIFT_HOST_MSG_E0) & BIT_MASK_HOST_MSG_E0) 2374 2375 /* 2 REG_SDIO_RESPONSE_TIMER (Offset 0x10250088) */ 2376 2377 #define BIT_SHIFT_CMDIN_2RESP_TIMER 0 2378 #define BIT_MASK_CMDIN_2RESP_TIMER 0xffff 2379 #define BIT_CMDIN_2RESP_TIMER(x) \ 2380 (((x) & BIT_MASK_CMDIN_2RESP_TIMER) << BIT_SHIFT_CMDIN_2RESP_TIMER) 2381 #define BIT_GET_CMDIN_2RESP_TIMER(x) \ 2382 (((x) >> BIT_SHIFT_CMDIN_2RESP_TIMER) & BIT_MASK_CMDIN_2RESP_TIMER) 2383 2384 /* 2 REG_SDIO_CMD_CRC (Offset 0x1025008A) */ 2385 2386 #define BIT_SHIFT_SDIO_CMD_CRC_V1 0 2387 #define BIT_MASK_SDIO_CMD_CRC_V1 0xff 2388 #define BIT_SDIO_CMD_CRC_V1(x) \ 2389 (((x) & BIT_MASK_SDIO_CMD_CRC_V1) << BIT_SHIFT_SDIO_CMD_CRC_V1) 2390 #define BIT_GET_SDIO_CMD_CRC_V1(x) \ 2391 (((x) >> BIT_SHIFT_SDIO_CMD_CRC_V1) & BIT_MASK_SDIO_CMD_CRC_V1) 2392 2393 /* 2 REG_HMEBOX_E2_E3 (Offset 0x008C) */ 2394 2395 #define BIT_SHIFT_HOST_MSG_E3 16 2396 #define BIT_MASK_HOST_MSG_E3 0xffff 2397 #define BIT_HOST_MSG_E3(x) \ 2398 (((x) & BIT_MASK_HOST_MSG_E3) << BIT_SHIFT_HOST_MSG_E3) 2399 #define BIT_GET_HOST_MSG_E3(x) \ 2400 (((x) >> BIT_SHIFT_HOST_MSG_E3) & BIT_MASK_HOST_MSG_E3) 2401 2402 #define BIT_SHIFT_HOST_MSG_E2 0 2403 #define BIT_MASK_HOST_MSG_E2 0xffff 2404 #define BIT_HOST_MSG_E2(x) \ 2405 (((x) & BIT_MASK_HOST_MSG_E2) << BIT_SHIFT_HOST_MSG_E2) 2406 #define BIT_GET_HOST_MSG_E2(x) \ 2407 (((x) >> BIT_SHIFT_HOST_MSG_E2) & BIT_MASK_HOST_MSG_E2) 2408 2409 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2410 2411 #define BIT_WLLPSOP_EABM BIT(31) 2412 2413 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2414 2415 #define BIT_WLLPSOP_ACKF BIT(30) 2416 2417 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2418 2419 #define BIT_WLLPSOP_DLDM BIT(29) 2420 2421 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2422 2423 #define BIT_WLLPSOP_ESWR BIT(28) 2424 2425 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2426 2427 #define BIT_WLLPSOP_PWMM BIT(27) 2428 #define BIT_WLLPSOP_EECK BIT(26) 2429 2430 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2431 2432 #define BIT_WLLPSOP_WLMACOFF BIT(25) 2433 2434 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2435 2436 #define BIT_WLLPSOP_EXTAL BIT(24) 2437 2438 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2439 2440 #define BIT_WL_SYNPON_VOLTSPDN BIT(23) 2441 2442 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2443 2444 #define BIT_WLLPSOP_WLBBOFF BIT(22) 2445 2446 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2447 2448 #define BIT_WLLPSOP_WLMEM_DS BIT(21) 2449 2450 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2451 2452 #define BIT_SHIFT_LPLDH12_VADJ_STEP_DN 12 2453 #define BIT_MASK_LPLDH12_VADJ_STEP_DN 0xf 2454 #define BIT_LPLDH12_VADJ_STEP_DN(x) \ 2455 (((x) & BIT_MASK_LPLDH12_VADJ_STEP_DN) \ 2456 << BIT_SHIFT_LPLDH12_VADJ_STEP_DN) 2457 #define BIT_GET_LPLDH12_VADJ_STEP_DN(x) \ 2458 (((x) >> BIT_SHIFT_LPLDH12_VADJ_STEP_DN) & \ 2459 BIT_MASK_LPLDH12_VADJ_STEP_DN) 2460 2461 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2462 2463 #define BIT_SHIFT_V15ADJ_L1_STEP_DN 8 2464 #define BIT_MASK_V15ADJ_L1_STEP_DN 0x7 2465 #define BIT_V15ADJ_L1_STEP_DN(x) \ 2466 (((x) & BIT_MASK_V15ADJ_L1_STEP_DN) << BIT_SHIFT_V15ADJ_L1_STEP_DN) 2467 #define BIT_GET_V15ADJ_L1_STEP_DN(x) \ 2468 (((x) >> BIT_SHIFT_V15ADJ_L1_STEP_DN) & BIT_MASK_V15ADJ_L1_STEP_DN) 2469 2470 #define BIT_REGU_32K_CLK_EN BIT(1) 2471 #define BIT_DRV_WLAN_INT_CLR BIT(1) 2472 2473 /* 2 REG_WLLPS_CTRL (Offset 0x0090) */ 2474 2475 #define BIT_WL_LPS_EN BIT(0) 2476 2477 /* 2 REG_SDIO_HSISR (Offset 0x10250090) */ 2478 2479 #define BIT_DRV_WLAN_INT BIT(0) 2480 2481 /* 2 REG_SDIO_HSIMR (Offset 0x10250091) */ 2482 2483 #define BIT_HISR_MASK BIT(0) 2484 2485 /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2486 2487 #define BIT_BB_DBG_SEL_AFE_SDM_BIT0 BIT(31) 2488 2489 /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2490 2491 #define BIT_ORDER_SDM BIT(30) 2492 #define BIT_RFE_SEL_SDM BIT(29) 2493 2494 #define BIT_SHIFT_REF_SEL 25 2495 #define BIT_MASK_REF_SEL 0xf 2496 #define BIT_REF_SEL(x) (((x) & BIT_MASK_REF_SEL) << BIT_SHIFT_REF_SEL) 2497 #define BIT_GET_REF_SEL(x) (((x) >> BIT_SHIFT_REF_SEL) & BIT_MASK_REF_SEL) 2498 2499 /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2500 2501 #define BIT_SHIFT_F0F_SDM 12 2502 #define BIT_MASK_F0F_SDM 0x1fff 2503 #define BIT_F0F_SDM(x) (((x) & BIT_MASK_F0F_SDM) << BIT_SHIFT_F0F_SDM) 2504 #define BIT_GET_F0F_SDM(x) (((x) >> BIT_SHIFT_F0F_SDM) & BIT_MASK_F0F_SDM) 2505 2506 /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2507 2508 #define BIT_SHIFT_F0N_SDM 9 2509 #define BIT_MASK_F0N_SDM 0x7 2510 #define BIT_F0N_SDM(x) (((x) & BIT_MASK_F0N_SDM) << BIT_SHIFT_F0N_SDM) 2511 #define BIT_GET_F0N_SDM(x) (((x) >> BIT_SHIFT_F0N_SDM) & BIT_MASK_F0N_SDM) 2512 2513 /* 2 REG_AFE_CTRL5 (Offset 0x0094) */ 2514 2515 #define BIT_SHIFT_DIVN_SDM 3 2516 #define BIT_MASK_DIVN_SDM 0x3f 2517 #define BIT_DIVN_SDM(x) (((x) & BIT_MASK_DIVN_SDM) << BIT_SHIFT_DIVN_SDM) 2518 #define BIT_GET_DIVN_SDM(x) (((x) >> BIT_SHIFT_DIVN_SDM) & BIT_MASK_DIVN_SDM) 2519 2520 /* 2 REG_GPIO_DEBOUNCE_CTRL (Offset 0x0098) */ 2521 2522 #define BIT_WLGP_DBC1EN BIT(15) 2523 2524 #define BIT_SHIFT_WLGP_DBC1 8 2525 #define BIT_MASK_WLGP_DBC1 0xf 2526 #define BIT_WLGP_DBC1(x) (((x) & BIT_MASK_WLGP_DBC1) << BIT_SHIFT_WLGP_DBC1) 2527 #define BIT_GET_WLGP_DBC1(x) (((x) >> BIT_SHIFT_WLGP_DBC1) & BIT_MASK_WLGP_DBC1) 2528 2529 #define BIT_WLGP_DBC0EN BIT(7) 2530 2531 #define BIT_SHIFT_WLGP_DBC0 0 2532 #define BIT_MASK_WLGP_DBC0 0xf 2533 #define BIT_WLGP_DBC0(x) (((x) & BIT_MASK_WLGP_DBC0) << BIT_SHIFT_WLGP_DBC0) 2534 #define BIT_GET_WLGP_DBC0(x) (((x) >> BIT_SHIFT_WLGP_DBC0) & BIT_MASK_WLGP_DBC0) 2535 2536 /* 2 REG_RPWM2 (Offset 0x009C) */ 2537 2538 #define BIT_SHIFT_RPWM2 16 2539 #define BIT_MASK_RPWM2 0xffff 2540 #define BIT_RPWM2(x) (((x) & BIT_MASK_RPWM2) << BIT_SHIFT_RPWM2) 2541 #define BIT_GET_RPWM2(x) (((x) >> BIT_SHIFT_RPWM2) & BIT_MASK_RPWM2) 2542 2543 /* 2 REG_SYSON_FSM_MON (Offset 0x00A0) */ 2544 2545 #define BIT_SHIFT_FSM_MON_SEL 24 2546 #define BIT_MASK_FSM_MON_SEL 0x7 2547 #define BIT_FSM_MON_SEL(x) \ 2548 (((x) & BIT_MASK_FSM_MON_SEL) << BIT_SHIFT_FSM_MON_SEL) 2549 #define BIT_GET_FSM_MON_SEL(x) \ 2550 (((x) >> BIT_SHIFT_FSM_MON_SEL) & BIT_MASK_FSM_MON_SEL) 2551 2552 #define BIT_DOP_ELDO BIT(23) 2553 #define BIT_FSM_MON_UPD BIT(15) 2554 2555 #define BIT_SHIFT_FSM_PAR 0 2556 #define BIT_MASK_FSM_PAR 0x7fff 2557 #define BIT_FSM_PAR(x) (((x) & BIT_MASK_FSM_PAR) << BIT_SHIFT_FSM_PAR) 2558 #define BIT_GET_FSM_PAR(x) (((x) >> BIT_SHIFT_FSM_PAR) & BIT_MASK_FSM_PAR) 2559 2560 /* 2 REG_AFE_CTRL6 (Offset 0x00A4) */ 2561 2562 #define BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1 0 2563 #define BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1 0x7 2564 #define BIT_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ 2565 (((x) & BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) \ 2566 << BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) 2567 #define BIT_GET_BB_DBG_SEL_AFE_SDM_BIT3_1(x) \ 2568 (((x) >> BIT_SHIFT_BB_DBG_SEL_AFE_SDM_BIT3_1) & \ 2569 BIT_MASK_BB_DBG_SEL_AFE_SDM_BIT3_1) 2570 2571 /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ 2572 2573 #define BIT_BT_INT_EN BIT(31) 2574 2575 #define BIT_SHIFT_RD_WR_WIFI_BT_INFO 16 2576 #define BIT_MASK_RD_WR_WIFI_BT_INFO 0x7fff 2577 #define BIT_RD_WR_WIFI_BT_INFO(x) \ 2578 (((x) & BIT_MASK_RD_WR_WIFI_BT_INFO) << BIT_SHIFT_RD_WR_WIFI_BT_INFO) 2579 #define BIT_GET_RD_WR_WIFI_BT_INFO(x) \ 2580 (((x) >> BIT_SHIFT_RD_WR_WIFI_BT_INFO) & BIT_MASK_RD_WR_WIFI_BT_INFO) 2581 2582 /* 2 REG_PMC_DBG_CTRL1 (Offset 0x00A8) */ 2583 2584 #define BIT_PMC_WR_OVF BIT(8) 2585 2586 #define BIT_SHIFT_WLPMC_ERRINT 0 2587 #define BIT_MASK_WLPMC_ERRINT 0xff 2588 #define BIT_WLPMC_ERRINT(x) \ 2589 (((x) & BIT_MASK_WLPMC_ERRINT) << BIT_SHIFT_WLPMC_ERRINT) 2590 #define BIT_GET_WLPMC_ERRINT(x) \ 2591 (((x) >> BIT_SHIFT_WLPMC_ERRINT) & BIT_MASK_WLPMC_ERRINT) 2592 2593 /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2594 2595 #define BIT_SHIFT_SEL_V 30 2596 #define BIT_MASK_SEL_V 0x3 2597 #define BIT_SEL_V(x) (((x) & BIT_MASK_SEL_V) << BIT_SHIFT_SEL_V) 2598 #define BIT_GET_SEL_V(x) (((x) >> BIT_SHIFT_SEL_V) & BIT_MASK_SEL_V) 2599 2600 /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2601 2602 #define BIT_TXFIFO_TH_INT BIT(30) 2603 2604 /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2605 2606 #define BIT_SEL_LDO_PC BIT(29) 2607 2608 /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2609 2610 #define BIT_SHIFT_CK_MON_SEL 26 2611 #define BIT_MASK_CK_MON_SEL 0x7 2612 #define BIT_CK_MON_SEL(x) (((x) & BIT_MASK_CK_MON_SEL) << BIT_SHIFT_CK_MON_SEL) 2613 #define BIT_GET_CK_MON_SEL(x) \ 2614 (((x) >> BIT_SHIFT_CK_MON_SEL) & BIT_MASK_CK_MON_SEL) 2615 2616 /* 2 REG_AFE_CTRL7 (Offset 0x00AC) */ 2617 2618 #define BIT_CK_MON_EN BIT(25) 2619 #define BIT_FREF_EDGE BIT(24) 2620 #define BIT_CK320M_EN BIT(23) 2621 #define BIT_CK_5M_EN BIT(22) 2622 #define BIT_TESTEN BIT(21) 2623 2624 /* 2 REG_HIMR0 (Offset 0x00B0) */ 2625 2626 #define BIT_TIMEOUT_INTERRUPT2_MASK BIT(31) 2627 #define BIT_TIMEOUT_INTERRUTP1_MASK BIT(30) 2628 #define BIT_PSTIMEOUT_MSK BIT(29) 2629 #define BIT_GTINT4_MSK BIT(28) 2630 #define BIT_GTINT3_MSK BIT(27) 2631 #define BIT_TXBCN0ERR_MSK BIT(26) 2632 #define BIT_TXBCN0OK_MSK BIT(25) 2633 #define BIT_TSF_BIT32_TOGGLE_MSK BIT(24) 2634 #define BIT_BCNDMAINT0_MSK BIT(20) 2635 #define BIT_BCNDERR0_MSK BIT(16) 2636 #define BIT_HSISR_IND_ON_INT_MSK BIT(15) 2637 2638 /* 2 REG_HIMR0 (Offset 0x00B0) */ 2639 2640 #define BIT_BCNDMAINT_E_MSK BIT(14) 2641 2642 /* 2 REG_HIMR0 (Offset 0x00B0) */ 2643 2644 #define BIT_CTWEND_MSK BIT(12) 2645 #define BIT_HISR1_IND_MSK BIT(11) 2646 2647 /* 2 REG_HIMR0 (Offset 0x00B0) */ 2648 2649 #define BIT_C2HCMD_MSK BIT(10) 2650 #define BIT_CPWM2_MSK BIT(9) 2651 #define BIT_CPWM_MSK BIT(8) 2652 #define BIT_HIGHDOK_MSK BIT(7) 2653 #define BIT_MGTDOK_MSK BIT(6) 2654 #define BIT_BKDOK_MSK BIT(5) 2655 #define BIT_BEDOK_MSK BIT(4) 2656 #define BIT_VIDOK_MSK BIT(3) 2657 #define BIT_VODOK_MSK BIT(2) 2658 #define BIT_RDU_MSK BIT(1) 2659 #define BIT_RXOK_MSK BIT(0) 2660 2661 /* 2 REG_HISR0 (Offset 0x00B4) */ 2662 2663 #define BIT_TIMEOUT_INTERRUPT2 BIT(31) 2664 2665 /* 2 REG_HISR0 (Offset 0x00B4) */ 2666 2667 #define BIT_TIMEOUT_INTERRUTP1 BIT(30) 2668 2669 /* 2 REG_HISR0 (Offset 0x00B4) */ 2670 2671 #define BIT_PSTIMEOUT BIT(29) 2672 #define BIT_GTINT4 BIT(28) 2673 #define BIT_GTINT3 BIT(27) 2674 #define BIT_TXBCN0ERR BIT(26) 2675 #define BIT_TXBCN0OK BIT(25) 2676 #define BIT_TSF_BIT32_TOGGLE BIT(24) 2677 #define BIT_BCNDMAINT0 BIT(20) 2678 #define BIT_BCNDERR0 BIT(16) 2679 #define BIT_HSISR_IND_ON_INT BIT(15) 2680 2681 /* 2 REG_HISR0 (Offset 0x00B4) */ 2682 2683 #define BIT_BCNDMAINT_E BIT(14) 2684 2685 /* 2 REG_HISR0 (Offset 0x00B4) */ 2686 2687 #define BIT_CTWEND BIT(12) 2688 2689 /* 2 REG_HISR0 (Offset 0x00B4) */ 2690 2691 #define BIT_HISR1_IND_INT BIT(11) 2692 #define BIT_C2HCMD BIT(10) 2693 #define BIT_CPWM2 BIT(9) 2694 #define BIT_CPWM BIT(8) 2695 #define BIT_HIGHDOK BIT(7) 2696 #define BIT_MGTDOK BIT(6) 2697 #define BIT_BKDOK BIT(5) 2698 #define BIT_BEDOK BIT(4) 2699 #define BIT_VIDOK BIT(3) 2700 #define BIT_VODOK BIT(2) 2701 #define BIT_RDU BIT(1) 2702 #define BIT_RXOK BIT(0) 2703 2704 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2705 2706 #define BIT_BTON_STS_UPDATE_MASK BIT(29) 2707 2708 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2709 2710 #define BIT_MCU_ERR_MASK BIT(28) 2711 2712 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2713 2714 #define BIT_BCNDMAINT7__MSK BIT(27) 2715 2716 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2717 2718 #define BIT_BCNDMAINT6__MSK BIT(26) 2719 2720 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2721 2722 #define BIT_BCNDMAINT5__MSK BIT(25) 2723 2724 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2725 2726 #define BIT_BCNDMAINT4__MSK BIT(24) 2727 2728 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2729 2730 #define BIT_BCNDMAINT3_MSK BIT(23) 2731 #define BIT_BCNDMAINT2_MSK BIT(22) 2732 #define BIT_BCNDMAINT1_MSK BIT(21) 2733 #define BIT_BCNDERR7_MSK BIT(20) 2734 #define BIT_BCNDERR6_MSK BIT(19) 2735 #define BIT_BCNDERR5_MSK BIT(18) 2736 #define BIT_BCNDERR4_MSK BIT(17) 2737 #define BIT_BCNDERR3_MSK BIT(16) 2738 #define BIT_BCNDERR2_MSK BIT(15) 2739 #define BIT_BCNDERR1_MSK BIT(14) 2740 2741 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2742 2743 #define BIT_ATIMEND_E_MSK BIT(13) 2744 2745 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2746 2747 #define BIT_ATIMEND__MSK BIT(12) 2748 2749 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2750 2751 #define BIT_TXERR_MSK BIT(11) 2752 #define BIT_RXERR_MSK BIT(10) 2753 #define BIT_TXFOVW_MSK BIT(9) 2754 #define BIT_FOVW_MSK BIT(8) 2755 2756 /* 2 REG_HIMR1 (Offset 0x00B8) */ 2757 2758 #define BIT_CPU_MGQ_TXDONE_MSK BIT(5) 2759 #define BIT_PS_TIMER_C_MSK BIT(4) 2760 #define BIT_PS_TIMER_B_MSK BIT(3) 2761 #define BIT_PS_TIMER_A_MSK BIT(2) 2762 #define BIT_CPUMGQ_TX_TIMER_MSK BIT(1) 2763 2764 /* 2 REG_HISR1 (Offset 0x00BC) */ 2765 2766 #define BIT_BTON_STS_UPDATE_INT BIT(29) 2767 2768 /* 2 REG_HISR1 (Offset 0x00BC) */ 2769 2770 #define BIT_MCU_ERR BIT(28) 2771 2772 /* 2 REG_HISR1 (Offset 0x00BC) */ 2773 2774 #define BIT_BCNDMAINT7 BIT(27) 2775 #define BIT_BCNDMAINT6 BIT(26) 2776 #define BIT_BCNDMAINT5 BIT(25) 2777 #define BIT_BCNDMAINT4 BIT(24) 2778 #define BIT_BCNDMAINT3 BIT(23) 2779 #define BIT_BCNDMAINT2 BIT(22) 2780 #define BIT_BCNDMAINT1 BIT(21) 2781 #define BIT_BCNDERR7 BIT(20) 2782 #define BIT_BCNDERR6 BIT(19) 2783 #define BIT_BCNDERR5 BIT(18) 2784 #define BIT_BCNDERR4 BIT(17) 2785 #define BIT_BCNDERR3 BIT(16) 2786 #define BIT_BCNDERR2 BIT(15) 2787 #define BIT_BCNDERR1 BIT(14) 2788 2789 /* 2 REG_HISR1 (Offset 0x00BC) */ 2790 2791 #define BIT_ATIMEND_E BIT(13) 2792 2793 /* 2 REG_HISR1 (Offset 0x00BC) */ 2794 2795 #define BIT_ATIMEND BIT(12) 2796 #define BIT_TXERR_INT BIT(11) 2797 #define BIT_RXERR_INT BIT(10) 2798 #define BIT_TXFOVW BIT(9) 2799 #define BIT_FOVW BIT(8) 2800 2801 /* 2 REG_HISR1 (Offset 0x00BC) */ 2802 2803 #define BIT_CPU_MGQ_TXDONE BIT(5) 2804 #define BIT_PS_TIMER_C BIT(4) 2805 #define BIT_PS_TIMER_B BIT(3) 2806 #define BIT_PS_TIMER_A BIT(2) 2807 #define BIT_CPUMGQ_TX_TIMER BIT(1) 2808 2809 /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ 2810 2811 #define BIT_HR_FF_OVF BIT(6) 2812 #define BIT_HR_FF_UDN BIT(5) 2813 #define BIT_TXDMA_BUSY_ERR BIT(4) 2814 #define BIT_TXDMA_VLD_ERR BIT(3) 2815 #define BIT_QSEL_UNKNOWN_ERR BIT(2) 2816 #define BIT_QSEL_MIS_ERR BIT(1) 2817 2818 /* 2 REG_DBG_PORT_SEL (Offset 0x00C0) */ 2819 2820 #define BIT_SHIFT_DEBUG_ST 0 2821 #define BIT_MASK_DEBUG_ST 0xffffffffL 2822 #define BIT_DEBUG_ST(x) (((x) & BIT_MASK_DEBUG_ST) << BIT_SHIFT_DEBUG_ST) 2823 #define BIT_GET_DEBUG_ST(x) (((x) >> BIT_SHIFT_DEBUG_ST) & BIT_MASK_DEBUG_ST) 2824 2825 /* 2 REG_SDIO_ERR_RPT (Offset 0x102500C0) */ 2826 2827 #define BIT_SDIO_OVERRD_ERR BIT(0) 2828 2829 /* 2 REG_SDIO_CMD_ERRCNT (Offset 0x102500C1) */ 2830 2831 #define BIT_SHIFT_CMD_CRC_ERR_CNT 0 2832 #define BIT_MASK_CMD_CRC_ERR_CNT 0xff 2833 #define BIT_CMD_CRC_ERR_CNT(x) \ 2834 (((x) & BIT_MASK_CMD_CRC_ERR_CNT) << BIT_SHIFT_CMD_CRC_ERR_CNT) 2835 #define BIT_GET_CMD_CRC_ERR_CNT(x) \ 2836 (((x) >> BIT_SHIFT_CMD_CRC_ERR_CNT) & BIT_MASK_CMD_CRC_ERR_CNT) 2837 2838 /* 2 REG_SDIO_DATA_ERRCNT (Offset 0x102500C2) */ 2839 2840 #define BIT_SHIFT_DATA_CRC_ERR_CNT 0 2841 #define BIT_MASK_DATA_CRC_ERR_CNT 0xff 2842 #define BIT_DATA_CRC_ERR_CNT(x) \ 2843 (((x) & BIT_MASK_DATA_CRC_ERR_CNT) << BIT_SHIFT_DATA_CRC_ERR_CNT) 2844 #define BIT_GET_DATA_CRC_ERR_CNT(x) \ 2845 (((x) >> BIT_SHIFT_DATA_CRC_ERR_CNT) & BIT_MASK_DATA_CRC_ERR_CNT) 2846 2847 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2848 2849 #define BIT_USB3_USB2_TRANSITION BIT(20) 2850 2851 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2852 2853 #define BIT_SHIFT_USB23_SW_MODE_V1 18 2854 #define BIT_MASK_USB23_SW_MODE_V1 0x3 2855 #define BIT_USB23_SW_MODE_V1(x) \ 2856 (((x) & BIT_MASK_USB23_SW_MODE_V1) << BIT_SHIFT_USB23_SW_MODE_V1) 2857 #define BIT_GET_USB23_SW_MODE_V1(x) \ 2858 (((x) >> BIT_SHIFT_USB23_SW_MODE_V1) & BIT_MASK_USB23_SW_MODE_V1) 2859 2860 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2861 2862 #define BIT_NO_PDN_CHIPOFF_V1 BIT(17) 2863 2864 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2865 2866 #define BIT_RSM_EN_V1 BIT(16) 2867 2868 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2869 2870 #define BIT_LD_B12V_EN BIT(7) 2871 2872 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2873 2874 #define BIT_EECS_IOSEL_V1 BIT(6) 2875 2876 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2877 2878 #define BIT_EECS_DATA_O_V1 BIT(5) 2879 2880 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2881 2882 #define BIT_EECS_DATA_I_V1 BIT(4) 2883 2884 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2885 2886 #define BIT_EESK_IOSEL_V1 BIT(2) 2887 2888 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2889 2890 #define BIT_EESK_DATA_O_V1 BIT(1) 2891 2892 /* 2 REG_PAD_CTRL2 (Offset 0x00C4) */ 2893 2894 #define BIT_EESK_DATA_I_V1 BIT(0) 2895 2896 /* 2 REG_SDIO_CMD_ERR_CONTENT (Offset 0x102500C4) */ 2897 2898 #define BIT_SHIFT_SDIO_CMD_ERR_CONTENT 0 2899 #define BIT_MASK_SDIO_CMD_ERR_CONTENT 0xffffffffffL 2900 #define BIT_SDIO_CMD_ERR_CONTENT(x) \ 2901 (((x) & BIT_MASK_SDIO_CMD_ERR_CONTENT) \ 2902 << BIT_SHIFT_SDIO_CMD_ERR_CONTENT) 2903 #define BIT_GET_SDIO_CMD_ERR_CONTENT(x) \ 2904 (((x) >> BIT_SHIFT_SDIO_CMD_ERR_CONTENT) & \ 2905 BIT_MASK_SDIO_CMD_ERR_CONTENT) 2906 2907 /* 2 REG_SDIO_CRC_ERR_IDX (Offset 0x102500C9) */ 2908 2909 #define BIT_D3_CRC_ERR BIT(4) 2910 #define BIT_D2_CRC_ERR BIT(3) 2911 #define BIT_D1_CRC_ERR BIT(2) 2912 #define BIT_D0_CRC_ERR BIT(1) 2913 #define BIT_CMD_CRC_ERR BIT(0) 2914 2915 /* 2 REG_SDIO_DATA_CRC (Offset 0x102500CA) */ 2916 2917 #define BIT_SHIFT_SDIO_DATA_CRC 0 2918 #define BIT_MASK_SDIO_DATA_CRC 0xff 2919 #define BIT_SDIO_DATA_CRC(x) \ 2920 (((x) & BIT_MASK_SDIO_DATA_CRC) << BIT_SHIFT_SDIO_DATA_CRC) 2921 #define BIT_GET_SDIO_DATA_CRC(x) \ 2922 (((x) >> BIT_SHIFT_SDIO_DATA_CRC) & BIT_MASK_SDIO_DATA_CRC) 2923 2924 /* 2 REG_SDIO_DATA_REPLY_TIME (Offset 0x102500CB) */ 2925 2926 #define BIT_SHIFT_SDIO_DATA_REPLY_TIME 0 2927 #define BIT_MASK_SDIO_DATA_REPLY_TIME 0x7 2928 #define BIT_SDIO_DATA_REPLY_TIME(x) \ 2929 (((x) & BIT_MASK_SDIO_DATA_REPLY_TIME) \ 2930 << BIT_SHIFT_SDIO_DATA_REPLY_TIME) 2931 #define BIT_GET_SDIO_DATA_REPLY_TIME(x) \ 2932 (((x) >> BIT_SHIFT_SDIO_DATA_REPLY_TIME) & \ 2933 BIT_MASK_SDIO_DATA_REPLY_TIME) 2934 2935 /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ 2936 2937 #define BIT_SHIFT_EFUSE_BURN_GNT 24 2938 #define BIT_MASK_EFUSE_BURN_GNT 0xff 2939 #define BIT_EFUSE_BURN_GNT(x) \ 2940 (((x) & BIT_MASK_EFUSE_BURN_GNT) << BIT_SHIFT_EFUSE_BURN_GNT) 2941 #define BIT_GET_EFUSE_BURN_GNT(x) \ 2942 (((x) >> BIT_SHIFT_EFUSE_BURN_GNT) & BIT_MASK_EFUSE_BURN_GNT) 2943 2944 /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ 2945 2946 #define BIT_STOP_WL_PMC BIT(9) 2947 #define BIT_STOP_SYM_PMC BIT(8) 2948 2949 /* 2 REG_PMC_DBG_CTRL2 (Offset 0x00CC) */ 2950 2951 #define BIT_REG_RST_WLPMC BIT(5) 2952 #define BIT_REG_RST_PD12N BIT(4) 2953 #define BIT_SYSON_DIS_WLREG_WRMSK BIT(3) 2954 #define BIT_SYSON_DIS_PMCREG_WRMSK BIT(2) 2955 2956 #define BIT_SHIFT_SYSON_REG_ARB 0 2957 #define BIT_MASK_SYSON_REG_ARB 0x3 2958 #define BIT_SYSON_REG_ARB(x) \ 2959 (((x) & BIT_MASK_SYSON_REG_ARB) << BIT_SHIFT_SYSON_REG_ARB) 2960 #define BIT_GET_SYSON_REG_ARB(x) \ 2961 (((x) >> BIT_SHIFT_SYSON_REG_ARB) & BIT_MASK_SYSON_REG_ARB) 2962 2963 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2964 2965 #define BIT_BIST_USB_DIS BIT(27) 2966 2967 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2968 2969 #define BIT_BIST_PCI_DIS BIT(26) 2970 2971 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2972 2973 #define BIT_BIST_BT_DIS BIT(25) 2974 2975 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2976 2977 #define BIT_BIST_WL_DIS BIT(24) 2978 2979 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2980 2981 #define BIT_SHIFT_BIST_RPT_SEL 16 2982 #define BIT_MASK_BIST_RPT_SEL 0xf 2983 #define BIT_BIST_RPT_SEL(x) \ 2984 (((x) & BIT_MASK_BIST_RPT_SEL) << BIT_SHIFT_BIST_RPT_SEL) 2985 #define BIT_GET_BIST_RPT_SEL(x) \ 2986 (((x) >> BIT_SHIFT_BIST_RPT_SEL) & BIT_MASK_BIST_RPT_SEL) 2987 2988 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2989 2990 #define BIT_BIST_RESUME_PS BIT(4) 2991 2992 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2993 2994 #define BIT_BIST_RESUME BIT(3) 2995 #define BIT_BIST_NORMAL BIT(2) 2996 2997 /* 2 REG_BIST_CTRL (Offset 0x00D0) */ 2998 2999 #define BIT_BIST_RSTN BIT(1) 3000 #define BIT_BIST_CLK_EN BIT(0) 3001 3002 /* 2 REG_BIST_RPT (Offset 0x00D4) */ 3003 3004 #define BIT_SHIFT_MBIST_REPORT 0 3005 #define BIT_MASK_MBIST_REPORT 0xffffffffL 3006 #define BIT_MBIST_REPORT(x) \ 3007 (((x) & BIT_MASK_MBIST_REPORT) << BIT_SHIFT_MBIST_REPORT) 3008 #define BIT_GET_MBIST_REPORT(x) \ 3009 (((x) >> BIT_SHIFT_MBIST_REPORT) & BIT_MASK_MBIST_REPORT) 3010 3011 /* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3012 3013 #define BIT_UMEM_RME BIT(31) 3014 3015 /* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3016 3017 #define BIT_SHIFT_BT_SPRAM 28 3018 #define BIT_MASK_BT_SPRAM 0x3 3019 #define BIT_BT_SPRAM(x) (((x) & BIT_MASK_BT_SPRAM) << BIT_SHIFT_BT_SPRAM) 3020 #define BIT_GET_BT_SPRAM(x) (((x) >> BIT_SHIFT_BT_SPRAM) & BIT_MASK_BT_SPRAM) 3021 3022 /* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3023 3024 #define BIT_SHIFT_BT_ROM 24 3025 #define BIT_MASK_BT_ROM 0xf 3026 #define BIT_BT_ROM(x) (((x) & BIT_MASK_BT_ROM) << BIT_SHIFT_BT_ROM) 3027 #define BIT_GET_BT_ROM(x) (((x) >> BIT_SHIFT_BT_ROM) & BIT_MASK_BT_ROM) 3028 3029 #define BIT_SHIFT_PCI_DPRAM 10 3030 #define BIT_MASK_PCI_DPRAM 0x3 3031 #define BIT_PCI_DPRAM(x) (((x) & BIT_MASK_PCI_DPRAM) << BIT_SHIFT_PCI_DPRAM) 3032 #define BIT_GET_PCI_DPRAM(x) (((x) >> BIT_SHIFT_PCI_DPRAM) & BIT_MASK_PCI_DPRAM) 3033 3034 /* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3035 3036 #define BIT_SHIFT_PCI_SPRAM 8 3037 #define BIT_MASK_PCI_SPRAM 0x3 3038 #define BIT_PCI_SPRAM(x) (((x) & BIT_MASK_PCI_SPRAM) << BIT_SHIFT_PCI_SPRAM) 3039 #define BIT_GET_PCI_SPRAM(x) (((x) >> BIT_SHIFT_PCI_SPRAM) & BIT_MASK_PCI_SPRAM) 3040 3041 #define BIT_SHIFT_USB_SPRAM 6 3042 #define BIT_MASK_USB_SPRAM 0x3 3043 #define BIT_USB_SPRAM(x) (((x) & BIT_MASK_USB_SPRAM) << BIT_SHIFT_USB_SPRAM) 3044 #define BIT_GET_USB_SPRAM(x) (((x) >> BIT_SHIFT_USB_SPRAM) & BIT_MASK_USB_SPRAM) 3045 3046 /* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3047 3048 #define BIT_SHIFT_USB_SPRF 4 3049 #define BIT_MASK_USB_SPRF 0x3 3050 #define BIT_USB_SPRF(x) (((x) & BIT_MASK_USB_SPRF) << BIT_SHIFT_USB_SPRF) 3051 #define BIT_GET_USB_SPRF(x) (((x) >> BIT_SHIFT_USB_SPRF) & BIT_MASK_USB_SPRF) 3052 3053 /* 2 REG_MEM_CTRL (Offset 0x00D8) */ 3054 3055 #define BIT_SHIFT_MCU_ROM 0 3056 #define BIT_MASK_MCU_ROM 0xf 3057 #define BIT_MCU_ROM(x) (((x) & BIT_MASK_MCU_ROM) << BIT_SHIFT_MCU_ROM) 3058 #define BIT_GET_MCU_ROM(x) (((x) >> BIT_SHIFT_MCU_ROM) & BIT_MASK_MCU_ROM) 3059 3060 /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ 3061 3062 #define BIT_SYN_AGPIO BIT(20) 3063 3064 /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ 3065 3066 #define BIT_XTAL_LP BIT(4) 3067 #define BIT_XTAL_GM_SEP BIT(3) 3068 3069 /* 2 REG_AFE_CTRL8 (Offset 0x00DC) */ 3070 3071 #define BIT_SHIFT_XTAL_SEL_TOK 0 3072 #define BIT_MASK_XTAL_SEL_TOK 0x7 3073 #define BIT_XTAL_SEL_TOK(x) \ 3074 (((x) & BIT_MASK_XTAL_SEL_TOK) << BIT_SHIFT_XTAL_SEL_TOK) 3075 #define BIT_GET_XTAL_SEL_TOK(x) \ 3076 (((x) >> BIT_SHIFT_XTAL_SEL_TOK) & BIT_MASK_XTAL_SEL_TOK) 3077 3078 /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3079 3080 #define BIT_RD_SEL BIT(31) 3081 3082 /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3083 3084 #define BIT_USB_SIE_INTF_WE_V1 BIT(30) 3085 #define BIT_USB_SIE_INTF_BYIOREG_V1 BIT(29) 3086 #define BIT_USB_SIE_SELECT BIT(28) 3087 3088 /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3089 3090 #define BIT_SHIFT_USB_SIE_INTF_ADDR_V1 16 3091 #define BIT_MASK_USB_SIE_INTF_ADDR_V1 0x1ff 3092 #define BIT_USB_SIE_INTF_ADDR_V1(x) \ 3093 (((x) & BIT_MASK_USB_SIE_INTF_ADDR_V1) \ 3094 << BIT_SHIFT_USB_SIE_INTF_ADDR_V1) 3095 #define BIT_GET_USB_SIE_INTF_ADDR_V1(x) \ 3096 (((x) >> BIT_SHIFT_USB_SIE_INTF_ADDR_V1) & \ 3097 BIT_MASK_USB_SIE_INTF_ADDR_V1) 3098 3099 /* 2 REG_USB_SIE_INTF (Offset 0x00E0) */ 3100 3101 #define BIT_SHIFT_USB_SIE_INTF_RD 8 3102 #define BIT_MASK_USB_SIE_INTF_RD 0xff 3103 #define BIT_USB_SIE_INTF_RD(x) \ 3104 (((x) & BIT_MASK_USB_SIE_INTF_RD) << BIT_SHIFT_USB_SIE_INTF_RD) 3105 #define BIT_GET_USB_SIE_INTF_RD(x) \ 3106 (((x) >> BIT_SHIFT_USB_SIE_INTF_RD) & BIT_MASK_USB_SIE_INTF_RD) 3107 3108 #define BIT_SHIFT_USB_SIE_INTF_WD 0 3109 #define BIT_MASK_USB_SIE_INTF_WD 0xff 3110 #define BIT_USB_SIE_INTF_WD(x) \ 3111 (((x) & BIT_MASK_USB_SIE_INTF_WD) << BIT_SHIFT_USB_SIE_INTF_WD) 3112 #define BIT_GET_USB_SIE_INTF_WD(x) \ 3113 (((x) >> BIT_SHIFT_USB_SIE_INTF_WD) & BIT_MASK_USB_SIE_INTF_WD) 3114 3115 /* 2 REG_PCIE_MIO_INTF (Offset 0x00E4) */ 3116 3117 #define BIT_PCIE_MIO_BYIOREG BIT(13) 3118 #define BIT_PCIE_MIO_RE BIT(12) 3119 3120 #define BIT_SHIFT_PCIE_MIO_WE 8 3121 #define BIT_MASK_PCIE_MIO_WE 0xf 3122 #define BIT_PCIE_MIO_WE(x) \ 3123 (((x) & BIT_MASK_PCIE_MIO_WE) << BIT_SHIFT_PCIE_MIO_WE) 3124 #define BIT_GET_PCIE_MIO_WE(x) \ 3125 (((x) >> BIT_SHIFT_PCIE_MIO_WE) & BIT_MASK_PCIE_MIO_WE) 3126 3127 #define BIT_SHIFT_PCIE_MIO_ADDR 0 3128 #define BIT_MASK_PCIE_MIO_ADDR 0xff 3129 #define BIT_PCIE_MIO_ADDR(x) \ 3130 (((x) & BIT_MASK_PCIE_MIO_ADDR) << BIT_SHIFT_PCIE_MIO_ADDR) 3131 #define BIT_GET_PCIE_MIO_ADDR(x) \ 3132 (((x) >> BIT_SHIFT_PCIE_MIO_ADDR) & BIT_MASK_PCIE_MIO_ADDR) 3133 3134 /* 2 REG_PCIE_MIO_INTD (Offset 0x00E8) */ 3135 3136 #define BIT_SHIFT_PCIE_MIO_DATA 0 3137 #define BIT_MASK_PCIE_MIO_DATA 0xffffffffL 3138 #define BIT_PCIE_MIO_DATA(x) \ 3139 (((x) & BIT_MASK_PCIE_MIO_DATA) << BIT_SHIFT_PCIE_MIO_DATA) 3140 #define BIT_GET_PCIE_MIO_DATA(x) \ 3141 (((x) >> BIT_SHIFT_PCIE_MIO_DATA) & BIT_MASK_PCIE_MIO_DATA) 3142 3143 /* 2 REG_WLRF1 (Offset 0x00EC) */ 3144 3145 #define BIT_SHIFT_WLRF1_CTRL 24 3146 #define BIT_MASK_WLRF1_CTRL 0xff 3147 #define BIT_WLRF1_CTRL(x) (((x) & BIT_MASK_WLRF1_CTRL) << BIT_SHIFT_WLRF1_CTRL) 3148 #define BIT_GET_WLRF1_CTRL(x) \ 3149 (((x) >> BIT_SHIFT_WLRF1_CTRL) & BIT_MASK_WLRF1_CTRL) 3150 3151 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3152 3153 #define BIT_SHIFT_TRP_ICFG 28 3154 #define BIT_MASK_TRP_ICFG 0xf 3155 #define BIT_TRP_ICFG(x) (((x) & BIT_MASK_TRP_ICFG) << BIT_SHIFT_TRP_ICFG) 3156 #define BIT_GET_TRP_ICFG(x) (((x) >> BIT_SHIFT_TRP_ICFG) & BIT_MASK_TRP_ICFG) 3157 3158 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3159 3160 #define BIT_RF_TYPE_ID BIT(27) 3161 #define BIT_BD_HCI_SEL BIT(26) 3162 3163 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3164 3165 #define BIT_BD_PKG_SEL BIT(25) 3166 3167 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3168 3169 #define BIT_SPSLDO_SEL BIT(24) 3170 3171 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3172 3173 #define BIT_RTL_ID BIT(23) 3174 #define BIT_PAD_HWPD_IDN BIT(22) 3175 3176 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3177 3178 #define BIT_TESTMODE BIT(20) 3179 3180 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3181 3182 #define BIT_SHIFT_VENDOR_ID 16 3183 #define BIT_MASK_VENDOR_ID 0xf 3184 #define BIT_VENDOR_ID(x) (((x) & BIT_MASK_VENDOR_ID) << BIT_SHIFT_VENDOR_ID) 3185 #define BIT_GET_VENDOR_ID(x) (((x) >> BIT_SHIFT_VENDOR_ID) & BIT_MASK_VENDOR_ID) 3186 3187 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3188 3189 #define BIT_SHIFT_CHIP_VER 12 3190 #define BIT_MASK_CHIP_VER 0xf 3191 #define BIT_CHIP_VER(x) (((x) & BIT_MASK_CHIP_VER) << BIT_SHIFT_CHIP_VER) 3192 #define BIT_GET_CHIP_VER(x) (((x) >> BIT_SHIFT_CHIP_VER) & BIT_MASK_CHIP_VER) 3193 3194 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3195 3196 #define BIT_BD_MAC3 BIT(11) 3197 3198 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3199 3200 #define BIT_BD_MAC1 BIT(10) 3201 #define BIT_BD_MAC2 BIT(9) 3202 #define BIT_SIC_IDLE BIT(8) 3203 #define BIT_SW_OFFLOAD_EN BIT(7) 3204 3205 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3206 3207 #define BIT_OCP_SHUTDN BIT(6) 3208 3209 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3210 3211 #define BIT_V15_VLD BIT(5) 3212 3213 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3214 3215 #define BIT_PCIRSTB BIT(4) 3216 3217 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3218 3219 #define BIT_PCLK_VLD BIT(3) 3220 3221 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3222 3223 #define BIT_UCLK_VLD BIT(2) 3224 3225 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3226 3227 #define BIT_ACLK_VLD BIT(1) 3228 3229 /* 2 REG_SYS_CFG1 (Offset 0x00F0) */ 3230 3231 #define BIT_XCLK_VLD BIT(0) 3232 3233 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3234 3235 #define BIT_SHIFT_RF_RL_ID 28 3236 #define BIT_MASK_RF_RL_ID 0xf 3237 #define BIT_RF_RL_ID(x) (((x) & BIT_MASK_RF_RL_ID) << BIT_SHIFT_RF_RL_ID) 3238 #define BIT_GET_RF_RL_ID(x) (((x) >> BIT_SHIFT_RF_RL_ID) & BIT_MASK_RF_RL_ID) 3239 3240 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3241 3242 #define BIT_HPHY_ICFG BIT(19) 3243 3244 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3245 3246 #define BIT_SHIFT_SEL_0XC0 16 3247 #define BIT_MASK_SEL_0XC0 0x3 3248 #define BIT_SEL_0XC0(x) (((x) & BIT_MASK_SEL_0XC0) << BIT_SHIFT_SEL_0XC0) 3249 #define BIT_GET_SEL_0XC0(x) (((x) >> BIT_SHIFT_SEL_0XC0) & BIT_MASK_SEL_0XC0) 3250 3251 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3252 3253 #define BIT_SHIFT_HCI_SEL_V3 12 3254 #define BIT_MASK_HCI_SEL_V3 0x7 3255 #define BIT_HCI_SEL_V3(x) (((x) & BIT_MASK_HCI_SEL_V3) << BIT_SHIFT_HCI_SEL_V3) 3256 #define BIT_GET_HCI_SEL_V3(x) \ 3257 (((x) >> BIT_SHIFT_HCI_SEL_V3) & BIT_MASK_HCI_SEL_V3) 3258 3259 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3260 3261 #define BIT_USB_OPERATION_MODE BIT(10) 3262 #define BIT_BT_PDN BIT(9) 3263 #define BIT_AUTO_WLPON BIT(8) 3264 3265 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3266 3267 #define BIT_WL_MODE BIT(7) 3268 3269 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3270 3271 #define BIT_PKG_SEL_HCI BIT(6) 3272 3273 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3274 3275 #define BIT_SHIFT_PAD_HCI_SEL_V1 3 3276 #define BIT_MASK_PAD_HCI_SEL_V1 0x7 3277 #define BIT_PAD_HCI_SEL_V1(x) \ 3278 (((x) & BIT_MASK_PAD_HCI_SEL_V1) << BIT_SHIFT_PAD_HCI_SEL_V1) 3279 #define BIT_GET_PAD_HCI_SEL_V1(x) \ 3280 (((x) >> BIT_SHIFT_PAD_HCI_SEL_V1) & BIT_MASK_PAD_HCI_SEL_V1) 3281 3282 /* 2 REG_SYS_STATUS1 (Offset 0x00F4) */ 3283 3284 #define BIT_SHIFT_EFS_HCI_SEL_V1 0 3285 #define BIT_MASK_EFS_HCI_SEL_V1 0x7 3286 #define BIT_EFS_HCI_SEL_V1(x) \ 3287 (((x) & BIT_MASK_EFS_HCI_SEL_V1) << BIT_SHIFT_EFS_HCI_SEL_V1) 3288 #define BIT_GET_EFS_HCI_SEL_V1(x) \ 3289 (((x) >> BIT_SHIFT_EFS_HCI_SEL_V1) & BIT_MASK_EFS_HCI_SEL_V1) 3290 3291 /* 2 REG_SYS_STATUS2 (Offset 0x00F8) */ 3292 3293 #define BIT_SIO_ALDN BIT(19) 3294 #define BIT_USB_ALDN BIT(18) 3295 #define BIT_PCI_ALDN BIT(17) 3296 #define BIT_SYS_ALDN BIT(16) 3297 3298 #define BIT_SHIFT_EPVID1 8 3299 #define BIT_MASK_EPVID1 0xff 3300 #define BIT_EPVID1(x) (((x) & BIT_MASK_EPVID1) << BIT_SHIFT_EPVID1) 3301 #define BIT_GET_EPVID1(x) (((x) >> BIT_SHIFT_EPVID1) & BIT_MASK_EPVID1) 3302 3303 #define BIT_SHIFT_EPVID0 0 3304 #define BIT_MASK_EPVID0 0xff 3305 #define BIT_EPVID0(x) (((x) & BIT_MASK_EPVID0) << BIT_SHIFT_EPVID0) 3306 #define BIT_GET_EPVID0(x) (((x) >> BIT_SHIFT_EPVID0) & BIT_MASK_EPVID0) 3307 3308 /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ 3309 3310 #define BIT_HCI_SEL_EMBEDDED BIT(8) 3311 3312 /* 2 REG_SYS_CFG2 (Offset 0x00FC) */ 3313 3314 #define BIT_SHIFT_HW_ID 0 3315 #define BIT_MASK_HW_ID 0xff 3316 #define BIT_HW_ID(x) (((x) & BIT_MASK_HW_ID) << BIT_SHIFT_HW_ID) 3317 #define BIT_GET_HW_ID(x) (((x) >> BIT_SHIFT_HW_ID) & BIT_MASK_HW_ID) 3318 3319 /* 2 REG_CR (Offset 0x0100) */ 3320 3321 #define BIT_SHIFT_LBMODE 24 3322 #define BIT_MASK_LBMODE 0x1f 3323 #define BIT_LBMODE(x) (((x) & BIT_MASK_LBMODE) << BIT_SHIFT_LBMODE) 3324 #define BIT_GET_LBMODE(x) (((x) >> BIT_SHIFT_LBMODE) & BIT_MASK_LBMODE) 3325 3326 #define BIT_SHIFT_NETYPE1 18 3327 #define BIT_MASK_NETYPE1 0x3 3328 #define BIT_NETYPE1(x) (((x) & BIT_MASK_NETYPE1) << BIT_SHIFT_NETYPE1) 3329 #define BIT_GET_NETYPE1(x) (((x) >> BIT_SHIFT_NETYPE1) & BIT_MASK_NETYPE1) 3330 3331 #define BIT_SHIFT_NETYPE0 16 3332 #define BIT_MASK_NETYPE0 0x3 3333 #define BIT_NETYPE0(x) (((x) & BIT_MASK_NETYPE0) << BIT_SHIFT_NETYPE0) 3334 #define BIT_GET_NETYPE0(x) (((x) >> BIT_SHIFT_NETYPE0) & BIT_MASK_NETYPE0) 3335 3336 /* 2 REG_CR (Offset 0x0100) */ 3337 3338 #define BIT_I2C_MAILBOX_EN BIT(12) 3339 #define BIT_SHCUT_EN BIT(11) 3340 3341 /* 2 REG_CR (Offset 0x0100) */ 3342 3343 #define BIT_32K_CAL_TMR_EN BIT(10) 3344 #define BIT_MAC_SEC_EN BIT(9) 3345 #define BIT_ENSWBCN BIT(8) 3346 #define BIT_MACRXEN BIT(7) 3347 #define BIT_MACTXEN BIT(6) 3348 #define BIT_SCHEDULE_EN BIT(5) 3349 #define BIT_PROTOCOL_EN BIT(4) 3350 #define BIT_RXDMA_EN BIT(3) 3351 #define BIT_TXDMA_EN BIT(2) 3352 #define BIT_HCI_RXDMA_EN BIT(1) 3353 #define BIT_HCI_TXDMA_EN BIT(0) 3354 3355 /* 2 REG_PKT_BUFF_ACCESS_CTRL (Offset 0x0106) */ 3356 3357 #define BIT_SHIFT_PKT_BUFF_ACCESS_CTRL 0 3358 #define BIT_MASK_PKT_BUFF_ACCESS_CTRL 0xff 3359 #define BIT_PKT_BUFF_ACCESS_CTRL(x) \ 3360 (((x) & BIT_MASK_PKT_BUFF_ACCESS_CTRL) \ 3361 << BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) 3362 #define BIT_GET_PKT_BUFF_ACCESS_CTRL(x) \ 3363 (((x) >> BIT_SHIFT_PKT_BUFF_ACCESS_CTRL) & \ 3364 BIT_MASK_PKT_BUFF_ACCESS_CTRL) 3365 3366 /* 2 REG_TSF_CLK_STATE (Offset 0x0108) */ 3367 3368 #define BIT_TSF_CLK_STABLE BIT(15) 3369 3370 #define BIT_SHIFT_I2C_M_BUS_GNT_FW 4 3371 #define BIT_MASK_I2C_M_BUS_GNT_FW 0x7 3372 #define BIT_I2C_M_BUS_GNT_FW(x) \ 3373 (((x) & BIT_MASK_I2C_M_BUS_GNT_FW) << BIT_SHIFT_I2C_M_BUS_GNT_FW) 3374 #define BIT_GET_I2C_M_BUS_GNT_FW(x) \ 3375 (((x) >> BIT_SHIFT_I2C_M_BUS_GNT_FW) & BIT_MASK_I2C_M_BUS_GNT_FW) 3376 3377 #define BIT_I2C_M_GNT_FW BIT(3) 3378 3379 #define BIT_SHIFT_I2C_M_SPEED 1 3380 #define BIT_MASK_I2C_M_SPEED 0x3 3381 #define BIT_I2C_M_SPEED(x) \ 3382 (((x) & BIT_MASK_I2C_M_SPEED) << BIT_SHIFT_I2C_M_SPEED) 3383 #define BIT_GET_I2C_M_SPEED(x) \ 3384 (((x) >> BIT_SHIFT_I2C_M_SPEED) & BIT_MASK_I2C_M_SPEED) 3385 3386 #define BIT_I2C_M_UNLOCK BIT(0) 3387 3388 /* 2 REG_TXDMA_PQ_MAP (Offset 0x010C) */ 3389 3390 #define BIT_SHIFT_TXDMA_HIQ_MAP 14 3391 #define BIT_MASK_TXDMA_HIQ_MAP 0x3 3392 #define BIT_TXDMA_HIQ_MAP(x) \ 3393 (((x) & BIT_MASK_TXDMA_HIQ_MAP) << BIT_SHIFT_TXDMA_HIQ_MAP) 3394 #define BIT_GET_TXDMA_HIQ_MAP(x) \ 3395 (((x) >> BIT_SHIFT_TXDMA_HIQ_MAP) & BIT_MASK_TXDMA_HIQ_MAP) 3396 3397 #define BIT_SHIFT_TXDMA_MGQ_MAP 12 3398 #define BIT_MASK_TXDMA_MGQ_MAP 0x3 3399 #define BIT_TXDMA_MGQ_MAP(x) \ 3400 (((x) & BIT_MASK_TXDMA_MGQ_MAP) << BIT_SHIFT_TXDMA_MGQ_MAP) 3401 #define BIT_GET_TXDMA_MGQ_MAP(x) \ 3402 (((x) >> BIT_SHIFT_TXDMA_MGQ_MAP) & BIT_MASK_TXDMA_MGQ_MAP) 3403 3404 #define BIT_SHIFT_TXDMA_BKQ_MAP 10 3405 #define BIT_MASK_TXDMA_BKQ_MAP 0x3 3406 #define BIT_TXDMA_BKQ_MAP(x) \ 3407 (((x) & BIT_MASK_TXDMA_BKQ_MAP) << BIT_SHIFT_TXDMA_BKQ_MAP) 3408 #define BIT_GET_TXDMA_BKQ_MAP(x) \ 3409 (((x) >> BIT_SHIFT_TXDMA_BKQ_MAP) & BIT_MASK_TXDMA_BKQ_MAP) 3410 3411 #define BIT_SHIFT_TXDMA_BEQ_MAP 8 3412 #define BIT_MASK_TXDMA_BEQ_MAP 0x3 3413 #define BIT_TXDMA_BEQ_MAP(x) \ 3414 (((x) & BIT_MASK_TXDMA_BEQ_MAP) << BIT_SHIFT_TXDMA_BEQ_MAP) 3415 #define BIT_GET_TXDMA_BEQ_MAP(x) \ 3416 (((x) >> BIT_SHIFT_TXDMA_BEQ_MAP) & BIT_MASK_TXDMA_BEQ_MAP) 3417 3418 #define BIT_SHIFT_TXDMA_VIQ_MAP 6 3419 #define BIT_MASK_TXDMA_VIQ_MAP 0x3 3420 #define BIT_TXDMA_VIQ_MAP(x) \ 3421 (((x) & BIT_MASK_TXDMA_VIQ_MAP) << BIT_SHIFT_TXDMA_VIQ_MAP) 3422 #define BIT_GET_TXDMA_VIQ_MAP(x) \ 3423 (((x) >> BIT_SHIFT_TXDMA_VIQ_MAP) & BIT_MASK_TXDMA_VIQ_MAP) 3424 3425 #define BIT_SHIFT_TXDMA_VOQ_MAP 4 3426 #define BIT_MASK_TXDMA_VOQ_MAP 0x3 3427 #define BIT_TXDMA_VOQ_MAP(x) \ 3428 (((x) & BIT_MASK_TXDMA_VOQ_MAP) << BIT_SHIFT_TXDMA_VOQ_MAP) 3429 #define BIT_GET_TXDMA_VOQ_MAP(x) \ 3430 (((x) >> BIT_SHIFT_TXDMA_VOQ_MAP) & BIT_MASK_TXDMA_VOQ_MAP) 3431 3432 #define BIT_RXDMA_AGG_EN BIT(2) 3433 #define BIT_RXSHFT_EN BIT(1) 3434 #define BIT_RXDMA_ARBBW_EN BIT(0) 3435 3436 /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ 3437 3438 #define BIT_SHIFT_RXFFOVFL_RSV_V2 8 3439 #define BIT_MASK_RXFFOVFL_RSV_V2 0xf 3440 #define BIT_RXFFOVFL_RSV_V2(x) \ 3441 (((x) & BIT_MASK_RXFFOVFL_RSV_V2) << BIT_SHIFT_RXFFOVFL_RSV_V2) 3442 #define BIT_GET_RXFFOVFL_RSV_V2(x) \ 3443 (((x) >> BIT_SHIFT_RXFFOVFL_RSV_V2) & BIT_MASK_RXFFOVFL_RSV_V2) 3444 3445 /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ 3446 3447 #define BIT_SHIFT_TXPKTBUF_PGBNDY 0 3448 #define BIT_MASK_TXPKTBUF_PGBNDY 0xff 3449 #define BIT_TXPKTBUF_PGBNDY(x) \ 3450 (((x) & BIT_MASK_TXPKTBUF_PGBNDY) << BIT_SHIFT_TXPKTBUF_PGBNDY) 3451 #define BIT_GET_TXPKTBUF_PGBNDY(x) \ 3452 (((x) >> BIT_SHIFT_TXPKTBUF_PGBNDY) & BIT_MASK_TXPKTBUF_PGBNDY) 3453 3454 /* 2 REG_TRXFF_BNDY (Offset 0x0114) */ 3455 3456 #define BIT_SHIFT_RXFF0_BNDY_V2 0 3457 #define BIT_MASK_RXFF0_BNDY_V2 0x3ffff 3458 #define BIT_RXFF0_BNDY_V2(x) \ 3459 (((x) & BIT_MASK_RXFF0_BNDY_V2) << BIT_SHIFT_RXFF0_BNDY_V2) 3460 #define BIT_GET_RXFF0_BNDY_V2(x) \ 3461 (((x) >> BIT_SHIFT_RXFF0_BNDY_V2) & BIT_MASK_RXFF0_BNDY_V2) 3462 3463 #define BIT_SHIFT_RXFF0_RDPTR_V2 0 3464 #define BIT_MASK_RXFF0_RDPTR_V2 0x3ffff 3465 #define BIT_RXFF0_RDPTR_V2(x) \ 3466 (((x) & BIT_MASK_RXFF0_RDPTR_V2) << BIT_SHIFT_RXFF0_RDPTR_V2) 3467 #define BIT_GET_RXFF0_RDPTR_V2(x) \ 3468 (((x) >> BIT_SHIFT_RXFF0_RDPTR_V2) & BIT_MASK_RXFF0_RDPTR_V2) 3469 3470 #define BIT_SHIFT_RXFF0_WTPTR_V2 0 3471 #define BIT_MASK_RXFF0_WTPTR_V2 0x3ffff 3472 #define BIT_RXFF0_WTPTR_V2(x) \ 3473 (((x) & BIT_MASK_RXFF0_WTPTR_V2) << BIT_SHIFT_RXFF0_WTPTR_V2) 3474 #define BIT_GET_RXFF0_WTPTR_V2(x) \ 3475 (((x) >> BIT_SHIFT_RXFF0_WTPTR_V2) & BIT_MASK_RXFF0_WTPTR_V2) 3476 3477 /* 2 REG_PTA_I2C_MBOX (Offset 0x0118) */ 3478 3479 #define BIT_SHIFT_I2C_M_STATUS 8 3480 #define BIT_MASK_I2C_M_STATUS 0xf 3481 #define BIT_I2C_M_STATUS(x) \ 3482 (((x) & BIT_MASK_I2C_M_STATUS) << BIT_SHIFT_I2C_M_STATUS) 3483 #define BIT_GET_I2C_M_STATUS(x) \ 3484 (((x) >> BIT_SHIFT_I2C_M_STATUS) & BIT_MASK_I2C_M_STATUS) 3485 3486 /* 2 REG_FE1IMR (Offset 0x0120) */ 3487 3488 #define BIT_FS_RXDMA2_DONE_INT_EN BIT(28) 3489 #define BIT_FS_RXDONE3_INT_EN BIT(27) 3490 #define BIT_FS_RXDONE2_INT_EN BIT(26) 3491 #define BIT_FS_RX_BCN_P4_INT_EN BIT(25) 3492 #define BIT_FS_RX_BCN_P3_INT_EN BIT(24) 3493 #define BIT_FS_RX_BCN_P2_INT_EN BIT(23) 3494 #define BIT_FS_RX_BCN_P1_INT_EN BIT(22) 3495 #define BIT_FS_RX_BCN_P0_INT_EN BIT(21) 3496 #define BIT_FS_RX_UMD0_INT_EN BIT(20) 3497 #define BIT_FS_RX_UMD1_INT_EN BIT(19) 3498 #define BIT_FS_RX_BMD0_INT_EN BIT(18) 3499 #define BIT_FS_RX_BMD1_INT_EN BIT(17) 3500 #define BIT_FS_RXDONE_INT_EN BIT(16) 3501 #define BIT_FS_WWLAN_INT_EN BIT(15) 3502 #define BIT_FS_SOUND_DONE_INT_EN BIT(14) 3503 #define BIT_FS_LP_STBY_INT_EN BIT(13) 3504 #define BIT_FS_TRL_MTR_INT_EN BIT(12) 3505 #define BIT_FS_BF1_PRETO_INT_EN BIT(11) 3506 #define BIT_FS_BF0_PRETO_INT_EN BIT(10) 3507 #define BIT_FS_PTCL_RELEASE_MACID_INT_EN BIT(9) 3508 3509 /* 2 REG_FE1IMR (Offset 0x0120) */ 3510 3511 #define BIT_FS_LTE_COEX_EN BIT(6) 3512 3513 /* 2 REG_FE1IMR (Offset 0x0120) */ 3514 3515 #define BIT_FS_WLACTOFF_INT_EN BIT(5) 3516 #define BIT_FS_WLACTON_INT_EN BIT(4) 3517 #define BIT_FS_BTCMD_INT_EN BIT(3) 3518 3519 /* 2 REG_FE1IMR (Offset 0x0120) */ 3520 3521 #define BIT_FS_REG_MAILBOX_TO_I2C_INT_EN BIT(2) 3522 3523 /* 2 REG_FE1IMR (Offset 0x0120) */ 3524 3525 #define BIT_FS_TRPC_TO_INT_EN_V1 BIT(1) 3526 3527 /* 2 REG_FE1IMR (Offset 0x0120) */ 3528 3529 #define BIT_FS_RPC_O_T_INT_EN_V1 BIT(0) 3530 3531 /* 2 REG_FE1ISR (Offset 0x0124) */ 3532 3533 #define BIT_FS_RXDMA2_DONE_INT BIT(28) 3534 #define BIT_FS_RXDONE3_INT BIT(27) 3535 #define BIT_FS_RXDONE2_INT BIT(26) 3536 #define BIT_FS_RX_BCN_P4_INT BIT(25) 3537 #define BIT_FS_RX_BCN_P3_INT BIT(24) 3538 #define BIT_FS_RX_BCN_P2_INT BIT(23) 3539 #define BIT_FS_RX_BCN_P1_INT BIT(22) 3540 #define BIT_FS_RX_BCN_P0_INT BIT(21) 3541 #define BIT_FS_RX_UMD0_INT BIT(20) 3542 #define BIT_FS_RX_UMD1_INT BIT(19) 3543 #define BIT_FS_RX_BMD0_INT BIT(18) 3544 #define BIT_FS_RX_BMD1_INT BIT(17) 3545 #define BIT_FS_RXDONE_INT BIT(16) 3546 #define BIT_FS_WWLAN_INT BIT(15) 3547 #define BIT_FS_SOUND_DONE_INT BIT(14) 3548 #define BIT_FS_LP_STBY_INT BIT(13) 3549 #define BIT_FS_TRL_MTR_INT BIT(12) 3550 #define BIT_FS_BF1_PRETO_INT BIT(11) 3551 #define BIT_FS_BF0_PRETO_INT BIT(10) 3552 #define BIT_FS_PTCL_RELEASE_MACID_INT BIT(9) 3553 3554 /* 2 REG_FE1ISR (Offset 0x0124) */ 3555 3556 #define BIT_FS_LTE_COEX_INT BIT(6) 3557 3558 /* 2 REG_FE1ISR (Offset 0x0124) */ 3559 3560 #define BIT_FS_WLACTOFF_INT BIT(5) 3561 #define BIT_FS_WLACTON_INT BIT(4) 3562 #define BIT_FS_BCN_RX_INT_INT BIT(3) 3563 3564 /* 2 REG_FE1ISR (Offset 0x0124) */ 3565 3566 #define BIT_FS_MAILBOX_TO_I2C_INT BIT(2) 3567 3568 /* 2 REG_FE1ISR (Offset 0x0124) */ 3569 3570 #define BIT_FS_TRPC_TO_INT BIT(1) 3571 3572 /* 2 REG_FE1ISR (Offset 0x0124) */ 3573 3574 #define BIT_FS_RPC_O_T_INT BIT(0) 3575 3576 /* 2 REG_CPWM (Offset 0x012C) */ 3577 3578 #define BIT_CPWM_TOGGLING BIT(31) 3579 3580 #define BIT_SHIFT_CPWM_MOD 24 3581 #define BIT_MASK_CPWM_MOD 0x7f 3582 #define BIT_CPWM_MOD(x) (((x) & BIT_MASK_CPWM_MOD) << BIT_SHIFT_CPWM_MOD) 3583 #define BIT_GET_CPWM_MOD(x) (((x) >> BIT_SHIFT_CPWM_MOD) & BIT_MASK_CPWM_MOD) 3584 3585 /* 2 REG_FWIMR (Offset 0x0130) */ 3586 3587 #define BIT_FS_TXBCNOK_MB7_INT_EN BIT(31) 3588 3589 /* 2 REG_FWIMR (Offset 0x0130) */ 3590 3591 #define BIT_FS_TXBCNOK_MB6_INT_EN BIT(30) 3592 3593 /* 2 REG_FWIMR (Offset 0x0130) */ 3594 3595 #define BIT_FS_TXBCNOK_MB5_INT_EN BIT(29) 3596 3597 /* 2 REG_FWIMR (Offset 0x0130) */ 3598 3599 #define BIT_FS_TXBCNOK_MB4_INT_EN BIT(28) 3600 3601 /* 2 REG_FWIMR (Offset 0x0130) */ 3602 3603 #define BIT_FS_TXBCNOK_MB3_INT_EN BIT(27) 3604 3605 /* 2 REG_FWIMR (Offset 0x0130) */ 3606 3607 #define BIT_FS_TXBCNOK_MB2_INT_EN BIT(26) 3608 3609 /* 2 REG_FWIMR (Offset 0x0130) */ 3610 3611 #define BIT_FS_TXBCNOK_MB1_INT_EN BIT(25) 3612 3613 /* 2 REG_FWIMR (Offset 0x0130) */ 3614 3615 #define BIT_FS_TXBCNOK_MB0_INT_EN BIT(24) 3616 3617 /* 2 REG_FWIMR (Offset 0x0130) */ 3618 3619 #define BIT_FS_TXBCNERR_MB7_INT_EN BIT(23) 3620 3621 /* 2 REG_FWIMR (Offset 0x0130) */ 3622 3623 #define BIT_FS_TXBCNERR_MB6_INT_EN BIT(22) 3624 3625 /* 2 REG_FWIMR (Offset 0x0130) */ 3626 3627 #define BIT_FS_TXBCNERR_MB5_INT_EN BIT(21) 3628 3629 /* 2 REG_FWIMR (Offset 0x0130) */ 3630 3631 #define BIT_FS_TXBCNERR_MB4_INT_EN BIT(20) 3632 3633 /* 2 REG_FWIMR (Offset 0x0130) */ 3634 3635 #define BIT_FS_TXBCNERR_MB3_INT_EN BIT(19) 3636 3637 /* 2 REG_FWIMR (Offset 0x0130) */ 3638 3639 #define BIT_FS_TXBCNERR_MB2_INT_EN BIT(18) 3640 3641 /* 2 REG_FWIMR (Offset 0x0130) */ 3642 3643 #define BIT_FS_TXBCNERR_MB1_INT_EN BIT(17) 3644 3645 /* 2 REG_FWIMR (Offset 0x0130) */ 3646 3647 #define BIT_FS_TXBCNERR_MB0_INT_EN BIT(16) 3648 3649 /* 2 REG_FWIMR (Offset 0x0130) */ 3650 3651 #define BIT_CPU_MGQ_TXDONE_INT_EN BIT(15) 3652 3653 /* 2 REG_FWIMR (Offset 0x0130) */ 3654 3655 #define BIT_SIFS_OVERSPEC_INT_EN BIT(14) 3656 3657 /* 2 REG_FWIMR (Offset 0x0130) */ 3658 3659 #define BIT_FS_MGNTQ_RPTR_RELEASE_INT_EN BIT(13) 3660 3661 /* 2 REG_FWIMR (Offset 0x0130) */ 3662 3663 #define BIT_FS_MGNTQFF_TO_INT_EN BIT(12) 3664 3665 /* 2 REG_FWIMR (Offset 0x0130) */ 3666 3667 #define BIT_FS_DDMA1_LP_INT_EN BIT(11) 3668 3669 /* 2 REG_FWIMR (Offset 0x0130) */ 3670 3671 #define BIT_FS_DDMA1_HP_INT_EN BIT(10) 3672 3673 /* 2 REG_FWIMR (Offset 0x0130) */ 3674 3675 #define BIT_FS_DDMA0_LP_INT_EN BIT(9) 3676 3677 /* 2 REG_FWIMR (Offset 0x0130) */ 3678 3679 #define BIT_FS_DDMA0_HP_INT_EN BIT(8) 3680 3681 /* 2 REG_FWIMR (Offset 0x0130) */ 3682 3683 #define BIT_FS_TRXRPT_INT_EN BIT(7) 3684 3685 /* 2 REG_FWIMR (Offset 0x0130) */ 3686 3687 #define BIT_FS_C2H_W_READY_INT_EN BIT(6) 3688 3689 /* 2 REG_FWIMR (Offset 0x0130) */ 3690 3691 #define BIT_FS_HRCV_INT_EN BIT(5) 3692 3693 /* 2 REG_FWIMR (Offset 0x0130) */ 3694 3695 #define BIT_FS_H2CCMD_INT_EN BIT(4) 3696 3697 /* 2 REG_FWIMR (Offset 0x0130) */ 3698 3699 #define BIT_FS_TXPKTIN_INT_EN BIT(3) 3700 3701 /* 2 REG_FWIMR (Offset 0x0130) */ 3702 3703 #define BIT_FS_ERRORHDL_INT_EN BIT(2) 3704 3705 /* 2 REG_FWIMR (Offset 0x0130) */ 3706 3707 #define BIT_FS_TXCCX_INT_EN BIT(1) 3708 3709 /* 2 REG_FWIMR (Offset 0x0130) */ 3710 3711 #define BIT_FS_TXCLOSE_INT_EN BIT(0) 3712 3713 /* 2 REG_FWISR (Offset 0x0134) */ 3714 3715 #define BIT_FS_TXBCNOK_MB7_INT BIT(31) 3716 3717 /* 2 REG_FWISR (Offset 0x0134) */ 3718 3719 #define BIT_FS_TXBCNOK_MB6_INT BIT(30) 3720 3721 /* 2 REG_FWISR (Offset 0x0134) */ 3722 3723 #define BIT_FS_TXBCNOK_MB5_INT BIT(29) 3724 3725 /* 2 REG_FWISR (Offset 0x0134) */ 3726 3727 #define BIT_FS_TXBCNOK_MB4_INT BIT(28) 3728 3729 /* 2 REG_FWISR (Offset 0x0134) */ 3730 3731 #define BIT_FS_TXBCNOK_MB3_INT BIT(27) 3732 3733 /* 2 REG_FWISR (Offset 0x0134) */ 3734 3735 #define BIT_FS_TXBCNOK_MB2_INT BIT(26) 3736 3737 /* 2 REG_FWISR (Offset 0x0134) */ 3738 3739 #define BIT_FS_TXBCNOK_MB1_INT BIT(25) 3740 3741 /* 2 REG_FWISR (Offset 0x0134) */ 3742 3743 #define BIT_FS_TXBCNOK_MB0_INT BIT(24) 3744 3745 /* 2 REG_FWISR (Offset 0x0134) */ 3746 3747 #define BIT_FS_TXBCNERR_MB7_INT BIT(23) 3748 3749 /* 2 REG_FWISR (Offset 0x0134) */ 3750 3751 #define BIT_FS_TXBCNERR_MB6_INT BIT(22) 3752 3753 /* 2 REG_FWISR (Offset 0x0134) */ 3754 3755 #define BIT_FS_TXBCNERR_MB5_INT BIT(21) 3756 3757 /* 2 REG_FWISR (Offset 0x0134) */ 3758 3759 #define BIT_FS_TXBCNERR_MB4_INT BIT(20) 3760 3761 /* 2 REG_FWISR (Offset 0x0134) */ 3762 3763 #define BIT_FS_TXBCNERR_MB3_INT BIT(19) 3764 3765 /* 2 REG_FWISR (Offset 0x0134) */ 3766 3767 #define BIT_FS_TXBCNERR_MB2_INT BIT(18) 3768 3769 /* 2 REG_FWISR (Offset 0x0134) */ 3770 3771 #define BIT_FS_TXBCNERR_MB1_INT BIT(17) 3772 3773 /* 2 REG_FWISR (Offset 0x0134) */ 3774 3775 #define BIT_FS_TXBCNERR_MB0_INT BIT(16) 3776 3777 /* 2 REG_FWISR (Offset 0x0134) */ 3778 3779 #define BIT_CPU_MGQ_TXDONE_INT BIT(15) 3780 3781 /* 2 REG_FWISR (Offset 0x0134) */ 3782 3783 #define BIT_SIFS_OVERSPEC_INT BIT(14) 3784 3785 /* 2 REG_FWISR (Offset 0x0134) */ 3786 3787 #define BIT_FS_MGNTQ_RPTR_RELEASE_INT BIT(13) 3788 3789 /* 2 REG_FWISR (Offset 0x0134) */ 3790 3791 #define BIT_FS_MGNTQFF_TO_INT BIT(12) 3792 3793 /* 2 REG_FWISR (Offset 0x0134) */ 3794 3795 #define BIT_FS_DDMA1_LP_INT BIT(11) 3796 3797 /* 2 REG_FWISR (Offset 0x0134) */ 3798 3799 #define BIT_FS_DDMA1_HP_INT BIT(10) 3800 3801 /* 2 REG_FWISR (Offset 0x0134) */ 3802 3803 #define BIT_FS_DDMA0_LP_INT BIT(9) 3804 3805 /* 2 REG_FWISR (Offset 0x0134) */ 3806 3807 #define BIT_FS_DDMA0_HP_INT BIT(8) 3808 3809 /* 2 REG_FWISR (Offset 0x0134) */ 3810 3811 #define BIT_FS_TRXRPT_INT BIT(7) 3812 3813 /* 2 REG_FWISR (Offset 0x0134) */ 3814 3815 #define BIT_FS_C2H_W_READY_INT BIT(6) 3816 3817 /* 2 REG_FWISR (Offset 0x0134) */ 3818 3819 #define BIT_FS_HRCV_INT BIT(5) 3820 3821 /* 2 REG_FWISR (Offset 0x0134) */ 3822 3823 #define BIT_FS_H2CCMD_INT BIT(4) 3824 3825 /* 2 REG_FWISR (Offset 0x0134) */ 3826 3827 #define BIT_FS_TXPKTIN_INT BIT(3) 3828 3829 /* 2 REG_FWISR (Offset 0x0134) */ 3830 3831 #define BIT_FS_ERRORHDL_INT BIT(2) 3832 3833 /* 2 REG_FWISR (Offset 0x0134) */ 3834 3835 #define BIT_FS_TXCCX_INT BIT(1) 3836 3837 /* 2 REG_FWISR (Offset 0x0134) */ 3838 3839 #define BIT_FS_TXCLOSE_INT BIT(0) 3840 3841 /* 2 REG_FTIMR (Offset 0x0138) */ 3842 3843 #define BIT_PS_TIMER_C_EARLY_INT_EN BIT(23) 3844 3845 /* 2 REG_FTIMR (Offset 0x0138) */ 3846 3847 #define BIT_PS_TIMER_B_EARLY_INT_EN BIT(22) 3848 3849 /* 2 REG_FTIMR (Offset 0x0138) */ 3850 3851 #define BIT_PS_TIMER_A_EARLY_INT_EN BIT(21) 3852 3853 /* 2 REG_FTIMR (Offset 0x0138) */ 3854 3855 #define BIT_CPUMGQ_TX_TIMER_EARLY_INT_EN BIT(20) 3856 3857 /* 2 REG_FTIMR (Offset 0x0138) */ 3858 3859 #define BIT_PS_TIMER_C_INT_EN BIT(19) 3860 3861 /* 2 REG_FTIMR (Offset 0x0138) */ 3862 3863 #define BIT_PS_TIMER_B_INT_EN BIT(18) 3864 3865 /* 2 REG_FTIMR (Offset 0x0138) */ 3866 3867 #define BIT_PS_TIMER_A_INT_EN BIT(17) 3868 3869 /* 2 REG_FTIMR (Offset 0x0138) */ 3870 3871 #define BIT_CPUMGQ_TX_TIMER_INT_EN BIT(16) 3872 3873 /* 2 REG_FTIMR (Offset 0x0138) */ 3874 3875 #define BIT_FS_PS_TIMEOUT2_EN BIT(15) 3876 3877 /* 2 REG_FTIMR (Offset 0x0138) */ 3878 3879 #define BIT_FS_PS_TIMEOUT1_EN BIT(14) 3880 3881 /* 2 REG_FTIMR (Offset 0x0138) */ 3882 3883 #define BIT_FS_PS_TIMEOUT0_EN BIT(13) 3884 3885 /* 2 REG_FTIMR (Offset 0x0138) */ 3886 3887 #define BIT_FS_GTINT8_EN BIT(8) 3888 3889 /* 2 REG_FTIMR (Offset 0x0138) */ 3890 3891 #define BIT_FS_GTINT7_EN BIT(7) 3892 3893 /* 2 REG_FTIMR (Offset 0x0138) */ 3894 3895 #define BIT_FS_GTINT6_EN BIT(6) 3896 3897 /* 2 REG_FTIMR (Offset 0x0138) */ 3898 3899 #define BIT_FS_GTINT5_EN BIT(5) 3900 3901 /* 2 REG_FTIMR (Offset 0x0138) */ 3902 3903 #define BIT_FS_GTINT4_EN BIT(4) 3904 3905 /* 2 REG_FTIMR (Offset 0x0138) */ 3906 3907 #define BIT_FS_GTINT3_EN BIT(3) 3908 3909 /* 2 REG_FTIMR (Offset 0x0138) */ 3910 3911 #define BIT_FS_GTINT2_EN BIT(2) 3912 3913 /* 2 REG_FTIMR (Offset 0x0138) */ 3914 3915 #define BIT_FS_GTINT1_EN BIT(1) 3916 3917 /* 2 REG_FTIMR (Offset 0x0138) */ 3918 3919 #define BIT_FS_GTINT0_EN BIT(0) 3920 3921 /* 2 REG_FTISR (Offset 0x013C) */ 3922 3923 #define BIT_PS_TIMER_C_EARLY__INT BIT(23) 3924 3925 /* 2 REG_FTISR (Offset 0x013C) */ 3926 3927 #define BIT_PS_TIMER_B_EARLY__INT BIT(22) 3928 3929 /* 2 REG_FTISR (Offset 0x013C) */ 3930 3931 #define BIT_PS_TIMER_A_EARLY__INT BIT(21) 3932 3933 /* 2 REG_FTISR (Offset 0x013C) */ 3934 3935 #define BIT_CPUMGQ_TX_TIMER_EARLY_INT BIT(20) 3936 3937 /* 2 REG_FTISR (Offset 0x013C) */ 3938 3939 #define BIT_PS_TIMER_C_INT BIT(19) 3940 3941 /* 2 REG_FTISR (Offset 0x013C) */ 3942 3943 #define BIT_PS_TIMER_B_INT BIT(18) 3944 3945 /* 2 REG_FTISR (Offset 0x013C) */ 3946 3947 #define BIT_PS_TIMER_A_INT BIT(17) 3948 3949 /* 2 REG_FTISR (Offset 0x013C) */ 3950 3951 #define BIT_CPUMGQ_TX_TIMER_INT BIT(16) 3952 3953 /* 2 REG_FTISR (Offset 0x013C) */ 3954 3955 #define BIT_FS_PS_TIMEOUT2_INT BIT(15) 3956 3957 /* 2 REG_FTISR (Offset 0x013C) */ 3958 3959 #define BIT_FS_PS_TIMEOUT1_INT BIT(14) 3960 3961 /* 2 REG_FTISR (Offset 0x013C) */ 3962 3963 #define BIT_FS_PS_TIMEOUT0_INT BIT(13) 3964 3965 /* 2 REG_FTISR (Offset 0x013C) */ 3966 3967 #define BIT_FS_GTINT8_INT BIT(8) 3968 3969 /* 2 REG_FTISR (Offset 0x013C) */ 3970 3971 #define BIT_FS_GTINT7_INT BIT(7) 3972 3973 /* 2 REG_FTISR (Offset 0x013C) */ 3974 3975 #define BIT_FS_GTINT6_INT BIT(6) 3976 3977 /* 2 REG_FTISR (Offset 0x013C) */ 3978 3979 #define BIT_FS_GTINT5_INT BIT(5) 3980 3981 /* 2 REG_FTISR (Offset 0x013C) */ 3982 3983 #define BIT_FS_GTINT4_INT BIT(4) 3984 3985 /* 2 REG_FTISR (Offset 0x013C) */ 3986 3987 #define BIT_FS_GTINT3_INT BIT(3) 3988 3989 /* 2 REG_FTISR (Offset 0x013C) */ 3990 3991 #define BIT_FS_GTINT2_INT BIT(2) 3992 3993 /* 2 REG_FTISR (Offset 0x013C) */ 3994 3995 #define BIT_FS_GTINT1_INT BIT(1) 3996 3997 /* 2 REG_FTISR (Offset 0x013C) */ 3998 3999 #define BIT_FS_GTINT0_INT BIT(0) 4000 4001 /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4002 4003 #define BIT_SHIFT_PKTBUF_WRITE_EN 24 4004 #define BIT_MASK_PKTBUF_WRITE_EN 0xff 4005 #define BIT_PKTBUF_WRITE_EN(x) \ 4006 (((x) & BIT_MASK_PKTBUF_WRITE_EN) << BIT_SHIFT_PKTBUF_WRITE_EN) 4007 #define BIT_GET_PKTBUF_WRITE_EN(x) \ 4008 (((x) >> BIT_SHIFT_PKTBUF_WRITE_EN) & BIT_MASK_PKTBUF_WRITE_EN) 4009 4010 /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4011 4012 #define BIT_TXRPTBUF_DBG BIT(23) 4013 4014 /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4015 4016 #define BIT_TXPKTBUF_DBG_V2 BIT(20) 4017 4018 /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4019 4020 #define BIT_RXPKTBUF_DBG BIT(16) 4021 4022 /* 2 REG_PKTBUF_DBG_CTRL (Offset 0x0140) */ 4023 4024 #define BIT_SHIFT_PKTBUF_DBG_ADDR 0 4025 #define BIT_MASK_PKTBUF_DBG_ADDR 0x1fff 4026 #define BIT_PKTBUF_DBG_ADDR(x) \ 4027 (((x) & BIT_MASK_PKTBUF_DBG_ADDR) << BIT_SHIFT_PKTBUF_DBG_ADDR) 4028 #define BIT_GET_PKTBUF_DBG_ADDR(x) \ 4029 (((x) >> BIT_SHIFT_PKTBUF_DBG_ADDR) & BIT_MASK_PKTBUF_DBG_ADDR) 4030 4031 /* 2 REG_PKTBUF_DBG_DATA_L (Offset 0x0144) */ 4032 4033 #define BIT_SHIFT_PKTBUF_DBG_DATA_L 0 4034 #define BIT_MASK_PKTBUF_DBG_DATA_L 0xffffffffL 4035 #define BIT_PKTBUF_DBG_DATA_L(x) \ 4036 (((x) & BIT_MASK_PKTBUF_DBG_DATA_L) << BIT_SHIFT_PKTBUF_DBG_DATA_L) 4037 #define BIT_GET_PKTBUF_DBG_DATA_L(x) \ 4038 (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_L) & BIT_MASK_PKTBUF_DBG_DATA_L) 4039 4040 /* 2 REG_PKTBUF_DBG_DATA_H (Offset 0x0148) */ 4041 4042 #define BIT_SHIFT_PKTBUF_DBG_DATA_H 0 4043 #define BIT_MASK_PKTBUF_DBG_DATA_H 0xffffffffL 4044 #define BIT_PKTBUF_DBG_DATA_H(x) \ 4045 (((x) & BIT_MASK_PKTBUF_DBG_DATA_H) << BIT_SHIFT_PKTBUF_DBG_DATA_H) 4046 #define BIT_GET_PKTBUF_DBG_DATA_H(x) \ 4047 (((x) >> BIT_SHIFT_PKTBUF_DBG_DATA_H) & BIT_MASK_PKTBUF_DBG_DATA_H) 4048 4049 /* 2 REG_CPWM2 (Offset 0x014C) */ 4050 4051 #define BIT_SHIFT_L0S_TO_RCVY_NUM 16 4052 #define BIT_MASK_L0S_TO_RCVY_NUM 0xff 4053 #define BIT_L0S_TO_RCVY_NUM(x) \ 4054 (((x) & BIT_MASK_L0S_TO_RCVY_NUM) << BIT_SHIFT_L0S_TO_RCVY_NUM) 4055 #define BIT_GET_L0S_TO_RCVY_NUM(x) \ 4056 (((x) >> BIT_SHIFT_L0S_TO_RCVY_NUM) & BIT_MASK_L0S_TO_RCVY_NUM) 4057 4058 #define BIT_CPWM2_TOGGLING BIT(15) 4059 4060 #define BIT_SHIFT_CPWM2_MOD 0 4061 #define BIT_MASK_CPWM2_MOD 0x7fff 4062 #define BIT_CPWM2_MOD(x) (((x) & BIT_MASK_CPWM2_MOD) << BIT_SHIFT_CPWM2_MOD) 4063 #define BIT_GET_CPWM2_MOD(x) (((x) >> BIT_SHIFT_CPWM2_MOD) & BIT_MASK_CPWM2_MOD) 4064 4065 /* 2 REG_TC0_CTRL (Offset 0x0150) */ 4066 4067 #define BIT_TC0INT_EN BIT(26) 4068 #define BIT_TC0MODE BIT(25) 4069 #define BIT_TC0EN BIT(24) 4070 4071 #define BIT_SHIFT_TC0DATA 0 4072 #define BIT_MASK_TC0DATA 0xffffff 4073 #define BIT_TC0DATA(x) (((x) & BIT_MASK_TC0DATA) << BIT_SHIFT_TC0DATA) 4074 #define BIT_GET_TC0DATA(x) (((x) >> BIT_SHIFT_TC0DATA) & BIT_MASK_TC0DATA) 4075 4076 /* 2 REG_TC1_CTRL (Offset 0x0154) */ 4077 4078 #define BIT_TC1INT_EN BIT(26) 4079 #define BIT_TC1MODE BIT(25) 4080 #define BIT_TC1EN BIT(24) 4081 4082 #define BIT_SHIFT_TC1DATA 0 4083 #define BIT_MASK_TC1DATA 0xffffff 4084 #define BIT_TC1DATA(x) (((x) & BIT_MASK_TC1DATA) << BIT_SHIFT_TC1DATA) 4085 #define BIT_GET_TC1DATA(x) (((x) >> BIT_SHIFT_TC1DATA) & BIT_MASK_TC1DATA) 4086 4087 /* 2 REG_TC2_CTRL (Offset 0x0158) */ 4088 4089 #define BIT_TC2INT_EN BIT(26) 4090 #define BIT_TC2MODE BIT(25) 4091 #define BIT_TC2EN BIT(24) 4092 4093 #define BIT_SHIFT_TC2DATA 0 4094 #define BIT_MASK_TC2DATA 0xffffff 4095 #define BIT_TC2DATA(x) (((x) & BIT_MASK_TC2DATA) << BIT_SHIFT_TC2DATA) 4096 #define BIT_GET_TC2DATA(x) (((x) >> BIT_SHIFT_TC2DATA) & BIT_MASK_TC2DATA) 4097 4098 /* 2 REG_TC3_CTRL (Offset 0x015C) */ 4099 4100 #define BIT_TC3INT_EN BIT(26) 4101 #define BIT_TC3MODE BIT(25) 4102 #define BIT_TC3EN BIT(24) 4103 4104 #define BIT_SHIFT_TC3DATA 0 4105 #define BIT_MASK_TC3DATA 0xffffff 4106 #define BIT_TC3DATA(x) (((x) & BIT_MASK_TC3DATA) << BIT_SHIFT_TC3DATA) 4107 #define BIT_GET_TC3DATA(x) (((x) >> BIT_SHIFT_TC3DATA) & BIT_MASK_TC3DATA) 4108 4109 /* 2 REG_TC4_CTRL (Offset 0x0160) */ 4110 4111 #define BIT_TC4INT_EN BIT(26) 4112 #define BIT_TC4MODE BIT(25) 4113 #define BIT_TC4EN BIT(24) 4114 4115 #define BIT_SHIFT_TC4DATA 0 4116 #define BIT_MASK_TC4DATA 0xffffff 4117 #define BIT_TC4DATA(x) (((x) & BIT_MASK_TC4DATA) << BIT_SHIFT_TC4DATA) 4118 #define BIT_GET_TC4DATA(x) (((x) >> BIT_SHIFT_TC4DATA) & BIT_MASK_TC4DATA) 4119 4120 /* 2 REG_TCUNIT_BASE (Offset 0x0164) */ 4121 4122 #define BIT_SHIFT_TCUNIT_BASE 0 4123 #define BIT_MASK_TCUNIT_BASE 0x3fff 4124 #define BIT_TCUNIT_BASE(x) \ 4125 (((x) & BIT_MASK_TCUNIT_BASE) << BIT_SHIFT_TCUNIT_BASE) 4126 #define BIT_GET_TCUNIT_BASE(x) \ 4127 (((x) >> BIT_SHIFT_TCUNIT_BASE) & BIT_MASK_TCUNIT_BASE) 4128 4129 /* 2 REG_TC5_CTRL (Offset 0x0168) */ 4130 4131 #define BIT_TC5INT_EN BIT(26) 4132 4133 /* 2 REG_TC5_CTRL (Offset 0x0168) */ 4134 4135 #define BIT_TC5MODE BIT(25) 4136 #define BIT_TC5EN BIT(24) 4137 4138 #define BIT_SHIFT_TC5DATA 0 4139 #define BIT_MASK_TC5DATA 0xffffff 4140 #define BIT_TC5DATA(x) (((x) & BIT_MASK_TC5DATA) << BIT_SHIFT_TC5DATA) 4141 #define BIT_GET_TC5DATA(x) (((x) >> BIT_SHIFT_TC5DATA) & BIT_MASK_TC5DATA) 4142 4143 /* 2 REG_TC6_CTRL (Offset 0x016C) */ 4144 4145 #define BIT_TC6INT_EN BIT(26) 4146 4147 /* 2 REG_TC6_CTRL (Offset 0x016C) */ 4148 4149 #define BIT_TC6MODE BIT(25) 4150 #define BIT_TC6EN BIT(24) 4151 4152 #define BIT_SHIFT_TC6DATA 0 4153 #define BIT_MASK_TC6DATA 0xffffff 4154 #define BIT_TC6DATA(x) (((x) & BIT_MASK_TC6DATA) << BIT_SHIFT_TC6DATA) 4155 #define BIT_GET_TC6DATA(x) (((x) >> BIT_SHIFT_TC6DATA) & BIT_MASK_TC6DATA) 4156 4157 /* 2 REG_MBIST_FAIL (Offset 0x0170) */ 4158 4159 #define BIT_SHIFT_8051_MBIST_FAIL 26 4160 #define BIT_MASK_8051_MBIST_FAIL 0x7 4161 #define BIT_8051_MBIST_FAIL(x) \ 4162 (((x) & BIT_MASK_8051_MBIST_FAIL) << BIT_SHIFT_8051_MBIST_FAIL) 4163 #define BIT_GET_8051_MBIST_FAIL(x) \ 4164 (((x) >> BIT_SHIFT_8051_MBIST_FAIL) & BIT_MASK_8051_MBIST_FAIL) 4165 4166 #define BIT_SHIFT_USB_MBIST_FAIL 24 4167 #define BIT_MASK_USB_MBIST_FAIL 0x3 4168 #define BIT_USB_MBIST_FAIL(x) \ 4169 (((x) & BIT_MASK_USB_MBIST_FAIL) << BIT_SHIFT_USB_MBIST_FAIL) 4170 #define BIT_GET_USB_MBIST_FAIL(x) \ 4171 (((x) >> BIT_SHIFT_USB_MBIST_FAIL) & BIT_MASK_USB_MBIST_FAIL) 4172 4173 #define BIT_SHIFT_PCIE_MBIST_FAIL 16 4174 #define BIT_MASK_PCIE_MBIST_FAIL 0x3f 4175 #define BIT_PCIE_MBIST_FAIL(x) \ 4176 (((x) & BIT_MASK_PCIE_MBIST_FAIL) << BIT_SHIFT_PCIE_MBIST_FAIL) 4177 #define BIT_GET_PCIE_MBIST_FAIL(x) \ 4178 (((x) >> BIT_SHIFT_PCIE_MBIST_FAIL) & BIT_MASK_PCIE_MBIST_FAIL) 4179 4180 /* 2 REG_MBIST_FAIL (Offset 0x0170) */ 4181 4182 #define BIT_SHIFT_MAC_MBIST_FAIL 0 4183 #define BIT_MASK_MAC_MBIST_FAIL 0xfff 4184 #define BIT_MAC_MBIST_FAIL(x) \ 4185 (((x) & BIT_MASK_MAC_MBIST_FAIL) << BIT_SHIFT_MAC_MBIST_FAIL) 4186 #define BIT_GET_MAC_MBIST_FAIL(x) \ 4187 (((x) >> BIT_SHIFT_MAC_MBIST_FAIL) & BIT_MASK_MAC_MBIST_FAIL) 4188 4189 /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ 4190 4191 #define BIT_SHIFT_8051_MBIST_START_PAUSE 26 4192 #define BIT_MASK_8051_MBIST_START_PAUSE 0x7 4193 #define BIT_8051_MBIST_START_PAUSE(x) \ 4194 (((x) & BIT_MASK_8051_MBIST_START_PAUSE) \ 4195 << BIT_SHIFT_8051_MBIST_START_PAUSE) 4196 #define BIT_GET_8051_MBIST_START_PAUSE(x) \ 4197 (((x) >> BIT_SHIFT_8051_MBIST_START_PAUSE) & \ 4198 BIT_MASK_8051_MBIST_START_PAUSE) 4199 4200 #define BIT_SHIFT_USB_MBIST_START_PAUSE 24 4201 #define BIT_MASK_USB_MBIST_START_PAUSE 0x3 4202 #define BIT_USB_MBIST_START_PAUSE(x) \ 4203 (((x) & BIT_MASK_USB_MBIST_START_PAUSE) \ 4204 << BIT_SHIFT_USB_MBIST_START_PAUSE) 4205 #define BIT_GET_USB_MBIST_START_PAUSE(x) \ 4206 (((x) >> BIT_SHIFT_USB_MBIST_START_PAUSE) & \ 4207 BIT_MASK_USB_MBIST_START_PAUSE) 4208 4209 #define BIT_SHIFT_PCIE_MBIST_START_PAUSE 16 4210 #define BIT_MASK_PCIE_MBIST_START_PAUSE 0x3f 4211 #define BIT_PCIE_MBIST_START_PAUSE(x) \ 4212 (((x) & BIT_MASK_PCIE_MBIST_START_PAUSE) \ 4213 << BIT_SHIFT_PCIE_MBIST_START_PAUSE) 4214 #define BIT_GET_PCIE_MBIST_START_PAUSE(x) \ 4215 (((x) >> BIT_SHIFT_PCIE_MBIST_START_PAUSE) & \ 4216 BIT_MASK_PCIE_MBIST_START_PAUSE) 4217 4218 /* 2 REG_MBIST_START_PAUSE (Offset 0x0174) */ 4219 4220 #define BIT_SHIFT_MAC_MBIST_START_PAUSE 0 4221 #define BIT_MASK_MAC_MBIST_START_PAUSE 0xfff 4222 #define BIT_MAC_MBIST_START_PAUSE(x) \ 4223 (((x) & BIT_MASK_MAC_MBIST_START_PAUSE) \ 4224 << BIT_SHIFT_MAC_MBIST_START_PAUSE) 4225 #define BIT_GET_MAC_MBIST_START_PAUSE(x) \ 4226 (((x) >> BIT_SHIFT_MAC_MBIST_START_PAUSE) & \ 4227 BIT_MASK_MAC_MBIST_START_PAUSE) 4228 4229 /* 2 REG_MBIST_DONE (Offset 0x0178) */ 4230 4231 #define BIT_SHIFT_8051_MBIST_DONE 26 4232 #define BIT_MASK_8051_MBIST_DONE 0x7 4233 #define BIT_8051_MBIST_DONE(x) \ 4234 (((x) & BIT_MASK_8051_MBIST_DONE) << BIT_SHIFT_8051_MBIST_DONE) 4235 #define BIT_GET_8051_MBIST_DONE(x) \ 4236 (((x) >> BIT_SHIFT_8051_MBIST_DONE) & BIT_MASK_8051_MBIST_DONE) 4237 4238 #define BIT_SHIFT_USB_MBIST_DONE 24 4239 #define BIT_MASK_USB_MBIST_DONE 0x3 4240 #define BIT_USB_MBIST_DONE(x) \ 4241 (((x) & BIT_MASK_USB_MBIST_DONE) << BIT_SHIFT_USB_MBIST_DONE) 4242 #define BIT_GET_USB_MBIST_DONE(x) \ 4243 (((x) >> BIT_SHIFT_USB_MBIST_DONE) & BIT_MASK_USB_MBIST_DONE) 4244 4245 #define BIT_SHIFT_PCIE_MBIST_DONE 16 4246 #define BIT_MASK_PCIE_MBIST_DONE 0x3f 4247 #define BIT_PCIE_MBIST_DONE(x) \ 4248 (((x) & BIT_MASK_PCIE_MBIST_DONE) << BIT_SHIFT_PCIE_MBIST_DONE) 4249 #define BIT_GET_PCIE_MBIST_DONE(x) \ 4250 (((x) >> BIT_SHIFT_PCIE_MBIST_DONE) & BIT_MASK_PCIE_MBIST_DONE) 4251 4252 /* 2 REG_MBIST_DONE (Offset 0x0178) */ 4253 4254 #define BIT_SHIFT_MAC_MBIST_DONE 0 4255 #define BIT_MASK_MAC_MBIST_DONE 0xfff 4256 #define BIT_MAC_MBIST_DONE(x) \ 4257 (((x) & BIT_MASK_MAC_MBIST_DONE) << BIT_SHIFT_MAC_MBIST_DONE) 4258 #define BIT_GET_MAC_MBIST_DONE(x) \ 4259 (((x) >> BIT_SHIFT_MAC_MBIST_DONE) & BIT_MASK_MAC_MBIST_DONE) 4260 4261 /* 2 REG_MBIST_FAIL_NRML (Offset 0x017C) */ 4262 4263 #define BIT_SHIFT_MBIST_FAIL_NRML 0 4264 #define BIT_MASK_MBIST_FAIL_NRML 0xffffffffL 4265 #define BIT_MBIST_FAIL_NRML(x) \ 4266 (((x) & BIT_MASK_MBIST_FAIL_NRML) << BIT_SHIFT_MBIST_FAIL_NRML) 4267 #define BIT_GET_MBIST_FAIL_NRML(x) \ 4268 (((x) >> BIT_SHIFT_MBIST_FAIL_NRML) & BIT_MASK_MBIST_FAIL_NRML) 4269 4270 /* 2 REG_AES_DECRPT_DATA (Offset 0x0180) */ 4271 4272 #define BIT_SHIFT_IPS_CFG_ADDR 0 4273 #define BIT_MASK_IPS_CFG_ADDR 0xff 4274 #define BIT_IPS_CFG_ADDR(x) \ 4275 (((x) & BIT_MASK_IPS_CFG_ADDR) << BIT_SHIFT_IPS_CFG_ADDR) 4276 #define BIT_GET_IPS_CFG_ADDR(x) \ 4277 (((x) >> BIT_SHIFT_IPS_CFG_ADDR) & BIT_MASK_IPS_CFG_ADDR) 4278 4279 /* 2 REG_AES_DECRPT_CFG (Offset 0x0184) */ 4280 4281 #define BIT_SHIFT_IPS_CFG_DATA 0 4282 #define BIT_MASK_IPS_CFG_DATA 0xffffffffL 4283 #define BIT_IPS_CFG_DATA(x) \ 4284 (((x) & BIT_MASK_IPS_CFG_DATA) << BIT_SHIFT_IPS_CFG_DATA) 4285 #define BIT_GET_IPS_CFG_DATA(x) \ 4286 (((x) >> BIT_SHIFT_IPS_CFG_DATA) & BIT_MASK_IPS_CFG_DATA) 4287 4288 /* 2 REG_TMETER (Offset 0x0190) */ 4289 4290 #define BIT_TEMP_VALID BIT(31) 4291 4292 #define BIT_SHIFT_TEMP_VALUE 24 4293 #define BIT_MASK_TEMP_VALUE 0x3f 4294 #define BIT_TEMP_VALUE(x) (((x) & BIT_MASK_TEMP_VALUE) << BIT_SHIFT_TEMP_VALUE) 4295 #define BIT_GET_TEMP_VALUE(x) \ 4296 (((x) >> BIT_SHIFT_TEMP_VALUE) & BIT_MASK_TEMP_VALUE) 4297 4298 #define BIT_SHIFT_REG_TMETER_TIMER 8 4299 #define BIT_MASK_REG_TMETER_TIMER 0xfff 4300 #define BIT_REG_TMETER_TIMER(x) \ 4301 (((x) & BIT_MASK_REG_TMETER_TIMER) << BIT_SHIFT_REG_TMETER_TIMER) 4302 #define BIT_GET_REG_TMETER_TIMER(x) \ 4303 (((x) >> BIT_SHIFT_REG_TMETER_TIMER) & BIT_MASK_REG_TMETER_TIMER) 4304 4305 #define BIT_SHIFT_REG_TEMP_DELTA 2 4306 #define BIT_MASK_REG_TEMP_DELTA 0x3f 4307 #define BIT_REG_TEMP_DELTA(x) \ 4308 (((x) & BIT_MASK_REG_TEMP_DELTA) << BIT_SHIFT_REG_TEMP_DELTA) 4309 #define BIT_GET_REG_TEMP_DELTA(x) \ 4310 (((x) >> BIT_SHIFT_REG_TEMP_DELTA) & BIT_MASK_REG_TEMP_DELTA) 4311 4312 #define BIT_REG_TMETER_EN BIT(0) 4313 4314 /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4315 4316 #define BIT_SHIFT_OSC_32K_CLKGEN_0 16 4317 #define BIT_MASK_OSC_32K_CLKGEN_0 0xffff 4318 #define BIT_OSC_32K_CLKGEN_0(x) \ 4319 (((x) & BIT_MASK_OSC_32K_CLKGEN_0) << BIT_SHIFT_OSC_32K_CLKGEN_0) 4320 #define BIT_GET_OSC_32K_CLKGEN_0(x) \ 4321 (((x) >> BIT_SHIFT_OSC_32K_CLKGEN_0) & BIT_MASK_OSC_32K_CLKGEN_0) 4322 4323 /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4324 4325 #define BIT_SHIFT_OSC_32K_RES_COMP 4 4326 #define BIT_MASK_OSC_32K_RES_COMP 0x3 4327 #define BIT_OSC_32K_RES_COMP(x) \ 4328 (((x) & BIT_MASK_OSC_32K_RES_COMP) << BIT_SHIFT_OSC_32K_RES_COMP) 4329 #define BIT_GET_OSC_32K_RES_COMP(x) \ 4330 (((x) >> BIT_SHIFT_OSC_32K_RES_COMP) & BIT_MASK_OSC_32K_RES_COMP) 4331 4332 #define BIT_OSC_32K_OUT_SEL BIT(3) 4333 4334 /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4335 4336 #define BIT_ISO_WL_2_OSC_32K BIT(1) 4337 4338 /* 2 REG_OSC_32K_CTRL (Offset 0x0194) */ 4339 4340 #define BIT_POW_CKGEN BIT(0) 4341 4342 /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ 4343 4344 #define BIT_CAL_32K_REG_WR BIT(31) 4345 #define BIT_CAL_32K_DBG_SEL BIT(22) 4346 4347 #define BIT_SHIFT_CAL_32K_REG_ADDR 16 4348 #define BIT_MASK_CAL_32K_REG_ADDR 0x3f 4349 #define BIT_CAL_32K_REG_ADDR(x) \ 4350 (((x) & BIT_MASK_CAL_32K_REG_ADDR) << BIT_SHIFT_CAL_32K_REG_ADDR) 4351 #define BIT_GET_CAL_32K_REG_ADDR(x) \ 4352 (((x) >> BIT_SHIFT_CAL_32K_REG_ADDR) & BIT_MASK_CAL_32K_REG_ADDR) 4353 4354 /* 2 REG_32K_CAL_REG1 (Offset 0x0198) */ 4355 4356 #define BIT_SHIFT_CAL_32K_REG_DATA 0 4357 #define BIT_MASK_CAL_32K_REG_DATA 0xffff 4358 #define BIT_CAL_32K_REG_DATA(x) \ 4359 (((x) & BIT_MASK_CAL_32K_REG_DATA) << BIT_SHIFT_CAL_32K_REG_DATA) 4360 #define BIT_GET_CAL_32K_REG_DATA(x) \ 4361 (((x) >> BIT_SHIFT_CAL_32K_REG_DATA) & BIT_MASK_CAL_32K_REG_DATA) 4362 4363 /* 2 REG_C2HEVT (Offset 0x01A0) */ 4364 4365 #define BIT_SHIFT_C2HEVT_MSG 0 4366 #define BIT_MASK_C2HEVT_MSG 0xffffffffffffffffffffffffffffffffL 4367 #define BIT_C2HEVT_MSG(x) (((x) & BIT_MASK_C2HEVT_MSG) << BIT_SHIFT_C2HEVT_MSG) 4368 #define BIT_GET_C2HEVT_MSG(x) \ 4369 (((x) >> BIT_SHIFT_C2HEVT_MSG) & BIT_MASK_C2HEVT_MSG) 4370 4371 /* 2 REG_SW_DEFINED_PAGE1 (Offset 0x01B8) */ 4372 4373 #define BIT_SHIFT_SW_DEFINED_PAGE1 0 4374 #define BIT_MASK_SW_DEFINED_PAGE1 0xffffffffffffffffL 4375 #define BIT_SW_DEFINED_PAGE1(x) \ 4376 (((x) & BIT_MASK_SW_DEFINED_PAGE1) << BIT_SHIFT_SW_DEFINED_PAGE1) 4377 #define BIT_GET_SW_DEFINED_PAGE1(x) \ 4378 (((x) >> BIT_SHIFT_SW_DEFINED_PAGE1) & BIT_MASK_SW_DEFINED_PAGE1) 4379 4380 /* 2 REG_MCUTST_I (Offset 0x01C0) */ 4381 4382 #define BIT_SHIFT_MCUDMSG_I 0 4383 #define BIT_MASK_MCUDMSG_I 0xffffffffL 4384 #define BIT_MCUDMSG_I(x) (((x) & BIT_MASK_MCUDMSG_I) << BIT_SHIFT_MCUDMSG_I) 4385 #define BIT_GET_MCUDMSG_I(x) (((x) >> BIT_SHIFT_MCUDMSG_I) & BIT_MASK_MCUDMSG_I) 4386 4387 /* 2 REG_MCUTST_II (Offset 0x01C4) */ 4388 4389 #define BIT_SHIFT_MCUDMSG_II 0 4390 #define BIT_MASK_MCUDMSG_II 0xffffffffL 4391 #define BIT_MCUDMSG_II(x) (((x) & BIT_MASK_MCUDMSG_II) << BIT_SHIFT_MCUDMSG_II) 4392 #define BIT_GET_MCUDMSG_II(x) \ 4393 (((x) >> BIT_SHIFT_MCUDMSG_II) & BIT_MASK_MCUDMSG_II) 4394 4395 /* 2 REG_FMETHR (Offset 0x01C8) */ 4396 4397 #define BIT_FMSG_INT BIT(31) 4398 4399 #define BIT_SHIFT_FW_MSG 0 4400 #define BIT_MASK_FW_MSG 0xffffffffL 4401 #define BIT_FW_MSG(x) (((x) & BIT_MASK_FW_MSG) << BIT_SHIFT_FW_MSG) 4402 #define BIT_GET_FW_MSG(x) (((x) >> BIT_SHIFT_FW_MSG) & BIT_MASK_FW_MSG) 4403 4404 /* 2 REG_HMETFR (Offset 0x01CC) */ 4405 4406 #define BIT_SHIFT_HRCV_MSG 24 4407 #define BIT_MASK_HRCV_MSG 0xff 4408 #define BIT_HRCV_MSG(x) (((x) & BIT_MASK_HRCV_MSG) << BIT_SHIFT_HRCV_MSG) 4409 #define BIT_GET_HRCV_MSG(x) (((x) >> BIT_SHIFT_HRCV_MSG) & BIT_MASK_HRCV_MSG) 4410 4411 #define BIT_INT_BOX3 BIT(3) 4412 #define BIT_INT_BOX2 BIT(2) 4413 #define BIT_INT_BOX1 BIT(1) 4414 #define BIT_INT_BOX0 BIT(0) 4415 4416 /* 2 REG_HMEBOX0 (Offset 0x01D0) */ 4417 4418 #define BIT_SHIFT_HOST_MSG_0 0 4419 #define BIT_MASK_HOST_MSG_0 0xffffffffL 4420 #define BIT_HOST_MSG_0(x) (((x) & BIT_MASK_HOST_MSG_0) << BIT_SHIFT_HOST_MSG_0) 4421 #define BIT_GET_HOST_MSG_0(x) \ 4422 (((x) >> BIT_SHIFT_HOST_MSG_0) & BIT_MASK_HOST_MSG_0) 4423 4424 /* 2 REG_HMEBOX1 (Offset 0x01D4) */ 4425 4426 #define BIT_SHIFT_HOST_MSG_1 0 4427 #define BIT_MASK_HOST_MSG_1 0xffffffffL 4428 #define BIT_HOST_MSG_1(x) (((x) & BIT_MASK_HOST_MSG_1) << BIT_SHIFT_HOST_MSG_1) 4429 #define BIT_GET_HOST_MSG_1(x) \ 4430 (((x) >> BIT_SHIFT_HOST_MSG_1) & BIT_MASK_HOST_MSG_1) 4431 4432 /* 2 REG_HMEBOX2 (Offset 0x01D8) */ 4433 4434 #define BIT_SHIFT_HOST_MSG_2 0 4435 #define BIT_MASK_HOST_MSG_2 0xffffffffL 4436 #define BIT_HOST_MSG_2(x) (((x) & BIT_MASK_HOST_MSG_2) << BIT_SHIFT_HOST_MSG_2) 4437 #define BIT_GET_HOST_MSG_2(x) \ 4438 (((x) >> BIT_SHIFT_HOST_MSG_2) & BIT_MASK_HOST_MSG_2) 4439 4440 /* 2 REG_HMEBOX3 (Offset 0x01DC) */ 4441 4442 #define BIT_SHIFT_HOST_MSG_3 0 4443 #define BIT_MASK_HOST_MSG_3 0xffffffffL 4444 #define BIT_HOST_MSG_3(x) (((x) & BIT_MASK_HOST_MSG_3) << BIT_SHIFT_HOST_MSG_3) 4445 #define BIT_GET_HOST_MSG_3(x) \ 4446 (((x) >> BIT_SHIFT_HOST_MSG_3) & BIT_MASK_HOST_MSG_3) 4447 4448 /* 2 REG_LLT_INIT (Offset 0x01E0) */ 4449 4450 #define BIT_SHIFT_LLTE_RWM 30 4451 #define BIT_MASK_LLTE_RWM 0x3 4452 #define BIT_LLTE_RWM(x) (((x) & BIT_MASK_LLTE_RWM) << BIT_SHIFT_LLTE_RWM) 4453 #define BIT_GET_LLTE_RWM(x) (((x) >> BIT_SHIFT_LLTE_RWM) & BIT_MASK_LLTE_RWM) 4454 4455 /* 2 REG_LLT_INIT (Offset 0x01E0) */ 4456 4457 #define BIT_SHIFT_LLTINI_PDATA_V1 16 4458 #define BIT_MASK_LLTINI_PDATA_V1 0xfff 4459 #define BIT_LLTINI_PDATA_V1(x) \ 4460 (((x) & BIT_MASK_LLTINI_PDATA_V1) << BIT_SHIFT_LLTINI_PDATA_V1) 4461 #define BIT_GET_LLTINI_PDATA_V1(x) \ 4462 (((x) >> BIT_SHIFT_LLTINI_PDATA_V1) & BIT_MASK_LLTINI_PDATA_V1) 4463 4464 /* 2 REG_LLT_INIT (Offset 0x01E0) */ 4465 4466 #define BIT_SHIFT_LLTINI_HDATA_V1 0 4467 #define BIT_MASK_LLTINI_HDATA_V1 0xfff 4468 #define BIT_LLTINI_HDATA_V1(x) \ 4469 (((x) & BIT_MASK_LLTINI_HDATA_V1) << BIT_SHIFT_LLTINI_HDATA_V1) 4470 #define BIT_GET_LLTINI_HDATA_V1(x) \ 4471 (((x) >> BIT_SHIFT_LLTINI_HDATA_V1) & BIT_MASK_LLTINI_HDATA_V1) 4472 4473 /* 2 REG_LLT_INIT_ADDR (Offset 0x01E4) */ 4474 4475 #define BIT_SHIFT_LLTINI_ADDR_V1 0 4476 #define BIT_MASK_LLTINI_ADDR_V1 0xfff 4477 #define BIT_LLTINI_ADDR_V1(x) \ 4478 (((x) & BIT_MASK_LLTINI_ADDR_V1) << BIT_SHIFT_LLTINI_ADDR_V1) 4479 #define BIT_GET_LLTINI_ADDR_V1(x) \ 4480 (((x) >> BIT_SHIFT_LLTINI_ADDR_V1) & BIT_MASK_LLTINI_ADDR_V1) 4481 4482 /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ 4483 4484 #define BIT_SHIFT_BB_WRITE_READ 30 4485 #define BIT_MASK_BB_WRITE_READ 0x3 4486 #define BIT_BB_WRITE_READ(x) \ 4487 (((x) & BIT_MASK_BB_WRITE_READ) << BIT_SHIFT_BB_WRITE_READ) 4488 #define BIT_GET_BB_WRITE_READ(x) \ 4489 (((x) >> BIT_SHIFT_BB_WRITE_READ) & BIT_MASK_BB_WRITE_READ) 4490 4491 /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ 4492 4493 #define BIT_SHIFT_BB_WRITE_EN 12 4494 #define BIT_MASK_BB_WRITE_EN 0xf 4495 #define BIT_BB_WRITE_EN(x) \ 4496 (((x) & BIT_MASK_BB_WRITE_EN) << BIT_SHIFT_BB_WRITE_EN) 4497 #define BIT_GET_BB_WRITE_EN(x) \ 4498 (((x) >> BIT_SHIFT_BB_WRITE_EN) & BIT_MASK_BB_WRITE_EN) 4499 4500 #define BIT_SHIFT_BB_ADDR 2 4501 #define BIT_MASK_BB_ADDR 0x1ff 4502 #define BIT_BB_ADDR(x) (((x) & BIT_MASK_BB_ADDR) << BIT_SHIFT_BB_ADDR) 4503 #define BIT_GET_BB_ADDR(x) (((x) >> BIT_SHIFT_BB_ADDR) & BIT_MASK_BB_ADDR) 4504 4505 /* 2 REG_BB_ACCESS_CTRL (Offset 0x01E8) */ 4506 4507 #define BIT_BB_ERRACC BIT(0) 4508 4509 /* 2 REG_BB_ACCESS_DATA (Offset 0x01EC) */ 4510 4511 #define BIT_SHIFT_BB_DATA 0 4512 #define BIT_MASK_BB_DATA 0xffffffffL 4513 #define BIT_BB_DATA(x) (((x) & BIT_MASK_BB_DATA) << BIT_SHIFT_BB_DATA) 4514 #define BIT_GET_BB_DATA(x) (((x) >> BIT_SHIFT_BB_DATA) & BIT_MASK_BB_DATA) 4515 4516 /* 2 REG_HMEBOX_E0 (Offset 0x01F0) */ 4517 4518 #define BIT_SHIFT_HMEBOX_E0 0 4519 #define BIT_MASK_HMEBOX_E0 0xffffffffL 4520 #define BIT_HMEBOX_E0(x) (((x) & BIT_MASK_HMEBOX_E0) << BIT_SHIFT_HMEBOX_E0) 4521 #define BIT_GET_HMEBOX_E0(x) (((x) >> BIT_SHIFT_HMEBOX_E0) & BIT_MASK_HMEBOX_E0) 4522 4523 /* 2 REG_HMEBOX_E1 (Offset 0x01F4) */ 4524 4525 #define BIT_SHIFT_HMEBOX_E1 0 4526 #define BIT_MASK_HMEBOX_E1 0xffffffffL 4527 #define BIT_HMEBOX_E1(x) (((x) & BIT_MASK_HMEBOX_E1) << BIT_SHIFT_HMEBOX_E1) 4528 #define BIT_GET_HMEBOX_E1(x) (((x) >> BIT_SHIFT_HMEBOX_E1) & BIT_MASK_HMEBOX_E1) 4529 4530 /* 2 REG_HMEBOX_E2 (Offset 0x01F8) */ 4531 4532 #define BIT_SHIFT_HMEBOX_E2 0 4533 #define BIT_MASK_HMEBOX_E2 0xffffffffL 4534 #define BIT_HMEBOX_E2(x) (((x) & BIT_MASK_HMEBOX_E2) << BIT_SHIFT_HMEBOX_E2) 4535 #define BIT_GET_HMEBOX_E2(x) (((x) >> BIT_SHIFT_HMEBOX_E2) & BIT_MASK_HMEBOX_E2) 4536 4537 /* 2 REG_HMEBOX_E3 (Offset 0x01FC) */ 4538 4539 #define BIT_LD_RQPN BIT(31) 4540 4541 #define BIT_SHIFT_HMEBOX_E3 0 4542 #define BIT_MASK_HMEBOX_E3 0xffffffffL 4543 #define BIT_HMEBOX_E3(x) (((x) & BIT_MASK_HMEBOX_E3) << BIT_SHIFT_HMEBOX_E3) 4544 #define BIT_GET_HMEBOX_E3(x) (((x) >> BIT_SHIFT_HMEBOX_E3) & BIT_MASK_HMEBOX_E3) 4545 4546 /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ 4547 4548 #define BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1 16 4549 #define BIT_MASK_TX_OQT_HE_FREE_SPACE_V1 0xff 4550 #define BIT_TX_OQT_HE_FREE_SPACE_V1(x) \ 4551 (((x) & BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) \ 4552 << BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) 4553 #define BIT_GET_TX_OQT_HE_FREE_SPACE_V1(x) \ 4554 (((x) >> BIT_SHIFT_TX_OQT_HE_FREE_SPACE_V1) & \ 4555 BIT_MASK_TX_OQT_HE_FREE_SPACE_V1) 4556 4557 /* 2 REG_FIFOPAGE_CTRL_1 (Offset 0x0200) */ 4558 4559 #define BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1 0 4560 #define BIT_MASK_TX_OQT_NL_FREE_SPACE_V1 0xff 4561 #define BIT_TX_OQT_NL_FREE_SPACE_V1(x) \ 4562 (((x) & BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) \ 4563 << BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) 4564 #define BIT_GET_TX_OQT_NL_FREE_SPACE_V1(x) \ 4565 (((x) >> BIT_SHIFT_TX_OQT_NL_FREE_SPACE_V1) & \ 4566 BIT_MASK_TX_OQT_NL_FREE_SPACE_V1) 4567 4568 /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ 4569 4570 #define BIT_BCN_VALID_1_V1 BIT(31) 4571 4572 /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ 4573 4574 #define BIT_SHIFT_BCN_HEAD_1_V1 16 4575 #define BIT_MASK_BCN_HEAD_1_V1 0xfff 4576 #define BIT_BCN_HEAD_1_V1(x) \ 4577 (((x) & BIT_MASK_BCN_HEAD_1_V1) << BIT_SHIFT_BCN_HEAD_1_V1) 4578 #define BIT_GET_BCN_HEAD_1_V1(x) \ 4579 (((x) >> BIT_SHIFT_BCN_HEAD_1_V1) & BIT_MASK_BCN_HEAD_1_V1) 4580 4581 #define BIT_BCN_VALID_V1 BIT(15) 4582 4583 /* 2 REG_FIFOPAGE_CTRL_2 (Offset 0x0204) */ 4584 4585 #define BIT_SHIFT_BCN_HEAD_V1 0 4586 #define BIT_MASK_BCN_HEAD_V1 0xfff 4587 #define BIT_BCN_HEAD_V1(x) \ 4588 (((x) & BIT_MASK_BCN_HEAD_V1) << BIT_SHIFT_BCN_HEAD_V1) 4589 #define BIT_GET_BCN_HEAD_V1(x) \ 4590 (((x) >> BIT_SHIFT_BCN_HEAD_V1) & BIT_MASK_BCN_HEAD_V1) 4591 4592 /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ 4593 4594 #define BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 24 4595 #define BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1 0xff 4596 #define BIT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ 4597 (((x) & BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) \ 4598 << BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) 4599 #define BIT_GET_MAX_TX_PKT_FOR_USB_AND_SDIO_V1(x) \ 4600 (((x) >> BIT_SHIFT_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) & \ 4601 BIT_MASK_MAX_TX_PKT_FOR_USB_AND_SDIO_V1) 4602 4603 /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ 4604 4605 #define BIT_SHIFT_LLT_FREE_PAGE_V1 8 4606 #define BIT_MASK_LLT_FREE_PAGE_V1 0xffff 4607 #define BIT_LLT_FREE_PAGE_V1(x) \ 4608 (((x) & BIT_MASK_LLT_FREE_PAGE_V1) << BIT_SHIFT_LLT_FREE_PAGE_V1) 4609 #define BIT_GET_LLT_FREE_PAGE_V1(x) \ 4610 (((x) >> BIT_SHIFT_LLT_FREE_PAGE_V1) & BIT_MASK_LLT_FREE_PAGE_V1) 4611 4612 /* 2 REG_DWBCN0_CTRL (Offset 0x0208) */ 4613 4614 #define BIT_SHIFT_BLK_DESC_NUM 4 4615 #define BIT_MASK_BLK_DESC_NUM 0xf 4616 #define BIT_BLK_DESC_NUM(x) \ 4617 (((x) & BIT_MASK_BLK_DESC_NUM) << BIT_SHIFT_BLK_DESC_NUM) 4618 #define BIT_GET_BLK_DESC_NUM(x) \ 4619 (((x) >> BIT_SHIFT_BLK_DESC_NUM) & BIT_MASK_BLK_DESC_NUM) 4620 4621 /* 2 REG_AUTO_LLT_V1 (Offset 0x0208) */ 4622 4623 #define BIT_R_BCN_HEAD_SEL BIT(3) 4624 #define BIT_R_EN_BCN_SW_HEAD_SEL BIT(2) 4625 #define BIT_LLT_DBG_SEL BIT(1) 4626 #define BIT_AUTO_INIT_LLT_V1 BIT(0) 4627 4628 /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4629 4630 #define BIT_EM_CHKSUM_FIN BIT(31) 4631 #define BIT_EMN_PCIE_DMA_MOD BIT(30) 4632 4633 /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4634 4635 #define BIT_EN_TXQUE_CLR BIT(29) 4636 #define BIT_EN_PCIE_FIFO_MODE BIT(28) 4637 4638 /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4639 4640 #define BIT_SHIFT_PG_UNDER_TH_V1 16 4641 #define BIT_MASK_PG_UNDER_TH_V1 0xfff 4642 #define BIT_PG_UNDER_TH_V1(x) \ 4643 (((x) & BIT_MASK_PG_UNDER_TH_V1) << BIT_SHIFT_PG_UNDER_TH_V1) 4644 #define BIT_GET_PG_UNDER_TH_V1(x) \ 4645 (((x) >> BIT_SHIFT_PG_UNDER_TH_V1) & BIT_MASK_PG_UNDER_TH_V1) 4646 4647 /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4648 4649 #define BIT_RESTORE_H2C_ADDRESS BIT(15) 4650 4651 /* 2 REG_TXDMA_OFFSET_CHK (Offset 0x020C) */ 4652 4653 #define BIT_SDIO_TXDESC_CHKSUM_EN BIT(13) 4654 #define BIT_RST_RDPTR BIT(12) 4655 #define BIT_RST_WRPTR BIT(11) 4656 #define BIT_CHK_PG_TH_EN BIT(10) 4657 #define BIT_DROP_DATA_EN BIT(9) 4658 #define BIT_CHECK_OFFSET_EN BIT(8) 4659 4660 #define BIT_SHIFT_CHECK_OFFSET 0 4661 #define BIT_MASK_CHECK_OFFSET 0xff 4662 #define BIT_CHECK_OFFSET(x) \ 4663 (((x) & BIT_MASK_CHECK_OFFSET) << BIT_SHIFT_CHECK_OFFSET) 4664 #define BIT_GET_CHECK_OFFSET(x) \ 4665 (((x) >> BIT_SHIFT_CHECK_OFFSET) & BIT_MASK_CHECK_OFFSET) 4666 4667 /* 2 REG_TXDMA_STATUS (Offset 0x0210) */ 4668 4669 #define BIT_HI_OQT_UDN BIT(17) 4670 #define BIT_HI_OQT_OVF BIT(16) 4671 #define BIT_PAYLOAD_CHKSUM_ERR BIT(15) 4672 #define BIT_PAYLOAD_UDN BIT(14) 4673 #define BIT_PAYLOAD_OVF BIT(13) 4674 #define BIT_DSC_CHKSUM_FAIL BIT(12) 4675 #define BIT_UNKNOWN_QSEL BIT(11) 4676 #define BIT_EP_QSEL_DIFF BIT(10) 4677 #define BIT_TX_OFFS_UNMATCH BIT(9) 4678 #define BIT_TXOQT_UDN BIT(8) 4679 #define BIT_TXOQT_OVF BIT(7) 4680 #define BIT_TXDMA_SFF_UDN BIT(6) 4681 #define BIT_TXDMA_SFF_OVF BIT(5) 4682 #define BIT_LLT_NULL_PG BIT(4) 4683 #define BIT_PAGE_UDN BIT(3) 4684 #define BIT_PAGE_OVF BIT(2) 4685 #define BIT_TXFF_PG_UDN BIT(1) 4686 #define BIT_TXFF_PG_OVF BIT(0) 4687 4688 /* 2 REG_TQPNT1 (Offset 0x0218) */ 4689 4690 #define BIT_SHIFT_HPQ_HIGH_TH_V1 16 4691 #define BIT_MASK_HPQ_HIGH_TH_V1 0xfff 4692 #define BIT_HPQ_HIGH_TH_V1(x) \ 4693 (((x) & BIT_MASK_HPQ_HIGH_TH_V1) << BIT_SHIFT_HPQ_HIGH_TH_V1) 4694 #define BIT_GET_HPQ_HIGH_TH_V1(x) \ 4695 (((x) >> BIT_SHIFT_HPQ_HIGH_TH_V1) & BIT_MASK_HPQ_HIGH_TH_V1) 4696 4697 /* 2 REG_TQPNT1 (Offset 0x0218) */ 4698 4699 #define BIT_SHIFT_HPQ_LOW_TH_V1 0 4700 #define BIT_MASK_HPQ_LOW_TH_V1 0xfff 4701 #define BIT_HPQ_LOW_TH_V1(x) \ 4702 (((x) & BIT_MASK_HPQ_LOW_TH_V1) << BIT_SHIFT_HPQ_LOW_TH_V1) 4703 #define BIT_GET_HPQ_LOW_TH_V1(x) \ 4704 (((x) >> BIT_SHIFT_HPQ_LOW_TH_V1) & BIT_MASK_HPQ_LOW_TH_V1) 4705 4706 /* 2 REG_TQPNT2 (Offset 0x021C) */ 4707 4708 #define BIT_SHIFT_NPQ_HIGH_TH_V1 16 4709 #define BIT_MASK_NPQ_HIGH_TH_V1 0xfff 4710 #define BIT_NPQ_HIGH_TH_V1(x) \ 4711 (((x) & BIT_MASK_NPQ_HIGH_TH_V1) << BIT_SHIFT_NPQ_HIGH_TH_V1) 4712 #define BIT_GET_NPQ_HIGH_TH_V1(x) \ 4713 (((x) >> BIT_SHIFT_NPQ_HIGH_TH_V1) & BIT_MASK_NPQ_HIGH_TH_V1) 4714 4715 /* 2 REG_TQPNT2 (Offset 0x021C) */ 4716 4717 #define BIT_SHIFT_NPQ_LOW_TH_V1 0 4718 #define BIT_MASK_NPQ_LOW_TH_V1 0xfff 4719 #define BIT_NPQ_LOW_TH_V1(x) \ 4720 (((x) & BIT_MASK_NPQ_LOW_TH_V1) << BIT_SHIFT_NPQ_LOW_TH_V1) 4721 #define BIT_GET_NPQ_LOW_TH_V1(x) \ 4722 (((x) >> BIT_SHIFT_NPQ_LOW_TH_V1) & BIT_MASK_NPQ_LOW_TH_V1) 4723 4724 /* 2 REG_TQPNT3 (Offset 0x0220) */ 4725 4726 #define BIT_SHIFT_LPQ_HIGH_TH_V1 16 4727 #define BIT_MASK_LPQ_HIGH_TH_V1 0xfff 4728 #define BIT_LPQ_HIGH_TH_V1(x) \ 4729 (((x) & BIT_MASK_LPQ_HIGH_TH_V1) << BIT_SHIFT_LPQ_HIGH_TH_V1) 4730 #define BIT_GET_LPQ_HIGH_TH_V1(x) \ 4731 (((x) >> BIT_SHIFT_LPQ_HIGH_TH_V1) & BIT_MASK_LPQ_HIGH_TH_V1) 4732 4733 /* 2 REG_TQPNT3 (Offset 0x0220) */ 4734 4735 #define BIT_SHIFT_LPQ_LOW_TH_V1 0 4736 #define BIT_MASK_LPQ_LOW_TH_V1 0xfff 4737 #define BIT_LPQ_LOW_TH_V1(x) \ 4738 (((x) & BIT_MASK_LPQ_LOW_TH_V1) << BIT_SHIFT_LPQ_LOW_TH_V1) 4739 #define BIT_GET_LPQ_LOW_TH_V1(x) \ 4740 (((x) >> BIT_SHIFT_LPQ_LOW_TH_V1) & BIT_MASK_LPQ_LOW_TH_V1) 4741 4742 /* 2 REG_TQPNT4 (Offset 0x0224) */ 4743 4744 #define BIT_SHIFT_EXQ_HIGH_TH_V1 16 4745 #define BIT_MASK_EXQ_HIGH_TH_V1 0xfff 4746 #define BIT_EXQ_HIGH_TH_V1(x) \ 4747 (((x) & BIT_MASK_EXQ_HIGH_TH_V1) << BIT_SHIFT_EXQ_HIGH_TH_V1) 4748 #define BIT_GET_EXQ_HIGH_TH_V1(x) \ 4749 (((x) >> BIT_SHIFT_EXQ_HIGH_TH_V1) & BIT_MASK_EXQ_HIGH_TH_V1) 4750 4751 /* 2 REG_TQPNT4 (Offset 0x0224) */ 4752 4753 #define BIT_SHIFT_EXQ_LOW_TH_V1 0 4754 #define BIT_MASK_EXQ_LOW_TH_V1 0xfff 4755 #define BIT_EXQ_LOW_TH_V1(x) \ 4756 (((x) & BIT_MASK_EXQ_LOW_TH_V1) << BIT_SHIFT_EXQ_LOW_TH_V1) 4757 #define BIT_GET_EXQ_LOW_TH_V1(x) \ 4758 (((x) >> BIT_SHIFT_EXQ_LOW_TH_V1) & BIT_MASK_EXQ_LOW_TH_V1) 4759 4760 /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ 4761 4762 #define BIT_SHIFT_TXPKTNUM_H 16 4763 #define BIT_MASK_TXPKTNUM_H 0xffff 4764 #define BIT_TXPKTNUM_H(x) (((x) & BIT_MASK_TXPKTNUM_H) << BIT_SHIFT_TXPKTNUM_H) 4765 #define BIT_GET_TXPKTNUM_H(x) \ 4766 (((x) >> BIT_SHIFT_TXPKTNUM_H) & BIT_MASK_TXPKTNUM_H) 4767 4768 /* 2 REG_RQPN_CTRL_1 (Offset 0x0228) */ 4769 4770 #define BIT_SHIFT_TXPKTNUM_V2 0 4771 #define BIT_MASK_TXPKTNUM_V2 0xffff 4772 #define BIT_TXPKTNUM_V2(x) \ 4773 (((x) & BIT_MASK_TXPKTNUM_V2) << BIT_SHIFT_TXPKTNUM_V2) 4774 #define BIT_GET_TXPKTNUM_V2(x) \ 4775 (((x) >> BIT_SHIFT_TXPKTNUM_V2) & BIT_MASK_TXPKTNUM_V2) 4776 4777 /* 2 REG_RQPN_CTRL_2 (Offset 0x022C) */ 4778 4779 #define BIT_EXQ_PUBLIC_DIS_V1 BIT(19) 4780 #define BIT_NPQ_PUBLIC_DIS_V1 BIT(18) 4781 #define BIT_LPQ_PUBLIC_DIS_V1 BIT(17) 4782 #define BIT_HPQ_PUBLIC_DIS_V1 BIT(16) 4783 4784 /* 2 REG_FIFOPAGE_INFO_1 (Offset 0x0230) */ 4785 4786 #define BIT_SHIFT_HPQ_AVAL_PG_V1 16 4787 #define BIT_MASK_HPQ_AVAL_PG_V1 0xfff 4788 #define BIT_HPQ_AVAL_PG_V1(x) \ 4789 (((x) & BIT_MASK_HPQ_AVAL_PG_V1) << BIT_SHIFT_HPQ_AVAL_PG_V1) 4790 #define BIT_GET_HPQ_AVAL_PG_V1(x) \ 4791 (((x) >> BIT_SHIFT_HPQ_AVAL_PG_V1) & BIT_MASK_HPQ_AVAL_PG_V1) 4792 4793 #define BIT_SHIFT_HPQ_V1 0 4794 #define BIT_MASK_HPQ_V1 0xfff 4795 #define BIT_HPQ_V1(x) (((x) & BIT_MASK_HPQ_V1) << BIT_SHIFT_HPQ_V1) 4796 #define BIT_GET_HPQ_V1(x) (((x) >> BIT_SHIFT_HPQ_V1) & BIT_MASK_HPQ_V1) 4797 4798 /* 2 REG_FIFOPAGE_INFO_2 (Offset 0x0234) */ 4799 4800 #define BIT_SHIFT_LPQ_AVAL_PG_V1 16 4801 #define BIT_MASK_LPQ_AVAL_PG_V1 0xfff 4802 #define BIT_LPQ_AVAL_PG_V1(x) \ 4803 (((x) & BIT_MASK_LPQ_AVAL_PG_V1) << BIT_SHIFT_LPQ_AVAL_PG_V1) 4804 #define BIT_GET_LPQ_AVAL_PG_V1(x) \ 4805 (((x) >> BIT_SHIFT_LPQ_AVAL_PG_V1) & BIT_MASK_LPQ_AVAL_PG_V1) 4806 4807 #define BIT_SHIFT_LPQ_V1 0 4808 #define BIT_MASK_LPQ_V1 0xfff 4809 #define BIT_LPQ_V1(x) (((x) & BIT_MASK_LPQ_V1) << BIT_SHIFT_LPQ_V1) 4810 #define BIT_GET_LPQ_V1(x) (((x) >> BIT_SHIFT_LPQ_V1) & BIT_MASK_LPQ_V1) 4811 4812 /* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ 4813 4814 #define BIT_SHIFT_NPQ_AVAL_PG_V1 16 4815 #define BIT_MASK_NPQ_AVAL_PG_V1 0xfff 4816 #define BIT_NPQ_AVAL_PG_V1(x) \ 4817 (((x) & BIT_MASK_NPQ_AVAL_PG_V1) << BIT_SHIFT_NPQ_AVAL_PG_V1) 4818 #define BIT_GET_NPQ_AVAL_PG_V1(x) \ 4819 (((x) >> BIT_SHIFT_NPQ_AVAL_PG_V1) & BIT_MASK_NPQ_AVAL_PG_V1) 4820 4821 /* 2 REG_FIFOPAGE_INFO_3 (Offset 0x0238) */ 4822 4823 #define BIT_SHIFT_NPQ_V1 0 4824 #define BIT_MASK_NPQ_V1 0xfff 4825 #define BIT_NPQ_V1(x) (((x) & BIT_MASK_NPQ_V1) << BIT_SHIFT_NPQ_V1) 4826 #define BIT_GET_NPQ_V1(x) (((x) >> BIT_SHIFT_NPQ_V1) & BIT_MASK_NPQ_V1) 4827 4828 /* 2 REG_FIFOPAGE_INFO_4 (Offset 0x023C) */ 4829 4830 #define BIT_SHIFT_EXQ_AVAL_PG_V1 16 4831 #define BIT_MASK_EXQ_AVAL_PG_V1 0xfff 4832 #define BIT_EXQ_AVAL_PG_V1(x) \ 4833 (((x) & BIT_MASK_EXQ_AVAL_PG_V1) << BIT_SHIFT_EXQ_AVAL_PG_V1) 4834 #define BIT_GET_EXQ_AVAL_PG_V1(x) \ 4835 (((x) >> BIT_SHIFT_EXQ_AVAL_PG_V1) & BIT_MASK_EXQ_AVAL_PG_V1) 4836 4837 #define BIT_SHIFT_EXQ_V1 0 4838 #define BIT_MASK_EXQ_V1 0xfff 4839 #define BIT_EXQ_V1(x) (((x) & BIT_MASK_EXQ_V1) << BIT_SHIFT_EXQ_V1) 4840 #define BIT_GET_EXQ_V1(x) (((x) >> BIT_SHIFT_EXQ_V1) & BIT_MASK_EXQ_V1) 4841 4842 /* 2 REG_FIFOPAGE_INFO_5 (Offset 0x0240) */ 4843 4844 #define BIT_SHIFT_PUBQ_AVAL_PG_V1 16 4845 #define BIT_MASK_PUBQ_AVAL_PG_V1 0xfff 4846 #define BIT_PUBQ_AVAL_PG_V1(x) \ 4847 (((x) & BIT_MASK_PUBQ_AVAL_PG_V1) << BIT_SHIFT_PUBQ_AVAL_PG_V1) 4848 #define BIT_GET_PUBQ_AVAL_PG_V1(x) \ 4849 (((x) >> BIT_SHIFT_PUBQ_AVAL_PG_V1) & BIT_MASK_PUBQ_AVAL_PG_V1) 4850 4851 #define BIT_SHIFT_PUBQ_V1 0 4852 #define BIT_MASK_PUBQ_V1 0xfff 4853 #define BIT_PUBQ_V1(x) (((x) & BIT_MASK_PUBQ_V1) << BIT_SHIFT_PUBQ_V1) 4854 #define BIT_GET_PUBQ_V1(x) (((x) >> BIT_SHIFT_PUBQ_V1) & BIT_MASK_PUBQ_V1) 4855 4856 /* 2 REG_H2C_HEAD (Offset 0x0244) */ 4857 4858 #define BIT_SHIFT_H2C_HEAD 0 4859 #define BIT_MASK_H2C_HEAD 0x3ffff 4860 #define BIT_H2C_HEAD(x) (((x) & BIT_MASK_H2C_HEAD) << BIT_SHIFT_H2C_HEAD) 4861 #define BIT_GET_H2C_HEAD(x) (((x) >> BIT_SHIFT_H2C_HEAD) & BIT_MASK_H2C_HEAD) 4862 4863 /* 2 REG_H2C_TAIL (Offset 0x0248) */ 4864 4865 #define BIT_SHIFT_H2C_TAIL 0 4866 #define BIT_MASK_H2C_TAIL 0x3ffff 4867 #define BIT_H2C_TAIL(x) (((x) & BIT_MASK_H2C_TAIL) << BIT_SHIFT_H2C_TAIL) 4868 #define BIT_GET_H2C_TAIL(x) (((x) >> BIT_SHIFT_H2C_TAIL) & BIT_MASK_H2C_TAIL) 4869 4870 /* 2 REG_H2C_READ_ADDR (Offset 0x024C) */ 4871 4872 #define BIT_SHIFT_H2C_READ_ADDR 0 4873 #define BIT_MASK_H2C_READ_ADDR 0x3ffff 4874 #define BIT_H2C_READ_ADDR(x) \ 4875 (((x) & BIT_MASK_H2C_READ_ADDR) << BIT_SHIFT_H2C_READ_ADDR) 4876 #define BIT_GET_H2C_READ_ADDR(x) \ 4877 (((x) >> BIT_SHIFT_H2C_READ_ADDR) & BIT_MASK_H2C_READ_ADDR) 4878 4879 /* 2 REG_H2C_WR_ADDR (Offset 0x0250) */ 4880 4881 #define BIT_SHIFT_H2C_WR_ADDR 0 4882 #define BIT_MASK_H2C_WR_ADDR 0x3ffff 4883 #define BIT_H2C_WR_ADDR(x) \ 4884 (((x) & BIT_MASK_H2C_WR_ADDR) << BIT_SHIFT_H2C_WR_ADDR) 4885 #define BIT_GET_H2C_WR_ADDR(x) \ 4886 (((x) >> BIT_SHIFT_H2C_WR_ADDR) & BIT_MASK_H2C_WR_ADDR) 4887 4888 /* 2 REG_H2C_INFO (Offset 0x0254) */ 4889 4890 #define BIT_H2C_SPACE_VLD BIT(3) 4891 #define BIT_H2C_WR_ADDR_RST BIT(2) 4892 4893 #define BIT_SHIFT_H2C_LEN_SEL 0 4894 #define BIT_MASK_H2C_LEN_SEL 0x3 4895 #define BIT_H2C_LEN_SEL(x) \ 4896 (((x) & BIT_MASK_H2C_LEN_SEL) << BIT_SHIFT_H2C_LEN_SEL) 4897 #define BIT_GET_H2C_LEN_SEL(x) \ 4898 (((x) >> BIT_SHIFT_H2C_LEN_SEL) & BIT_MASK_H2C_LEN_SEL) 4899 4900 /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4901 4902 #define BIT_SHIFT_RXDMA_AGG_OLD_MOD 24 4903 #define BIT_MASK_RXDMA_AGG_OLD_MOD 0xff 4904 #define BIT_RXDMA_AGG_OLD_MOD(x) \ 4905 (((x) & BIT_MASK_RXDMA_AGG_OLD_MOD) << BIT_SHIFT_RXDMA_AGG_OLD_MOD) 4906 #define BIT_GET_RXDMA_AGG_OLD_MOD(x) \ 4907 (((x) >> BIT_SHIFT_RXDMA_AGG_OLD_MOD) & BIT_MASK_RXDMA_AGG_OLD_MOD) 4908 4909 /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4910 4911 #define BIT_SHIFT_PKT_NUM_WOL 16 4912 #define BIT_MASK_PKT_NUM_WOL 0xff 4913 #define BIT_PKT_NUM_WOL(x) \ 4914 (((x) & BIT_MASK_PKT_NUM_WOL) << BIT_SHIFT_PKT_NUM_WOL) 4915 #define BIT_GET_PKT_NUM_WOL(x) \ 4916 (((x) >> BIT_SHIFT_PKT_NUM_WOL) & BIT_MASK_PKT_NUM_WOL) 4917 4918 /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4919 4920 #define BIT_SHIFT_DMA_AGG_TO 8 4921 #define BIT_MASK_DMA_AGG_TO 0xf 4922 #define BIT_DMA_AGG_TO(x) (((x) & BIT_MASK_DMA_AGG_TO) << BIT_SHIFT_DMA_AGG_TO) 4923 #define BIT_GET_DMA_AGG_TO(x) \ 4924 (((x) >> BIT_SHIFT_DMA_AGG_TO) & BIT_MASK_DMA_AGG_TO) 4925 4926 /* 2 REG_RXDMA_AGG_PG_TH (Offset 0x0280) */ 4927 4928 #define BIT_SHIFT_RXDMA_AGG_PG_TH_V1 0 4929 #define BIT_MASK_RXDMA_AGG_PG_TH_V1 0xf 4930 #define BIT_RXDMA_AGG_PG_TH_V1(x) \ 4931 (((x) & BIT_MASK_RXDMA_AGG_PG_TH_V1) << BIT_SHIFT_RXDMA_AGG_PG_TH_V1) 4932 #define BIT_GET_RXDMA_AGG_PG_TH_V1(x) \ 4933 (((x) >> BIT_SHIFT_RXDMA_AGG_PG_TH_V1) & BIT_MASK_RXDMA_AGG_PG_TH_V1) 4934 4935 /* 2 REG_RXPKT_NUM (Offset 0x0284) */ 4936 4937 #define BIT_SHIFT_RXPKT_NUM 24 4938 #define BIT_MASK_RXPKT_NUM 0xff 4939 #define BIT_RXPKT_NUM(x) (((x) & BIT_MASK_RXPKT_NUM) << BIT_SHIFT_RXPKT_NUM) 4940 #define BIT_GET_RXPKT_NUM(x) (((x) >> BIT_SHIFT_RXPKT_NUM) & BIT_MASK_RXPKT_NUM) 4941 4942 /* 2 REG_RXPKT_NUM (Offset 0x0284) */ 4943 4944 #define BIT_SHIFT_FW_UPD_RDPTR19_TO_16 20 4945 #define BIT_MASK_FW_UPD_RDPTR19_TO_16 0xf 4946 #define BIT_FW_UPD_RDPTR19_TO_16(x) \ 4947 (((x) & BIT_MASK_FW_UPD_RDPTR19_TO_16) \ 4948 << BIT_SHIFT_FW_UPD_RDPTR19_TO_16) 4949 #define BIT_GET_FW_UPD_RDPTR19_TO_16(x) \ 4950 (((x) >> BIT_SHIFT_FW_UPD_RDPTR19_TO_16) & \ 4951 BIT_MASK_FW_UPD_RDPTR19_TO_16) 4952 4953 /* 2 REG_RXPKT_NUM (Offset 0x0284) */ 4954 4955 #define BIT_RXDMA_REQ BIT(19) 4956 #define BIT_RW_RELEASE_EN BIT(18) 4957 #define BIT_RXDMA_IDLE BIT(17) 4958 #define BIT_RXPKT_RELEASE_POLL BIT(16) 4959 4960 #define BIT_SHIFT_FW_UPD_RDPTR 0 4961 #define BIT_MASK_FW_UPD_RDPTR 0xffff 4962 #define BIT_FW_UPD_RDPTR(x) \ 4963 (((x) & BIT_MASK_FW_UPD_RDPTR) << BIT_SHIFT_FW_UPD_RDPTR) 4964 #define BIT_GET_FW_UPD_RDPTR(x) \ 4965 (((x) >> BIT_SHIFT_FW_UPD_RDPTR) & BIT_MASK_FW_UPD_RDPTR) 4966 4967 /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4968 4969 #define BIT_C2H_PKT_OVF BIT(7) 4970 4971 /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4972 4973 #define BIT_AGG_CONFGI_ISSUE BIT(6) 4974 4975 /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4976 4977 #define BIT_FW_POLL_ISSUE BIT(5) 4978 #define BIT_RX_DATA_UDN BIT(4) 4979 #define BIT_RX_SFF_UDN BIT(3) 4980 #define BIT_RX_SFF_OVF BIT(2) 4981 4982 /* 2 REG_RXDMA_STATUS (Offset 0x0288) */ 4983 4984 #define BIT_RXPKT_OVF BIT(0) 4985 4986 /* 2 REG_RXDMA_DPR (Offset 0x028C) */ 4987 4988 #define BIT_SHIFT_RDE_DEBUG 0 4989 #define BIT_MASK_RDE_DEBUG 0xffffffffL 4990 #define BIT_RDE_DEBUG(x) (((x) & BIT_MASK_RDE_DEBUG) << BIT_SHIFT_RDE_DEBUG) 4991 #define BIT_GET_RDE_DEBUG(x) (((x) >> BIT_SHIFT_RDE_DEBUG) & BIT_MASK_RDE_DEBUG) 4992 4993 /* 2 REG_RXDMA_MODE (Offset 0x0290) */ 4994 4995 #define BIT_SHIFT_PKTNUM_TH_V2 24 4996 #define BIT_MASK_PKTNUM_TH_V2 0x1f 4997 #define BIT_PKTNUM_TH_V2(x) \ 4998 (((x) & BIT_MASK_PKTNUM_TH_V2) << BIT_SHIFT_PKTNUM_TH_V2) 4999 #define BIT_GET_PKTNUM_TH_V2(x) \ 5000 (((x) >> BIT_SHIFT_PKTNUM_TH_V2) & BIT_MASK_PKTNUM_TH_V2) 5001 5002 #define BIT_TXBA_BREAK_USBAGG BIT(23) 5003 5004 #define BIT_SHIFT_PKTLEN_PARA 16 5005 #define BIT_MASK_PKTLEN_PARA 0x7 5006 #define BIT_PKTLEN_PARA(x) \ 5007 (((x) & BIT_MASK_PKTLEN_PARA) << BIT_SHIFT_PKTLEN_PARA) 5008 #define BIT_GET_PKTLEN_PARA(x) \ 5009 (((x) >> BIT_SHIFT_PKTLEN_PARA) & BIT_MASK_PKTLEN_PARA) 5010 5011 /* 2 REG_RXDMA_MODE (Offset 0x0290) */ 5012 5013 #define BIT_SHIFT_BURST_SIZE 4 5014 #define BIT_MASK_BURST_SIZE 0x3 5015 #define BIT_BURST_SIZE(x) (((x) & BIT_MASK_BURST_SIZE) << BIT_SHIFT_BURST_SIZE) 5016 #define BIT_GET_BURST_SIZE(x) \ 5017 (((x) >> BIT_SHIFT_BURST_SIZE) & BIT_MASK_BURST_SIZE) 5018 5019 #define BIT_SHIFT_BURST_CNT 2 5020 #define BIT_MASK_BURST_CNT 0x3 5021 #define BIT_BURST_CNT(x) (((x) & BIT_MASK_BURST_CNT) << BIT_SHIFT_BURST_CNT) 5022 #define BIT_GET_BURST_CNT(x) (((x) >> BIT_SHIFT_BURST_CNT) & BIT_MASK_BURST_CNT) 5023 5024 /* 2 REG_RXDMA_MODE (Offset 0x0290) */ 5025 5026 #define BIT_DMA_MODE BIT(1) 5027 5028 /* 2 REG_C2H_PKT (Offset 0x0294) */ 5029 5030 #define BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19 24 5031 #define BIT_MASK_R_C2H_STR_ADDR_16_TO_19 0xf 5032 #define BIT_R_C2H_STR_ADDR_16_TO_19(x) \ 5033 (((x) & BIT_MASK_R_C2H_STR_ADDR_16_TO_19) \ 5034 << BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) 5035 #define BIT_GET_R_C2H_STR_ADDR_16_TO_19(x) \ 5036 (((x) >> BIT_SHIFT_R_C2H_STR_ADDR_16_TO_19) & \ 5037 BIT_MASK_R_C2H_STR_ADDR_16_TO_19) 5038 5039 #define BIT_SHIFT_MDIO_PHY_ADDR 24 5040 #define BIT_MASK_MDIO_PHY_ADDR 0x1f 5041 #define BIT_MDIO_PHY_ADDR(x) \ 5042 (((x) & BIT_MASK_MDIO_PHY_ADDR) << BIT_SHIFT_MDIO_PHY_ADDR) 5043 #define BIT_GET_MDIO_PHY_ADDR(x) \ 5044 (((x) >> BIT_SHIFT_MDIO_PHY_ADDR) & BIT_MASK_MDIO_PHY_ADDR) 5045 5046 /* 2 REG_C2H_PKT (Offset 0x0294) */ 5047 5048 #define BIT_R_C2H_PKT_REQ BIT(16) 5049 #define BIT_RX_CLOSE_EN BIT(15) 5050 #define BIT_STOP_BCNQ BIT(14) 5051 #define BIT_STOP_MGQ BIT(13) 5052 #define BIT_STOP_VOQ BIT(12) 5053 #define BIT_STOP_VIQ BIT(11) 5054 #define BIT_STOP_BEQ BIT(10) 5055 #define BIT_STOP_BKQ BIT(9) 5056 #define BIT_STOP_RXQ BIT(8) 5057 #define BIT_STOP_HI7Q BIT(7) 5058 #define BIT_STOP_HI6Q BIT(6) 5059 #define BIT_STOP_HI5Q BIT(5) 5060 #define BIT_STOP_HI4Q BIT(4) 5061 #define BIT_STOP_HI3Q BIT(3) 5062 #define BIT_STOP_HI2Q BIT(2) 5063 #define BIT_STOP_HI1Q BIT(1) 5064 5065 #define BIT_SHIFT_R_C2H_STR_ADDR 0 5066 #define BIT_MASK_R_C2H_STR_ADDR 0xffff 5067 #define BIT_R_C2H_STR_ADDR(x) \ 5068 (((x) & BIT_MASK_R_C2H_STR_ADDR) << BIT_SHIFT_R_C2H_STR_ADDR) 5069 #define BIT_GET_R_C2H_STR_ADDR(x) \ 5070 (((x) >> BIT_SHIFT_R_C2H_STR_ADDR) & BIT_MASK_R_C2H_STR_ADDR) 5071 5072 #define BIT_STOP_HI0Q BIT(0) 5073 5074 /* 2 REG_FWFF_C2H (Offset 0x0298) */ 5075 5076 #define BIT_SHIFT_C2H_DMA_ADDR 0 5077 #define BIT_MASK_C2H_DMA_ADDR 0x3ffff 5078 #define BIT_C2H_DMA_ADDR(x) \ 5079 (((x) & BIT_MASK_C2H_DMA_ADDR) << BIT_SHIFT_C2H_DMA_ADDR) 5080 #define BIT_GET_C2H_DMA_ADDR(x) \ 5081 (((x) >> BIT_SHIFT_C2H_DMA_ADDR) & BIT_MASK_C2H_DMA_ADDR) 5082 5083 /* 2 REG_FWFF_CTRL (Offset 0x029C) */ 5084 5085 #define BIT_FWFF_DMAPKT_REQ BIT(31) 5086 5087 #define BIT_SHIFT_FWFF_DMA_PKT_NUM 16 5088 #define BIT_MASK_FWFF_DMA_PKT_NUM 0xff 5089 #define BIT_FWFF_DMA_PKT_NUM(x) \ 5090 (((x) & BIT_MASK_FWFF_DMA_PKT_NUM) << BIT_SHIFT_FWFF_DMA_PKT_NUM) 5091 #define BIT_GET_FWFF_DMA_PKT_NUM(x) \ 5092 (((x) >> BIT_SHIFT_FWFF_DMA_PKT_NUM) & BIT_MASK_FWFF_DMA_PKT_NUM) 5093 5094 #define BIT_SHIFT_FWFF_STR_ADDR 0 5095 #define BIT_MASK_FWFF_STR_ADDR 0xffff 5096 #define BIT_FWFF_STR_ADDR(x) \ 5097 (((x) & BIT_MASK_FWFF_STR_ADDR) << BIT_SHIFT_FWFF_STR_ADDR) 5098 #define BIT_GET_FWFF_STR_ADDR(x) \ 5099 (((x) >> BIT_SHIFT_FWFF_STR_ADDR) & BIT_MASK_FWFF_STR_ADDR) 5100 5101 /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ 5102 5103 #define BIT_SHIFT_FWFF_PKT_QUEUED 16 5104 #define BIT_MASK_FWFF_PKT_QUEUED 0xff 5105 #define BIT_FWFF_PKT_QUEUED(x) \ 5106 (((x) & BIT_MASK_FWFF_PKT_QUEUED) << BIT_SHIFT_FWFF_PKT_QUEUED) 5107 #define BIT_GET_FWFF_PKT_QUEUED(x) \ 5108 (((x) >> BIT_SHIFT_FWFF_PKT_QUEUED) & BIT_MASK_FWFF_PKT_QUEUED) 5109 5110 /* 2 REG_FWFF_PKT_INFO (Offset 0x02A0) */ 5111 5112 #define BIT_SHIFT_FWFF_PKT_STR_ADDR 0 5113 #define BIT_MASK_FWFF_PKT_STR_ADDR 0xffff 5114 #define BIT_FWFF_PKT_STR_ADDR(x) \ 5115 (((x) & BIT_MASK_FWFF_PKT_STR_ADDR) << BIT_SHIFT_FWFF_PKT_STR_ADDR) 5116 #define BIT_GET_FWFF_PKT_STR_ADDR(x) \ 5117 (((x) >> BIT_SHIFT_FWFF_PKT_STR_ADDR) & BIT_MASK_FWFF_PKT_STR_ADDR) 5118 5119 /* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5120 5121 #define BIT_PCIEIO_PERSTB_SEL BIT(31) 5122 5123 /* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5124 5125 #define BIT_SHIFT_PCIE_MAX_RXDMA 28 5126 #define BIT_MASK_PCIE_MAX_RXDMA 0x7 5127 #define BIT_PCIE_MAX_RXDMA(x) \ 5128 (((x) & BIT_MASK_PCIE_MAX_RXDMA) << BIT_SHIFT_PCIE_MAX_RXDMA) 5129 #define BIT_GET_PCIE_MAX_RXDMA(x) \ 5130 (((x) >> BIT_SHIFT_PCIE_MAX_RXDMA) & BIT_MASK_PCIE_MAX_RXDMA) 5131 5132 /* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5133 5134 #define BIT_SHIFT_PCIE_MAX_TXDMA 24 5135 #define BIT_MASK_PCIE_MAX_TXDMA 0x7 5136 #define BIT_PCIE_MAX_TXDMA(x) \ 5137 (((x) & BIT_MASK_PCIE_MAX_TXDMA) << BIT_SHIFT_PCIE_MAX_TXDMA) 5138 #define BIT_GET_PCIE_MAX_TXDMA(x) \ 5139 (((x) >> BIT_SHIFT_PCIE_MAX_TXDMA) & BIT_MASK_PCIE_MAX_TXDMA) 5140 5141 /* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5142 5143 #define BIT_PCIE_RST_TRXDMA_INTF BIT(20) 5144 5145 /* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5146 5147 #define BIT_PCIE_EN_SWENT_L23 BIT(17) 5148 5149 /* 2 REG_PCIE_CTRL (Offset 0x0300) */ 5150 5151 #define BIT_PCIE_EN_HWEXT_L1 BIT(16) 5152 5153 /* 2 REG_INT_MIG (Offset 0x0304) */ 5154 5155 #define BIT_SHIFT_TXTTIMER_MATCH_NUM 28 5156 #define BIT_MASK_TXTTIMER_MATCH_NUM 0xf 5157 #define BIT_TXTTIMER_MATCH_NUM(x) \ 5158 (((x) & BIT_MASK_TXTTIMER_MATCH_NUM) << BIT_SHIFT_TXTTIMER_MATCH_NUM) 5159 #define BIT_GET_TXTTIMER_MATCH_NUM(x) \ 5160 (((x) >> BIT_SHIFT_TXTTIMER_MATCH_NUM) & BIT_MASK_TXTTIMER_MATCH_NUM) 5161 5162 #define BIT_SHIFT_TXPKT_NUM_MATCH 24 5163 #define BIT_MASK_TXPKT_NUM_MATCH 0xf 5164 #define BIT_TXPKT_NUM_MATCH(x) \ 5165 (((x) & BIT_MASK_TXPKT_NUM_MATCH) << BIT_SHIFT_TXPKT_NUM_MATCH) 5166 #define BIT_GET_TXPKT_NUM_MATCH(x) \ 5167 (((x) >> BIT_SHIFT_TXPKT_NUM_MATCH) & BIT_MASK_TXPKT_NUM_MATCH) 5168 5169 #define BIT_SHIFT_RXTTIMER_MATCH_NUM 20 5170 #define BIT_MASK_RXTTIMER_MATCH_NUM 0xf 5171 #define BIT_RXTTIMER_MATCH_NUM(x) \ 5172 (((x) & BIT_MASK_RXTTIMER_MATCH_NUM) << BIT_SHIFT_RXTTIMER_MATCH_NUM) 5173 #define BIT_GET_RXTTIMER_MATCH_NUM(x) \ 5174 (((x) >> BIT_SHIFT_RXTTIMER_MATCH_NUM) & BIT_MASK_RXTTIMER_MATCH_NUM) 5175 5176 #define BIT_SHIFT_RXPKT_NUM_MATCH 16 5177 #define BIT_MASK_RXPKT_NUM_MATCH 0xf 5178 #define BIT_RXPKT_NUM_MATCH(x) \ 5179 (((x) & BIT_MASK_RXPKT_NUM_MATCH) << BIT_SHIFT_RXPKT_NUM_MATCH) 5180 #define BIT_GET_RXPKT_NUM_MATCH(x) \ 5181 (((x) >> BIT_SHIFT_RXPKT_NUM_MATCH) & BIT_MASK_RXPKT_NUM_MATCH) 5182 5183 #define BIT_SHIFT_MIGRATE_TIMER 0 5184 #define BIT_MASK_MIGRATE_TIMER 0xffff 5185 #define BIT_MIGRATE_TIMER(x) \ 5186 (((x) & BIT_MASK_MIGRATE_TIMER) << BIT_SHIFT_MIGRATE_TIMER) 5187 #define BIT_GET_MIGRATE_TIMER(x) \ 5188 (((x) >> BIT_SHIFT_MIGRATE_TIMER) & BIT_MASK_MIGRATE_TIMER) 5189 5190 /* 2 REG_BCNQ_TXBD_DESA (Offset 0x0308) */ 5191 5192 #define BIT_SHIFT_BCNQ_TXBD_DESA 0 5193 #define BIT_MASK_BCNQ_TXBD_DESA 0xffffffffffffffffL 5194 #define BIT_BCNQ_TXBD_DESA(x) \ 5195 (((x) & BIT_MASK_BCNQ_TXBD_DESA) << BIT_SHIFT_BCNQ_TXBD_DESA) 5196 #define BIT_GET_BCNQ_TXBD_DESA(x) \ 5197 (((x) >> BIT_SHIFT_BCNQ_TXBD_DESA) & BIT_MASK_BCNQ_TXBD_DESA) 5198 5199 /* 2 REG_MGQ_TXBD_DESA (Offset 0x0310) */ 5200 5201 #define BIT_SHIFT_MGQ_TXBD_DESA 0 5202 #define BIT_MASK_MGQ_TXBD_DESA 0xffffffffffffffffL 5203 #define BIT_MGQ_TXBD_DESA(x) \ 5204 (((x) & BIT_MASK_MGQ_TXBD_DESA) << BIT_SHIFT_MGQ_TXBD_DESA) 5205 #define BIT_GET_MGQ_TXBD_DESA(x) \ 5206 (((x) >> BIT_SHIFT_MGQ_TXBD_DESA) & BIT_MASK_MGQ_TXBD_DESA) 5207 5208 /* 2 REG_VOQ_TXBD_DESA (Offset 0x0318) */ 5209 5210 #define BIT_SHIFT_VOQ_TXBD_DESA 0 5211 #define BIT_MASK_VOQ_TXBD_DESA 0xffffffffffffffffL 5212 #define BIT_VOQ_TXBD_DESA(x) \ 5213 (((x) & BIT_MASK_VOQ_TXBD_DESA) << BIT_SHIFT_VOQ_TXBD_DESA) 5214 #define BIT_GET_VOQ_TXBD_DESA(x) \ 5215 (((x) >> BIT_SHIFT_VOQ_TXBD_DESA) & BIT_MASK_VOQ_TXBD_DESA) 5216 5217 /* 2 REG_VIQ_TXBD_DESA (Offset 0x0320) */ 5218 5219 #define BIT_SHIFT_VIQ_TXBD_DESA 0 5220 #define BIT_MASK_VIQ_TXBD_DESA 0xffffffffffffffffL 5221 #define BIT_VIQ_TXBD_DESA(x) \ 5222 (((x) & BIT_MASK_VIQ_TXBD_DESA) << BIT_SHIFT_VIQ_TXBD_DESA) 5223 #define BIT_GET_VIQ_TXBD_DESA(x) \ 5224 (((x) >> BIT_SHIFT_VIQ_TXBD_DESA) & BIT_MASK_VIQ_TXBD_DESA) 5225 5226 /* 2 REG_BEQ_TXBD_DESA (Offset 0x0328) */ 5227 5228 #define BIT_SHIFT_BEQ_TXBD_DESA 0 5229 #define BIT_MASK_BEQ_TXBD_DESA 0xffffffffffffffffL 5230 #define BIT_BEQ_TXBD_DESA(x) \ 5231 (((x) & BIT_MASK_BEQ_TXBD_DESA) << BIT_SHIFT_BEQ_TXBD_DESA) 5232 #define BIT_GET_BEQ_TXBD_DESA(x) \ 5233 (((x) >> BIT_SHIFT_BEQ_TXBD_DESA) & BIT_MASK_BEQ_TXBD_DESA) 5234 5235 /* 2 REG_BKQ_TXBD_DESA (Offset 0x0330) */ 5236 5237 #define BIT_SHIFT_BKQ_TXBD_DESA 0 5238 #define BIT_MASK_BKQ_TXBD_DESA 0xffffffffffffffffL 5239 #define BIT_BKQ_TXBD_DESA(x) \ 5240 (((x) & BIT_MASK_BKQ_TXBD_DESA) << BIT_SHIFT_BKQ_TXBD_DESA) 5241 #define BIT_GET_BKQ_TXBD_DESA(x) \ 5242 (((x) >> BIT_SHIFT_BKQ_TXBD_DESA) & BIT_MASK_BKQ_TXBD_DESA) 5243 5244 /* 2 REG_RXQ_RXBD_DESA (Offset 0x0338) */ 5245 5246 #define BIT_SHIFT_RXQ_RXBD_DESA 0 5247 #define BIT_MASK_RXQ_RXBD_DESA 0xffffffffffffffffL 5248 #define BIT_RXQ_RXBD_DESA(x) \ 5249 (((x) & BIT_MASK_RXQ_RXBD_DESA) << BIT_SHIFT_RXQ_RXBD_DESA) 5250 #define BIT_GET_RXQ_RXBD_DESA(x) \ 5251 (((x) >> BIT_SHIFT_RXQ_RXBD_DESA) & BIT_MASK_RXQ_RXBD_DESA) 5252 5253 /* 2 REG_HI0Q_TXBD_DESA (Offset 0x0340) */ 5254 5255 #define BIT_SHIFT_HI0Q_TXBD_DESA 0 5256 #define BIT_MASK_HI0Q_TXBD_DESA 0xffffffffffffffffL 5257 #define BIT_HI0Q_TXBD_DESA(x) \ 5258 (((x) & BIT_MASK_HI0Q_TXBD_DESA) << BIT_SHIFT_HI0Q_TXBD_DESA) 5259 #define BIT_GET_HI0Q_TXBD_DESA(x) \ 5260 (((x) >> BIT_SHIFT_HI0Q_TXBD_DESA) & BIT_MASK_HI0Q_TXBD_DESA) 5261 5262 /* 2 REG_HI1Q_TXBD_DESA (Offset 0x0348) */ 5263 5264 #define BIT_SHIFT_HI1Q_TXBD_DESA 0 5265 #define BIT_MASK_HI1Q_TXBD_DESA 0xffffffffffffffffL 5266 #define BIT_HI1Q_TXBD_DESA(x) \ 5267 (((x) & BIT_MASK_HI1Q_TXBD_DESA) << BIT_SHIFT_HI1Q_TXBD_DESA) 5268 #define BIT_GET_HI1Q_TXBD_DESA(x) \ 5269 (((x) >> BIT_SHIFT_HI1Q_TXBD_DESA) & BIT_MASK_HI1Q_TXBD_DESA) 5270 5271 /* 2 REG_HI2Q_TXBD_DESA (Offset 0x0350) */ 5272 5273 #define BIT_SHIFT_HI2Q_TXBD_DESA 0 5274 #define BIT_MASK_HI2Q_TXBD_DESA 0xffffffffffffffffL 5275 #define BIT_HI2Q_TXBD_DESA(x) \ 5276 (((x) & BIT_MASK_HI2Q_TXBD_DESA) << BIT_SHIFT_HI2Q_TXBD_DESA) 5277 #define BIT_GET_HI2Q_TXBD_DESA(x) \ 5278 (((x) >> BIT_SHIFT_HI2Q_TXBD_DESA) & BIT_MASK_HI2Q_TXBD_DESA) 5279 5280 /* 2 REG_HI3Q_TXBD_DESA (Offset 0x0358) */ 5281 5282 #define BIT_SHIFT_HI3Q_TXBD_DESA 0 5283 #define BIT_MASK_HI3Q_TXBD_DESA 0xffffffffffffffffL 5284 #define BIT_HI3Q_TXBD_DESA(x) \ 5285 (((x) & BIT_MASK_HI3Q_TXBD_DESA) << BIT_SHIFT_HI3Q_TXBD_DESA) 5286 #define BIT_GET_HI3Q_TXBD_DESA(x) \ 5287 (((x) >> BIT_SHIFT_HI3Q_TXBD_DESA) & BIT_MASK_HI3Q_TXBD_DESA) 5288 5289 /* 2 REG_HI4Q_TXBD_DESA (Offset 0x0360) */ 5290 5291 #define BIT_SHIFT_HI4Q_TXBD_DESA 0 5292 #define BIT_MASK_HI4Q_TXBD_DESA 0xffffffffffffffffL 5293 #define BIT_HI4Q_TXBD_DESA(x) \ 5294 (((x) & BIT_MASK_HI4Q_TXBD_DESA) << BIT_SHIFT_HI4Q_TXBD_DESA) 5295 #define BIT_GET_HI4Q_TXBD_DESA(x) \ 5296 (((x) >> BIT_SHIFT_HI4Q_TXBD_DESA) & BIT_MASK_HI4Q_TXBD_DESA) 5297 5298 /* 2 REG_HI5Q_TXBD_DESA (Offset 0x0368) */ 5299 5300 #define BIT_SHIFT_HI5Q_TXBD_DESA 0 5301 #define BIT_MASK_HI5Q_TXBD_DESA 0xffffffffffffffffL 5302 #define BIT_HI5Q_TXBD_DESA(x) \ 5303 (((x) & BIT_MASK_HI5Q_TXBD_DESA) << BIT_SHIFT_HI5Q_TXBD_DESA) 5304 #define BIT_GET_HI5Q_TXBD_DESA(x) \ 5305 (((x) >> BIT_SHIFT_HI5Q_TXBD_DESA) & BIT_MASK_HI5Q_TXBD_DESA) 5306 5307 /* 2 REG_HI6Q_TXBD_DESA (Offset 0x0370) */ 5308 5309 #define BIT_SHIFT_HI6Q_TXBD_DESA 0 5310 #define BIT_MASK_HI6Q_TXBD_DESA 0xffffffffffffffffL 5311 #define BIT_HI6Q_TXBD_DESA(x) \ 5312 (((x) & BIT_MASK_HI6Q_TXBD_DESA) << BIT_SHIFT_HI6Q_TXBD_DESA) 5313 #define BIT_GET_HI6Q_TXBD_DESA(x) \ 5314 (((x) >> BIT_SHIFT_HI6Q_TXBD_DESA) & BIT_MASK_HI6Q_TXBD_DESA) 5315 5316 /* 2 REG_HI7Q_TXBD_DESA (Offset 0x0378) */ 5317 5318 #define BIT_SHIFT_HI7Q_TXBD_DESA 0 5319 #define BIT_MASK_HI7Q_TXBD_DESA 0xffffffffffffffffL 5320 #define BIT_HI7Q_TXBD_DESA(x) \ 5321 (((x) & BIT_MASK_HI7Q_TXBD_DESA) << BIT_SHIFT_HI7Q_TXBD_DESA) 5322 #define BIT_GET_HI7Q_TXBD_DESA(x) \ 5323 (((x) >> BIT_SHIFT_HI7Q_TXBD_DESA) & BIT_MASK_HI7Q_TXBD_DESA) 5324 5325 /* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ 5326 5327 #define BIT_PCIE_MGQ_FLAG BIT(14) 5328 5329 /* 2 REG_MGQ_TXBD_NUM (Offset 0x0380) */ 5330 5331 #define BIT_SHIFT_MGQ_DESC_MODE 12 5332 #define BIT_MASK_MGQ_DESC_MODE 0x3 5333 #define BIT_MGQ_DESC_MODE(x) \ 5334 (((x) & BIT_MASK_MGQ_DESC_MODE) << BIT_SHIFT_MGQ_DESC_MODE) 5335 #define BIT_GET_MGQ_DESC_MODE(x) \ 5336 (((x) >> BIT_SHIFT_MGQ_DESC_MODE) & BIT_MASK_MGQ_DESC_MODE) 5337 5338 #define BIT_SHIFT_MGQ_DESC_NUM 0 5339 #define BIT_MASK_MGQ_DESC_NUM 0xfff 5340 #define BIT_MGQ_DESC_NUM(x) \ 5341 (((x) & BIT_MASK_MGQ_DESC_NUM) << BIT_SHIFT_MGQ_DESC_NUM) 5342 #define BIT_GET_MGQ_DESC_NUM(x) \ 5343 (((x) >> BIT_SHIFT_MGQ_DESC_NUM) & BIT_MASK_MGQ_DESC_NUM) 5344 5345 /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ 5346 5347 #define BIT_SYS_32_64 BIT(15) 5348 5349 #define BIT_SHIFT_BCNQ_DESC_MODE 13 5350 #define BIT_MASK_BCNQ_DESC_MODE 0x3 5351 #define BIT_BCNQ_DESC_MODE(x) \ 5352 (((x) & BIT_MASK_BCNQ_DESC_MODE) << BIT_SHIFT_BCNQ_DESC_MODE) 5353 #define BIT_GET_BCNQ_DESC_MODE(x) \ 5354 (((x) >> BIT_SHIFT_BCNQ_DESC_MODE) & BIT_MASK_BCNQ_DESC_MODE) 5355 5356 /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ 5357 5358 #define BIT_PCIE_BCNQ_FLAG BIT(12) 5359 5360 /* 2 REG_RX_RXBD_NUM (Offset 0x0382) */ 5361 5362 #define BIT_SHIFT_RXQ_DESC_NUM 0 5363 #define BIT_MASK_RXQ_DESC_NUM 0xfff 5364 #define BIT_RXQ_DESC_NUM(x) \ 5365 (((x) & BIT_MASK_RXQ_DESC_NUM) << BIT_SHIFT_RXQ_DESC_NUM) 5366 #define BIT_GET_RXQ_DESC_NUM(x) \ 5367 (((x) >> BIT_SHIFT_RXQ_DESC_NUM) & BIT_MASK_RXQ_DESC_NUM) 5368 5369 /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ 5370 5371 #define BIT_PCIE_VOQ_FLAG BIT(14) 5372 5373 /* 2 REG_VOQ_TXBD_NUM (Offset 0x0384) */ 5374 5375 #define BIT_SHIFT_VOQ_DESC_MODE 12 5376 #define BIT_MASK_VOQ_DESC_MODE 0x3 5377 #define BIT_VOQ_DESC_MODE(x) \ 5378 (((x) & BIT_MASK_VOQ_DESC_MODE) << BIT_SHIFT_VOQ_DESC_MODE) 5379 #define BIT_GET_VOQ_DESC_MODE(x) \ 5380 (((x) >> BIT_SHIFT_VOQ_DESC_MODE) & BIT_MASK_VOQ_DESC_MODE) 5381 5382 #define BIT_SHIFT_VOQ_DESC_NUM 0 5383 #define BIT_MASK_VOQ_DESC_NUM 0xfff 5384 #define BIT_VOQ_DESC_NUM(x) \ 5385 (((x) & BIT_MASK_VOQ_DESC_NUM) << BIT_SHIFT_VOQ_DESC_NUM) 5386 #define BIT_GET_VOQ_DESC_NUM(x) \ 5387 (((x) >> BIT_SHIFT_VOQ_DESC_NUM) & BIT_MASK_VOQ_DESC_NUM) 5388 5389 /* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ 5390 5391 #define BIT_PCIE_VIQ_FLAG BIT(14) 5392 5393 /* 2 REG_VIQ_TXBD_NUM (Offset 0x0386) */ 5394 5395 #define BIT_SHIFT_VIQ_DESC_MODE 12 5396 #define BIT_MASK_VIQ_DESC_MODE 0x3 5397 #define BIT_VIQ_DESC_MODE(x) \ 5398 (((x) & BIT_MASK_VIQ_DESC_MODE) << BIT_SHIFT_VIQ_DESC_MODE) 5399 #define BIT_GET_VIQ_DESC_MODE(x) \ 5400 (((x) >> BIT_SHIFT_VIQ_DESC_MODE) & BIT_MASK_VIQ_DESC_MODE) 5401 5402 #define BIT_SHIFT_VIQ_DESC_NUM 0 5403 #define BIT_MASK_VIQ_DESC_NUM 0xfff 5404 #define BIT_VIQ_DESC_NUM(x) \ 5405 (((x) & BIT_MASK_VIQ_DESC_NUM) << BIT_SHIFT_VIQ_DESC_NUM) 5406 #define BIT_GET_VIQ_DESC_NUM(x) \ 5407 (((x) >> BIT_SHIFT_VIQ_DESC_NUM) & BIT_MASK_VIQ_DESC_NUM) 5408 5409 /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ 5410 5411 #define BIT_PCIE_BEQ_FLAG BIT(14) 5412 5413 /* 2 REG_BEQ_TXBD_NUM (Offset 0x0388) */ 5414 5415 #define BIT_SHIFT_BEQ_DESC_MODE 12 5416 #define BIT_MASK_BEQ_DESC_MODE 0x3 5417 #define BIT_BEQ_DESC_MODE(x) \ 5418 (((x) & BIT_MASK_BEQ_DESC_MODE) << BIT_SHIFT_BEQ_DESC_MODE) 5419 #define BIT_GET_BEQ_DESC_MODE(x) \ 5420 (((x) >> BIT_SHIFT_BEQ_DESC_MODE) & BIT_MASK_BEQ_DESC_MODE) 5421 5422 #define BIT_SHIFT_BEQ_DESC_NUM 0 5423 #define BIT_MASK_BEQ_DESC_NUM 0xfff 5424 #define BIT_BEQ_DESC_NUM(x) \ 5425 (((x) & BIT_MASK_BEQ_DESC_NUM) << BIT_SHIFT_BEQ_DESC_NUM) 5426 #define BIT_GET_BEQ_DESC_NUM(x) \ 5427 (((x) >> BIT_SHIFT_BEQ_DESC_NUM) & BIT_MASK_BEQ_DESC_NUM) 5428 5429 /* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ 5430 5431 #define BIT_PCIE_BKQ_FLAG BIT(14) 5432 5433 /* 2 REG_BKQ_TXBD_NUM (Offset 0x038A) */ 5434 5435 #define BIT_SHIFT_BKQ_DESC_MODE 12 5436 #define BIT_MASK_BKQ_DESC_MODE 0x3 5437 #define BIT_BKQ_DESC_MODE(x) \ 5438 (((x) & BIT_MASK_BKQ_DESC_MODE) << BIT_SHIFT_BKQ_DESC_MODE) 5439 #define BIT_GET_BKQ_DESC_MODE(x) \ 5440 (((x) >> BIT_SHIFT_BKQ_DESC_MODE) & BIT_MASK_BKQ_DESC_MODE) 5441 5442 #define BIT_SHIFT_BKQ_DESC_NUM 0 5443 #define BIT_MASK_BKQ_DESC_NUM 0xfff 5444 #define BIT_BKQ_DESC_NUM(x) \ 5445 (((x) & BIT_MASK_BKQ_DESC_NUM) << BIT_SHIFT_BKQ_DESC_NUM) 5446 #define BIT_GET_BKQ_DESC_NUM(x) \ 5447 (((x) >> BIT_SHIFT_BKQ_DESC_NUM) & BIT_MASK_BKQ_DESC_NUM) 5448 5449 /* 2 REG_HI0Q_TXBD_NUM (Offset 0x038C) */ 5450 5451 #define BIT_HI0Q_FLAG BIT(14) 5452 5453 #define BIT_SHIFT_HI0Q_DESC_MODE 12 5454 #define BIT_MASK_HI0Q_DESC_MODE 0x3 5455 #define BIT_HI0Q_DESC_MODE(x) \ 5456 (((x) & BIT_MASK_HI0Q_DESC_MODE) << BIT_SHIFT_HI0Q_DESC_MODE) 5457 #define BIT_GET_HI0Q_DESC_MODE(x) \ 5458 (((x) >> BIT_SHIFT_HI0Q_DESC_MODE) & BIT_MASK_HI0Q_DESC_MODE) 5459 5460 #define BIT_SHIFT_HI0Q_DESC_NUM 0 5461 #define BIT_MASK_HI0Q_DESC_NUM 0xfff 5462 #define BIT_HI0Q_DESC_NUM(x) \ 5463 (((x) & BIT_MASK_HI0Q_DESC_NUM) << BIT_SHIFT_HI0Q_DESC_NUM) 5464 #define BIT_GET_HI0Q_DESC_NUM(x) \ 5465 (((x) >> BIT_SHIFT_HI0Q_DESC_NUM) & BIT_MASK_HI0Q_DESC_NUM) 5466 5467 /* 2 REG_HI1Q_TXBD_NUM (Offset 0x038E) */ 5468 5469 #define BIT_HI1Q_FLAG BIT(14) 5470 5471 #define BIT_SHIFT_HI1Q_DESC_MODE 12 5472 #define BIT_MASK_HI1Q_DESC_MODE 0x3 5473 #define BIT_HI1Q_DESC_MODE(x) \ 5474 (((x) & BIT_MASK_HI1Q_DESC_MODE) << BIT_SHIFT_HI1Q_DESC_MODE) 5475 #define BIT_GET_HI1Q_DESC_MODE(x) \ 5476 (((x) >> BIT_SHIFT_HI1Q_DESC_MODE) & BIT_MASK_HI1Q_DESC_MODE) 5477 5478 #define BIT_SHIFT_HI1Q_DESC_NUM 0 5479 #define BIT_MASK_HI1Q_DESC_NUM 0xfff 5480 #define BIT_HI1Q_DESC_NUM(x) \ 5481 (((x) & BIT_MASK_HI1Q_DESC_NUM) << BIT_SHIFT_HI1Q_DESC_NUM) 5482 #define BIT_GET_HI1Q_DESC_NUM(x) \ 5483 (((x) >> BIT_SHIFT_HI1Q_DESC_NUM) & BIT_MASK_HI1Q_DESC_NUM) 5484 5485 /* 2 REG_HI2Q_TXBD_NUM (Offset 0x0390) */ 5486 5487 #define BIT_HI2Q_FLAG BIT(14) 5488 5489 #define BIT_SHIFT_HI2Q_DESC_MODE 12 5490 #define BIT_MASK_HI2Q_DESC_MODE 0x3 5491 #define BIT_HI2Q_DESC_MODE(x) \ 5492 (((x) & BIT_MASK_HI2Q_DESC_MODE) << BIT_SHIFT_HI2Q_DESC_MODE) 5493 #define BIT_GET_HI2Q_DESC_MODE(x) \ 5494 (((x) >> BIT_SHIFT_HI2Q_DESC_MODE) & BIT_MASK_HI2Q_DESC_MODE) 5495 5496 #define BIT_SHIFT_HI2Q_DESC_NUM 0 5497 #define BIT_MASK_HI2Q_DESC_NUM 0xfff 5498 #define BIT_HI2Q_DESC_NUM(x) \ 5499 (((x) & BIT_MASK_HI2Q_DESC_NUM) << BIT_SHIFT_HI2Q_DESC_NUM) 5500 #define BIT_GET_HI2Q_DESC_NUM(x) \ 5501 (((x) >> BIT_SHIFT_HI2Q_DESC_NUM) & BIT_MASK_HI2Q_DESC_NUM) 5502 5503 /* 2 REG_HI3Q_TXBD_NUM (Offset 0x0392) */ 5504 5505 #define BIT_HI3Q_FLAG BIT(14) 5506 5507 #define BIT_SHIFT_HI3Q_DESC_MODE 12 5508 #define BIT_MASK_HI3Q_DESC_MODE 0x3 5509 #define BIT_HI3Q_DESC_MODE(x) \ 5510 (((x) & BIT_MASK_HI3Q_DESC_MODE) << BIT_SHIFT_HI3Q_DESC_MODE) 5511 #define BIT_GET_HI3Q_DESC_MODE(x) \ 5512 (((x) >> BIT_SHIFT_HI3Q_DESC_MODE) & BIT_MASK_HI3Q_DESC_MODE) 5513 5514 #define BIT_SHIFT_HI3Q_DESC_NUM 0 5515 #define BIT_MASK_HI3Q_DESC_NUM 0xfff 5516 #define BIT_HI3Q_DESC_NUM(x) \ 5517 (((x) & BIT_MASK_HI3Q_DESC_NUM) << BIT_SHIFT_HI3Q_DESC_NUM) 5518 #define BIT_GET_HI3Q_DESC_NUM(x) \ 5519 (((x) >> BIT_SHIFT_HI3Q_DESC_NUM) & BIT_MASK_HI3Q_DESC_NUM) 5520 5521 /* 2 REG_HI4Q_TXBD_NUM (Offset 0x0394) */ 5522 5523 #define BIT_HI4Q_FLAG BIT(14) 5524 5525 #define BIT_SHIFT_HI4Q_DESC_MODE 12 5526 #define BIT_MASK_HI4Q_DESC_MODE 0x3 5527 #define BIT_HI4Q_DESC_MODE(x) \ 5528 (((x) & BIT_MASK_HI4Q_DESC_MODE) << BIT_SHIFT_HI4Q_DESC_MODE) 5529 #define BIT_GET_HI4Q_DESC_MODE(x) \ 5530 (((x) >> BIT_SHIFT_HI4Q_DESC_MODE) & BIT_MASK_HI4Q_DESC_MODE) 5531 5532 #define BIT_SHIFT_HI4Q_DESC_NUM 0 5533 #define BIT_MASK_HI4Q_DESC_NUM 0xfff 5534 #define BIT_HI4Q_DESC_NUM(x) \ 5535 (((x) & BIT_MASK_HI4Q_DESC_NUM) << BIT_SHIFT_HI4Q_DESC_NUM) 5536 #define BIT_GET_HI4Q_DESC_NUM(x) \ 5537 (((x) >> BIT_SHIFT_HI4Q_DESC_NUM) & BIT_MASK_HI4Q_DESC_NUM) 5538 5539 /* 2 REG_HI5Q_TXBD_NUM (Offset 0x0396) */ 5540 5541 #define BIT_HI5Q_FLAG BIT(14) 5542 5543 #define BIT_SHIFT_HI5Q_DESC_MODE 12 5544 #define BIT_MASK_HI5Q_DESC_MODE 0x3 5545 #define BIT_HI5Q_DESC_MODE(x) \ 5546 (((x) & BIT_MASK_HI5Q_DESC_MODE) << BIT_SHIFT_HI5Q_DESC_MODE) 5547 #define BIT_GET_HI5Q_DESC_MODE(x) \ 5548 (((x) >> BIT_SHIFT_HI5Q_DESC_MODE) & BIT_MASK_HI5Q_DESC_MODE) 5549 5550 #define BIT_SHIFT_HI5Q_DESC_NUM 0 5551 #define BIT_MASK_HI5Q_DESC_NUM 0xfff 5552 #define BIT_HI5Q_DESC_NUM(x) \ 5553 (((x) & BIT_MASK_HI5Q_DESC_NUM) << BIT_SHIFT_HI5Q_DESC_NUM) 5554 #define BIT_GET_HI5Q_DESC_NUM(x) \ 5555 (((x) >> BIT_SHIFT_HI5Q_DESC_NUM) & BIT_MASK_HI5Q_DESC_NUM) 5556 5557 /* 2 REG_HI6Q_TXBD_NUM (Offset 0x0398) */ 5558 5559 #define BIT_HI6Q_FLAG BIT(14) 5560 5561 #define BIT_SHIFT_HI6Q_DESC_MODE 12 5562 #define BIT_MASK_HI6Q_DESC_MODE 0x3 5563 #define BIT_HI6Q_DESC_MODE(x) \ 5564 (((x) & BIT_MASK_HI6Q_DESC_MODE) << BIT_SHIFT_HI6Q_DESC_MODE) 5565 #define BIT_GET_HI6Q_DESC_MODE(x) \ 5566 (((x) >> BIT_SHIFT_HI6Q_DESC_MODE) & BIT_MASK_HI6Q_DESC_MODE) 5567 5568 #define BIT_SHIFT_HI6Q_DESC_NUM 0 5569 #define BIT_MASK_HI6Q_DESC_NUM 0xfff 5570 #define BIT_HI6Q_DESC_NUM(x) \ 5571 (((x) & BIT_MASK_HI6Q_DESC_NUM) << BIT_SHIFT_HI6Q_DESC_NUM) 5572 #define BIT_GET_HI6Q_DESC_NUM(x) \ 5573 (((x) >> BIT_SHIFT_HI6Q_DESC_NUM) & BIT_MASK_HI6Q_DESC_NUM) 5574 5575 /* 2 REG_HI7Q_TXBD_NUM (Offset 0x039A) */ 5576 5577 #define BIT_HI7Q_FLAG BIT(14) 5578 5579 #define BIT_SHIFT_HI7Q_DESC_MODE 12 5580 #define BIT_MASK_HI7Q_DESC_MODE 0x3 5581 #define BIT_HI7Q_DESC_MODE(x) \ 5582 (((x) & BIT_MASK_HI7Q_DESC_MODE) << BIT_SHIFT_HI7Q_DESC_MODE) 5583 #define BIT_GET_HI7Q_DESC_MODE(x) \ 5584 (((x) >> BIT_SHIFT_HI7Q_DESC_MODE) & BIT_MASK_HI7Q_DESC_MODE) 5585 5586 #define BIT_SHIFT_HI7Q_DESC_NUM 0 5587 #define BIT_MASK_HI7Q_DESC_NUM 0xfff 5588 #define BIT_HI7Q_DESC_NUM(x) \ 5589 (((x) & BIT_MASK_HI7Q_DESC_NUM) << BIT_SHIFT_HI7Q_DESC_NUM) 5590 #define BIT_GET_HI7Q_DESC_NUM(x) \ 5591 (((x) >> BIT_SHIFT_HI7Q_DESC_NUM) & BIT_MASK_HI7Q_DESC_NUM) 5592 5593 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5594 5595 #define BIT_CLR_HI7Q_HW_IDX BIT(29) 5596 #define BIT_CLR_HI6Q_HW_IDX BIT(28) 5597 #define BIT_CLR_HI5Q_HW_IDX BIT(27) 5598 #define BIT_CLR_HI4Q_HW_IDX BIT(26) 5599 #define BIT_CLR_HI3Q_HW_IDX BIT(25) 5600 #define BIT_CLR_HI2Q_HW_IDX BIT(24) 5601 #define BIT_CLR_HI1Q_HW_IDX BIT(23) 5602 5603 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5604 5605 #define BIT_CLR_HI0Q_HW_IDX BIT(22) 5606 5607 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5608 5609 #define BIT_CLR_BKQ_HW_IDX BIT(21) 5610 5611 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5612 5613 #define BIT_CLR_BEQ_HW_IDX BIT(20) 5614 5615 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5616 5617 #define BIT_CLR_VIQ_HW_IDX BIT(19) 5618 5619 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5620 5621 #define BIT_CLR_VOQ_HW_IDX BIT(18) 5622 5623 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5624 5625 #define BIT_CLR_MGQ_HW_IDX BIT(17) 5626 5627 /* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ 5628 5629 #define BIT_SHIFT_TSFT2_HCI 16 5630 #define BIT_MASK_TSFT2_HCI 0xffff 5631 #define BIT_TSFT2_HCI(x) (((x) & BIT_MASK_TSFT2_HCI) << BIT_SHIFT_TSFT2_HCI) 5632 #define BIT_GET_TSFT2_HCI(x) (((x) >> BIT_SHIFT_TSFT2_HCI) & BIT_MASK_TSFT2_HCI) 5633 5634 #define BIT_CLR_RXQ_HW_IDX BIT(16) 5635 5636 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5637 5638 #define BIT_CLR_HI7Q_HOST_IDX BIT(13) 5639 5640 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5641 5642 #define BIT_CLR_HI6Q_HOST_IDX BIT(12) 5643 5644 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5645 5646 #define BIT_CLR_HI5Q_HOST_IDX BIT(11) 5647 5648 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5649 5650 #define BIT_CLR_HI4Q_HOST_IDX BIT(10) 5651 5652 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5653 5654 #define BIT_CLR_HI3Q_HOST_IDX BIT(9) 5655 5656 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5657 5658 #define BIT_CLR_HI2Q_HOST_IDX BIT(8) 5659 5660 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5661 5662 #define BIT_CLR_HI1Q_HOST_IDX BIT(7) 5663 #define BIT_CLR_HI0Q_HOST_IDX BIT(6) 5664 5665 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5666 5667 #define BIT_CLR_BKQ_HOST_IDX BIT(5) 5668 5669 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5670 5671 #define BIT_CLR_BEQ_HOST_IDX BIT(4) 5672 5673 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5674 5675 #define BIT_CLR_VIQ_HOST_IDX BIT(3) 5676 5677 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5678 5679 #define BIT_CLR_VOQ_HOST_IDX BIT(2) 5680 5681 /* 2 REG_BD_RWPTR_CLR (Offset 0x039C) */ 5682 5683 #define BIT_CLR_MGQ_HOST_IDX BIT(1) 5684 5685 /* 2 REG_TSFTIMER_HCI (Offset 0x039C) */ 5686 5687 #define BIT_SHIFT_TSFT1_HCI 0 5688 #define BIT_MASK_TSFT1_HCI 0xffff 5689 #define BIT_TSFT1_HCI(x) (((x) & BIT_MASK_TSFT1_HCI) << BIT_SHIFT_TSFT1_HCI) 5690 #define BIT_GET_TSFT1_HCI(x) (((x) >> BIT_SHIFT_TSFT1_HCI) & BIT_MASK_TSFT1_HCI) 5691 5692 #define BIT_CLR_RXQ_HOST_IDX BIT(0) 5693 5694 /* 2 REG_VOQ_TXBD_IDX (Offset 0x03A0) */ 5695 5696 #define BIT_SHIFT_VOQ_HW_IDX 16 5697 #define BIT_MASK_VOQ_HW_IDX 0xfff 5698 #define BIT_VOQ_HW_IDX(x) (((x) & BIT_MASK_VOQ_HW_IDX) << BIT_SHIFT_VOQ_HW_IDX) 5699 #define BIT_GET_VOQ_HW_IDX(x) \ 5700 (((x) >> BIT_SHIFT_VOQ_HW_IDX) & BIT_MASK_VOQ_HW_IDX) 5701 5702 #define BIT_SHIFT_VOQ_HOST_IDX 0 5703 #define BIT_MASK_VOQ_HOST_IDX 0xfff 5704 #define BIT_VOQ_HOST_IDX(x) \ 5705 (((x) & BIT_MASK_VOQ_HOST_IDX) << BIT_SHIFT_VOQ_HOST_IDX) 5706 #define BIT_GET_VOQ_HOST_IDX(x) \ 5707 (((x) >> BIT_SHIFT_VOQ_HOST_IDX) & BIT_MASK_VOQ_HOST_IDX) 5708 5709 /* 2 REG_VIQ_TXBD_IDX (Offset 0x03A4) */ 5710 5711 #define BIT_SHIFT_VIQ_HW_IDX 16 5712 #define BIT_MASK_VIQ_HW_IDX 0xfff 5713 #define BIT_VIQ_HW_IDX(x) (((x) & BIT_MASK_VIQ_HW_IDX) << BIT_SHIFT_VIQ_HW_IDX) 5714 #define BIT_GET_VIQ_HW_IDX(x) \ 5715 (((x) >> BIT_SHIFT_VIQ_HW_IDX) & BIT_MASK_VIQ_HW_IDX) 5716 5717 #define BIT_SHIFT_VIQ_HOST_IDX 0 5718 #define BIT_MASK_VIQ_HOST_IDX 0xfff 5719 #define BIT_VIQ_HOST_IDX(x) \ 5720 (((x) & BIT_MASK_VIQ_HOST_IDX) << BIT_SHIFT_VIQ_HOST_IDX) 5721 #define BIT_GET_VIQ_HOST_IDX(x) \ 5722 (((x) >> BIT_SHIFT_VIQ_HOST_IDX) & BIT_MASK_VIQ_HOST_IDX) 5723 5724 /* 2 REG_BEQ_TXBD_IDX (Offset 0x03A8) */ 5725 5726 #define BIT_SHIFT_BEQ_HW_IDX 16 5727 #define BIT_MASK_BEQ_HW_IDX 0xfff 5728 #define BIT_BEQ_HW_IDX(x) (((x) & BIT_MASK_BEQ_HW_IDX) << BIT_SHIFT_BEQ_HW_IDX) 5729 #define BIT_GET_BEQ_HW_IDX(x) \ 5730 (((x) >> BIT_SHIFT_BEQ_HW_IDX) & BIT_MASK_BEQ_HW_IDX) 5731 5732 #define BIT_SHIFT_BEQ_HOST_IDX 0 5733 #define BIT_MASK_BEQ_HOST_IDX 0xfff 5734 #define BIT_BEQ_HOST_IDX(x) \ 5735 (((x) & BIT_MASK_BEQ_HOST_IDX) << BIT_SHIFT_BEQ_HOST_IDX) 5736 #define BIT_GET_BEQ_HOST_IDX(x) \ 5737 (((x) >> BIT_SHIFT_BEQ_HOST_IDX) & BIT_MASK_BEQ_HOST_IDX) 5738 5739 /* 2 REG_BKQ_TXBD_IDX (Offset 0x03AC) */ 5740 5741 #define BIT_SHIFT_BKQ_HW_IDX 16 5742 #define BIT_MASK_BKQ_HW_IDX 0xfff 5743 #define BIT_BKQ_HW_IDX(x) (((x) & BIT_MASK_BKQ_HW_IDX) << BIT_SHIFT_BKQ_HW_IDX) 5744 #define BIT_GET_BKQ_HW_IDX(x) \ 5745 (((x) >> BIT_SHIFT_BKQ_HW_IDX) & BIT_MASK_BKQ_HW_IDX) 5746 5747 #define BIT_SHIFT_BKQ_HOST_IDX 0 5748 #define BIT_MASK_BKQ_HOST_IDX 0xfff 5749 #define BIT_BKQ_HOST_IDX(x) \ 5750 (((x) & BIT_MASK_BKQ_HOST_IDX) << BIT_SHIFT_BKQ_HOST_IDX) 5751 #define BIT_GET_BKQ_HOST_IDX(x) \ 5752 (((x) >> BIT_SHIFT_BKQ_HOST_IDX) & BIT_MASK_BKQ_HOST_IDX) 5753 5754 /* 2 REG_MGQ_TXBD_IDX (Offset 0x03B0) */ 5755 5756 #define BIT_SHIFT_MGQ_HW_IDX 16 5757 #define BIT_MASK_MGQ_HW_IDX 0xfff 5758 #define BIT_MGQ_HW_IDX(x) (((x) & BIT_MASK_MGQ_HW_IDX) << BIT_SHIFT_MGQ_HW_IDX) 5759 #define BIT_GET_MGQ_HW_IDX(x) \ 5760 (((x) >> BIT_SHIFT_MGQ_HW_IDX) & BIT_MASK_MGQ_HW_IDX) 5761 5762 #define BIT_SHIFT_MGQ_HOST_IDX 0 5763 #define BIT_MASK_MGQ_HOST_IDX 0xfff 5764 #define BIT_MGQ_HOST_IDX(x) \ 5765 (((x) & BIT_MASK_MGQ_HOST_IDX) << BIT_SHIFT_MGQ_HOST_IDX) 5766 #define BIT_GET_MGQ_HOST_IDX(x) \ 5767 (((x) >> BIT_SHIFT_MGQ_HOST_IDX) & BIT_MASK_MGQ_HOST_IDX) 5768 5769 /* 2 REG_RXQ_RXBD_IDX (Offset 0x03B4) */ 5770 5771 #define BIT_SHIFT_RXQ_HW_IDX 16 5772 #define BIT_MASK_RXQ_HW_IDX 0xfff 5773 #define BIT_RXQ_HW_IDX(x) (((x) & BIT_MASK_RXQ_HW_IDX) << BIT_SHIFT_RXQ_HW_IDX) 5774 #define BIT_GET_RXQ_HW_IDX(x) \ 5775 (((x) >> BIT_SHIFT_RXQ_HW_IDX) & BIT_MASK_RXQ_HW_IDX) 5776 5777 #define BIT_SHIFT_RXQ_HOST_IDX 0 5778 #define BIT_MASK_RXQ_HOST_IDX 0xfff 5779 #define BIT_RXQ_HOST_IDX(x) \ 5780 (((x) & BIT_MASK_RXQ_HOST_IDX) << BIT_SHIFT_RXQ_HOST_IDX) 5781 #define BIT_GET_RXQ_HOST_IDX(x) \ 5782 (((x) >> BIT_SHIFT_RXQ_HOST_IDX) & BIT_MASK_RXQ_HOST_IDX) 5783 5784 /* 2 REG_HI0Q_TXBD_IDX (Offset 0x03B8) */ 5785 5786 #define BIT_SHIFT_HI0Q_HW_IDX 16 5787 #define BIT_MASK_HI0Q_HW_IDX 0xfff 5788 #define BIT_HI0Q_HW_IDX(x) \ 5789 (((x) & BIT_MASK_HI0Q_HW_IDX) << BIT_SHIFT_HI0Q_HW_IDX) 5790 #define BIT_GET_HI0Q_HW_IDX(x) \ 5791 (((x) >> BIT_SHIFT_HI0Q_HW_IDX) & BIT_MASK_HI0Q_HW_IDX) 5792 5793 #define BIT_SHIFT_HI0Q_HOST_IDX 0 5794 #define BIT_MASK_HI0Q_HOST_IDX 0xfff 5795 #define BIT_HI0Q_HOST_IDX(x) \ 5796 (((x) & BIT_MASK_HI0Q_HOST_IDX) << BIT_SHIFT_HI0Q_HOST_IDX) 5797 #define BIT_GET_HI0Q_HOST_IDX(x) \ 5798 (((x) >> BIT_SHIFT_HI0Q_HOST_IDX) & BIT_MASK_HI0Q_HOST_IDX) 5799 5800 /* 2 REG_HI1Q_TXBD_IDX (Offset 0x03BC) */ 5801 5802 #define BIT_SHIFT_HI1Q_HW_IDX 16 5803 #define BIT_MASK_HI1Q_HW_IDX 0xfff 5804 #define BIT_HI1Q_HW_IDX(x) \ 5805 (((x) & BIT_MASK_HI1Q_HW_IDX) << BIT_SHIFT_HI1Q_HW_IDX) 5806 #define BIT_GET_HI1Q_HW_IDX(x) \ 5807 (((x) >> BIT_SHIFT_HI1Q_HW_IDX) & BIT_MASK_HI1Q_HW_IDX) 5808 5809 #define BIT_SHIFT_HI1Q_HOST_IDX 0 5810 #define BIT_MASK_HI1Q_HOST_IDX 0xfff 5811 #define BIT_HI1Q_HOST_IDX(x) \ 5812 (((x) & BIT_MASK_HI1Q_HOST_IDX) << BIT_SHIFT_HI1Q_HOST_IDX) 5813 #define BIT_GET_HI1Q_HOST_IDX(x) \ 5814 (((x) >> BIT_SHIFT_HI1Q_HOST_IDX) & BIT_MASK_HI1Q_HOST_IDX) 5815 5816 /* 2 REG_HI2Q_TXBD_IDX (Offset 0x03C0) */ 5817 5818 #define BIT_SHIFT_HI2Q_HW_IDX 16 5819 #define BIT_MASK_HI2Q_HW_IDX 0xfff 5820 #define BIT_HI2Q_HW_IDX(x) \ 5821 (((x) & BIT_MASK_HI2Q_HW_IDX) << BIT_SHIFT_HI2Q_HW_IDX) 5822 #define BIT_GET_HI2Q_HW_IDX(x) \ 5823 (((x) >> BIT_SHIFT_HI2Q_HW_IDX) & BIT_MASK_HI2Q_HW_IDX) 5824 5825 #define BIT_SHIFT_HI2Q_HOST_IDX 0 5826 #define BIT_MASK_HI2Q_HOST_IDX 0xfff 5827 #define BIT_HI2Q_HOST_IDX(x) \ 5828 (((x) & BIT_MASK_HI2Q_HOST_IDX) << BIT_SHIFT_HI2Q_HOST_IDX) 5829 #define BIT_GET_HI2Q_HOST_IDX(x) \ 5830 (((x) >> BIT_SHIFT_HI2Q_HOST_IDX) & BIT_MASK_HI2Q_HOST_IDX) 5831 5832 /* 2 REG_HI3Q_TXBD_IDX (Offset 0x03C4) */ 5833 5834 #define BIT_SHIFT_HI3Q_HW_IDX 16 5835 #define BIT_MASK_HI3Q_HW_IDX 0xfff 5836 #define BIT_HI3Q_HW_IDX(x) \ 5837 (((x) & BIT_MASK_HI3Q_HW_IDX) << BIT_SHIFT_HI3Q_HW_IDX) 5838 #define BIT_GET_HI3Q_HW_IDX(x) \ 5839 (((x) >> BIT_SHIFT_HI3Q_HW_IDX) & BIT_MASK_HI3Q_HW_IDX) 5840 5841 #define BIT_SHIFT_HI3Q_HOST_IDX 0 5842 #define BIT_MASK_HI3Q_HOST_IDX 0xfff 5843 #define BIT_HI3Q_HOST_IDX(x) \ 5844 (((x) & BIT_MASK_HI3Q_HOST_IDX) << BIT_SHIFT_HI3Q_HOST_IDX) 5845 #define BIT_GET_HI3Q_HOST_IDX(x) \ 5846 (((x) >> BIT_SHIFT_HI3Q_HOST_IDX) & BIT_MASK_HI3Q_HOST_IDX) 5847 5848 /* 2 REG_HI4Q_TXBD_IDX (Offset 0x03C8) */ 5849 5850 #define BIT_SHIFT_HI4Q_HW_IDX 16 5851 #define BIT_MASK_HI4Q_HW_IDX 0xfff 5852 #define BIT_HI4Q_HW_IDX(x) \ 5853 (((x) & BIT_MASK_HI4Q_HW_IDX) << BIT_SHIFT_HI4Q_HW_IDX) 5854 #define BIT_GET_HI4Q_HW_IDX(x) \ 5855 (((x) >> BIT_SHIFT_HI4Q_HW_IDX) & BIT_MASK_HI4Q_HW_IDX) 5856 5857 #define BIT_SHIFT_HI4Q_HOST_IDX 0 5858 #define BIT_MASK_HI4Q_HOST_IDX 0xfff 5859 #define BIT_HI4Q_HOST_IDX(x) \ 5860 (((x) & BIT_MASK_HI4Q_HOST_IDX) << BIT_SHIFT_HI4Q_HOST_IDX) 5861 #define BIT_GET_HI4Q_HOST_IDX(x) \ 5862 (((x) >> BIT_SHIFT_HI4Q_HOST_IDX) & BIT_MASK_HI4Q_HOST_IDX) 5863 5864 /* 2 REG_HI5Q_TXBD_IDX (Offset 0x03CC) */ 5865 5866 #define BIT_SHIFT_HI5Q_HW_IDX 16 5867 #define BIT_MASK_HI5Q_HW_IDX 0xfff 5868 #define BIT_HI5Q_HW_IDX(x) \ 5869 (((x) & BIT_MASK_HI5Q_HW_IDX) << BIT_SHIFT_HI5Q_HW_IDX) 5870 #define BIT_GET_HI5Q_HW_IDX(x) \ 5871 (((x) >> BIT_SHIFT_HI5Q_HW_IDX) & BIT_MASK_HI5Q_HW_IDX) 5872 5873 #define BIT_SHIFT_HI5Q_HOST_IDX 0 5874 #define BIT_MASK_HI5Q_HOST_IDX 0xfff 5875 #define BIT_HI5Q_HOST_IDX(x) \ 5876 (((x) & BIT_MASK_HI5Q_HOST_IDX) << BIT_SHIFT_HI5Q_HOST_IDX) 5877 #define BIT_GET_HI5Q_HOST_IDX(x) \ 5878 (((x) >> BIT_SHIFT_HI5Q_HOST_IDX) & BIT_MASK_HI5Q_HOST_IDX) 5879 5880 /* 2 REG_HI6Q_TXBD_IDX (Offset 0x03D0) */ 5881 5882 #define BIT_SHIFT_HI6Q_HW_IDX 16 5883 #define BIT_MASK_HI6Q_HW_IDX 0xfff 5884 #define BIT_HI6Q_HW_IDX(x) \ 5885 (((x) & BIT_MASK_HI6Q_HW_IDX) << BIT_SHIFT_HI6Q_HW_IDX) 5886 #define BIT_GET_HI6Q_HW_IDX(x) \ 5887 (((x) >> BIT_SHIFT_HI6Q_HW_IDX) & BIT_MASK_HI6Q_HW_IDX) 5888 5889 #define BIT_SHIFT_HI6Q_HOST_IDX 0 5890 #define BIT_MASK_HI6Q_HOST_IDX 0xfff 5891 #define BIT_HI6Q_HOST_IDX(x) \ 5892 (((x) & BIT_MASK_HI6Q_HOST_IDX) << BIT_SHIFT_HI6Q_HOST_IDX) 5893 #define BIT_GET_HI6Q_HOST_IDX(x) \ 5894 (((x) >> BIT_SHIFT_HI6Q_HOST_IDX) & BIT_MASK_HI6Q_HOST_IDX) 5895 5896 /* 2 REG_HI7Q_TXBD_IDX (Offset 0x03D4) */ 5897 5898 #define BIT_SHIFT_HI7Q_HW_IDX 16 5899 #define BIT_MASK_HI7Q_HW_IDX 0xfff 5900 #define BIT_HI7Q_HW_IDX(x) \ 5901 (((x) & BIT_MASK_HI7Q_HW_IDX) << BIT_SHIFT_HI7Q_HW_IDX) 5902 #define BIT_GET_HI7Q_HW_IDX(x) \ 5903 (((x) >> BIT_SHIFT_HI7Q_HW_IDX) & BIT_MASK_HI7Q_HW_IDX) 5904 5905 #define BIT_SHIFT_HI7Q_HOST_IDX 0 5906 #define BIT_MASK_HI7Q_HOST_IDX 0xfff 5907 #define BIT_HI7Q_HOST_IDX(x) \ 5908 (((x) & BIT_MASK_HI7Q_HOST_IDX) << BIT_SHIFT_HI7Q_HOST_IDX) 5909 #define BIT_GET_HI7Q_HOST_IDX(x) \ 5910 (((x) >> BIT_SHIFT_HI7Q_HOST_IDX) & BIT_MASK_HI7Q_HOST_IDX) 5911 5912 /* 2 REG_DBG_SEL_V1 (Offset 0x03D8) */ 5913 5914 #define BIT_DIS_TXDMA_PRE BIT(7) 5915 #define BIT_DIS_RXDMA_PRE BIT(6) 5916 #define BIT_TXFLAG_EXIT_L1_EN BIT(2) 5917 5918 #define BIT_SHIFT_DBG_SEL 0 5919 #define BIT_MASK_DBG_SEL 0xff 5920 #define BIT_DBG_SEL(x) (((x) & BIT_MASK_DBG_SEL) << BIT_SHIFT_DBG_SEL) 5921 #define BIT_GET_DBG_SEL(x) (((x) >> BIT_SHIFT_DBG_SEL) & BIT_MASK_DBG_SEL) 5922 5923 /* 2 REG_PCIE_HRPWM1_V1 (Offset 0x03D9) */ 5924 5925 #define BIT_SHIFT_PCIE_HRPWM 0 5926 #define BIT_MASK_PCIE_HRPWM 0xff 5927 #define BIT_PCIE_HRPWM(x) (((x) & BIT_MASK_PCIE_HRPWM) << BIT_SHIFT_PCIE_HRPWM) 5928 #define BIT_GET_PCIE_HRPWM(x) \ 5929 (((x) >> BIT_SHIFT_PCIE_HRPWM) & BIT_MASK_PCIE_HRPWM) 5930 5931 /* 2 REG_PCIE_HCPWM1_V1 (Offset 0x03DA) */ 5932 5933 #define BIT_SHIFT_PCIE_HCPWM 0 5934 #define BIT_MASK_PCIE_HCPWM 0xff 5935 #define BIT_PCIE_HCPWM(x) (((x) & BIT_MASK_PCIE_HCPWM) << BIT_SHIFT_PCIE_HCPWM) 5936 #define BIT_GET_PCIE_HCPWM(x) \ 5937 (((x) >> BIT_SHIFT_PCIE_HCPWM) & BIT_MASK_PCIE_HCPWM) 5938 5939 /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ 5940 5941 #define BIT_SHIFT_HPS_CLKR_PCIE 4 5942 #define BIT_MASK_HPS_CLKR_PCIE 0x3 5943 #define BIT_HPS_CLKR_PCIE(x) \ 5944 (((x) & BIT_MASK_HPS_CLKR_PCIE) << BIT_SHIFT_HPS_CLKR_PCIE) 5945 #define BIT_GET_HPS_CLKR_PCIE(x) \ 5946 (((x) >> BIT_SHIFT_HPS_CLKR_PCIE) & BIT_MASK_HPS_CLKR_PCIE) 5947 5948 /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ 5949 5950 #define BIT_PCIE_INT BIT(3) 5951 5952 /* 2 REG_PCIE_CTRL2 (Offset 0x03DB) */ 5953 5954 #define BIT_EN_RXDMA_ALIGN BIT(1) 5955 #define BIT_EN_TXDMA_ALIGN BIT(0) 5956 5957 /* 2 REG_PCIE_HRPWM2_V1 (Offset 0x03DC) */ 5958 5959 #define BIT_SHIFT_PCIE_HRPWM2 0 5960 #define BIT_MASK_PCIE_HRPWM2 0xffff 5961 #define BIT_PCIE_HRPWM2(x) \ 5962 (((x) & BIT_MASK_PCIE_HRPWM2) << BIT_SHIFT_PCIE_HRPWM2) 5963 #define BIT_GET_PCIE_HRPWM2(x) \ 5964 (((x) >> BIT_SHIFT_PCIE_HRPWM2) & BIT_MASK_PCIE_HRPWM2) 5965 5966 /* 2 REG_PCIE_HCPWM2_V1 (Offset 0x03DE) */ 5967 5968 #define BIT_SHIFT_PCIE_HCPWM2 0 5969 #define BIT_MASK_PCIE_HCPWM2 0xffff 5970 #define BIT_PCIE_HCPWM2(x) \ 5971 (((x) & BIT_MASK_PCIE_HCPWM2) << BIT_SHIFT_PCIE_HCPWM2) 5972 #define BIT_GET_PCIE_HCPWM2(x) \ 5973 (((x) >> BIT_SHIFT_PCIE_HCPWM2) & BIT_MASK_PCIE_HCPWM2) 5974 5975 /* 2 REG_PCIE_H2C_MSG_V1 (Offset 0x03E0) */ 5976 5977 #define BIT_SHIFT_DRV2FW_INFO 0 5978 #define BIT_MASK_DRV2FW_INFO 0xffffffffL 5979 #define BIT_DRV2FW_INFO(x) \ 5980 (((x) & BIT_MASK_DRV2FW_INFO) << BIT_SHIFT_DRV2FW_INFO) 5981 #define BIT_GET_DRV2FW_INFO(x) \ 5982 (((x) >> BIT_SHIFT_DRV2FW_INFO) & BIT_MASK_DRV2FW_INFO) 5983 5984 /* 2 REG_PCIE_C2H_MSG_V1 (Offset 0x03E4) */ 5985 5986 #define BIT_SHIFT_HCI_PCIE_C2H_MSG 0 5987 #define BIT_MASK_HCI_PCIE_C2H_MSG 0xffffffffL 5988 #define BIT_HCI_PCIE_C2H_MSG(x) \ 5989 (((x) & BIT_MASK_HCI_PCIE_C2H_MSG) << BIT_SHIFT_HCI_PCIE_C2H_MSG) 5990 #define BIT_GET_HCI_PCIE_C2H_MSG(x) \ 5991 (((x) >> BIT_SHIFT_HCI_PCIE_C2H_MSG) & BIT_MASK_HCI_PCIE_C2H_MSG) 5992 5993 /* 2 REG_DBI_WDATA_V1 (Offset 0x03E8) */ 5994 5995 #define BIT_SHIFT_DBI_WDATA 0 5996 #define BIT_MASK_DBI_WDATA 0xffffffffL 5997 #define BIT_DBI_WDATA(x) (((x) & BIT_MASK_DBI_WDATA) << BIT_SHIFT_DBI_WDATA) 5998 #define BIT_GET_DBI_WDATA(x) (((x) >> BIT_SHIFT_DBI_WDATA) & BIT_MASK_DBI_WDATA) 5999 6000 /* 2 REG_DBI_RDATA_V1 (Offset 0x03EC) */ 6001 6002 #define BIT_SHIFT_DBI_RDATA 0 6003 #define BIT_MASK_DBI_RDATA 0xffffffffL 6004 #define BIT_DBI_RDATA(x) (((x) & BIT_MASK_DBI_RDATA) << BIT_SHIFT_DBI_RDATA) 6005 #define BIT_GET_DBI_RDATA(x) (((x) >> BIT_SHIFT_DBI_RDATA) & BIT_MASK_DBI_RDATA) 6006 6007 /* 2 REG_DBI_FLAG_V1 (Offset 0x03F0) */ 6008 6009 #define BIT_EN_STUCK_DBG BIT(26) 6010 #define BIT_RX_STUCK BIT(25) 6011 #define BIT_TX_STUCK BIT(24) 6012 #define BIT_DBI_RFLAG BIT(17) 6013 #define BIT_DBI_WFLAG BIT(16) 6014 6015 #define BIT_SHIFT_DBI_WREN 12 6016 #define BIT_MASK_DBI_WREN 0xf 6017 #define BIT_DBI_WREN(x) (((x) & BIT_MASK_DBI_WREN) << BIT_SHIFT_DBI_WREN) 6018 #define BIT_GET_DBI_WREN(x) (((x) >> BIT_SHIFT_DBI_WREN) & BIT_MASK_DBI_WREN) 6019 6020 #define BIT_SHIFT_DBI_ADDR 0 6021 #define BIT_MASK_DBI_ADDR 0xfff 6022 #define BIT_DBI_ADDR(x) (((x) & BIT_MASK_DBI_ADDR) << BIT_SHIFT_DBI_ADDR) 6023 #define BIT_GET_DBI_ADDR(x) (((x) >> BIT_SHIFT_DBI_ADDR) & BIT_MASK_DBI_ADDR) 6024 6025 /* 2 REG_MDIO_V1 (Offset 0x03F4) */ 6026 6027 #define BIT_SHIFT_MDIO_RDATA 16 6028 #define BIT_MASK_MDIO_RDATA 0xffff 6029 #define BIT_MDIO_RDATA(x) (((x) & BIT_MASK_MDIO_RDATA) << BIT_SHIFT_MDIO_RDATA) 6030 #define BIT_GET_MDIO_RDATA(x) \ 6031 (((x) >> BIT_SHIFT_MDIO_RDATA) & BIT_MASK_MDIO_RDATA) 6032 6033 #define BIT_SHIFT_MDIO_WDATA 0 6034 #define BIT_MASK_MDIO_WDATA 0xffff 6035 #define BIT_MDIO_WDATA(x) (((x) & BIT_MASK_MDIO_WDATA) << BIT_SHIFT_MDIO_WDATA) 6036 #define BIT_GET_MDIO_WDATA(x) \ 6037 (((x) >> BIT_SHIFT_MDIO_WDATA) & BIT_MASK_MDIO_WDATA) 6038 6039 /* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ 6040 6041 #define BIT_EN_WATCH_DOG BIT(8) 6042 6043 /* 2 REG_PCIE_MIX_CFG (Offset 0x03F8) */ 6044 6045 #define BIT_SHIFT_MDIO_REG_ADDR_V1 0 6046 #define BIT_MASK_MDIO_REG_ADDR_V1 0x1f 6047 #define BIT_MDIO_REG_ADDR_V1(x) \ 6048 (((x) & BIT_MASK_MDIO_REG_ADDR_V1) << BIT_SHIFT_MDIO_REG_ADDR_V1) 6049 #define BIT_GET_MDIO_REG_ADDR_V1(x) \ 6050 (((x) >> BIT_SHIFT_MDIO_REG_ADDR_V1) & BIT_MASK_MDIO_REG_ADDR_V1) 6051 6052 /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ 6053 6054 #define BIT_HOST_GEN2_SUPPORT BIT(20) 6055 6056 #define BIT_SHIFT_TXDMA_ERR_FLAG 16 6057 #define BIT_MASK_TXDMA_ERR_FLAG 0xf 6058 #define BIT_TXDMA_ERR_FLAG(x) \ 6059 (((x) & BIT_MASK_TXDMA_ERR_FLAG) << BIT_SHIFT_TXDMA_ERR_FLAG) 6060 #define BIT_GET_TXDMA_ERR_FLAG(x) \ 6061 (((x) >> BIT_SHIFT_TXDMA_ERR_FLAG) & BIT_MASK_TXDMA_ERR_FLAG) 6062 6063 #define BIT_SHIFT_EARLY_MODE_SEL 12 6064 #define BIT_MASK_EARLY_MODE_SEL 0xf 6065 #define BIT_EARLY_MODE_SEL(x) \ 6066 (((x) & BIT_MASK_EARLY_MODE_SEL) << BIT_SHIFT_EARLY_MODE_SEL) 6067 #define BIT_GET_EARLY_MODE_SEL(x) \ 6068 (((x) >> BIT_SHIFT_EARLY_MODE_SEL) & BIT_MASK_EARLY_MODE_SEL) 6069 6070 #define BIT_EPHY_RX50_EN BIT(11) 6071 6072 #define BIT_SHIFT_MSI_TIMEOUT_ID_V1 8 6073 #define BIT_MASK_MSI_TIMEOUT_ID_V1 0x7 6074 #define BIT_MSI_TIMEOUT_ID_V1(x) \ 6075 (((x) & BIT_MASK_MSI_TIMEOUT_ID_V1) << BIT_SHIFT_MSI_TIMEOUT_ID_V1) 6076 #define BIT_GET_MSI_TIMEOUT_ID_V1(x) \ 6077 (((x) >> BIT_SHIFT_MSI_TIMEOUT_ID_V1) & BIT_MASK_MSI_TIMEOUT_ID_V1) 6078 6079 #define BIT_RADDR_RD BIT(7) 6080 #define BIT_EN_MUL_TAG BIT(6) 6081 #define BIT_EN_EARLY_MODE BIT(5) 6082 #define BIT_L0S_LINK_OFF BIT(4) 6083 #define BIT_ACT_LINK_OFF BIT(3) 6084 6085 /* 2 REG_HCI_MIX_CFG (Offset 0x03FC) */ 6086 6087 #define BIT_EN_SLOW_MAC_TX BIT(2) 6088 #define BIT_EN_SLOW_MAC_RX BIT(1) 6089 6090 /* 2 REG_Q0_INFO (Offset 0x0400) */ 6091 6092 #define BIT_SHIFT_QUEUEMACID_Q0_V1 25 6093 #define BIT_MASK_QUEUEMACID_Q0_V1 0x7f 6094 #define BIT_QUEUEMACID_Q0_V1(x) \ 6095 (((x) & BIT_MASK_QUEUEMACID_Q0_V1) << BIT_SHIFT_QUEUEMACID_Q0_V1) 6096 #define BIT_GET_QUEUEMACID_Q0_V1(x) \ 6097 (((x) >> BIT_SHIFT_QUEUEMACID_Q0_V1) & BIT_MASK_QUEUEMACID_Q0_V1) 6098 6099 #define BIT_SHIFT_QUEUEAC_Q0_V1 23 6100 #define BIT_MASK_QUEUEAC_Q0_V1 0x3 6101 #define BIT_QUEUEAC_Q0_V1(x) \ 6102 (((x) & BIT_MASK_QUEUEAC_Q0_V1) << BIT_SHIFT_QUEUEAC_Q0_V1) 6103 #define BIT_GET_QUEUEAC_Q0_V1(x) \ 6104 (((x) >> BIT_SHIFT_QUEUEAC_Q0_V1) & BIT_MASK_QUEUEAC_Q0_V1) 6105 6106 /* 2 REG_Q0_INFO (Offset 0x0400) */ 6107 6108 #define BIT_TIDEMPTY_Q0_V1 BIT(22) 6109 6110 /* 2 REG_Q0_INFO (Offset 0x0400) */ 6111 6112 #define BIT_SHIFT_TAIL_PKT_Q0_V2 11 6113 #define BIT_MASK_TAIL_PKT_Q0_V2 0x7ff 6114 #define BIT_TAIL_PKT_Q0_V2(x) \ 6115 (((x) & BIT_MASK_TAIL_PKT_Q0_V2) << BIT_SHIFT_TAIL_PKT_Q0_V2) 6116 #define BIT_GET_TAIL_PKT_Q0_V2(x) \ 6117 (((x) >> BIT_SHIFT_TAIL_PKT_Q0_V2) & BIT_MASK_TAIL_PKT_Q0_V2) 6118 6119 /* 2 REG_Q0_INFO (Offset 0x0400) */ 6120 6121 #define BIT_SHIFT_HEAD_PKT_Q0_V1 0 6122 #define BIT_MASK_HEAD_PKT_Q0_V1 0x7ff 6123 #define BIT_HEAD_PKT_Q0_V1(x) \ 6124 (((x) & BIT_MASK_HEAD_PKT_Q0_V1) << BIT_SHIFT_HEAD_PKT_Q0_V1) 6125 #define BIT_GET_HEAD_PKT_Q0_V1(x) \ 6126 (((x) >> BIT_SHIFT_HEAD_PKT_Q0_V1) & BIT_MASK_HEAD_PKT_Q0_V1) 6127 6128 /* 2 REG_Q1_INFO (Offset 0x0404) */ 6129 6130 #define BIT_SHIFT_QUEUEMACID_Q1_V1 25 6131 #define BIT_MASK_QUEUEMACID_Q1_V1 0x7f 6132 #define BIT_QUEUEMACID_Q1_V1(x) \ 6133 (((x) & BIT_MASK_QUEUEMACID_Q1_V1) << BIT_SHIFT_QUEUEMACID_Q1_V1) 6134 #define BIT_GET_QUEUEMACID_Q1_V1(x) \ 6135 (((x) >> BIT_SHIFT_QUEUEMACID_Q1_V1) & BIT_MASK_QUEUEMACID_Q1_V1) 6136 6137 #define BIT_SHIFT_QUEUEAC_Q1_V1 23 6138 #define BIT_MASK_QUEUEAC_Q1_V1 0x3 6139 #define BIT_QUEUEAC_Q1_V1(x) \ 6140 (((x) & BIT_MASK_QUEUEAC_Q1_V1) << BIT_SHIFT_QUEUEAC_Q1_V1) 6141 #define BIT_GET_QUEUEAC_Q1_V1(x) \ 6142 (((x) >> BIT_SHIFT_QUEUEAC_Q1_V1) & BIT_MASK_QUEUEAC_Q1_V1) 6143 6144 /* 2 REG_Q1_INFO (Offset 0x0404) */ 6145 6146 #define BIT_TIDEMPTY_Q1_V1 BIT(22) 6147 6148 /* 2 REG_Q1_INFO (Offset 0x0404) */ 6149 6150 #define BIT_SHIFT_TAIL_PKT_Q1_V2 11 6151 #define BIT_MASK_TAIL_PKT_Q1_V2 0x7ff 6152 #define BIT_TAIL_PKT_Q1_V2(x) \ 6153 (((x) & BIT_MASK_TAIL_PKT_Q1_V2) << BIT_SHIFT_TAIL_PKT_Q1_V2) 6154 #define BIT_GET_TAIL_PKT_Q1_V2(x) \ 6155 (((x) >> BIT_SHIFT_TAIL_PKT_Q1_V2) & BIT_MASK_TAIL_PKT_Q1_V2) 6156 6157 /* 2 REG_Q1_INFO (Offset 0x0404) */ 6158 6159 #define BIT_SHIFT_HEAD_PKT_Q1_V1 0 6160 #define BIT_MASK_HEAD_PKT_Q1_V1 0x7ff 6161 #define BIT_HEAD_PKT_Q1_V1(x) \ 6162 (((x) & BIT_MASK_HEAD_PKT_Q1_V1) << BIT_SHIFT_HEAD_PKT_Q1_V1) 6163 #define BIT_GET_HEAD_PKT_Q1_V1(x) \ 6164 (((x) >> BIT_SHIFT_HEAD_PKT_Q1_V1) & BIT_MASK_HEAD_PKT_Q1_V1) 6165 6166 /* 2 REG_Q2_INFO (Offset 0x0408) */ 6167 6168 #define BIT_SHIFT_QUEUEMACID_Q2_V1 25 6169 #define BIT_MASK_QUEUEMACID_Q2_V1 0x7f 6170 #define BIT_QUEUEMACID_Q2_V1(x) \ 6171 (((x) & BIT_MASK_QUEUEMACID_Q2_V1) << BIT_SHIFT_QUEUEMACID_Q2_V1) 6172 #define BIT_GET_QUEUEMACID_Q2_V1(x) \ 6173 (((x) >> BIT_SHIFT_QUEUEMACID_Q2_V1) & BIT_MASK_QUEUEMACID_Q2_V1) 6174 6175 #define BIT_SHIFT_QUEUEAC_Q2_V1 23 6176 #define BIT_MASK_QUEUEAC_Q2_V1 0x3 6177 #define BIT_QUEUEAC_Q2_V1(x) \ 6178 (((x) & BIT_MASK_QUEUEAC_Q2_V1) << BIT_SHIFT_QUEUEAC_Q2_V1) 6179 #define BIT_GET_QUEUEAC_Q2_V1(x) \ 6180 (((x) >> BIT_SHIFT_QUEUEAC_Q2_V1) & BIT_MASK_QUEUEAC_Q2_V1) 6181 6182 /* 2 REG_Q2_INFO (Offset 0x0408) */ 6183 6184 #define BIT_TIDEMPTY_Q2_V1 BIT(22) 6185 6186 /* 2 REG_Q2_INFO (Offset 0x0408) */ 6187 6188 #define BIT_SHIFT_TAIL_PKT_Q2_V2 11 6189 #define BIT_MASK_TAIL_PKT_Q2_V2 0x7ff 6190 #define BIT_TAIL_PKT_Q2_V2(x) \ 6191 (((x) & BIT_MASK_TAIL_PKT_Q2_V2) << BIT_SHIFT_TAIL_PKT_Q2_V2) 6192 #define BIT_GET_TAIL_PKT_Q2_V2(x) \ 6193 (((x) >> BIT_SHIFT_TAIL_PKT_Q2_V2) & BIT_MASK_TAIL_PKT_Q2_V2) 6194 6195 /* 2 REG_Q2_INFO (Offset 0x0408) */ 6196 6197 #define BIT_SHIFT_HEAD_PKT_Q2_V1 0 6198 #define BIT_MASK_HEAD_PKT_Q2_V1 0x7ff 6199 #define BIT_HEAD_PKT_Q2_V1(x) \ 6200 (((x) & BIT_MASK_HEAD_PKT_Q2_V1) << BIT_SHIFT_HEAD_PKT_Q2_V1) 6201 #define BIT_GET_HEAD_PKT_Q2_V1(x) \ 6202 (((x) >> BIT_SHIFT_HEAD_PKT_Q2_V1) & BIT_MASK_HEAD_PKT_Q2_V1) 6203 6204 /* 2 REG_Q3_INFO (Offset 0x040C) */ 6205 6206 #define BIT_SHIFT_QUEUEMACID_Q3_V1 25 6207 #define BIT_MASK_QUEUEMACID_Q3_V1 0x7f 6208 #define BIT_QUEUEMACID_Q3_V1(x) \ 6209 (((x) & BIT_MASK_QUEUEMACID_Q3_V1) << BIT_SHIFT_QUEUEMACID_Q3_V1) 6210 #define BIT_GET_QUEUEMACID_Q3_V1(x) \ 6211 (((x) >> BIT_SHIFT_QUEUEMACID_Q3_V1) & BIT_MASK_QUEUEMACID_Q3_V1) 6212 6213 #define BIT_SHIFT_QUEUEAC_Q3_V1 23 6214 #define BIT_MASK_QUEUEAC_Q3_V1 0x3 6215 #define BIT_QUEUEAC_Q3_V1(x) \ 6216 (((x) & BIT_MASK_QUEUEAC_Q3_V1) << BIT_SHIFT_QUEUEAC_Q3_V1) 6217 #define BIT_GET_QUEUEAC_Q3_V1(x) \ 6218 (((x) >> BIT_SHIFT_QUEUEAC_Q3_V1) & BIT_MASK_QUEUEAC_Q3_V1) 6219 6220 /* 2 REG_Q3_INFO (Offset 0x040C) */ 6221 6222 #define BIT_TIDEMPTY_Q3_V1 BIT(22) 6223 6224 /* 2 REG_Q3_INFO (Offset 0x040C) */ 6225 6226 #define BIT_SHIFT_TAIL_PKT_Q3_V2 11 6227 #define BIT_MASK_TAIL_PKT_Q3_V2 0x7ff 6228 #define BIT_TAIL_PKT_Q3_V2(x) \ 6229 (((x) & BIT_MASK_TAIL_PKT_Q3_V2) << BIT_SHIFT_TAIL_PKT_Q3_V2) 6230 #define BIT_GET_TAIL_PKT_Q3_V2(x) \ 6231 (((x) >> BIT_SHIFT_TAIL_PKT_Q3_V2) & BIT_MASK_TAIL_PKT_Q3_V2) 6232 6233 /* 2 REG_Q3_INFO (Offset 0x040C) */ 6234 6235 #define BIT_SHIFT_HEAD_PKT_Q3_V1 0 6236 #define BIT_MASK_HEAD_PKT_Q3_V1 0x7ff 6237 #define BIT_HEAD_PKT_Q3_V1(x) \ 6238 (((x) & BIT_MASK_HEAD_PKT_Q3_V1) << BIT_SHIFT_HEAD_PKT_Q3_V1) 6239 #define BIT_GET_HEAD_PKT_Q3_V1(x) \ 6240 (((x) >> BIT_SHIFT_HEAD_PKT_Q3_V1) & BIT_MASK_HEAD_PKT_Q3_V1) 6241 6242 /* 2 REG_MGQ_INFO (Offset 0x0410) */ 6243 6244 #define BIT_SHIFT_QUEUEMACID_MGQ_V1 25 6245 #define BIT_MASK_QUEUEMACID_MGQ_V1 0x7f 6246 #define BIT_QUEUEMACID_MGQ_V1(x) \ 6247 (((x) & BIT_MASK_QUEUEMACID_MGQ_V1) << BIT_SHIFT_QUEUEMACID_MGQ_V1) 6248 #define BIT_GET_QUEUEMACID_MGQ_V1(x) \ 6249 (((x) >> BIT_SHIFT_QUEUEMACID_MGQ_V1) & BIT_MASK_QUEUEMACID_MGQ_V1) 6250 6251 #define BIT_SHIFT_QUEUEAC_MGQ_V1 23 6252 #define BIT_MASK_QUEUEAC_MGQ_V1 0x3 6253 #define BIT_QUEUEAC_MGQ_V1(x) \ 6254 (((x) & BIT_MASK_QUEUEAC_MGQ_V1) << BIT_SHIFT_QUEUEAC_MGQ_V1) 6255 #define BIT_GET_QUEUEAC_MGQ_V1(x) \ 6256 (((x) >> BIT_SHIFT_QUEUEAC_MGQ_V1) & BIT_MASK_QUEUEAC_MGQ_V1) 6257 6258 /* 2 REG_MGQ_INFO (Offset 0x0410) */ 6259 6260 #define BIT_TIDEMPTY_MGQ_V1 BIT(22) 6261 6262 /* 2 REG_MGQ_INFO (Offset 0x0410) */ 6263 6264 #define BIT_SHIFT_TAIL_PKT_MGQ_V2 11 6265 #define BIT_MASK_TAIL_PKT_MGQ_V2 0x7ff 6266 #define BIT_TAIL_PKT_MGQ_V2(x) \ 6267 (((x) & BIT_MASK_TAIL_PKT_MGQ_V2) << BIT_SHIFT_TAIL_PKT_MGQ_V2) 6268 #define BIT_GET_TAIL_PKT_MGQ_V2(x) \ 6269 (((x) >> BIT_SHIFT_TAIL_PKT_MGQ_V2) & BIT_MASK_TAIL_PKT_MGQ_V2) 6270 6271 /* 2 REG_MGQ_INFO (Offset 0x0410) */ 6272 6273 #define BIT_SHIFT_HEAD_PKT_MGQ_V1 0 6274 #define BIT_MASK_HEAD_PKT_MGQ_V1 0x7ff 6275 #define BIT_HEAD_PKT_MGQ_V1(x) \ 6276 (((x) & BIT_MASK_HEAD_PKT_MGQ_V1) << BIT_SHIFT_HEAD_PKT_MGQ_V1) 6277 #define BIT_GET_HEAD_PKT_MGQ_V1(x) \ 6278 (((x) >> BIT_SHIFT_HEAD_PKT_MGQ_V1) & BIT_MASK_HEAD_PKT_MGQ_V1) 6279 6280 /* 2 REG_HIQ_INFO (Offset 0x0414) */ 6281 6282 #define BIT_SHIFT_QUEUEMACID_HIQ_V1 25 6283 #define BIT_MASK_QUEUEMACID_HIQ_V1 0x7f 6284 #define BIT_QUEUEMACID_HIQ_V1(x) \ 6285 (((x) & BIT_MASK_QUEUEMACID_HIQ_V1) << BIT_SHIFT_QUEUEMACID_HIQ_V1) 6286 #define BIT_GET_QUEUEMACID_HIQ_V1(x) \ 6287 (((x) >> BIT_SHIFT_QUEUEMACID_HIQ_V1) & BIT_MASK_QUEUEMACID_HIQ_V1) 6288 6289 #define BIT_SHIFT_QUEUEAC_HIQ_V1 23 6290 #define BIT_MASK_QUEUEAC_HIQ_V1 0x3 6291 #define BIT_QUEUEAC_HIQ_V1(x) \ 6292 (((x) & BIT_MASK_QUEUEAC_HIQ_V1) << BIT_SHIFT_QUEUEAC_HIQ_V1) 6293 #define BIT_GET_QUEUEAC_HIQ_V1(x) \ 6294 (((x) >> BIT_SHIFT_QUEUEAC_HIQ_V1) & BIT_MASK_QUEUEAC_HIQ_V1) 6295 6296 /* 2 REG_HIQ_INFO (Offset 0x0414) */ 6297 6298 #define BIT_TIDEMPTY_HIQ_V1 BIT(22) 6299 6300 /* 2 REG_HIQ_INFO (Offset 0x0414) */ 6301 6302 #define BIT_SHIFT_TAIL_PKT_HIQ_V2 11 6303 #define BIT_MASK_TAIL_PKT_HIQ_V2 0x7ff 6304 #define BIT_TAIL_PKT_HIQ_V2(x) \ 6305 (((x) & BIT_MASK_TAIL_PKT_HIQ_V2) << BIT_SHIFT_TAIL_PKT_HIQ_V2) 6306 #define BIT_GET_TAIL_PKT_HIQ_V2(x) \ 6307 (((x) >> BIT_SHIFT_TAIL_PKT_HIQ_V2) & BIT_MASK_TAIL_PKT_HIQ_V2) 6308 6309 /* 2 REG_HIQ_INFO (Offset 0x0414) */ 6310 6311 #define BIT_SHIFT_HEAD_PKT_HIQ_V1 0 6312 #define BIT_MASK_HEAD_PKT_HIQ_V1 0x7ff 6313 #define BIT_HEAD_PKT_HIQ_V1(x) \ 6314 (((x) & BIT_MASK_HEAD_PKT_HIQ_V1) << BIT_SHIFT_HEAD_PKT_HIQ_V1) 6315 #define BIT_GET_HEAD_PKT_HIQ_V1(x) \ 6316 (((x) >> BIT_SHIFT_HEAD_PKT_HIQ_V1) & BIT_MASK_HEAD_PKT_HIQ_V1) 6317 6318 /* 2 REG_BCNQ_INFO (Offset 0x0418) */ 6319 6320 #define BIT_SHIFT_BCNQ_HEAD_PG_V1 0 6321 #define BIT_MASK_BCNQ_HEAD_PG_V1 0xfff 6322 #define BIT_BCNQ_HEAD_PG_V1(x) \ 6323 (((x) & BIT_MASK_BCNQ_HEAD_PG_V1) << BIT_SHIFT_BCNQ_HEAD_PG_V1) 6324 #define BIT_GET_BCNQ_HEAD_PG_V1(x) \ 6325 (((x) >> BIT_SHIFT_BCNQ_HEAD_PG_V1) & BIT_MASK_BCNQ_HEAD_PG_V1) 6326 6327 /* 2 REG_TXPKT_EMPTY (Offset 0x041A) */ 6328 6329 #define BIT_BCNQ_EMPTY BIT(11) 6330 #define BIT_HQQ_EMPTY BIT(10) 6331 #define BIT_MQQ_EMPTY BIT(9) 6332 #define BIT_MGQ_CPU_EMPTY BIT(8) 6333 #define BIT_AC7Q_EMPTY BIT(7) 6334 #define BIT_AC6Q_EMPTY BIT(6) 6335 #define BIT_AC5Q_EMPTY BIT(5) 6336 #define BIT_AC4Q_EMPTY BIT(4) 6337 #define BIT_AC3Q_EMPTY BIT(3) 6338 #define BIT_AC2Q_EMPTY BIT(2) 6339 #define BIT_AC1Q_EMPTY BIT(1) 6340 #define BIT_AC0Q_EMPTY BIT(0) 6341 6342 /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6343 6344 #define BIT_BCN1_POLL BIT(30) 6345 6346 /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6347 6348 #define BIT_CPUMGT_POLL BIT(29) 6349 #define BIT_BCN_POLL BIT(28) 6350 6351 /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6352 6353 #define BIT_CPUMGQ_FW_NUM_V1 BIT(12) 6354 6355 /* 2 REG_CPU_MGQ_INFO (Offset 0x041C) */ 6356 6357 #define BIT_SHIFT_FW_FREE_TAIL_V1 0 6358 #define BIT_MASK_FW_FREE_TAIL_V1 0xfff 6359 #define BIT_FW_FREE_TAIL_V1(x) \ 6360 (((x) & BIT_MASK_FW_FREE_TAIL_V1) << BIT_SHIFT_FW_FREE_TAIL_V1) 6361 #define BIT_GET_FW_FREE_TAIL_V1(x) \ 6362 (((x) >> BIT_SHIFT_FW_FREE_TAIL_V1) & BIT_MASK_FW_FREE_TAIL_V1) 6363 6364 /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6365 6366 #define BIT_RTS_LIMIT_IN_OFDM BIT(23) 6367 #define BIT_EN_BCNQ_DL BIT(22) 6368 #define BIT_EN_RD_RESP_NAV_BK BIT(21) 6369 #define BIT_EN_WR_FREE_TAIL BIT(20) 6370 6371 #define BIT_SHIFT_EN_QUEUE_RPT 8 6372 #define BIT_MASK_EN_QUEUE_RPT 0xff 6373 #define BIT_EN_QUEUE_RPT(x) \ 6374 (((x) & BIT_MASK_EN_QUEUE_RPT) << BIT_SHIFT_EN_QUEUE_RPT) 6375 #define BIT_GET_EN_QUEUE_RPT(x) \ 6376 (((x) >> BIT_SHIFT_EN_QUEUE_RPT) & BIT_MASK_EN_QUEUE_RPT) 6377 6378 #define BIT_EN_RTY_BK BIT(7) 6379 #define BIT_EN_USE_INI_RAT BIT(6) 6380 #define BIT_EN_RTS_NAV_BK BIT(5) 6381 #define BIT_DIS_SSN_CHECK BIT(4) 6382 #define BIT_MACID_MATCH_RTS BIT(3) 6383 6384 /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6385 6386 #define BIT_EN_BCN_TRXRPT_V1 BIT(2) 6387 6388 /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6389 6390 #define BIT_EN_FTMACKRPT BIT(1) 6391 6392 /* 2 REG_FWHW_TXQ_CTRL (Offset 0x0420) */ 6393 6394 #define BIT_EN_FTMRPT BIT(0) 6395 6396 /* 2 REG_DATAFB_SEL (Offset 0x0423) */ 6397 6398 #define BIT__R_EN_RTY_BK_COD BIT(2) 6399 6400 /* 2 REG_DATAFB_SEL (Offset 0x0423) */ 6401 6402 #define BIT_SHIFT__R_DATA_FALLBACK_SEL 0 6403 #define BIT_MASK__R_DATA_FALLBACK_SEL 0x3 6404 #define BIT__R_DATA_FALLBACK_SEL(x) \ 6405 (((x) & BIT_MASK__R_DATA_FALLBACK_SEL) \ 6406 << BIT_SHIFT__R_DATA_FALLBACK_SEL) 6407 #define BIT_GET__R_DATA_FALLBACK_SEL(x) \ 6408 (((x) >> BIT_SHIFT__R_DATA_FALLBACK_SEL) & \ 6409 BIT_MASK__R_DATA_FALLBACK_SEL) 6410 6411 /* 2 REG_BCNQ_BDNY_V1 (Offset 0x0424) */ 6412 6413 #define BIT_SHIFT_BCNQ_PGBNDY_V1 0 6414 #define BIT_MASK_BCNQ_PGBNDY_V1 0xfff 6415 #define BIT_BCNQ_PGBNDY_V1(x) \ 6416 (((x) & BIT_MASK_BCNQ_PGBNDY_V1) << BIT_SHIFT_BCNQ_PGBNDY_V1) 6417 #define BIT_GET_BCNQ_PGBNDY_V1(x) \ 6418 (((x) >> BIT_SHIFT_BCNQ_PGBNDY_V1) & BIT_MASK_BCNQ_PGBNDY_V1) 6419 6420 /* 2 REG_LIFETIME_EN (Offset 0x0426) */ 6421 6422 #define BIT_BT_INT_CPU BIT(7) 6423 #define BIT_BT_INT_PTA BIT(6) 6424 6425 /* 2 REG_LIFETIME_EN (Offset 0x0426) */ 6426 6427 #define BIT_EN_CTRL_RTYBIT BIT(4) 6428 6429 /* 2 REG_LIFETIME_EN (Offset 0x0426) */ 6430 6431 #define BIT_LIFETIME_BK_EN BIT(3) 6432 #define BIT_LIFETIME_BE_EN BIT(2) 6433 #define BIT_LIFETIME_VI_EN BIT(1) 6434 #define BIT_LIFETIME_VO_EN BIT(0) 6435 6436 /* 2 REG_SPEC_SIFS (Offset 0x0428) */ 6437 6438 #define BIT_SHIFT_SPEC_SIFS_OFDM_PTCL 8 6439 #define BIT_MASK_SPEC_SIFS_OFDM_PTCL 0xff 6440 #define BIT_SPEC_SIFS_OFDM_PTCL(x) \ 6441 (((x) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) << BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) 6442 #define BIT_GET_SPEC_SIFS_OFDM_PTCL(x) \ 6443 (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM_PTCL) & BIT_MASK_SPEC_SIFS_OFDM_PTCL) 6444 6445 #define BIT_SHIFT_SPEC_SIFS_CCK_PTCL 0 6446 #define BIT_MASK_SPEC_SIFS_CCK_PTCL 0xff 6447 #define BIT_SPEC_SIFS_CCK_PTCL(x) \ 6448 (((x) & BIT_MASK_SPEC_SIFS_CCK_PTCL) << BIT_SHIFT_SPEC_SIFS_CCK_PTCL) 6449 #define BIT_GET_SPEC_SIFS_CCK_PTCL(x) \ 6450 (((x) >> BIT_SHIFT_SPEC_SIFS_CCK_PTCL) & BIT_MASK_SPEC_SIFS_CCK_PTCL) 6451 6452 /* 2 REG_RETRY_LIMIT (Offset 0x042A) */ 6453 6454 #define BIT_SHIFT_SRL 8 6455 #define BIT_MASK_SRL 0x3f 6456 #define BIT_SRL(x) (((x) & BIT_MASK_SRL) << BIT_SHIFT_SRL) 6457 #define BIT_GET_SRL(x) (((x) >> BIT_SHIFT_SRL) & BIT_MASK_SRL) 6458 6459 #define BIT_SHIFT_LRL 0 6460 #define BIT_MASK_LRL 0x3f 6461 #define BIT_LRL(x) (((x) & BIT_MASK_LRL) << BIT_SHIFT_LRL) 6462 #define BIT_GET_LRL(x) (((x) >> BIT_SHIFT_LRL) & BIT_MASK_LRL) 6463 6464 /* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6465 6466 #define BIT_R_ENABLE_NDPA BIT(31) 6467 #define BIT_USE_NDPA_PARAMETER BIT(30) 6468 #define BIT_R_PROP_TXBF BIT(29) 6469 #define BIT_R_EN_NDPA_INT BIT(28) 6470 #define BIT_R_TXBF1_80M BIT(27) 6471 #define BIT_R_TXBF1_40M BIT(26) 6472 #define BIT_R_TXBF1_20M BIT(25) 6473 6474 #define BIT_SHIFT_R_TXBF1_AID 16 6475 #define BIT_MASK_R_TXBF1_AID 0x1ff 6476 #define BIT_R_TXBF1_AID(x) \ 6477 (((x) & BIT_MASK_R_TXBF1_AID) << BIT_SHIFT_R_TXBF1_AID) 6478 #define BIT_GET_R_TXBF1_AID(x) \ 6479 (((x) >> BIT_SHIFT_R_TXBF1_AID) & BIT_MASK_R_TXBF1_AID) 6480 6481 /* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6482 6483 #define BIT_DIS_NDP_BFEN BIT(15) 6484 6485 /* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6486 6487 #define BIT_R_TXBCN_NOBLOCK_NDP BIT(14) 6488 6489 /* 2 REG_TXBF_CTRL (Offset 0x042C) */ 6490 6491 #define BIT_R_TXBF0_80M BIT(11) 6492 #define BIT_R_TXBF0_40M BIT(10) 6493 #define BIT_R_TXBF0_20M BIT(9) 6494 6495 #define BIT_SHIFT_R_TXBF0_AID 0 6496 #define BIT_MASK_R_TXBF0_AID 0x1ff 6497 #define BIT_R_TXBF0_AID(x) \ 6498 (((x) & BIT_MASK_R_TXBF0_AID) << BIT_SHIFT_R_TXBF0_AID) 6499 #define BIT_GET_R_TXBF0_AID(x) \ 6500 (((x) >> BIT_SHIFT_R_TXBF0_AID) & BIT_MASK_R_TXBF0_AID) 6501 6502 /* 2 REG_DARFRC (Offset 0x0430) */ 6503 6504 #define BIT_SHIFT_DARF_RC8 (56 & CPU_OPT_WIDTH) 6505 #define BIT_MASK_DARF_RC8 0x1f 6506 #define BIT_DARF_RC8(x) (((x) & BIT_MASK_DARF_RC8) << BIT_SHIFT_DARF_RC8) 6507 #define BIT_GET_DARF_RC8(x) (((x) >> BIT_SHIFT_DARF_RC8) & BIT_MASK_DARF_RC8) 6508 6509 #define BIT_SHIFT_DARF_RC7 (48 & CPU_OPT_WIDTH) 6510 #define BIT_MASK_DARF_RC7 0x1f 6511 #define BIT_DARF_RC7(x) (((x) & BIT_MASK_DARF_RC7) << BIT_SHIFT_DARF_RC7) 6512 #define BIT_GET_DARF_RC7(x) (((x) >> BIT_SHIFT_DARF_RC7) & BIT_MASK_DARF_RC7) 6513 6514 #define BIT_SHIFT_DARF_RC6 (40 & CPU_OPT_WIDTH) 6515 #define BIT_MASK_DARF_RC6 0x1f 6516 #define BIT_DARF_RC6(x) (((x) & BIT_MASK_DARF_RC6) << BIT_SHIFT_DARF_RC6) 6517 #define BIT_GET_DARF_RC6(x) (((x) >> BIT_SHIFT_DARF_RC6) & BIT_MASK_DARF_RC6) 6518 6519 #define BIT_SHIFT_DARF_RC5 (32 & CPU_OPT_WIDTH) 6520 #define BIT_MASK_DARF_RC5 0x1f 6521 #define BIT_DARF_RC5(x) (((x) & BIT_MASK_DARF_RC5) << BIT_SHIFT_DARF_RC5) 6522 #define BIT_GET_DARF_RC5(x) (((x) >> BIT_SHIFT_DARF_RC5) & BIT_MASK_DARF_RC5) 6523 6524 #define BIT_SHIFT_DARF_RC4 24 6525 #define BIT_MASK_DARF_RC4 0x1f 6526 #define BIT_DARF_RC4(x) (((x) & BIT_MASK_DARF_RC4) << BIT_SHIFT_DARF_RC4) 6527 #define BIT_GET_DARF_RC4(x) (((x) >> BIT_SHIFT_DARF_RC4) & BIT_MASK_DARF_RC4) 6528 6529 #define BIT_SHIFT_DARF_RC3 16 6530 #define BIT_MASK_DARF_RC3 0x1f 6531 #define BIT_DARF_RC3(x) (((x) & BIT_MASK_DARF_RC3) << BIT_SHIFT_DARF_RC3) 6532 #define BIT_GET_DARF_RC3(x) (((x) >> BIT_SHIFT_DARF_RC3) & BIT_MASK_DARF_RC3) 6533 6534 #define BIT_SHIFT_DARF_RC2 8 6535 #define BIT_MASK_DARF_RC2 0x1f 6536 #define BIT_DARF_RC2(x) (((x) & BIT_MASK_DARF_RC2) << BIT_SHIFT_DARF_RC2) 6537 #define BIT_GET_DARF_RC2(x) (((x) >> BIT_SHIFT_DARF_RC2) & BIT_MASK_DARF_RC2) 6538 6539 #define BIT_SHIFT_DARF_RC1 0 6540 #define BIT_MASK_DARF_RC1 0x1f 6541 #define BIT_DARF_RC1(x) (((x) & BIT_MASK_DARF_RC1) << BIT_SHIFT_DARF_RC1) 6542 #define BIT_GET_DARF_RC1(x) (((x) >> BIT_SHIFT_DARF_RC1) & BIT_MASK_DARF_RC1) 6543 6544 /* 2 REG_RARFRC (Offset 0x0438) */ 6545 6546 #define BIT_SHIFT_RARF_RC8 (56 & CPU_OPT_WIDTH) 6547 #define BIT_MASK_RARF_RC8 0x1f 6548 #define BIT_RARF_RC8(x) (((x) & BIT_MASK_RARF_RC8) << BIT_SHIFT_RARF_RC8) 6549 #define BIT_GET_RARF_RC8(x) (((x) >> BIT_SHIFT_RARF_RC8) & BIT_MASK_RARF_RC8) 6550 6551 #define BIT_SHIFT_RARF_RC7 (48 & CPU_OPT_WIDTH) 6552 #define BIT_MASK_RARF_RC7 0x1f 6553 #define BIT_RARF_RC7(x) (((x) & BIT_MASK_RARF_RC7) << BIT_SHIFT_RARF_RC7) 6554 #define BIT_GET_RARF_RC7(x) (((x) >> BIT_SHIFT_RARF_RC7) & BIT_MASK_RARF_RC7) 6555 6556 #define BIT_SHIFT_RARF_RC6 (40 & CPU_OPT_WIDTH) 6557 #define BIT_MASK_RARF_RC6 0x1f 6558 #define BIT_RARF_RC6(x) (((x) & BIT_MASK_RARF_RC6) << BIT_SHIFT_RARF_RC6) 6559 #define BIT_GET_RARF_RC6(x) (((x) >> BIT_SHIFT_RARF_RC6) & BIT_MASK_RARF_RC6) 6560 6561 #define BIT_SHIFT_RARF_RC5 (32 & CPU_OPT_WIDTH) 6562 #define BIT_MASK_RARF_RC5 0x1f 6563 #define BIT_RARF_RC5(x) (((x) & BIT_MASK_RARF_RC5) << BIT_SHIFT_RARF_RC5) 6564 #define BIT_GET_RARF_RC5(x) (((x) >> BIT_SHIFT_RARF_RC5) & BIT_MASK_RARF_RC5) 6565 6566 #define BIT_SHIFT_RARF_RC4 24 6567 #define BIT_MASK_RARF_RC4 0x1f 6568 #define BIT_RARF_RC4(x) (((x) & BIT_MASK_RARF_RC4) << BIT_SHIFT_RARF_RC4) 6569 #define BIT_GET_RARF_RC4(x) (((x) >> BIT_SHIFT_RARF_RC4) & BIT_MASK_RARF_RC4) 6570 6571 #define BIT_SHIFT_RARF_RC3 16 6572 #define BIT_MASK_RARF_RC3 0x1f 6573 #define BIT_RARF_RC3(x) (((x) & BIT_MASK_RARF_RC3) << BIT_SHIFT_RARF_RC3) 6574 #define BIT_GET_RARF_RC3(x) (((x) >> BIT_SHIFT_RARF_RC3) & BIT_MASK_RARF_RC3) 6575 6576 #define BIT_SHIFT_RARF_RC2 8 6577 #define BIT_MASK_RARF_RC2 0x1f 6578 #define BIT_RARF_RC2(x) (((x) & BIT_MASK_RARF_RC2) << BIT_SHIFT_RARF_RC2) 6579 #define BIT_GET_RARF_RC2(x) (((x) >> BIT_SHIFT_RARF_RC2) & BIT_MASK_RARF_RC2) 6580 6581 #define BIT_SHIFT_RARF_RC1 0 6582 #define BIT_MASK_RARF_RC1 0x1f 6583 #define BIT_RARF_RC1(x) (((x) & BIT_MASK_RARF_RC1) << BIT_SHIFT_RARF_RC1) 6584 #define BIT_GET_RARF_RC1(x) (((x) >> BIT_SHIFT_RARF_RC1) & BIT_MASK_RARF_RC1) 6585 6586 /* 2 REG_RRSR (Offset 0x0440) */ 6587 6588 #define BIT_SHIFT_RRSR_RSC 21 6589 #define BIT_MASK_RRSR_RSC 0x3 6590 #define BIT_RRSR_RSC(x) (((x) & BIT_MASK_RRSR_RSC) << BIT_SHIFT_RRSR_RSC) 6591 #define BIT_GET_RRSR_RSC(x) (((x) >> BIT_SHIFT_RRSR_RSC) & BIT_MASK_RRSR_RSC) 6592 6593 #define BIT_RRSR_BW BIT(20) 6594 6595 #define BIT_SHIFT_RRSC_BITMAP 0 6596 #define BIT_MASK_RRSC_BITMAP 0xfffff 6597 #define BIT_RRSC_BITMAP(x) \ 6598 (((x) & BIT_MASK_RRSC_BITMAP) << BIT_SHIFT_RRSC_BITMAP) 6599 #define BIT_GET_RRSC_BITMAP(x) \ 6600 (((x) >> BIT_SHIFT_RRSC_BITMAP) & BIT_MASK_RRSC_BITMAP) 6601 6602 /* 2 REG_ARFR0 (Offset 0x0444) */ 6603 6604 #define BIT_SHIFT_ARFR0_V1 0 6605 #define BIT_MASK_ARFR0_V1 0xffffffffffffffffL 6606 #define BIT_ARFR0_V1(x) (((x) & BIT_MASK_ARFR0_V1) << BIT_SHIFT_ARFR0_V1) 6607 #define BIT_GET_ARFR0_V1(x) (((x) >> BIT_SHIFT_ARFR0_V1) & BIT_MASK_ARFR0_V1) 6608 6609 /* 2 REG_ARFR1_V1 (Offset 0x044C) */ 6610 6611 #define BIT_SHIFT_ARFR1_V1 0 6612 #define BIT_MASK_ARFR1_V1 0xffffffffffffffffL 6613 #define BIT_ARFR1_V1(x) (((x) & BIT_MASK_ARFR1_V1) << BIT_SHIFT_ARFR1_V1) 6614 #define BIT_GET_ARFR1_V1(x) (((x) >> BIT_SHIFT_ARFR1_V1) & BIT_MASK_ARFR1_V1) 6615 6616 /* 2 REG_CCK_CHECK (Offset 0x0454) */ 6617 6618 #define BIT_CHECK_CCK_EN BIT(7) 6619 #define BIT_EN_BCN_PKT_REL BIT(6) 6620 #define BIT_BCN_PORT_SEL BIT(5) 6621 #define BIT_MOREDATA_BYPASS BIT(4) 6622 #define BIT_EN_CLR_CMD_REL_BCN_PKT BIT(3) 6623 6624 /* 2 REG_CCK_CHECK (Offset 0x0454) */ 6625 6626 #define BIT_R_EN_SET_MOREDATA BIT(2) 6627 #define BIT__R_DIS_CLEAR_MACID_RELEASE BIT(1) 6628 #define BIT__R_MACID_RELEASE_EN BIT(0) 6629 6630 /* 2 REG_AMPDU_MAX_TIME (Offset 0x0456) */ 6631 6632 #define BIT_SHIFT_AMPDU_MAX_TIME 0 6633 #define BIT_MASK_AMPDU_MAX_TIME 0xff 6634 #define BIT_AMPDU_MAX_TIME(x) \ 6635 (((x) & BIT_MASK_AMPDU_MAX_TIME) << BIT_SHIFT_AMPDU_MAX_TIME) 6636 #define BIT_GET_AMPDU_MAX_TIME(x) \ 6637 (((x) >> BIT_SHIFT_AMPDU_MAX_TIME) & BIT_MASK_AMPDU_MAX_TIME) 6638 6639 /* 2 REG_BCNQ1_BDNY_V1 (Offset 0x0456) */ 6640 6641 #define BIT_SHIFT_BCNQ1_PGBNDY_V1 0 6642 #define BIT_MASK_BCNQ1_PGBNDY_V1 0xfff 6643 #define BIT_BCNQ1_PGBNDY_V1(x) \ 6644 (((x) & BIT_MASK_BCNQ1_PGBNDY_V1) << BIT_SHIFT_BCNQ1_PGBNDY_V1) 6645 #define BIT_GET_BCNQ1_PGBNDY_V1(x) \ 6646 (((x) >> BIT_SHIFT_BCNQ1_PGBNDY_V1) & BIT_MASK_BCNQ1_PGBNDY_V1) 6647 6648 /* 2 REG_AMPDU_MAX_LENGTH (Offset 0x0458) */ 6649 6650 #define BIT_SHIFT_AMPDU_MAX_LENGTH 0 6651 #define BIT_MASK_AMPDU_MAX_LENGTH 0xffffffffL 6652 #define BIT_AMPDU_MAX_LENGTH(x) \ 6653 (((x) & BIT_MASK_AMPDU_MAX_LENGTH) << BIT_SHIFT_AMPDU_MAX_LENGTH) 6654 #define BIT_GET_AMPDU_MAX_LENGTH(x) \ 6655 (((x) >> BIT_SHIFT_AMPDU_MAX_LENGTH) & BIT_MASK_AMPDU_MAX_LENGTH) 6656 6657 /* 2 REG_ACQ_STOP (Offset 0x045C) */ 6658 6659 #define BIT_AC7Q_STOP BIT(7) 6660 #define BIT_AC6Q_STOP BIT(6) 6661 #define BIT_AC5Q_STOP BIT(5) 6662 #define BIT_AC4Q_STOP BIT(4) 6663 #define BIT_AC3Q_STOP BIT(3) 6664 #define BIT_AC2Q_STOP BIT(2) 6665 #define BIT_AC1Q_STOP BIT(1) 6666 #define BIT_AC0Q_STOP BIT(0) 6667 6668 /* 2 REG_NDPA_RATE (Offset 0x045D) */ 6669 6670 #define BIT_SHIFT_R_NDPA_RATE_V1 0 6671 #define BIT_MASK_R_NDPA_RATE_V1 0xff 6672 #define BIT_R_NDPA_RATE_V1(x) \ 6673 (((x) & BIT_MASK_R_NDPA_RATE_V1) << BIT_SHIFT_R_NDPA_RATE_V1) 6674 #define BIT_GET_R_NDPA_RATE_V1(x) \ 6675 (((x) >> BIT_SHIFT_R_NDPA_RATE_V1) & BIT_MASK_R_NDPA_RATE_V1) 6676 6677 /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ 6678 6679 #define BIT_R_EN_GNT_BT_AWAKE BIT(3) 6680 6681 /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ 6682 6683 #define BIT_EN_EOF_V1 BIT(2) 6684 6685 /* 2 REG_TX_HANG_CTRL (Offset 0x045E) */ 6686 6687 #define BIT_DIS_OQT_BLOCK BIT(1) 6688 #define BIT_SEARCH_QUEUE_EN BIT(0) 6689 6690 /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6691 6692 #define BIT_R_DIS_MACID_RELEASE_RTY BIT(5) 6693 6694 /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6695 6696 #define BIT_SHIFT_BW_SIGTA 3 6697 #define BIT_MASK_BW_SIGTA 0x3 6698 #define BIT_BW_SIGTA(x) (((x) & BIT_MASK_BW_SIGTA) << BIT_SHIFT_BW_SIGTA) 6699 #define BIT_GET_BW_SIGTA(x) (((x) >> BIT_SHIFT_BW_SIGTA) & BIT_MASK_BW_SIGTA) 6700 6701 /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6702 6703 #define BIT_EN_BAR_SIGTA BIT(2) 6704 6705 /* 2 REG_NDPA_OPT_CTRL (Offset 0x045F) */ 6706 6707 #define BIT_SHIFT_R_NDPA_BW 0 6708 #define BIT_MASK_R_NDPA_BW 0x3 6709 #define BIT_R_NDPA_BW(x) (((x) & BIT_MASK_R_NDPA_BW) << BIT_SHIFT_R_NDPA_BW) 6710 #define BIT_GET_R_NDPA_BW(x) (((x) >> BIT_SHIFT_R_NDPA_BW) & BIT_MASK_R_NDPA_BW) 6711 6712 /* 2 REG_RD_RESP_PKT_TH (Offset 0x0463) */ 6713 6714 #define BIT_SHIFT_RD_RESP_PKT_TH_V1 0 6715 #define BIT_MASK_RD_RESP_PKT_TH_V1 0x3f 6716 #define BIT_RD_RESP_PKT_TH_V1(x) \ 6717 (((x) & BIT_MASK_RD_RESP_PKT_TH_V1) << BIT_SHIFT_RD_RESP_PKT_TH_V1) 6718 #define BIT_GET_RD_RESP_PKT_TH_V1(x) \ 6719 (((x) >> BIT_SHIFT_RD_RESP_PKT_TH_V1) & BIT_MASK_RD_RESP_PKT_TH_V1) 6720 6721 /* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6722 6723 #define BIT_SHIFT_QUEUEMACID_CMDQ_V1 25 6724 #define BIT_MASK_QUEUEMACID_CMDQ_V1 0x7f 6725 #define BIT_QUEUEMACID_CMDQ_V1(x) \ 6726 (((x) & BIT_MASK_QUEUEMACID_CMDQ_V1) << BIT_SHIFT_QUEUEMACID_CMDQ_V1) 6727 #define BIT_GET_QUEUEMACID_CMDQ_V1(x) \ 6728 (((x) >> BIT_SHIFT_QUEUEMACID_CMDQ_V1) & BIT_MASK_QUEUEMACID_CMDQ_V1) 6729 6730 /* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6731 6732 #define BIT_SHIFT_QUEUEAC_CMDQ_V1 23 6733 #define BIT_MASK_QUEUEAC_CMDQ_V1 0x3 6734 #define BIT_QUEUEAC_CMDQ_V1(x) \ 6735 (((x) & BIT_MASK_QUEUEAC_CMDQ_V1) << BIT_SHIFT_QUEUEAC_CMDQ_V1) 6736 #define BIT_GET_QUEUEAC_CMDQ_V1(x) \ 6737 (((x) >> BIT_SHIFT_QUEUEAC_CMDQ_V1) & BIT_MASK_QUEUEAC_CMDQ_V1) 6738 6739 /* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6740 6741 #define BIT_TIDEMPTY_CMDQ_V1 BIT(22) 6742 6743 /* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6744 6745 #define BIT_SHIFT_TAIL_PKT_CMDQ_V2 11 6746 #define BIT_MASK_TAIL_PKT_CMDQ_V2 0x7ff 6747 #define BIT_TAIL_PKT_CMDQ_V2(x) \ 6748 (((x) & BIT_MASK_TAIL_PKT_CMDQ_V2) << BIT_SHIFT_TAIL_PKT_CMDQ_V2) 6749 #define BIT_GET_TAIL_PKT_CMDQ_V2(x) \ 6750 (((x) >> BIT_SHIFT_TAIL_PKT_CMDQ_V2) & BIT_MASK_TAIL_PKT_CMDQ_V2) 6751 6752 /* 2 REG_CMDQ_INFO (Offset 0x0464) */ 6753 6754 #define BIT_SHIFT_HEAD_PKT_CMDQ_V1 0 6755 #define BIT_MASK_HEAD_PKT_CMDQ_V1 0x7ff 6756 #define BIT_HEAD_PKT_CMDQ_V1(x) \ 6757 (((x) & BIT_MASK_HEAD_PKT_CMDQ_V1) << BIT_SHIFT_HEAD_PKT_CMDQ_V1) 6758 #define BIT_GET_HEAD_PKT_CMDQ_V1(x) \ 6759 (((x) >> BIT_SHIFT_HEAD_PKT_CMDQ_V1) & BIT_MASK_HEAD_PKT_CMDQ_V1) 6760 6761 /* 2 REG_Q4_INFO (Offset 0x0468) */ 6762 6763 #define BIT_SHIFT_QUEUEMACID_Q4_V1 25 6764 #define BIT_MASK_QUEUEMACID_Q4_V1 0x7f 6765 #define BIT_QUEUEMACID_Q4_V1(x) \ 6766 (((x) & BIT_MASK_QUEUEMACID_Q4_V1) << BIT_SHIFT_QUEUEMACID_Q4_V1) 6767 #define BIT_GET_QUEUEMACID_Q4_V1(x) \ 6768 (((x) >> BIT_SHIFT_QUEUEMACID_Q4_V1) & BIT_MASK_QUEUEMACID_Q4_V1) 6769 6770 #define BIT_SHIFT_QUEUEAC_Q4_V1 23 6771 #define BIT_MASK_QUEUEAC_Q4_V1 0x3 6772 #define BIT_QUEUEAC_Q4_V1(x) \ 6773 (((x) & BIT_MASK_QUEUEAC_Q4_V1) << BIT_SHIFT_QUEUEAC_Q4_V1) 6774 #define BIT_GET_QUEUEAC_Q4_V1(x) \ 6775 (((x) >> BIT_SHIFT_QUEUEAC_Q4_V1) & BIT_MASK_QUEUEAC_Q4_V1) 6776 6777 /* 2 REG_Q4_INFO (Offset 0x0468) */ 6778 6779 #define BIT_TIDEMPTY_Q4_V1 BIT(22) 6780 6781 /* 2 REG_Q4_INFO (Offset 0x0468) */ 6782 6783 #define BIT_SHIFT_TAIL_PKT_Q4_V2 11 6784 #define BIT_MASK_TAIL_PKT_Q4_V2 0x7ff 6785 #define BIT_TAIL_PKT_Q4_V2(x) \ 6786 (((x) & BIT_MASK_TAIL_PKT_Q4_V2) << BIT_SHIFT_TAIL_PKT_Q4_V2) 6787 #define BIT_GET_TAIL_PKT_Q4_V2(x) \ 6788 (((x) >> BIT_SHIFT_TAIL_PKT_Q4_V2) & BIT_MASK_TAIL_PKT_Q4_V2) 6789 6790 /* 2 REG_Q4_INFO (Offset 0x0468) */ 6791 6792 #define BIT_SHIFT_HEAD_PKT_Q4_V1 0 6793 #define BIT_MASK_HEAD_PKT_Q4_V1 0x7ff 6794 #define BIT_HEAD_PKT_Q4_V1(x) \ 6795 (((x) & BIT_MASK_HEAD_PKT_Q4_V1) << BIT_SHIFT_HEAD_PKT_Q4_V1) 6796 #define BIT_GET_HEAD_PKT_Q4_V1(x) \ 6797 (((x) >> BIT_SHIFT_HEAD_PKT_Q4_V1) & BIT_MASK_HEAD_PKT_Q4_V1) 6798 6799 /* 2 REG_Q5_INFO (Offset 0x046C) */ 6800 6801 #define BIT_SHIFT_QUEUEMACID_Q5_V1 25 6802 #define BIT_MASK_QUEUEMACID_Q5_V1 0x7f 6803 #define BIT_QUEUEMACID_Q5_V1(x) \ 6804 (((x) & BIT_MASK_QUEUEMACID_Q5_V1) << BIT_SHIFT_QUEUEMACID_Q5_V1) 6805 #define BIT_GET_QUEUEMACID_Q5_V1(x) \ 6806 (((x) >> BIT_SHIFT_QUEUEMACID_Q5_V1) & BIT_MASK_QUEUEMACID_Q5_V1) 6807 6808 #define BIT_SHIFT_QUEUEAC_Q5_V1 23 6809 #define BIT_MASK_QUEUEAC_Q5_V1 0x3 6810 #define BIT_QUEUEAC_Q5_V1(x) \ 6811 (((x) & BIT_MASK_QUEUEAC_Q5_V1) << BIT_SHIFT_QUEUEAC_Q5_V1) 6812 #define BIT_GET_QUEUEAC_Q5_V1(x) \ 6813 (((x) >> BIT_SHIFT_QUEUEAC_Q5_V1) & BIT_MASK_QUEUEAC_Q5_V1) 6814 6815 /* 2 REG_Q5_INFO (Offset 0x046C) */ 6816 6817 #define BIT_TIDEMPTY_Q5_V1 BIT(22) 6818 6819 /* 2 REG_Q5_INFO (Offset 0x046C) */ 6820 6821 #define BIT_SHIFT_TAIL_PKT_Q5_V2 11 6822 #define BIT_MASK_TAIL_PKT_Q5_V2 0x7ff 6823 #define BIT_TAIL_PKT_Q5_V2(x) \ 6824 (((x) & BIT_MASK_TAIL_PKT_Q5_V2) << BIT_SHIFT_TAIL_PKT_Q5_V2) 6825 #define BIT_GET_TAIL_PKT_Q5_V2(x) \ 6826 (((x) >> BIT_SHIFT_TAIL_PKT_Q5_V2) & BIT_MASK_TAIL_PKT_Q5_V2) 6827 6828 /* 2 REG_Q5_INFO (Offset 0x046C) */ 6829 6830 #define BIT_SHIFT_HEAD_PKT_Q5_V1 0 6831 #define BIT_MASK_HEAD_PKT_Q5_V1 0x7ff 6832 #define BIT_HEAD_PKT_Q5_V1(x) \ 6833 (((x) & BIT_MASK_HEAD_PKT_Q5_V1) << BIT_SHIFT_HEAD_PKT_Q5_V1) 6834 #define BIT_GET_HEAD_PKT_Q5_V1(x) \ 6835 (((x) >> BIT_SHIFT_HEAD_PKT_Q5_V1) & BIT_MASK_HEAD_PKT_Q5_V1) 6836 6837 /* 2 REG_Q6_INFO (Offset 0x0470) */ 6838 6839 #define BIT_SHIFT_QUEUEMACID_Q6_V1 25 6840 #define BIT_MASK_QUEUEMACID_Q6_V1 0x7f 6841 #define BIT_QUEUEMACID_Q6_V1(x) \ 6842 (((x) & BIT_MASK_QUEUEMACID_Q6_V1) << BIT_SHIFT_QUEUEMACID_Q6_V1) 6843 #define BIT_GET_QUEUEMACID_Q6_V1(x) \ 6844 (((x) >> BIT_SHIFT_QUEUEMACID_Q6_V1) & BIT_MASK_QUEUEMACID_Q6_V1) 6845 6846 #define BIT_SHIFT_QUEUEAC_Q6_V1 23 6847 #define BIT_MASK_QUEUEAC_Q6_V1 0x3 6848 #define BIT_QUEUEAC_Q6_V1(x) \ 6849 (((x) & BIT_MASK_QUEUEAC_Q6_V1) << BIT_SHIFT_QUEUEAC_Q6_V1) 6850 #define BIT_GET_QUEUEAC_Q6_V1(x) \ 6851 (((x) >> BIT_SHIFT_QUEUEAC_Q6_V1) & BIT_MASK_QUEUEAC_Q6_V1) 6852 6853 /* 2 REG_Q6_INFO (Offset 0x0470) */ 6854 6855 #define BIT_TIDEMPTY_Q6_V1 BIT(22) 6856 6857 /* 2 REG_Q6_INFO (Offset 0x0470) */ 6858 6859 #define BIT_SHIFT_TAIL_PKT_Q6_V2 11 6860 #define BIT_MASK_TAIL_PKT_Q6_V2 0x7ff 6861 #define BIT_TAIL_PKT_Q6_V2(x) \ 6862 (((x) & BIT_MASK_TAIL_PKT_Q6_V2) << BIT_SHIFT_TAIL_PKT_Q6_V2) 6863 #define BIT_GET_TAIL_PKT_Q6_V2(x) \ 6864 (((x) >> BIT_SHIFT_TAIL_PKT_Q6_V2) & BIT_MASK_TAIL_PKT_Q6_V2) 6865 6866 /* 2 REG_Q6_INFO (Offset 0x0470) */ 6867 6868 #define BIT_SHIFT_HEAD_PKT_Q6_V1 0 6869 #define BIT_MASK_HEAD_PKT_Q6_V1 0x7ff 6870 #define BIT_HEAD_PKT_Q6_V1(x) \ 6871 (((x) & BIT_MASK_HEAD_PKT_Q6_V1) << BIT_SHIFT_HEAD_PKT_Q6_V1) 6872 #define BIT_GET_HEAD_PKT_Q6_V1(x) \ 6873 (((x) >> BIT_SHIFT_HEAD_PKT_Q6_V1) & BIT_MASK_HEAD_PKT_Q6_V1) 6874 6875 /* 2 REG_Q7_INFO (Offset 0x0474) */ 6876 6877 #define BIT_SHIFT_QUEUEMACID_Q7_V1 25 6878 #define BIT_MASK_QUEUEMACID_Q7_V1 0x7f 6879 #define BIT_QUEUEMACID_Q7_V1(x) \ 6880 (((x) & BIT_MASK_QUEUEMACID_Q7_V1) << BIT_SHIFT_QUEUEMACID_Q7_V1) 6881 #define BIT_GET_QUEUEMACID_Q7_V1(x) \ 6882 (((x) >> BIT_SHIFT_QUEUEMACID_Q7_V1) & BIT_MASK_QUEUEMACID_Q7_V1) 6883 6884 #define BIT_SHIFT_QUEUEAC_Q7_V1 23 6885 #define BIT_MASK_QUEUEAC_Q7_V1 0x3 6886 #define BIT_QUEUEAC_Q7_V1(x) \ 6887 (((x) & BIT_MASK_QUEUEAC_Q7_V1) << BIT_SHIFT_QUEUEAC_Q7_V1) 6888 #define BIT_GET_QUEUEAC_Q7_V1(x) \ 6889 (((x) >> BIT_SHIFT_QUEUEAC_Q7_V1) & BIT_MASK_QUEUEAC_Q7_V1) 6890 6891 /* 2 REG_Q7_INFO (Offset 0x0474) */ 6892 6893 #define BIT_TIDEMPTY_Q7_V1 BIT(22) 6894 6895 /* 2 REG_Q7_INFO (Offset 0x0474) */ 6896 6897 #define BIT_SHIFT_TAIL_PKT_Q7_V2 11 6898 #define BIT_MASK_TAIL_PKT_Q7_V2 0x7ff 6899 #define BIT_TAIL_PKT_Q7_V2(x) \ 6900 (((x) & BIT_MASK_TAIL_PKT_Q7_V2) << BIT_SHIFT_TAIL_PKT_Q7_V2) 6901 #define BIT_GET_TAIL_PKT_Q7_V2(x) \ 6902 (((x) >> BIT_SHIFT_TAIL_PKT_Q7_V2) & BIT_MASK_TAIL_PKT_Q7_V2) 6903 6904 /* 2 REG_Q7_INFO (Offset 0x0474) */ 6905 6906 #define BIT_SHIFT_HEAD_PKT_Q7_V1 0 6907 #define BIT_MASK_HEAD_PKT_Q7_V1 0x7ff 6908 #define BIT_HEAD_PKT_Q7_V1(x) \ 6909 (((x) & BIT_MASK_HEAD_PKT_Q7_V1) << BIT_SHIFT_HEAD_PKT_Q7_V1) 6910 #define BIT_GET_HEAD_PKT_Q7_V1(x) \ 6911 (((x) >> BIT_SHIFT_HEAD_PKT_Q7_V1) & BIT_MASK_HEAD_PKT_Q7_V1) 6912 6913 /* 2 REG_WMAC_LBK_BUF_HD_V1 (Offset 0x0478) */ 6914 6915 #define BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1 0 6916 #define BIT_MASK_WMAC_LBK_BUF_HEAD_V1 0xfff 6917 #define BIT_WMAC_LBK_BUF_HEAD_V1(x) \ 6918 (((x) & BIT_MASK_WMAC_LBK_BUF_HEAD_V1) \ 6919 << BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) 6920 #define BIT_GET_WMAC_LBK_BUF_HEAD_V1(x) \ 6921 (((x) >> BIT_SHIFT_WMAC_LBK_BUF_HEAD_V1) & \ 6922 BIT_MASK_WMAC_LBK_BUF_HEAD_V1) 6923 6924 /* 2 REG_MGQ_BDNY_V1 (Offset 0x047A) */ 6925 6926 #define BIT_SHIFT_MGQ_PGBNDY_V1 0 6927 #define BIT_MASK_MGQ_PGBNDY_V1 0xfff 6928 #define BIT_MGQ_PGBNDY_V1(x) \ 6929 (((x) & BIT_MASK_MGQ_PGBNDY_V1) << BIT_SHIFT_MGQ_PGBNDY_V1) 6930 #define BIT_GET_MGQ_PGBNDY_V1(x) \ 6931 (((x) >> BIT_SHIFT_MGQ_PGBNDY_V1) & BIT_MASK_MGQ_PGBNDY_V1) 6932 6933 /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6934 6935 #define BIT_SHIFT_TRXRPT_TIMER_TH 24 6936 #define BIT_MASK_TRXRPT_TIMER_TH 0xff 6937 #define BIT_TRXRPT_TIMER_TH(x) \ 6938 (((x) & BIT_MASK_TRXRPT_TIMER_TH) << BIT_SHIFT_TRXRPT_TIMER_TH) 6939 #define BIT_GET_TRXRPT_TIMER_TH(x) \ 6940 (((x) >> BIT_SHIFT_TRXRPT_TIMER_TH) & BIT_MASK_TRXRPT_TIMER_TH) 6941 6942 /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6943 6944 #define BIT_SHIFT_TRXRPT_LEN_TH 16 6945 #define BIT_MASK_TRXRPT_LEN_TH 0xff 6946 #define BIT_TRXRPT_LEN_TH(x) \ 6947 (((x) & BIT_MASK_TRXRPT_LEN_TH) << BIT_SHIFT_TRXRPT_LEN_TH) 6948 #define BIT_GET_TRXRPT_LEN_TH(x) \ 6949 (((x) >> BIT_SHIFT_TRXRPT_LEN_TH) & BIT_MASK_TRXRPT_LEN_TH) 6950 6951 /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6952 6953 #define BIT_SHIFT_TRXRPT_READ_PTR 8 6954 #define BIT_MASK_TRXRPT_READ_PTR 0xff 6955 #define BIT_TRXRPT_READ_PTR(x) \ 6956 (((x) & BIT_MASK_TRXRPT_READ_PTR) << BIT_SHIFT_TRXRPT_READ_PTR) 6957 #define BIT_GET_TRXRPT_READ_PTR(x) \ 6958 (((x) >> BIT_SHIFT_TRXRPT_READ_PTR) & BIT_MASK_TRXRPT_READ_PTR) 6959 6960 /* 2 REG_TXRPT_CTRL (Offset 0x047C) */ 6961 6962 #define BIT_SHIFT_TRXRPT_WRITE_PTR 0 6963 #define BIT_MASK_TRXRPT_WRITE_PTR 0xff 6964 #define BIT_TRXRPT_WRITE_PTR(x) \ 6965 (((x) & BIT_MASK_TRXRPT_WRITE_PTR) << BIT_SHIFT_TRXRPT_WRITE_PTR) 6966 #define BIT_GET_TRXRPT_WRITE_PTR(x) \ 6967 (((x) >> BIT_SHIFT_TRXRPT_WRITE_PTR) & BIT_MASK_TRXRPT_WRITE_PTR) 6968 6969 /* 2 REG_INIRTS_RATE_SEL (Offset 0x0480) */ 6970 6971 #define BIT_LEAG_RTS_BW_DUP BIT(5) 6972 6973 /* 2 REG_BASIC_CFEND_RATE (Offset 0x0481) */ 6974 6975 #define BIT_SHIFT_BASIC_CFEND_RATE 0 6976 #define BIT_MASK_BASIC_CFEND_RATE 0x1f 6977 #define BIT_BASIC_CFEND_RATE(x) \ 6978 (((x) & BIT_MASK_BASIC_CFEND_RATE) << BIT_SHIFT_BASIC_CFEND_RATE) 6979 #define BIT_GET_BASIC_CFEND_RATE(x) \ 6980 (((x) >> BIT_SHIFT_BASIC_CFEND_RATE) & BIT_MASK_BASIC_CFEND_RATE) 6981 6982 /* 2 REG_STBC_CFEND_RATE (Offset 0x0482) */ 6983 6984 #define BIT_SHIFT_STBC_CFEND_RATE 0 6985 #define BIT_MASK_STBC_CFEND_RATE 0x1f 6986 #define BIT_STBC_CFEND_RATE(x) \ 6987 (((x) & BIT_MASK_STBC_CFEND_RATE) << BIT_SHIFT_STBC_CFEND_RATE) 6988 #define BIT_GET_STBC_CFEND_RATE(x) \ 6989 (((x) >> BIT_SHIFT_STBC_CFEND_RATE) & BIT_MASK_STBC_CFEND_RATE) 6990 6991 /* 2 REG_DATA_SC (Offset 0x0483) */ 6992 6993 #define BIT_SHIFT_TXSC_40M 4 6994 #define BIT_MASK_TXSC_40M 0xf 6995 #define BIT_TXSC_40M(x) (((x) & BIT_MASK_TXSC_40M) << BIT_SHIFT_TXSC_40M) 6996 #define BIT_GET_TXSC_40M(x) (((x) >> BIT_SHIFT_TXSC_40M) & BIT_MASK_TXSC_40M) 6997 6998 #define BIT_SHIFT_TXSC_20M 0 6999 #define BIT_MASK_TXSC_20M 0xf 7000 #define BIT_TXSC_20M(x) (((x) & BIT_MASK_TXSC_20M) << BIT_SHIFT_TXSC_20M) 7001 #define BIT_GET_TXSC_20M(x) (((x) >> BIT_SHIFT_TXSC_20M) & BIT_MASK_TXSC_20M) 7002 7003 /* 2 REG_MACID_SLEEP3 (Offset 0x0484) */ 7004 7005 #define BIT_SHIFT_MACID127_96_PKTSLEEP 0 7006 #define BIT_MASK_MACID127_96_PKTSLEEP 0xffffffffL 7007 #define BIT_MACID127_96_PKTSLEEP(x) \ 7008 (((x) & BIT_MASK_MACID127_96_PKTSLEEP) \ 7009 << BIT_SHIFT_MACID127_96_PKTSLEEP) 7010 #define BIT_GET_MACID127_96_PKTSLEEP(x) \ 7011 (((x) >> BIT_SHIFT_MACID127_96_PKTSLEEP) & \ 7012 BIT_MASK_MACID127_96_PKTSLEEP) 7013 7014 /* 2 REG_MACID_SLEEP1 (Offset 0x0488) */ 7015 7016 #define BIT_SHIFT_MACID63_32_PKTSLEEP 0 7017 #define BIT_MASK_MACID63_32_PKTSLEEP 0xffffffffL 7018 #define BIT_MACID63_32_PKTSLEEP(x) \ 7019 (((x) & BIT_MASK_MACID63_32_PKTSLEEP) << BIT_SHIFT_MACID63_32_PKTSLEEP) 7020 #define BIT_GET_MACID63_32_PKTSLEEP(x) \ 7021 (((x) >> BIT_SHIFT_MACID63_32_PKTSLEEP) & BIT_MASK_MACID63_32_PKTSLEEP) 7022 7023 /* 2 REG_ARFR2_V1 (Offset 0x048C) */ 7024 7025 #define BIT_SHIFT_ARFR2_V1 0 7026 #define BIT_MASK_ARFR2_V1 0xffffffffffffffffL 7027 #define BIT_ARFR2_V1(x) (((x) & BIT_MASK_ARFR2_V1) << BIT_SHIFT_ARFR2_V1) 7028 #define BIT_GET_ARFR2_V1(x) (((x) >> BIT_SHIFT_ARFR2_V1) & BIT_MASK_ARFR2_V1) 7029 7030 /* 2 REG_ARFR3_V1 (Offset 0x0494) */ 7031 7032 #define BIT_SHIFT_ARFR3_V1 0 7033 #define BIT_MASK_ARFR3_V1 0xffffffffffffffffL 7034 #define BIT_ARFR3_V1(x) (((x) & BIT_MASK_ARFR3_V1) << BIT_SHIFT_ARFR3_V1) 7035 #define BIT_GET_ARFR3_V1(x) (((x) >> BIT_SHIFT_ARFR3_V1) & BIT_MASK_ARFR3_V1) 7036 7037 /* 2 REG_ARFR4 (Offset 0x049C) */ 7038 7039 #define BIT_SHIFT_ARFR4 0 7040 #define BIT_MASK_ARFR4 0xffffffffffffffffL 7041 #define BIT_ARFR4(x) (((x) & BIT_MASK_ARFR4) << BIT_SHIFT_ARFR4) 7042 #define BIT_GET_ARFR4(x) (((x) >> BIT_SHIFT_ARFR4) & BIT_MASK_ARFR4) 7043 7044 /* 2 REG_ARFR5 (Offset 0x04A4) */ 7045 7046 #define BIT_SHIFT_ARFR5 0 7047 #define BIT_MASK_ARFR5 0xffffffffffffffffL 7048 #define BIT_ARFR5(x) (((x) & BIT_MASK_ARFR5) << BIT_SHIFT_ARFR5) 7049 #define BIT_GET_ARFR5(x) (((x) >> BIT_SHIFT_ARFR5) & BIT_MASK_ARFR5) 7050 7051 /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7052 7053 #define BIT_SHIFT_MACID_MURATE_OFFSET 24 7054 #define BIT_MASK_MACID_MURATE_OFFSET 0xff 7055 #define BIT_MACID_MURATE_OFFSET(x) \ 7056 (((x) & BIT_MASK_MACID_MURATE_OFFSET) << BIT_SHIFT_MACID_MURATE_OFFSET) 7057 #define BIT_GET_MACID_MURATE_OFFSET(x) \ 7058 (((x) >> BIT_SHIFT_MACID_MURATE_OFFSET) & BIT_MASK_MACID_MURATE_OFFSET) 7059 7060 /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7061 7062 #define BIT_RPTFIFO_SIZE_OPT BIT(16) 7063 7064 /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7065 7066 #define BIT_SHIFT_MACID_CTRL_OFFSET 8 7067 #define BIT_MASK_MACID_CTRL_OFFSET 0xff 7068 #define BIT_MACID_CTRL_OFFSET(x) \ 7069 (((x) & BIT_MASK_MACID_CTRL_OFFSET) << BIT_SHIFT_MACID_CTRL_OFFSET) 7070 #define BIT_GET_MACID_CTRL_OFFSET(x) \ 7071 (((x) >> BIT_SHIFT_MACID_CTRL_OFFSET) & BIT_MASK_MACID_CTRL_OFFSET) 7072 7073 /* 2 REG_TXRPT_START_OFFSET (Offset 0x04AC) */ 7074 7075 #define BIT_SHIFT_AMPDU_TXRPT_OFFSET 0 7076 #define BIT_MASK_AMPDU_TXRPT_OFFSET 0xff 7077 #define BIT_AMPDU_TXRPT_OFFSET(x) \ 7078 (((x) & BIT_MASK_AMPDU_TXRPT_OFFSET) << BIT_SHIFT_AMPDU_TXRPT_OFFSET) 7079 #define BIT_GET_AMPDU_TXRPT_OFFSET(x) \ 7080 (((x) >> BIT_SHIFT_AMPDU_TXRPT_OFFSET) & BIT_MASK_AMPDU_TXRPT_OFFSET) 7081 7082 /* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ 7083 7084 #define BIT_PTA_WL_PRI_MASK_CPU_MGQ BIT(31) 7085 #define BIT_PTA_WL_PRI_MASK_BCNQ BIT(30) 7086 #define BIT_PTA_WL_PRI_MASK_HIQ BIT(29) 7087 #define BIT_PTA_WL_PRI_MASK_MGQ BIT(28) 7088 #define BIT_PTA_WL_PRI_MASK_BK BIT(27) 7089 #define BIT_PTA_WL_PRI_MASK_BE BIT(26) 7090 #define BIT_PTA_WL_PRI_MASK_VI BIT(25) 7091 #define BIT_PTA_WL_PRI_MASK_VO BIT(24) 7092 7093 /* 2 REG_POWER_STAGE1 (Offset 0x04B4) */ 7094 7095 #define BIT_SHIFT_POWER_STAGE1 0 7096 #define BIT_MASK_POWER_STAGE1 0xffffff 7097 #define BIT_POWER_STAGE1(x) \ 7098 (((x) & BIT_MASK_POWER_STAGE1) << BIT_SHIFT_POWER_STAGE1) 7099 #define BIT_GET_POWER_STAGE1(x) \ 7100 (((x) >> BIT_SHIFT_POWER_STAGE1) & BIT_MASK_POWER_STAGE1) 7101 7102 /* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ 7103 7104 #define BIT__R_CTRL_PKT_POW_ADJ BIT(24) 7105 7106 /* 2 REG_POWER_STAGE2 (Offset 0x04B8) */ 7107 7108 #define BIT_SHIFT_POWER_STAGE2 0 7109 #define BIT_MASK_POWER_STAGE2 0xffffff 7110 #define BIT_POWER_STAGE2(x) \ 7111 (((x) & BIT_MASK_POWER_STAGE2) << BIT_SHIFT_POWER_STAGE2) 7112 #define BIT_GET_POWER_STAGE2(x) \ 7113 (((x) >> BIT_SHIFT_POWER_STAGE2) & BIT_MASK_POWER_STAGE2) 7114 7115 /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7116 7117 #define BIT_SHIFT_PAD_NUM_THRES 24 7118 #define BIT_MASK_PAD_NUM_THRES 0x3f 7119 #define BIT_PAD_NUM_THRES(x) \ 7120 (((x) & BIT_MASK_PAD_NUM_THRES) << BIT_SHIFT_PAD_NUM_THRES) 7121 #define BIT_GET_PAD_NUM_THRES(x) \ 7122 (((x) >> BIT_SHIFT_PAD_NUM_THRES) & BIT_MASK_PAD_NUM_THRES) 7123 7124 /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7125 7126 #define BIT_R_DMA_THIS_QUEUE_BK BIT(23) 7127 #define BIT_R_DMA_THIS_QUEUE_BE BIT(22) 7128 #define BIT_R_DMA_THIS_QUEUE_VI BIT(21) 7129 #define BIT_R_DMA_THIS_QUEUE_VO BIT(20) 7130 7131 #define BIT_SHIFT_R_TOTAL_LEN_TH 8 7132 #define BIT_MASK_R_TOTAL_LEN_TH 0xfff 7133 #define BIT_R_TOTAL_LEN_TH(x) \ 7134 (((x) & BIT_MASK_R_TOTAL_LEN_TH) << BIT_SHIFT_R_TOTAL_LEN_TH) 7135 #define BIT_GET_R_TOTAL_LEN_TH(x) \ 7136 (((x) >> BIT_SHIFT_R_TOTAL_LEN_TH) & BIT_MASK_R_TOTAL_LEN_TH) 7137 7138 /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7139 7140 #define BIT_EN_NEW_EARLY BIT(7) 7141 7142 /* 2 REG_SW_AMPDU_BURST_MODE_CTRL (Offset 0x04BC) */ 7143 7144 #define BIT_PRE_TX_CMD BIT(6) 7145 7146 #define BIT_SHIFT_NUM_SCL_EN 4 7147 #define BIT_MASK_NUM_SCL_EN 0x3 7148 #define BIT_NUM_SCL_EN(x) (((x) & BIT_MASK_NUM_SCL_EN) << BIT_SHIFT_NUM_SCL_EN) 7149 #define BIT_GET_NUM_SCL_EN(x) \ 7150 (((x) >> BIT_SHIFT_NUM_SCL_EN) & BIT_MASK_NUM_SCL_EN) 7151 7152 #define BIT_BK_EN BIT(3) 7153 #define BIT_BE_EN BIT(2) 7154 #define BIT_VI_EN BIT(1) 7155 #define BIT_VO_EN BIT(0) 7156 7157 /* 2 REG_PKT_LIFE_TIME (Offset 0x04C0) */ 7158 7159 #define BIT_SHIFT_PKT_LIFTIME_BEBK 16 7160 #define BIT_MASK_PKT_LIFTIME_BEBK 0xffff 7161 #define BIT_PKT_LIFTIME_BEBK(x) \ 7162 (((x) & BIT_MASK_PKT_LIFTIME_BEBK) << BIT_SHIFT_PKT_LIFTIME_BEBK) 7163 #define BIT_GET_PKT_LIFTIME_BEBK(x) \ 7164 (((x) >> BIT_SHIFT_PKT_LIFTIME_BEBK) & BIT_MASK_PKT_LIFTIME_BEBK) 7165 7166 #define BIT_SHIFT_PKT_LIFTIME_VOVI 0 7167 #define BIT_MASK_PKT_LIFTIME_VOVI 0xffff 7168 #define BIT_PKT_LIFTIME_VOVI(x) \ 7169 (((x) & BIT_MASK_PKT_LIFTIME_VOVI) << BIT_SHIFT_PKT_LIFTIME_VOVI) 7170 #define BIT_GET_PKT_LIFTIME_VOVI(x) \ 7171 (((x) >> BIT_SHIFT_PKT_LIFTIME_VOVI) & BIT_MASK_PKT_LIFTIME_VOVI) 7172 7173 /* 2 REG_STBC_SETTING (Offset 0x04C4) */ 7174 7175 #define BIT_SHIFT_CDEND_TXTIME_L 4 7176 #define BIT_MASK_CDEND_TXTIME_L 0xf 7177 #define BIT_CDEND_TXTIME_L(x) \ 7178 (((x) & BIT_MASK_CDEND_TXTIME_L) << BIT_SHIFT_CDEND_TXTIME_L) 7179 #define BIT_GET_CDEND_TXTIME_L(x) \ 7180 (((x) >> BIT_SHIFT_CDEND_TXTIME_L) & BIT_MASK_CDEND_TXTIME_L) 7181 7182 #define BIT_SHIFT_NESS 2 7183 #define BIT_MASK_NESS 0x3 7184 #define BIT_NESS(x) (((x) & BIT_MASK_NESS) << BIT_SHIFT_NESS) 7185 #define BIT_GET_NESS(x) (((x) >> BIT_SHIFT_NESS) & BIT_MASK_NESS) 7186 7187 #define BIT_SHIFT_STBC_CFEND 0 7188 #define BIT_MASK_STBC_CFEND 0x3 7189 #define BIT_STBC_CFEND(x) (((x) & BIT_MASK_STBC_CFEND) << BIT_SHIFT_STBC_CFEND) 7190 #define BIT_GET_STBC_CFEND(x) \ 7191 (((x) >> BIT_SHIFT_STBC_CFEND) & BIT_MASK_STBC_CFEND) 7192 7193 /* 2 REG_STBC_SETTING2 (Offset 0x04C5) */ 7194 7195 #define BIT_SHIFT_CDEND_TXTIME_H 0 7196 #define BIT_MASK_CDEND_TXTIME_H 0x1f 7197 #define BIT_CDEND_TXTIME_H(x) \ 7198 (((x) & BIT_MASK_CDEND_TXTIME_H) << BIT_SHIFT_CDEND_TXTIME_H) 7199 #define BIT_GET_CDEND_TXTIME_H(x) \ 7200 (((x) >> BIT_SHIFT_CDEND_TXTIME_H) & BIT_MASK_CDEND_TXTIME_H) 7201 7202 /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ 7203 7204 #define BIT_PTA_EDCCA_EN BIT(5) 7205 #define BIT_PTA_WL_TX_EN BIT(4) 7206 7207 /* 2 REG_QUEUE_CTRL (Offset 0x04C6) */ 7208 7209 #define BIT_R_USE_DATA_BW BIT(3) 7210 #define BIT_TRI_PKT_INT_MODE1 BIT(2) 7211 #define BIT_TRI_PKT_INT_MODE0 BIT(1) 7212 #define BIT_ACQ_MODE_SEL BIT(0) 7213 7214 /* 2 REG_SINGLE_AMPDU_CTRL (Offset 0x04C7) */ 7215 7216 #define BIT_EN_SINGLE_APMDU BIT(7) 7217 7218 /* 2 REG_PROT_MODE_CTRL (Offset 0x04C8) */ 7219 7220 #define BIT_SHIFT_RTS_MAX_AGG_NUM 24 7221 #define BIT_MASK_RTS_MAX_AGG_NUM 0x3f 7222 #define BIT_RTS_MAX_AGG_NUM(x) \ 7223 (((x) & BIT_MASK_RTS_MAX_AGG_NUM) << BIT_SHIFT_RTS_MAX_AGG_NUM) 7224 #define BIT_GET_RTS_MAX_AGG_NUM(x) \ 7225 (((x) >> BIT_SHIFT_RTS_MAX_AGG_NUM) & BIT_MASK_RTS_MAX_AGG_NUM) 7226 7227 #define BIT_SHIFT_MAX_AGG_NUM 16 7228 #define BIT_MASK_MAX_AGG_NUM 0x3f 7229 #define BIT_MAX_AGG_NUM(x) \ 7230 (((x) & BIT_MASK_MAX_AGG_NUM) << BIT_SHIFT_MAX_AGG_NUM) 7231 #define BIT_GET_MAX_AGG_NUM(x) \ 7232 (((x) >> BIT_SHIFT_MAX_AGG_NUM) & BIT_MASK_MAX_AGG_NUM) 7233 7234 #define BIT_SHIFT_RTS_TXTIME_TH 8 7235 #define BIT_MASK_RTS_TXTIME_TH 0xff 7236 #define BIT_RTS_TXTIME_TH(x) \ 7237 (((x) & BIT_MASK_RTS_TXTIME_TH) << BIT_SHIFT_RTS_TXTIME_TH) 7238 #define BIT_GET_RTS_TXTIME_TH(x) \ 7239 (((x) >> BIT_SHIFT_RTS_TXTIME_TH) & BIT_MASK_RTS_TXTIME_TH) 7240 7241 #define BIT_SHIFT_RTS_LEN_TH 0 7242 #define BIT_MASK_RTS_LEN_TH 0xff 7243 #define BIT_RTS_LEN_TH(x) (((x) & BIT_MASK_RTS_LEN_TH) << BIT_SHIFT_RTS_LEN_TH) 7244 #define BIT_GET_RTS_LEN_TH(x) \ 7245 (((x) >> BIT_SHIFT_RTS_LEN_TH) & BIT_MASK_RTS_LEN_TH) 7246 7247 /* 2 REG_BAR_MODE_CTRL (Offset 0x04CC) */ 7248 7249 #define BIT_SHIFT_BAR_RTY_LMT 16 7250 #define BIT_MASK_BAR_RTY_LMT 0x3 7251 #define BIT_BAR_RTY_LMT(x) \ 7252 (((x) & BIT_MASK_BAR_RTY_LMT) << BIT_SHIFT_BAR_RTY_LMT) 7253 #define BIT_GET_BAR_RTY_LMT(x) \ 7254 (((x) >> BIT_SHIFT_BAR_RTY_LMT) & BIT_MASK_BAR_RTY_LMT) 7255 7256 #define BIT_SHIFT_BAR_PKT_TXTIME_TH 8 7257 #define BIT_MASK_BAR_PKT_TXTIME_TH 0xff 7258 #define BIT_BAR_PKT_TXTIME_TH(x) \ 7259 (((x) & BIT_MASK_BAR_PKT_TXTIME_TH) << BIT_SHIFT_BAR_PKT_TXTIME_TH) 7260 #define BIT_GET_BAR_PKT_TXTIME_TH(x) \ 7261 (((x) >> BIT_SHIFT_BAR_PKT_TXTIME_TH) & BIT_MASK_BAR_PKT_TXTIME_TH) 7262 7263 #define BIT_BAR_EN_V1 BIT(6) 7264 7265 #define BIT_SHIFT_BAR_PKTNUM_TH_V1 0 7266 #define BIT_MASK_BAR_PKTNUM_TH_V1 0x3f 7267 #define BIT_BAR_PKTNUM_TH_V1(x) \ 7268 (((x) & BIT_MASK_BAR_PKTNUM_TH_V1) << BIT_SHIFT_BAR_PKTNUM_TH_V1) 7269 #define BIT_GET_BAR_PKTNUM_TH_V1(x) \ 7270 (((x) >> BIT_SHIFT_BAR_PKTNUM_TH_V1) & BIT_MASK_BAR_PKTNUM_TH_V1) 7271 7272 /* 2 REG_RA_TRY_RATE_AGG_LMT (Offset 0x04CF) */ 7273 7274 #define BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1 0 7275 #define BIT_MASK_RA_TRY_RATE_AGG_LMT_V1 0x3f 7276 #define BIT_RA_TRY_RATE_AGG_LMT_V1(x) \ 7277 (((x) & BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) \ 7278 << BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) 7279 #define BIT_GET_RA_TRY_RATE_AGG_LMT_V1(x) \ 7280 (((x) >> BIT_SHIFT_RA_TRY_RATE_AGG_LMT_V1) & \ 7281 BIT_MASK_RA_TRY_RATE_AGG_LMT_V1) 7282 7283 /* 2 REG_MACID_SLEEP2 (Offset 0x04D0) */ 7284 7285 #define BIT_SHIFT_MACID95_64PKTSLEEP 0 7286 #define BIT_MASK_MACID95_64PKTSLEEP 0xffffffffL 7287 #define BIT_MACID95_64PKTSLEEP(x) \ 7288 (((x) & BIT_MASK_MACID95_64PKTSLEEP) << BIT_SHIFT_MACID95_64PKTSLEEP) 7289 #define BIT_GET_MACID95_64PKTSLEEP(x) \ 7290 (((x) >> BIT_SHIFT_MACID95_64PKTSLEEP) & BIT_MASK_MACID95_64PKTSLEEP) 7291 7292 /* 2 REG_MACID_SLEEP (Offset 0x04D4) */ 7293 7294 #define BIT_SHIFT_MACID31_0_PKTSLEEP 0 7295 #define BIT_MASK_MACID31_0_PKTSLEEP 0xffffffffL 7296 #define BIT_MACID31_0_PKTSLEEP(x) \ 7297 (((x) & BIT_MASK_MACID31_0_PKTSLEEP) << BIT_SHIFT_MACID31_0_PKTSLEEP) 7298 #define BIT_GET_MACID31_0_PKTSLEEP(x) \ 7299 (((x) >> BIT_SHIFT_MACID31_0_PKTSLEEP) & BIT_MASK_MACID31_0_PKTSLEEP) 7300 7301 /* 2 REG_HW_SEQ0 (Offset 0x04D8) */ 7302 7303 #define BIT_SHIFT_HW_SSN_SEQ0 0 7304 #define BIT_MASK_HW_SSN_SEQ0 0xfff 7305 #define BIT_HW_SSN_SEQ0(x) \ 7306 (((x) & BIT_MASK_HW_SSN_SEQ0) << BIT_SHIFT_HW_SSN_SEQ0) 7307 #define BIT_GET_HW_SSN_SEQ0(x) \ 7308 (((x) >> BIT_SHIFT_HW_SSN_SEQ0) & BIT_MASK_HW_SSN_SEQ0) 7309 7310 /* 2 REG_HW_SEQ1 (Offset 0x04DA) */ 7311 7312 #define BIT_SHIFT_HW_SSN_SEQ1 0 7313 #define BIT_MASK_HW_SSN_SEQ1 0xfff 7314 #define BIT_HW_SSN_SEQ1(x) \ 7315 (((x) & BIT_MASK_HW_SSN_SEQ1) << BIT_SHIFT_HW_SSN_SEQ1) 7316 #define BIT_GET_HW_SSN_SEQ1(x) \ 7317 (((x) >> BIT_SHIFT_HW_SSN_SEQ1) & BIT_MASK_HW_SSN_SEQ1) 7318 7319 /* 2 REG_HW_SEQ2 (Offset 0x04DC) */ 7320 7321 #define BIT_SHIFT_HW_SSN_SEQ2 0 7322 #define BIT_MASK_HW_SSN_SEQ2 0xfff 7323 #define BIT_HW_SSN_SEQ2(x) \ 7324 (((x) & BIT_MASK_HW_SSN_SEQ2) << BIT_SHIFT_HW_SSN_SEQ2) 7325 #define BIT_GET_HW_SSN_SEQ2(x) \ 7326 (((x) >> BIT_SHIFT_HW_SSN_SEQ2) & BIT_MASK_HW_SSN_SEQ2) 7327 7328 /* 2 REG_HW_SEQ3 (Offset 0x04DE) */ 7329 7330 #define BIT_SHIFT_HW_SSN_SEQ3 0 7331 #define BIT_MASK_HW_SSN_SEQ3 0xfff 7332 #define BIT_HW_SSN_SEQ3(x) \ 7333 (((x) & BIT_MASK_HW_SSN_SEQ3) << BIT_SHIFT_HW_SSN_SEQ3) 7334 #define BIT_GET_HW_SSN_SEQ3(x) \ 7335 (((x) >> BIT_SHIFT_HW_SSN_SEQ3) & BIT_MASK_HW_SSN_SEQ3) 7336 7337 /* 2 REG_NULL_PKT_STATUS_V1 (Offset 0x04E0) */ 7338 7339 #define BIT_SHIFT_PTCL_TOTAL_PG_V2 2 7340 #define BIT_MASK_PTCL_TOTAL_PG_V2 0x3fff 7341 #define BIT_PTCL_TOTAL_PG_V2(x) \ 7342 (((x) & BIT_MASK_PTCL_TOTAL_PG_V2) << BIT_SHIFT_PTCL_TOTAL_PG_V2) 7343 #define BIT_GET_PTCL_TOTAL_PG_V2(x) \ 7344 (((x) >> BIT_SHIFT_PTCL_TOTAL_PG_V2) & BIT_MASK_PTCL_TOTAL_PG_V2) 7345 7346 /* 2 REG_NULL_PKT_STATUS (Offset 0x04E0) */ 7347 7348 #define BIT_TX_NULL_1 BIT(1) 7349 #define BIT_TX_NULL_0 BIT(0) 7350 7351 /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ 7352 7353 #define BIT_PTCL_RATE_TABLE_INVALID BIT(7) 7354 #define BIT_FTM_T2R_ERROR BIT(6) 7355 7356 /* 2 REG_PTCL_ERR_STATUS (Offset 0x04E2) */ 7357 7358 #define BIT_PTCL_ERR0 BIT(5) 7359 #define BIT_PTCL_ERR1 BIT(4) 7360 #define BIT_PTCL_ERR2 BIT(3) 7361 #define BIT_PTCL_ERR3 BIT(2) 7362 #define BIT_PTCL_ERR4 BIT(1) 7363 #define BIT_PTCL_ERR5 BIT(0) 7364 7365 /* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ 7366 7367 #define BIT_CLI3_TX_NULL_1 BIT(7) 7368 #define BIT_CLI3_TX_NULL_0 BIT(6) 7369 #define BIT_CLI2_TX_NULL_1 BIT(5) 7370 #define BIT_CLI2_TX_NULL_0 BIT(4) 7371 #define BIT_CLI1_TX_NULL_1 BIT(3) 7372 #define BIT_CLI1_TX_NULL_0 BIT(2) 7373 #define BIT_CLI0_TX_NULL_1 BIT(1) 7374 7375 /* 2 REG_NULL_PKT_STATUS_EXTEND (Offset 0x04E3) */ 7376 7377 #define BIT_CLI0_TX_NULL_0 BIT(0) 7378 7379 /* 2 REG_VIDEO_ENHANCEMENT_FUN (Offset 0x04E4) */ 7380 7381 #define BIT_VIDEO_JUST_DROP BIT(1) 7382 #define BIT_VIDEO_ENHANCEMENT_FUN_EN BIT(0) 7383 7384 /* 2 REG_BT_POLLUTE_PKT_CNT (Offset 0x04E8) */ 7385 7386 #define BIT_SHIFT_BT_POLLUTE_PKT_CNT 0 7387 #define BIT_MASK_BT_POLLUTE_PKT_CNT 0xffff 7388 #define BIT_BT_POLLUTE_PKT_CNT(x) \ 7389 (((x) & BIT_MASK_BT_POLLUTE_PKT_CNT) << BIT_SHIFT_BT_POLLUTE_PKT_CNT) 7390 #define BIT_GET_BT_POLLUTE_PKT_CNT(x) \ 7391 (((x) >> BIT_SHIFT_BT_POLLUTE_PKT_CNT) & BIT_MASK_BT_POLLUTE_PKT_CNT) 7392 7393 /* 2 REG_PTCL_DBG (Offset 0x04EC) */ 7394 7395 #define BIT_SHIFT_PTCL_DBG 0 7396 #define BIT_MASK_PTCL_DBG 0xffffffffL 7397 #define BIT_PTCL_DBG(x) (((x) & BIT_MASK_PTCL_DBG) << BIT_SHIFT_PTCL_DBG) 7398 #define BIT_GET_PTCL_DBG(x) (((x) >> BIT_SHIFT_PTCL_DBG) & BIT_MASK_PTCL_DBG) 7399 7400 /* 2 REG_CPUMGQ_TIMER_CTRL2 (Offset 0x04F4) */ 7401 7402 #define BIT_QUEUE_MACID_AC_NOT_THE_SAME BIT(31) 7403 7404 #define BIT_SHIFT_GTAB_ID 28 7405 #define BIT_MASK_GTAB_ID 0x7 7406 #define BIT_GTAB_ID(x) (((x) & BIT_MASK_GTAB_ID) << BIT_SHIFT_GTAB_ID) 7407 #define BIT_GET_GTAB_ID(x) (((x) >> BIT_SHIFT_GTAB_ID) & BIT_MASK_GTAB_ID) 7408 7409 #define BIT_SHIFT_TRI_HEAD_ADDR 16 7410 #define BIT_MASK_TRI_HEAD_ADDR 0xfff 7411 #define BIT_TRI_HEAD_ADDR(x) \ 7412 (((x) & BIT_MASK_TRI_HEAD_ADDR) << BIT_SHIFT_TRI_HEAD_ADDR) 7413 #define BIT_GET_TRI_HEAD_ADDR(x) \ 7414 (((x) >> BIT_SHIFT_TRI_HEAD_ADDR) & BIT_MASK_TRI_HEAD_ADDR) 7415 7416 #define BIT_QUEUE_MACID_AC_NOT_THE_SAME_V1 BIT(15) 7417 7418 #define BIT_SHIFT_GTAB_ID_V1 12 7419 #define BIT_MASK_GTAB_ID_V1 0x7 7420 #define BIT_GTAB_ID_V1(x) (((x) & BIT_MASK_GTAB_ID_V1) << BIT_SHIFT_GTAB_ID_V1) 7421 #define BIT_GET_GTAB_ID_V1(x) \ 7422 (((x) >> BIT_SHIFT_GTAB_ID_V1) & BIT_MASK_GTAB_ID_V1) 7423 7424 #define BIT_DROP_TH_EN BIT(8) 7425 7426 #define BIT_SHIFT_DROP_TH 0 7427 #define BIT_MASK_DROP_TH 0xff 7428 #define BIT_DROP_TH(x) (((x) & BIT_MASK_DROP_TH) << BIT_SHIFT_DROP_TH) 7429 #define BIT_GET_DROP_TH(x) (((x) >> BIT_SHIFT_DROP_TH) & BIT_MASK_DROP_TH) 7430 7431 /* 2 REG_DUMMY_PAGE4_V1 (Offset 0x04FC) */ 7432 7433 #define BIT_BCN_EN_EXTHWSEQ BIT(1) 7434 #define BIT_BCN_EN_HWSEQ BIT(0) 7435 7436 /* 2 REG_MOREDATA (Offset 0x04FE) */ 7437 7438 #define BIT_MOREDATA_CTRL2_EN_V1 BIT(3) 7439 #define BIT_MOREDATA_CTRL1_EN_V1 BIT(2) 7440 #define BIT_PKTIN_MOREDATA_REPLACE_ENABLE_V1 BIT(0) 7441 7442 /* 2 REG_EDCA_VO_PARAM (Offset 0x0500) */ 7443 7444 #define BIT_SHIFT_TXOPLIMIT 16 7445 #define BIT_MASK_TXOPLIMIT 0x7ff 7446 #define BIT_TXOPLIMIT(x) (((x) & BIT_MASK_TXOPLIMIT) << BIT_SHIFT_TXOPLIMIT) 7447 #define BIT_GET_TXOPLIMIT(x) (((x) >> BIT_SHIFT_TXOPLIMIT) & BIT_MASK_TXOPLIMIT) 7448 7449 #define BIT_SHIFT_CW 8 7450 #define BIT_MASK_CW 0xff 7451 #define BIT_CW(x) (((x) & BIT_MASK_CW) << BIT_SHIFT_CW) 7452 #define BIT_GET_CW(x) (((x) >> BIT_SHIFT_CW) & BIT_MASK_CW) 7453 7454 #define BIT_SHIFT_AIFS 0 7455 #define BIT_MASK_AIFS 0xff 7456 #define BIT_AIFS(x) (((x) & BIT_MASK_AIFS) << BIT_SHIFT_AIFS) 7457 #define BIT_GET_AIFS(x) (((x) >> BIT_SHIFT_AIFS) & BIT_MASK_AIFS) 7458 7459 /* 2 REG_BCNTCFG (Offset 0x0510) */ 7460 7461 #define BIT_SHIFT_BCNCW_MAX 12 7462 #define BIT_MASK_BCNCW_MAX 0xf 7463 #define BIT_BCNCW_MAX(x) (((x) & BIT_MASK_BCNCW_MAX) << BIT_SHIFT_BCNCW_MAX) 7464 #define BIT_GET_BCNCW_MAX(x) (((x) >> BIT_SHIFT_BCNCW_MAX) & BIT_MASK_BCNCW_MAX) 7465 7466 #define BIT_SHIFT_BCNCW_MIN 8 7467 #define BIT_MASK_BCNCW_MIN 0xf 7468 #define BIT_BCNCW_MIN(x) (((x) & BIT_MASK_BCNCW_MIN) << BIT_SHIFT_BCNCW_MIN) 7469 #define BIT_GET_BCNCW_MIN(x) (((x) >> BIT_SHIFT_BCNCW_MIN) & BIT_MASK_BCNCW_MIN) 7470 7471 #define BIT_SHIFT_BCNIFS 0 7472 #define BIT_MASK_BCNIFS 0xff 7473 #define BIT_BCNIFS(x) (((x) & BIT_MASK_BCNIFS) << BIT_SHIFT_BCNIFS) 7474 #define BIT_GET_BCNIFS(x) (((x) >> BIT_SHIFT_BCNIFS) & BIT_MASK_BCNIFS) 7475 7476 /* 2 REG_PIFS (Offset 0x0512) */ 7477 7478 #define BIT_SHIFT_PIFS 0 7479 #define BIT_MASK_PIFS 0xff 7480 #define BIT_PIFS(x) (((x) & BIT_MASK_PIFS) << BIT_SHIFT_PIFS) 7481 #define BIT_GET_PIFS(x) (((x) >> BIT_SHIFT_PIFS) & BIT_MASK_PIFS) 7482 7483 /* 2 REG_RDG_PIFS (Offset 0x0513) */ 7484 7485 #define BIT_SHIFT_RDG_PIFS 0 7486 #define BIT_MASK_RDG_PIFS 0xff 7487 #define BIT_RDG_PIFS(x) (((x) & BIT_MASK_RDG_PIFS) << BIT_SHIFT_RDG_PIFS) 7488 #define BIT_GET_RDG_PIFS(x) (((x) >> BIT_SHIFT_RDG_PIFS) & BIT_MASK_RDG_PIFS) 7489 7490 /* 2 REG_SIFS (Offset 0x0514) */ 7491 7492 #define BIT_SHIFT_SIFS_OFDM_TRX 24 7493 #define BIT_MASK_SIFS_OFDM_TRX 0xff 7494 #define BIT_SIFS_OFDM_TRX(x) \ 7495 (((x) & BIT_MASK_SIFS_OFDM_TRX) << BIT_SHIFT_SIFS_OFDM_TRX) 7496 #define BIT_GET_SIFS_OFDM_TRX(x) \ 7497 (((x) >> BIT_SHIFT_SIFS_OFDM_TRX) & BIT_MASK_SIFS_OFDM_TRX) 7498 7499 #define BIT_SHIFT_SIFS_CCK_TRX 16 7500 #define BIT_MASK_SIFS_CCK_TRX 0xff 7501 #define BIT_SIFS_CCK_TRX(x) \ 7502 (((x) & BIT_MASK_SIFS_CCK_TRX) << BIT_SHIFT_SIFS_CCK_TRX) 7503 #define BIT_GET_SIFS_CCK_TRX(x) \ 7504 (((x) >> BIT_SHIFT_SIFS_CCK_TRX) & BIT_MASK_SIFS_CCK_TRX) 7505 7506 #define BIT_SHIFT_SIFS_OFDM_CTX 8 7507 #define BIT_MASK_SIFS_OFDM_CTX 0xff 7508 #define BIT_SIFS_OFDM_CTX(x) \ 7509 (((x) & BIT_MASK_SIFS_OFDM_CTX) << BIT_SHIFT_SIFS_OFDM_CTX) 7510 #define BIT_GET_SIFS_OFDM_CTX(x) \ 7511 (((x) >> BIT_SHIFT_SIFS_OFDM_CTX) & BIT_MASK_SIFS_OFDM_CTX) 7512 7513 #define BIT_SHIFT_SIFS_CCK_CTX 0 7514 #define BIT_MASK_SIFS_CCK_CTX 0xff 7515 #define BIT_SIFS_CCK_CTX(x) \ 7516 (((x) & BIT_MASK_SIFS_CCK_CTX) << BIT_SHIFT_SIFS_CCK_CTX) 7517 #define BIT_GET_SIFS_CCK_CTX(x) \ 7518 (((x) >> BIT_SHIFT_SIFS_CCK_CTX) & BIT_MASK_SIFS_CCK_CTX) 7519 7520 /* 2 REG_TSFTR_SYN_OFFSET (Offset 0x0518) */ 7521 7522 #define BIT_SHIFT_TSFTR_SNC_OFFSET 0 7523 #define BIT_MASK_TSFTR_SNC_OFFSET 0xffff 7524 #define BIT_TSFTR_SNC_OFFSET(x) \ 7525 (((x) & BIT_MASK_TSFTR_SNC_OFFSET) << BIT_SHIFT_TSFTR_SNC_OFFSET) 7526 #define BIT_GET_TSFTR_SNC_OFFSET(x) \ 7527 (((x) >> BIT_SHIFT_TSFTR_SNC_OFFSET) & BIT_MASK_TSFTR_SNC_OFFSET) 7528 7529 /* 2 REG_AGGR_BREAK_TIME (Offset 0x051A) */ 7530 7531 #define BIT_SHIFT_AGGR_BK_TIME 0 7532 #define BIT_MASK_AGGR_BK_TIME 0xff 7533 #define BIT_AGGR_BK_TIME(x) \ 7534 (((x) & BIT_MASK_AGGR_BK_TIME) << BIT_SHIFT_AGGR_BK_TIME) 7535 #define BIT_GET_AGGR_BK_TIME(x) \ 7536 (((x) >> BIT_SHIFT_AGGR_BK_TIME) & BIT_MASK_AGGR_BK_TIME) 7537 7538 /* 2 REG_SLOT (Offset 0x051B) */ 7539 7540 #define BIT_SHIFT_SLOT 0 7541 #define BIT_MASK_SLOT 0xff 7542 #define BIT_SLOT(x) (((x) & BIT_MASK_SLOT) << BIT_SHIFT_SLOT) 7543 #define BIT_GET_SLOT(x) (((x) >> BIT_SHIFT_SLOT) & BIT_MASK_SLOT) 7544 7545 /* 2 REG_TX_PTCL_CTRL (Offset 0x0520) */ 7546 7547 #define BIT_DIS_EDCCA BIT(15) 7548 #define BIT_DIS_CCA BIT(14) 7549 #define BIT_LSIG_TXOP_TXCMD_NAV BIT(13) 7550 #define BIT_SIFS_BK_EN BIT(12) 7551 7552 #define BIT_SHIFT_TXQ_NAV_MSK 8 7553 #define BIT_MASK_TXQ_NAV_MSK 0xf 7554 #define BIT_TXQ_NAV_MSK(x) \ 7555 (((x) & BIT_MASK_TXQ_NAV_MSK) << BIT_SHIFT_TXQ_NAV_MSK) 7556 #define BIT_GET_TXQ_NAV_MSK(x) \ 7557 (((x) >> BIT_SHIFT_TXQ_NAV_MSK) & BIT_MASK_TXQ_NAV_MSK) 7558 7559 #define BIT_DIS_CW BIT(7) 7560 #define BIT_NAV_END_TXOP BIT(6) 7561 #define BIT_RDG_END_TXOP BIT(5) 7562 #define BIT_AC_INBCN_HOLD BIT(4) 7563 #define BIT_MGTQ_TXOP_EN BIT(3) 7564 #define BIT_MGTQ_RTSMF_EN BIT(2) 7565 #define BIT_HIQ_RTSMF_EN BIT(1) 7566 #define BIT_BCN_RTSMF_EN BIT(0) 7567 7568 /* 2 REG_TXPAUSE (Offset 0x0522) */ 7569 7570 #define BIT_STOP_BCN_HI_MGT BIT(7) 7571 #define BIT_MAC_STOPBCNQ BIT(6) 7572 #define BIT_MAC_STOPHIQ BIT(5) 7573 #define BIT_MAC_STOPMGQ BIT(4) 7574 #define BIT_MAC_STOPBK BIT(3) 7575 #define BIT_MAC_STOPBE BIT(2) 7576 #define BIT_MAC_STOPVI BIT(1) 7577 #define BIT_MAC_STOPVO BIT(0) 7578 7579 /* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ 7580 7581 #define BIT_DIS_BT_CCA BIT(7) 7582 7583 /* 2 REG_DIS_TXREQ_CLR (Offset 0x0523) */ 7584 7585 #define BIT_DIS_TXREQ_CLR_HI BIT(5) 7586 #define BIT_DIS_TXREQ_CLR_MGQ BIT(4) 7587 #define BIT_DIS_TXREQ_CLR_VO BIT(3) 7588 #define BIT_DIS_TXREQ_CLR_VI BIT(2) 7589 #define BIT_DIS_TXREQ_CLR_BE BIT(1) 7590 #define BIT_DIS_TXREQ_CLR_BK BIT(0) 7591 7592 /* 2 REG_RD_CTRL (Offset 0x0524) */ 7593 7594 #define BIT_EN_CLR_TXREQ_INCCA BIT(15) 7595 #define BIT_DIS_TX_OVER_BCNQ BIT(14) 7596 7597 /* 2 REG_RD_CTRL (Offset 0x0524) */ 7598 7599 #define BIT_EN_BCNERR_INCCCA BIT(13) 7600 7601 /* 2 REG_RD_CTRL (Offset 0x0524) */ 7602 7603 #define BIT_EDCCA_MSK_CNTDOWN_EN BIT(11) 7604 #define BIT_DIS_TXOP_CFE BIT(10) 7605 #define BIT_DIS_LSIG_CFE BIT(9) 7606 #define BIT_DIS_STBC_CFE BIT(8) 7607 #define BIT_BKQ_RD_INIT_EN BIT(7) 7608 #define BIT_BEQ_RD_INIT_EN BIT(6) 7609 #define BIT_VIQ_RD_INIT_EN BIT(5) 7610 #define BIT_VOQ_RD_INIT_EN BIT(4) 7611 #define BIT_BKQ_RD_RESP_EN BIT(3) 7612 #define BIT_BEQ_RD_RESP_EN BIT(2) 7613 #define BIT_VIQ_RD_RESP_EN BIT(1) 7614 #define BIT_VOQ_RD_RESP_EN BIT(0) 7615 7616 /* 2 REG_MBSSID_CTRL (Offset 0x0526) */ 7617 7618 #define BIT_MBID_BCNQ7_EN BIT(7) 7619 #define BIT_MBID_BCNQ6_EN BIT(6) 7620 #define BIT_MBID_BCNQ5_EN BIT(5) 7621 #define BIT_MBID_BCNQ4_EN BIT(4) 7622 #define BIT_MBID_BCNQ3_EN BIT(3) 7623 #define BIT_MBID_BCNQ2_EN BIT(2) 7624 #define BIT_MBID_BCNQ1_EN BIT(1) 7625 #define BIT_MBID_BCNQ0_EN BIT(0) 7626 7627 /* 2 REG_P2PPS_CTRL (Offset 0x0527) */ 7628 7629 #define BIT_P2P_CTW_ALLSTASLEEP BIT(7) 7630 #define BIT_P2P_OFF_DISTX_EN BIT(6) 7631 #define BIT_PWR_MGT_EN BIT(5) 7632 7633 /* 2 REG_P2PPS_CTRL (Offset 0x0527) */ 7634 7635 #define BIT_P2P_NOA1_EN BIT(2) 7636 #define BIT_P2P_NOA0_EN BIT(1) 7637 7638 /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ 7639 7640 #define BIT_EN_P2P_CTWND1 BIT(23) 7641 7642 /* 2 REG_PKT_LIFETIME_CTRL (Offset 0x0528) */ 7643 7644 #define BIT_EN_BKF_CLR_TXREQ BIT(22) 7645 #define BIT_EN_TSFBIT32_RST_P2P BIT(21) 7646 #define BIT_EN_BCN_TX_BTCCA BIT(20) 7647 #define BIT_DIS_PKT_TX_ATIM BIT(19) 7648 #define BIT_DIS_BCN_DIS_CTN BIT(18) 7649 #define BIT_EN_NAVEND_RST_TXOP BIT(17) 7650 #define BIT_EN_FILTER_CCA BIT(16) 7651 7652 #define BIT_SHIFT_CCA_FILTER_THRS 8 7653 #define BIT_MASK_CCA_FILTER_THRS 0xff 7654 #define BIT_CCA_FILTER_THRS(x) \ 7655 (((x) & BIT_MASK_CCA_FILTER_THRS) << BIT_SHIFT_CCA_FILTER_THRS) 7656 #define BIT_GET_CCA_FILTER_THRS(x) \ 7657 (((x) >> BIT_SHIFT_CCA_FILTER_THRS) & BIT_MASK_CCA_FILTER_THRS) 7658 7659 #define BIT_SHIFT_EDCCA_THRS 0 7660 #define BIT_MASK_EDCCA_THRS 0xff 7661 #define BIT_EDCCA_THRS(x) (((x) & BIT_MASK_EDCCA_THRS) << BIT_SHIFT_EDCCA_THRS) 7662 #define BIT_GET_EDCCA_THRS(x) \ 7663 (((x) >> BIT_SHIFT_EDCCA_THRS) & BIT_MASK_EDCCA_THRS) 7664 7665 /* 2 REG_P2PPS_SPEC_STATE (Offset 0x052B) */ 7666 7667 #define BIT_SPEC_POWER_STATE BIT(7) 7668 #define BIT_SPEC_CTWINDOW_ON BIT(6) 7669 #define BIT_SPEC_BEACON_AREA_ON BIT(5) 7670 #define BIT_SPEC_CTWIN_EARLY_DISTX BIT(4) 7671 #define BIT_SPEC_NOA1_OFF_PERIOD BIT(3) 7672 #define BIT_SPEC_FORCE_DOZE1 BIT(2) 7673 #define BIT_SPEC_NOA0_OFF_PERIOD BIT(1) 7674 #define BIT_SPEC_FORCE_DOZE0 BIT(0) 7675 7676 /* 2 REG_QUEUE_INCOL_THR (Offset 0x0538) */ 7677 7678 #define BIT_SHIFT_BK_QUEUE_THR 24 7679 #define BIT_MASK_BK_QUEUE_THR 0xff 7680 #define BIT_BK_QUEUE_THR(x) \ 7681 (((x) & BIT_MASK_BK_QUEUE_THR) << BIT_SHIFT_BK_QUEUE_THR) 7682 #define BIT_GET_BK_QUEUE_THR(x) \ 7683 (((x) >> BIT_SHIFT_BK_QUEUE_THR) & BIT_MASK_BK_QUEUE_THR) 7684 7685 #define BIT_SHIFT_BE_QUEUE_THR 16 7686 #define BIT_MASK_BE_QUEUE_THR 0xff 7687 #define BIT_BE_QUEUE_THR(x) \ 7688 (((x) & BIT_MASK_BE_QUEUE_THR) << BIT_SHIFT_BE_QUEUE_THR) 7689 #define BIT_GET_BE_QUEUE_THR(x) \ 7690 (((x) >> BIT_SHIFT_BE_QUEUE_THR) & BIT_MASK_BE_QUEUE_THR) 7691 7692 #define BIT_SHIFT_VI_QUEUE_THR 8 7693 #define BIT_MASK_VI_QUEUE_THR 0xff 7694 #define BIT_VI_QUEUE_THR(x) \ 7695 (((x) & BIT_MASK_VI_QUEUE_THR) << BIT_SHIFT_VI_QUEUE_THR) 7696 #define BIT_GET_VI_QUEUE_THR(x) \ 7697 (((x) >> BIT_SHIFT_VI_QUEUE_THR) & BIT_MASK_VI_QUEUE_THR) 7698 7699 #define BIT_SHIFT_VO_QUEUE_THR 0 7700 #define BIT_MASK_VO_QUEUE_THR 0xff 7701 #define BIT_VO_QUEUE_THR(x) \ 7702 (((x) & BIT_MASK_VO_QUEUE_THR) << BIT_SHIFT_VO_QUEUE_THR) 7703 #define BIT_GET_VO_QUEUE_THR(x) \ 7704 (((x) >> BIT_SHIFT_VO_QUEUE_THR) & BIT_MASK_VO_QUEUE_THR) 7705 7706 /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7707 7708 #define BIT_QUEUE_INCOL_EN BIT(16) 7709 7710 /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7711 7712 #define BIT_SHIFT_BE_TRIGGER_NUM 12 7713 #define BIT_MASK_BE_TRIGGER_NUM 0xf 7714 #define BIT_BE_TRIGGER_NUM(x) \ 7715 (((x) & BIT_MASK_BE_TRIGGER_NUM) << BIT_SHIFT_BE_TRIGGER_NUM) 7716 #define BIT_GET_BE_TRIGGER_NUM(x) \ 7717 (((x) >> BIT_SHIFT_BE_TRIGGER_NUM) & BIT_MASK_BE_TRIGGER_NUM) 7718 7719 /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7720 7721 #define BIT_SHIFT_BK_TRIGGER_NUM 8 7722 #define BIT_MASK_BK_TRIGGER_NUM 0xf 7723 #define BIT_BK_TRIGGER_NUM(x) \ 7724 (((x) & BIT_MASK_BK_TRIGGER_NUM) << BIT_SHIFT_BK_TRIGGER_NUM) 7725 #define BIT_GET_BK_TRIGGER_NUM(x) \ 7726 (((x) >> BIT_SHIFT_BK_TRIGGER_NUM) & BIT_MASK_BK_TRIGGER_NUM) 7727 7728 /* 2 REG_QUEUE_INCOL_EN (Offset 0x053C) */ 7729 7730 #define BIT_SHIFT_VI_TRIGGER_NUM 4 7731 #define BIT_MASK_VI_TRIGGER_NUM 0xf 7732 #define BIT_VI_TRIGGER_NUM(x) \ 7733 (((x) & BIT_MASK_VI_TRIGGER_NUM) << BIT_SHIFT_VI_TRIGGER_NUM) 7734 #define BIT_GET_VI_TRIGGER_NUM(x) \ 7735 (((x) >> BIT_SHIFT_VI_TRIGGER_NUM) & BIT_MASK_VI_TRIGGER_NUM) 7736 7737 #define BIT_SHIFT_VO_TRIGGER_NUM 0 7738 #define BIT_MASK_VO_TRIGGER_NUM 0xf 7739 #define BIT_VO_TRIGGER_NUM(x) \ 7740 (((x) & BIT_MASK_VO_TRIGGER_NUM) << BIT_SHIFT_VO_TRIGGER_NUM) 7741 #define BIT_GET_VO_TRIGGER_NUM(x) \ 7742 (((x) >> BIT_SHIFT_VO_TRIGGER_NUM) & BIT_MASK_VO_TRIGGER_NUM) 7743 7744 /* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ 7745 7746 #define BIT_SHIFT_TBTT_HOLD_TIME_AP 8 7747 #define BIT_MASK_TBTT_HOLD_TIME_AP 0xfff 7748 #define BIT_TBTT_HOLD_TIME_AP(x) \ 7749 (((x) & BIT_MASK_TBTT_HOLD_TIME_AP) << BIT_SHIFT_TBTT_HOLD_TIME_AP) 7750 #define BIT_GET_TBTT_HOLD_TIME_AP(x) \ 7751 (((x) >> BIT_SHIFT_TBTT_HOLD_TIME_AP) & BIT_MASK_TBTT_HOLD_TIME_AP) 7752 7753 /* 2 REG_TBTT_PROHIBIT (Offset 0x0540) */ 7754 7755 #define BIT_SHIFT_TBTT_PROHIBIT_SETUP 0 7756 #define BIT_MASK_TBTT_PROHIBIT_SETUP 0xf 7757 #define BIT_TBTT_PROHIBIT_SETUP(x) \ 7758 (((x) & BIT_MASK_TBTT_PROHIBIT_SETUP) << BIT_SHIFT_TBTT_PROHIBIT_SETUP) 7759 #define BIT_GET_TBTT_PROHIBIT_SETUP(x) \ 7760 (((x) >> BIT_SHIFT_TBTT_PROHIBIT_SETUP) & BIT_MASK_TBTT_PROHIBIT_SETUP) 7761 7762 /* 2 REG_P2PPS_STATE (Offset 0x0543) */ 7763 7764 #define BIT_POWER_STATE BIT(7) 7765 #define BIT_CTWINDOW_ON BIT(6) 7766 #define BIT_BEACON_AREA_ON BIT(5) 7767 #define BIT_CTWIN_EARLY_DISTX BIT(4) 7768 #define BIT_NOA1_OFF_PERIOD BIT(3) 7769 #define BIT_FORCE_DOZE1 BIT(2) 7770 #define BIT_NOA0_OFF_PERIOD BIT(1) 7771 #define BIT_FORCE_DOZE0 BIT(0) 7772 7773 /* 2 REG_RD_NAV_NXT (Offset 0x0544) */ 7774 7775 #define BIT_SHIFT_RD_NAV_PROT_NXT 0 7776 #define BIT_MASK_RD_NAV_PROT_NXT 0xffff 7777 #define BIT_RD_NAV_PROT_NXT(x) \ 7778 (((x) & BIT_MASK_RD_NAV_PROT_NXT) << BIT_SHIFT_RD_NAV_PROT_NXT) 7779 #define BIT_GET_RD_NAV_PROT_NXT(x) \ 7780 (((x) >> BIT_SHIFT_RD_NAV_PROT_NXT) & BIT_MASK_RD_NAV_PROT_NXT) 7781 7782 /* 2 REG_NAV_PROT_LEN (Offset 0x0546) */ 7783 7784 #define BIT_SHIFT_NAV_PROT_LEN 0 7785 #define BIT_MASK_NAV_PROT_LEN 0xffff 7786 #define BIT_NAV_PROT_LEN(x) \ 7787 (((x) & BIT_MASK_NAV_PROT_LEN) << BIT_SHIFT_NAV_PROT_LEN) 7788 #define BIT_GET_NAV_PROT_LEN(x) \ 7789 (((x) >> BIT_SHIFT_NAV_PROT_LEN) & BIT_MASK_NAV_PROT_LEN) 7790 7791 /* 2 REG_BCN_CTRL (Offset 0x0550) */ 7792 7793 #define BIT_DIS_RX_BSSID_FIT BIT(6) 7794 7795 /* 2 REG_BCN_CTRL (Offset 0x0550) */ 7796 7797 #define BIT_P0_EN_TXBCN_RPT BIT(5) 7798 7799 /* 2 REG_BCN_CTRL (Offset 0x0550) */ 7800 7801 #define BIT_DIS_TSF_UDT BIT(4) 7802 #define BIT_EN_BCN_FUNCTION BIT(3) 7803 7804 /* 2 REG_BCN_CTRL (Offset 0x0550) */ 7805 7806 #define BIT_P0_EN_RXBCN_RPT BIT(2) 7807 7808 /* 2 REG_BCN_CTRL (Offset 0x0550) */ 7809 7810 #define BIT_EN_P2P_CTWINDOW BIT(1) 7811 #define BIT_EN_P2P_BCNQ_AREA BIT(0) 7812 7813 /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7814 7815 #define BIT_CLI0_DIS_RX_BSSID_FIT BIT(6) 7816 7817 /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7818 7819 #define BIT_CLI0_DIS_TSF_UDT BIT(4) 7820 7821 /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7822 7823 #define BIT_CLI0_EN_BCN_FUNCTION BIT(3) 7824 7825 /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7826 7827 #define BIT_CLI0_EN_RXBCN_RPT BIT(2) 7828 7829 /* 2 REG_BCN_CTRL_CLINT0 (Offset 0x0551) */ 7830 7831 #define BIT_CLI0_ENP2P_CTWINDOW BIT(1) 7832 #define BIT_CLI0_ENP2P_BCNQ_AREA BIT(0) 7833 7834 /* 2 REG_MBID_NUM (Offset 0x0552) */ 7835 7836 #define BIT_EN_PRE_DL_BEACON BIT(3) 7837 7838 #define BIT_SHIFT_MBID_BCN_NUM 0 7839 #define BIT_MASK_MBID_BCN_NUM 0x7 7840 #define BIT_MBID_BCN_NUM(x) \ 7841 (((x) & BIT_MASK_MBID_BCN_NUM) << BIT_SHIFT_MBID_BCN_NUM) 7842 #define BIT_GET_MBID_BCN_NUM(x) \ 7843 (((x) >> BIT_SHIFT_MBID_BCN_NUM) & BIT_MASK_MBID_BCN_NUM) 7844 7845 /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7846 7847 #define BIT_FREECNT_RST BIT(5) 7848 7849 /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7850 7851 #define BIT_TSFTR_CLI3_RST BIT(4) 7852 7853 /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7854 7855 #define BIT_TSFTR_CLI2_RST BIT(3) 7856 7857 /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7858 7859 #define BIT_TSFTR_CLI1_RST BIT(2) 7860 7861 /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7862 7863 #define BIT_TSFTR_CLI0_RST BIT(1) 7864 7865 /* 2 REG_DUAL_TSF_RST (Offset 0x0553) */ 7866 7867 #define BIT_TSFTR_RST BIT(0) 7868 7869 /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ 7870 7871 #define BIT_SHIFT_BCN_TIMER_SEL_FWRD 28 7872 #define BIT_MASK_BCN_TIMER_SEL_FWRD 0x7 7873 #define BIT_BCN_TIMER_SEL_FWRD(x) \ 7874 (((x) & BIT_MASK_BCN_TIMER_SEL_FWRD) << BIT_SHIFT_BCN_TIMER_SEL_FWRD) 7875 #define BIT_GET_BCN_TIMER_SEL_FWRD(x) \ 7876 (((x) >> BIT_SHIFT_BCN_TIMER_SEL_FWRD) & BIT_MASK_BCN_TIMER_SEL_FWRD) 7877 7878 /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ 7879 7880 #define BIT_SHIFT_BCN_SPACE_CLINT0 16 7881 #define BIT_MASK_BCN_SPACE_CLINT0 0xfff 7882 #define BIT_BCN_SPACE_CLINT0(x) \ 7883 (((x) & BIT_MASK_BCN_SPACE_CLINT0) << BIT_SHIFT_BCN_SPACE_CLINT0) 7884 #define BIT_GET_BCN_SPACE_CLINT0(x) \ 7885 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT0) & BIT_MASK_BCN_SPACE_CLINT0) 7886 7887 /* 2 REG_MBSSID_BCN_SPACE (Offset 0x0554) */ 7888 7889 #define BIT_SHIFT_BCN_SPACE0 0 7890 #define BIT_MASK_BCN_SPACE0 0xffff 7891 #define BIT_BCN_SPACE0(x) (((x) & BIT_MASK_BCN_SPACE0) << BIT_SHIFT_BCN_SPACE0) 7892 #define BIT_GET_BCN_SPACE0(x) \ 7893 (((x) >> BIT_SHIFT_BCN_SPACE0) & BIT_MASK_BCN_SPACE0) 7894 7895 /* 2 REG_DRVERLYINT (Offset 0x0558) */ 7896 7897 #define BIT_SHIFT_DRVERLYITV 0 7898 #define BIT_MASK_DRVERLYITV 0xff 7899 #define BIT_DRVERLYITV(x) (((x) & BIT_MASK_DRVERLYITV) << BIT_SHIFT_DRVERLYITV) 7900 #define BIT_GET_DRVERLYITV(x) \ 7901 (((x) >> BIT_SHIFT_DRVERLYITV) & BIT_MASK_DRVERLYITV) 7902 7903 /* 2 REG_BCNDMATIM (Offset 0x0559) */ 7904 7905 #define BIT_SHIFT_BCNDMATIM 0 7906 #define BIT_MASK_BCNDMATIM 0xff 7907 #define BIT_BCNDMATIM(x) (((x) & BIT_MASK_BCNDMATIM) << BIT_SHIFT_BCNDMATIM) 7908 #define BIT_GET_BCNDMATIM(x) (((x) >> BIT_SHIFT_BCNDMATIM) & BIT_MASK_BCNDMATIM) 7909 7910 /* 2 REG_ATIMWND (Offset 0x055A) */ 7911 7912 #define BIT_SHIFT_ATIMWND0 0 7913 #define BIT_MASK_ATIMWND0 0xffff 7914 #define BIT_ATIMWND0(x) (((x) & BIT_MASK_ATIMWND0) << BIT_SHIFT_ATIMWND0) 7915 #define BIT_GET_ATIMWND0(x) (((x) >> BIT_SHIFT_ATIMWND0) & BIT_MASK_ATIMWND0) 7916 7917 /* 2 REG_USTIME_TSF (Offset 0x055C) */ 7918 7919 #define BIT_SHIFT_USTIME_TSF_V1 0 7920 #define BIT_MASK_USTIME_TSF_V1 0xff 7921 #define BIT_USTIME_TSF_V1(x) \ 7922 (((x) & BIT_MASK_USTIME_TSF_V1) << BIT_SHIFT_USTIME_TSF_V1) 7923 #define BIT_GET_USTIME_TSF_V1(x) \ 7924 (((x) >> BIT_SHIFT_USTIME_TSF_V1) & BIT_MASK_USTIME_TSF_V1) 7925 7926 /* 2 REG_BCN_MAX_ERR (Offset 0x055D) */ 7927 7928 #define BIT_SHIFT_BCN_MAX_ERR 0 7929 #define BIT_MASK_BCN_MAX_ERR 0xff 7930 #define BIT_BCN_MAX_ERR(x) \ 7931 (((x) & BIT_MASK_BCN_MAX_ERR) << BIT_SHIFT_BCN_MAX_ERR) 7932 #define BIT_GET_BCN_MAX_ERR(x) \ 7933 (((x) >> BIT_SHIFT_BCN_MAX_ERR) & BIT_MASK_BCN_MAX_ERR) 7934 7935 /* 2 REG_RXTSF_OFFSET_CCK (Offset 0x055E) */ 7936 7937 #define BIT_SHIFT_CCK_RXTSF_OFFSET 0 7938 #define BIT_MASK_CCK_RXTSF_OFFSET 0xff 7939 #define BIT_CCK_RXTSF_OFFSET(x) \ 7940 (((x) & BIT_MASK_CCK_RXTSF_OFFSET) << BIT_SHIFT_CCK_RXTSF_OFFSET) 7941 #define BIT_GET_CCK_RXTSF_OFFSET(x) \ 7942 (((x) >> BIT_SHIFT_CCK_RXTSF_OFFSET) & BIT_MASK_CCK_RXTSF_OFFSET) 7943 7944 /* 2 REG_RXTSF_OFFSET_OFDM (Offset 0x055F) */ 7945 7946 #define BIT_SHIFT_OFDM_RXTSF_OFFSET 0 7947 #define BIT_MASK_OFDM_RXTSF_OFFSET 0xff 7948 #define BIT_OFDM_RXTSF_OFFSET(x) \ 7949 (((x) & BIT_MASK_OFDM_RXTSF_OFFSET) << BIT_SHIFT_OFDM_RXTSF_OFFSET) 7950 #define BIT_GET_OFDM_RXTSF_OFFSET(x) \ 7951 (((x) >> BIT_SHIFT_OFDM_RXTSF_OFFSET) & BIT_MASK_OFDM_RXTSF_OFFSET) 7952 7953 /* 2 REG_TSFTR (Offset 0x0560) */ 7954 7955 #define BIT_SHIFT_TSF_TIMER 0 7956 #define BIT_MASK_TSF_TIMER 0xffffffffffffffffL 7957 #define BIT_TSF_TIMER(x) (((x) & BIT_MASK_TSF_TIMER) << BIT_SHIFT_TSF_TIMER) 7958 #define BIT_GET_TSF_TIMER(x) (((x) >> BIT_SHIFT_TSF_TIMER) & BIT_MASK_TSF_TIMER) 7959 7960 /* 2 REG_FREERUN_CNT (Offset 0x0568) */ 7961 7962 #define BIT_SHIFT_FREERUN_CNT 0 7963 #define BIT_MASK_FREERUN_CNT 0xffffffffffffffffL 7964 #define BIT_FREERUN_CNT(x) \ 7965 (((x) & BIT_MASK_FREERUN_CNT) << BIT_SHIFT_FREERUN_CNT) 7966 #define BIT_GET_FREERUN_CNT(x) \ 7967 (((x) >> BIT_SHIFT_FREERUN_CNT) & BIT_MASK_FREERUN_CNT) 7968 7969 /* 2 REG_ATIMWND1_V1 (Offset 0x0570) */ 7970 7971 #define BIT_SHIFT_ATIMWND1_V1 0 7972 #define BIT_MASK_ATIMWND1_V1 0xff 7973 #define BIT_ATIMWND1_V1(x) \ 7974 (((x) & BIT_MASK_ATIMWND1_V1) << BIT_SHIFT_ATIMWND1_V1) 7975 #define BIT_GET_ATIMWND1_V1(x) \ 7976 (((x) >> BIT_SHIFT_ATIMWND1_V1) & BIT_MASK_ATIMWND1_V1) 7977 7978 /* 2 REG_TBTT_PROHIBIT_INFRA (Offset 0x0571) */ 7979 7980 #define BIT_SHIFT_TBTT_PROHIBIT_INFRA 0 7981 #define BIT_MASK_TBTT_PROHIBIT_INFRA 0xff 7982 #define BIT_TBTT_PROHIBIT_INFRA(x) \ 7983 (((x) & BIT_MASK_TBTT_PROHIBIT_INFRA) << BIT_SHIFT_TBTT_PROHIBIT_INFRA) 7984 #define BIT_GET_TBTT_PROHIBIT_INFRA(x) \ 7985 (((x) >> BIT_SHIFT_TBTT_PROHIBIT_INFRA) & BIT_MASK_TBTT_PROHIBIT_INFRA) 7986 7987 /* 2 REG_CTWND (Offset 0x0572) */ 7988 7989 #define BIT_SHIFT_CTWND 0 7990 #define BIT_MASK_CTWND 0xff 7991 #define BIT_CTWND(x) (((x) & BIT_MASK_CTWND) << BIT_SHIFT_CTWND) 7992 #define BIT_GET_CTWND(x) (((x) >> BIT_SHIFT_CTWND) & BIT_MASK_CTWND) 7993 7994 /* 2 REG_BCNIVLCUNT (Offset 0x0573) */ 7995 7996 #define BIT_SHIFT_BCNIVLCUNT 0 7997 #define BIT_MASK_BCNIVLCUNT 0x7f 7998 #define BIT_BCNIVLCUNT(x) (((x) & BIT_MASK_BCNIVLCUNT) << BIT_SHIFT_BCNIVLCUNT) 7999 #define BIT_GET_BCNIVLCUNT(x) \ 8000 (((x) >> BIT_SHIFT_BCNIVLCUNT) & BIT_MASK_BCNIVLCUNT) 8001 8002 /* 2 REG_BCNDROPCTRL (Offset 0x0574) */ 8003 8004 #define BIT_BEACON_DROP_EN BIT(7) 8005 8006 #define BIT_SHIFT_BEACON_DROP_IVL 0 8007 #define BIT_MASK_BEACON_DROP_IVL 0x7f 8008 #define BIT_BEACON_DROP_IVL(x) \ 8009 (((x) & BIT_MASK_BEACON_DROP_IVL) << BIT_SHIFT_BEACON_DROP_IVL) 8010 #define BIT_GET_BEACON_DROP_IVL(x) \ 8011 (((x) >> BIT_SHIFT_BEACON_DROP_IVL) & BIT_MASK_BEACON_DROP_IVL) 8012 8013 /* 2 REG_HGQ_TIMEOUT_PERIOD (Offset 0x0575) */ 8014 8015 #define BIT_SHIFT_HGQ_TIMEOUT_PERIOD 0 8016 #define BIT_MASK_HGQ_TIMEOUT_PERIOD 0xff 8017 #define BIT_HGQ_TIMEOUT_PERIOD(x) \ 8018 (((x) & BIT_MASK_HGQ_TIMEOUT_PERIOD) << BIT_SHIFT_HGQ_TIMEOUT_PERIOD) 8019 #define BIT_GET_HGQ_TIMEOUT_PERIOD(x) \ 8020 (((x) >> BIT_SHIFT_HGQ_TIMEOUT_PERIOD) & BIT_MASK_HGQ_TIMEOUT_PERIOD) 8021 8022 /* 2 REG_TXCMD_TIMEOUT_PERIOD (Offset 0x0576) */ 8023 8024 #define BIT_SHIFT_TXCMD_TIMEOUT_PERIOD 0 8025 #define BIT_MASK_TXCMD_TIMEOUT_PERIOD 0xff 8026 #define BIT_TXCMD_TIMEOUT_PERIOD(x) \ 8027 (((x) & BIT_MASK_TXCMD_TIMEOUT_PERIOD) \ 8028 << BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) 8029 #define BIT_GET_TXCMD_TIMEOUT_PERIOD(x) \ 8030 (((x) >> BIT_SHIFT_TXCMD_TIMEOUT_PERIOD) & \ 8031 BIT_MASK_TXCMD_TIMEOUT_PERIOD) 8032 8033 /* 2 REG_MISC_CTRL (Offset 0x0577) */ 8034 8035 #define BIT_DIS_TRX_CAL_BCN BIT(5) 8036 #define BIT_DIS_TX_CAL_TBTT BIT(4) 8037 #define BIT_EN_FREECNT BIT(3) 8038 #define BIT_BCN_AGGRESSION BIT(2) 8039 8040 #define BIT_SHIFT_DIS_SECONDARY_CCA 0 8041 #define BIT_MASK_DIS_SECONDARY_CCA 0x3 8042 #define BIT_DIS_SECONDARY_CCA(x) \ 8043 (((x) & BIT_MASK_DIS_SECONDARY_CCA) << BIT_SHIFT_DIS_SECONDARY_CCA) 8044 #define BIT_GET_DIS_SECONDARY_CCA(x) \ 8045 (((x) >> BIT_SHIFT_DIS_SECONDARY_CCA) & BIT_MASK_DIS_SECONDARY_CCA) 8046 8047 /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ 8048 8049 #define BIT_CLI1_DIS_RX_BSSID_FIT BIT(6) 8050 #define BIT_CLI1_DIS_TSF_UDT BIT(4) 8051 #define BIT_CLI1_EN_BCN_FUNCTION BIT(3) 8052 8053 /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ 8054 8055 #define BIT_CLI1_EN_RXBCN_RPT BIT(2) 8056 8057 /* 2 REG_BCN_CTRL_CLINT1 (Offset 0x0578) */ 8058 8059 #define BIT_CLI1_ENP2P_CTWINDOW BIT(1) 8060 #define BIT_CLI1_ENP2P_BCNQ_AREA BIT(0) 8061 8062 /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ 8063 8064 #define BIT_CLI2_DIS_RX_BSSID_FIT BIT(6) 8065 #define BIT_CLI2_DIS_TSF_UDT BIT(4) 8066 #define BIT_CLI2_EN_BCN_FUNCTION BIT(3) 8067 8068 /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ 8069 8070 #define BIT_CLI2_EN_RXBCN_RPT BIT(2) 8071 8072 /* 2 REG_BCN_CTRL_CLINT2 (Offset 0x0579) */ 8073 8074 #define BIT_CLI2_ENP2P_CTWINDOW BIT(1) 8075 #define BIT_CLI2_ENP2P_BCNQ_AREA BIT(0) 8076 8077 /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ 8078 8079 #define BIT_CLI3_DIS_RX_BSSID_FIT BIT(6) 8080 #define BIT_CLI3_DIS_TSF_UDT BIT(4) 8081 #define BIT_CLI3_EN_BCN_FUNCTION BIT(3) 8082 8083 /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ 8084 8085 #define BIT_CLI3_EN_RXBCN_RPT BIT(2) 8086 8087 /* 2 REG_BCN_CTRL_CLINT3 (Offset 0x057A) */ 8088 8089 #define BIT_CLI3_ENP2P_CTWINDOW BIT(1) 8090 #define BIT_CLI3_ENP2P_BCNQ_AREA BIT(0) 8091 8092 /* 2 REG_EXTEND_CTRL (Offset 0x057B) */ 8093 8094 #define BIT_EN_TSFBIT32_RST_P2P2 BIT(5) 8095 #define BIT_EN_TSFBIT32_RST_P2P1 BIT(4) 8096 8097 #define BIT_SHIFT_PORT_SEL 0 8098 #define BIT_MASK_PORT_SEL 0x7 8099 #define BIT_PORT_SEL(x) (((x) & BIT_MASK_PORT_SEL) << BIT_SHIFT_PORT_SEL) 8100 #define BIT_GET_PORT_SEL(x) (((x) >> BIT_SHIFT_PORT_SEL) & BIT_MASK_PORT_SEL) 8101 8102 /* 2 REG_P2PPS1_SPEC_STATE (Offset 0x057C) */ 8103 8104 #define BIT_P2P1_SPEC_POWER_STATE BIT(7) 8105 #define BIT_P2P1_SPEC_CTWINDOW_ON BIT(6) 8106 #define BIT_P2P1_SPEC_BCN_AREA_ON BIT(5) 8107 #define BIT_P2P1_SPEC_CTWIN_EARLY_DISTX BIT(4) 8108 #define BIT_P2P1_SPEC_NOA1_OFF_PERIOD BIT(3) 8109 #define BIT_P2P1_SPEC_FORCE_DOZE1 BIT(2) 8110 #define BIT_P2P1_SPEC_NOA0_OFF_PERIOD BIT(1) 8111 #define BIT_P2P1_SPEC_FORCE_DOZE0 BIT(0) 8112 8113 /* 2 REG_P2PPS1_STATE (Offset 0x057D) */ 8114 8115 #define BIT_P2P1_POWER_STATE BIT(7) 8116 #define BIT_P2P1_CTWINDOW_ON BIT(6) 8117 #define BIT_P2P1_BEACON_AREA_ON BIT(5) 8118 #define BIT_P2P1_CTWIN_EARLY_DISTX BIT(4) 8119 #define BIT_P2P1_NOA1_OFF_PERIOD BIT(3) 8120 #define BIT_P2P1_FORCE_DOZE1 BIT(2) 8121 #define BIT_P2P1_NOA0_OFF_PERIOD BIT(1) 8122 #define BIT_P2P1_FORCE_DOZE0 BIT(0) 8123 8124 /* 2 REG_P2PPS2_SPEC_STATE (Offset 0x057E) */ 8125 8126 #define BIT_P2P2_SPEC_POWER_STATE BIT(7) 8127 #define BIT_P2P2_SPEC_CTWINDOW_ON BIT(6) 8128 #define BIT_P2P2_SPEC_BCN_AREA_ON BIT(5) 8129 #define BIT_P2P2_SPEC_CTWIN_EARLY_DISTX BIT(4) 8130 #define BIT_P2P2_SPEC_NOA1_OFF_PERIOD BIT(3) 8131 #define BIT_P2P2_SPEC_FORCE_DOZE1 BIT(2) 8132 #define BIT_P2P2_SPEC_NOA0_OFF_PERIOD BIT(1) 8133 #define BIT_P2P2_SPEC_FORCE_DOZE0 BIT(0) 8134 8135 /* 2 REG_P2PPS2_STATE (Offset 0x057F) */ 8136 8137 #define BIT_P2P2_POWER_STATE BIT(7) 8138 #define BIT_P2P2_CTWINDOW_ON BIT(6) 8139 #define BIT_P2P2_BEACON_AREA_ON BIT(5) 8140 #define BIT_P2P2_CTWIN_EARLY_DISTX BIT(4) 8141 #define BIT_P2P2_NOA1_OFF_PERIOD BIT(3) 8142 #define BIT_P2P2_FORCE_DOZE1 BIT(2) 8143 #define BIT_P2P2_NOA0_OFF_PERIOD BIT(1) 8144 #define BIT_P2P2_FORCE_DOZE0 BIT(0) 8145 8146 /* 2 REG_PS_TIMER0 (Offset 0x0580) */ 8147 8148 #define BIT_SHIFT_PSTIMER0_INT 5 8149 #define BIT_MASK_PSTIMER0_INT 0x7ffffff 8150 #define BIT_PSTIMER0_INT(x) \ 8151 (((x) & BIT_MASK_PSTIMER0_INT) << BIT_SHIFT_PSTIMER0_INT) 8152 #define BIT_GET_PSTIMER0_INT(x) \ 8153 (((x) >> BIT_SHIFT_PSTIMER0_INT) & BIT_MASK_PSTIMER0_INT) 8154 8155 /* 2 REG_PS_TIMER1 (Offset 0x0584) */ 8156 8157 #define BIT_SHIFT_PSTIMER1_INT 5 8158 #define BIT_MASK_PSTIMER1_INT 0x7ffffff 8159 #define BIT_PSTIMER1_INT(x) \ 8160 (((x) & BIT_MASK_PSTIMER1_INT) << BIT_SHIFT_PSTIMER1_INT) 8161 #define BIT_GET_PSTIMER1_INT(x) \ 8162 (((x) >> BIT_SHIFT_PSTIMER1_INT) & BIT_MASK_PSTIMER1_INT) 8163 8164 /* 2 REG_PS_TIMER2 (Offset 0x0588) */ 8165 8166 #define BIT_SHIFT_PSTIMER2_INT 5 8167 #define BIT_MASK_PSTIMER2_INT 0x7ffffff 8168 #define BIT_PSTIMER2_INT(x) \ 8169 (((x) & BIT_MASK_PSTIMER2_INT) << BIT_SHIFT_PSTIMER2_INT) 8170 #define BIT_GET_PSTIMER2_INT(x) \ 8171 (((x) >> BIT_SHIFT_PSTIMER2_INT) & BIT_MASK_PSTIMER2_INT) 8172 8173 /* 2 REG_TBTT_CTN_AREA (Offset 0x058C) */ 8174 8175 #define BIT_SHIFT_TBTT_CTN_AREA 0 8176 #define BIT_MASK_TBTT_CTN_AREA 0xff 8177 #define BIT_TBTT_CTN_AREA(x) \ 8178 (((x) & BIT_MASK_TBTT_CTN_AREA) << BIT_SHIFT_TBTT_CTN_AREA) 8179 #define BIT_GET_TBTT_CTN_AREA(x) \ 8180 (((x) >> BIT_SHIFT_TBTT_CTN_AREA) & BIT_MASK_TBTT_CTN_AREA) 8181 8182 /* 2 REG_FORCE_BCN_IFS (Offset 0x058E) */ 8183 8184 #define BIT_SHIFT_FORCE_BCN_IFS 0 8185 #define BIT_MASK_FORCE_BCN_IFS 0xff 8186 #define BIT_FORCE_BCN_IFS(x) \ 8187 (((x) & BIT_MASK_FORCE_BCN_IFS) << BIT_SHIFT_FORCE_BCN_IFS) 8188 #define BIT_GET_FORCE_BCN_IFS(x) \ 8189 (((x) >> BIT_SHIFT_FORCE_BCN_IFS) & BIT_MASK_FORCE_BCN_IFS) 8190 8191 /* 2 REG_TXOP_MIN (Offset 0x0590) */ 8192 8193 #define BIT_SHIFT_TXOP_MIN 0 8194 #define BIT_MASK_TXOP_MIN 0x3fff 8195 #define BIT_TXOP_MIN(x) (((x) & BIT_MASK_TXOP_MIN) << BIT_SHIFT_TXOP_MIN) 8196 #define BIT_GET_TXOP_MIN(x) (((x) >> BIT_SHIFT_TXOP_MIN) & BIT_MASK_TXOP_MIN) 8197 8198 /* 2 REG_PRE_BKF_TIME (Offset 0x0592) */ 8199 8200 #define BIT_SHIFT_PRE_BKF_TIME 0 8201 #define BIT_MASK_PRE_BKF_TIME 0xff 8202 #define BIT_PRE_BKF_TIME(x) \ 8203 (((x) & BIT_MASK_PRE_BKF_TIME) << BIT_SHIFT_PRE_BKF_TIME) 8204 #define BIT_GET_PRE_BKF_TIME(x) \ 8205 (((x) >> BIT_SHIFT_PRE_BKF_TIME) & BIT_MASK_PRE_BKF_TIME) 8206 8207 /* 2 REG_CROSS_TXOP_CTRL (Offset 0x0593) */ 8208 8209 #define BIT_DTIM_BYPASS BIT(2) 8210 #define BIT_RTS_NAV_TXOP BIT(1) 8211 #define BIT_NOT_CROSS_TXOP BIT(0) 8212 8213 /* 2 REG_ATIMWND2 (Offset 0x05A0) */ 8214 8215 #define BIT_SHIFT_ATIMWND2 0 8216 #define BIT_MASK_ATIMWND2 0xff 8217 #define BIT_ATIMWND2(x) (((x) & BIT_MASK_ATIMWND2) << BIT_SHIFT_ATIMWND2) 8218 #define BIT_GET_ATIMWND2(x) (((x) >> BIT_SHIFT_ATIMWND2) & BIT_MASK_ATIMWND2) 8219 8220 /* 2 REG_ATIMWND3 (Offset 0x05A1) */ 8221 8222 #define BIT_SHIFT_ATIMWND3 0 8223 #define BIT_MASK_ATIMWND3 0xff 8224 #define BIT_ATIMWND3(x) (((x) & BIT_MASK_ATIMWND3) << BIT_SHIFT_ATIMWND3) 8225 #define BIT_GET_ATIMWND3(x) (((x) >> BIT_SHIFT_ATIMWND3) & BIT_MASK_ATIMWND3) 8226 8227 /* 2 REG_ATIMWND4 (Offset 0x05A2) */ 8228 8229 #define BIT_SHIFT_ATIMWND4 0 8230 #define BIT_MASK_ATIMWND4 0xff 8231 #define BIT_ATIMWND4(x) (((x) & BIT_MASK_ATIMWND4) << BIT_SHIFT_ATIMWND4) 8232 #define BIT_GET_ATIMWND4(x) (((x) >> BIT_SHIFT_ATIMWND4) & BIT_MASK_ATIMWND4) 8233 8234 /* 2 REG_ATIMWND5 (Offset 0x05A3) */ 8235 8236 #define BIT_SHIFT_ATIMWND5 0 8237 #define BIT_MASK_ATIMWND5 0xff 8238 #define BIT_ATIMWND5(x) (((x) & BIT_MASK_ATIMWND5) << BIT_SHIFT_ATIMWND5) 8239 #define BIT_GET_ATIMWND5(x) (((x) >> BIT_SHIFT_ATIMWND5) & BIT_MASK_ATIMWND5) 8240 8241 /* 2 REG_ATIMWND6 (Offset 0x05A4) */ 8242 8243 #define BIT_SHIFT_ATIMWND6 0 8244 #define BIT_MASK_ATIMWND6 0xff 8245 #define BIT_ATIMWND6(x) (((x) & BIT_MASK_ATIMWND6) << BIT_SHIFT_ATIMWND6) 8246 #define BIT_GET_ATIMWND6(x) (((x) >> BIT_SHIFT_ATIMWND6) & BIT_MASK_ATIMWND6) 8247 8248 /* 2 REG_ATIMWND7 (Offset 0x05A5) */ 8249 8250 #define BIT_SHIFT_ATIMWND7 0 8251 #define BIT_MASK_ATIMWND7 0xff 8252 #define BIT_ATIMWND7(x) (((x) & BIT_MASK_ATIMWND7) << BIT_SHIFT_ATIMWND7) 8253 #define BIT_GET_ATIMWND7(x) (((x) >> BIT_SHIFT_ATIMWND7) & BIT_MASK_ATIMWND7) 8254 8255 /* 2 REG_ATIMUGT (Offset 0x05A6) */ 8256 8257 #define BIT_SHIFT_ATIM_URGENT 0 8258 #define BIT_MASK_ATIM_URGENT 0xff 8259 #define BIT_ATIM_URGENT(x) \ 8260 (((x) & BIT_MASK_ATIM_URGENT) << BIT_SHIFT_ATIM_URGENT) 8261 #define BIT_GET_ATIM_URGENT(x) \ 8262 (((x) >> BIT_SHIFT_ATIM_URGENT) & BIT_MASK_ATIM_URGENT) 8263 8264 /* 2 REG_HIQ_NO_LMT_EN (Offset 0x05A7) */ 8265 8266 #define BIT_HIQ_NO_LMT_EN_VAP7 BIT(7) 8267 #define BIT_HIQ_NO_LMT_EN_VAP6 BIT(6) 8268 #define BIT_HIQ_NO_LMT_EN_VAP5 BIT(5) 8269 #define BIT_HIQ_NO_LMT_EN_VAP4 BIT(4) 8270 #define BIT_HIQ_NO_LMT_EN_VAP3 BIT(3) 8271 #define BIT_HIQ_NO_LMT_EN_VAP2 BIT(2) 8272 #define BIT_HIQ_NO_LMT_EN_VAP1 BIT(1) 8273 #define BIT_HIQ_NO_LMT_EN_ROOT BIT(0) 8274 8275 /* 2 REG_DTIM_COUNTER_ROOT (Offset 0x05A8) */ 8276 8277 #define BIT_SHIFT_DTIM_COUNT_ROOT 0 8278 #define BIT_MASK_DTIM_COUNT_ROOT 0xff 8279 #define BIT_DTIM_COUNT_ROOT(x) \ 8280 (((x) & BIT_MASK_DTIM_COUNT_ROOT) << BIT_SHIFT_DTIM_COUNT_ROOT) 8281 #define BIT_GET_DTIM_COUNT_ROOT(x) \ 8282 (((x) >> BIT_SHIFT_DTIM_COUNT_ROOT) & BIT_MASK_DTIM_COUNT_ROOT) 8283 8284 /* 2 REG_DTIM_COUNTER_VAP1 (Offset 0x05A9) */ 8285 8286 #define BIT_SHIFT_DTIM_COUNT_VAP1 0 8287 #define BIT_MASK_DTIM_COUNT_VAP1 0xff 8288 #define BIT_DTIM_COUNT_VAP1(x) \ 8289 (((x) & BIT_MASK_DTIM_COUNT_VAP1) << BIT_SHIFT_DTIM_COUNT_VAP1) 8290 #define BIT_GET_DTIM_COUNT_VAP1(x) \ 8291 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP1) & BIT_MASK_DTIM_COUNT_VAP1) 8292 8293 /* 2 REG_DTIM_COUNTER_VAP2 (Offset 0x05AA) */ 8294 8295 #define BIT_SHIFT_DTIM_COUNT_VAP2 0 8296 #define BIT_MASK_DTIM_COUNT_VAP2 0xff 8297 #define BIT_DTIM_COUNT_VAP2(x) \ 8298 (((x) & BIT_MASK_DTIM_COUNT_VAP2) << BIT_SHIFT_DTIM_COUNT_VAP2) 8299 #define BIT_GET_DTIM_COUNT_VAP2(x) \ 8300 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP2) & BIT_MASK_DTIM_COUNT_VAP2) 8301 8302 /* 2 REG_DTIM_COUNTER_VAP3 (Offset 0x05AB) */ 8303 8304 #define BIT_SHIFT_DTIM_COUNT_VAP3 0 8305 #define BIT_MASK_DTIM_COUNT_VAP3 0xff 8306 #define BIT_DTIM_COUNT_VAP3(x) \ 8307 (((x) & BIT_MASK_DTIM_COUNT_VAP3) << BIT_SHIFT_DTIM_COUNT_VAP3) 8308 #define BIT_GET_DTIM_COUNT_VAP3(x) \ 8309 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP3) & BIT_MASK_DTIM_COUNT_VAP3) 8310 8311 /* 2 REG_DTIM_COUNTER_VAP4 (Offset 0x05AC) */ 8312 8313 #define BIT_SHIFT_DTIM_COUNT_VAP4 0 8314 #define BIT_MASK_DTIM_COUNT_VAP4 0xff 8315 #define BIT_DTIM_COUNT_VAP4(x) \ 8316 (((x) & BIT_MASK_DTIM_COUNT_VAP4) << BIT_SHIFT_DTIM_COUNT_VAP4) 8317 #define BIT_GET_DTIM_COUNT_VAP4(x) \ 8318 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP4) & BIT_MASK_DTIM_COUNT_VAP4) 8319 8320 /* 2 REG_DTIM_COUNTER_VAP5 (Offset 0x05AD) */ 8321 8322 #define BIT_SHIFT_DTIM_COUNT_VAP5 0 8323 #define BIT_MASK_DTIM_COUNT_VAP5 0xff 8324 #define BIT_DTIM_COUNT_VAP5(x) \ 8325 (((x) & BIT_MASK_DTIM_COUNT_VAP5) << BIT_SHIFT_DTIM_COUNT_VAP5) 8326 #define BIT_GET_DTIM_COUNT_VAP5(x) \ 8327 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP5) & BIT_MASK_DTIM_COUNT_VAP5) 8328 8329 /* 2 REG_DTIM_COUNTER_VAP6 (Offset 0x05AE) */ 8330 8331 #define BIT_SHIFT_DTIM_COUNT_VAP6 0 8332 #define BIT_MASK_DTIM_COUNT_VAP6 0xff 8333 #define BIT_DTIM_COUNT_VAP6(x) \ 8334 (((x) & BIT_MASK_DTIM_COUNT_VAP6) << BIT_SHIFT_DTIM_COUNT_VAP6) 8335 #define BIT_GET_DTIM_COUNT_VAP6(x) \ 8336 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP6) & BIT_MASK_DTIM_COUNT_VAP6) 8337 8338 /* 2 REG_DTIM_COUNTER_VAP7 (Offset 0x05AF) */ 8339 8340 #define BIT_SHIFT_DTIM_COUNT_VAP7 0 8341 #define BIT_MASK_DTIM_COUNT_VAP7 0xff 8342 #define BIT_DTIM_COUNT_VAP7(x) \ 8343 (((x) & BIT_MASK_DTIM_COUNT_VAP7) << BIT_SHIFT_DTIM_COUNT_VAP7) 8344 #define BIT_GET_DTIM_COUNT_VAP7(x) \ 8345 (((x) >> BIT_SHIFT_DTIM_COUNT_VAP7) & BIT_MASK_DTIM_COUNT_VAP7) 8346 8347 /* 2 REG_DIS_ATIM (Offset 0x05B0) */ 8348 8349 #define BIT_DIS_ATIM_VAP7 BIT(7) 8350 #define BIT_DIS_ATIM_VAP6 BIT(6) 8351 #define BIT_DIS_ATIM_VAP5 BIT(5) 8352 #define BIT_DIS_ATIM_VAP4 BIT(4) 8353 #define BIT_DIS_ATIM_VAP3 BIT(3) 8354 #define BIT_DIS_ATIM_VAP2 BIT(2) 8355 #define BIT_DIS_ATIM_VAP1 BIT(1) 8356 #define BIT_DIS_ATIM_ROOT BIT(0) 8357 8358 /* 2 REG_EARLY_128US (Offset 0x05B1) */ 8359 8360 #define BIT_SHIFT_TSFT_SEL_TIMER1 3 8361 #define BIT_MASK_TSFT_SEL_TIMER1 0x7 8362 #define BIT_TSFT_SEL_TIMER1(x) \ 8363 (((x) & BIT_MASK_TSFT_SEL_TIMER1) << BIT_SHIFT_TSFT_SEL_TIMER1) 8364 #define BIT_GET_TSFT_SEL_TIMER1(x) \ 8365 (((x) >> BIT_SHIFT_TSFT_SEL_TIMER1) & BIT_MASK_TSFT_SEL_TIMER1) 8366 8367 #define BIT_SHIFT_EARLY_128US 0 8368 #define BIT_MASK_EARLY_128US 0x7 8369 #define BIT_EARLY_128US(x) \ 8370 (((x) & BIT_MASK_EARLY_128US) << BIT_SHIFT_EARLY_128US) 8371 #define BIT_GET_EARLY_128US(x) \ 8372 (((x) >> BIT_SHIFT_EARLY_128US) & BIT_MASK_EARLY_128US) 8373 8374 /* 2 REG_P2PPS1_CTRL (Offset 0x05B2) */ 8375 8376 #define BIT_P2P1_CTW_ALLSTASLEEP BIT(7) 8377 #define BIT_P2P1_OFF_DISTX_EN BIT(6) 8378 #define BIT_P2P1_PWR_MGT_EN BIT(5) 8379 #define BIT_P2P1_NOA1_EN BIT(2) 8380 #define BIT_P2P1_NOA0_EN BIT(1) 8381 8382 /* 2 REG_P2PPS2_CTRL (Offset 0x05B3) */ 8383 8384 #define BIT_P2P2_CTW_ALLSTASLEEP BIT(7) 8385 #define BIT_P2P2_OFF_DISTX_EN BIT(6) 8386 #define BIT_P2P2_PWR_MGT_EN BIT(5) 8387 #define BIT_P2P2_NOA1_EN BIT(2) 8388 #define BIT_P2P2_NOA0_EN BIT(1) 8389 8390 /* 2 REG_TIMER0_SRC_SEL (Offset 0x05B4) */ 8391 8392 #define BIT_SHIFT_SYNC_CLI_SEL 4 8393 #define BIT_MASK_SYNC_CLI_SEL 0x7 8394 #define BIT_SYNC_CLI_SEL(x) \ 8395 (((x) & BIT_MASK_SYNC_CLI_SEL) << BIT_SHIFT_SYNC_CLI_SEL) 8396 #define BIT_GET_SYNC_CLI_SEL(x) \ 8397 (((x) >> BIT_SHIFT_SYNC_CLI_SEL) & BIT_MASK_SYNC_CLI_SEL) 8398 8399 #define BIT_SHIFT_TSFT_SEL_TIMER0 0 8400 #define BIT_MASK_TSFT_SEL_TIMER0 0x7 8401 #define BIT_TSFT_SEL_TIMER0(x) \ 8402 (((x) & BIT_MASK_TSFT_SEL_TIMER0) << BIT_SHIFT_TSFT_SEL_TIMER0) 8403 #define BIT_GET_TSFT_SEL_TIMER0(x) \ 8404 (((x) >> BIT_SHIFT_TSFT_SEL_TIMER0) & BIT_MASK_TSFT_SEL_TIMER0) 8405 8406 /* 2 REG_NOA_UNIT_SEL (Offset 0x05B5) */ 8407 8408 #define BIT_SHIFT_NOA_UNIT2_SEL 8 8409 #define BIT_MASK_NOA_UNIT2_SEL 0x7 8410 #define BIT_NOA_UNIT2_SEL(x) \ 8411 (((x) & BIT_MASK_NOA_UNIT2_SEL) << BIT_SHIFT_NOA_UNIT2_SEL) 8412 #define BIT_GET_NOA_UNIT2_SEL(x) \ 8413 (((x) >> BIT_SHIFT_NOA_UNIT2_SEL) & BIT_MASK_NOA_UNIT2_SEL) 8414 8415 #define BIT_SHIFT_NOA_UNIT1_SEL 4 8416 #define BIT_MASK_NOA_UNIT1_SEL 0x7 8417 #define BIT_NOA_UNIT1_SEL(x) \ 8418 (((x) & BIT_MASK_NOA_UNIT1_SEL) << BIT_SHIFT_NOA_UNIT1_SEL) 8419 #define BIT_GET_NOA_UNIT1_SEL(x) \ 8420 (((x) >> BIT_SHIFT_NOA_UNIT1_SEL) & BIT_MASK_NOA_UNIT1_SEL) 8421 8422 #define BIT_SHIFT_NOA_UNIT0_SEL 0 8423 #define BIT_MASK_NOA_UNIT0_SEL 0x7 8424 #define BIT_NOA_UNIT0_SEL(x) \ 8425 (((x) & BIT_MASK_NOA_UNIT0_SEL) << BIT_SHIFT_NOA_UNIT0_SEL) 8426 #define BIT_GET_NOA_UNIT0_SEL(x) \ 8427 (((x) >> BIT_SHIFT_NOA_UNIT0_SEL) & BIT_MASK_NOA_UNIT0_SEL) 8428 8429 /* 2 REG_P2POFF_DIS_TXTIME (Offset 0x05B7) */ 8430 8431 #define BIT_SHIFT_P2POFF_DIS_TXTIME 0 8432 #define BIT_MASK_P2POFF_DIS_TXTIME 0xff 8433 #define BIT_P2POFF_DIS_TXTIME(x) \ 8434 (((x) & BIT_MASK_P2POFF_DIS_TXTIME) << BIT_SHIFT_P2POFF_DIS_TXTIME) 8435 #define BIT_GET_P2POFF_DIS_TXTIME(x) \ 8436 (((x) >> BIT_SHIFT_P2POFF_DIS_TXTIME) & BIT_MASK_P2POFF_DIS_TXTIME) 8437 8438 /* 2 REG_MBSSID_BCN_SPACE2 (Offset 0x05B8) */ 8439 8440 #define BIT_SHIFT_BCN_SPACE_CLINT2 16 8441 #define BIT_MASK_BCN_SPACE_CLINT2 0xfff 8442 #define BIT_BCN_SPACE_CLINT2(x) \ 8443 (((x) & BIT_MASK_BCN_SPACE_CLINT2) << BIT_SHIFT_BCN_SPACE_CLINT2) 8444 #define BIT_GET_BCN_SPACE_CLINT2(x) \ 8445 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT2) & BIT_MASK_BCN_SPACE_CLINT2) 8446 8447 #define BIT_SHIFT_BCN_SPACE_CLINT1 0 8448 #define BIT_MASK_BCN_SPACE_CLINT1 0xfff 8449 #define BIT_BCN_SPACE_CLINT1(x) \ 8450 (((x) & BIT_MASK_BCN_SPACE_CLINT1) << BIT_SHIFT_BCN_SPACE_CLINT1) 8451 #define BIT_GET_BCN_SPACE_CLINT1(x) \ 8452 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT1) & BIT_MASK_BCN_SPACE_CLINT1) 8453 8454 /* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ 8455 8456 #define BIT_SHIFT_SUB_BCN_SPACE 16 8457 #define BIT_MASK_SUB_BCN_SPACE 0xff 8458 #define BIT_SUB_BCN_SPACE(x) \ 8459 (((x) & BIT_MASK_SUB_BCN_SPACE) << BIT_SHIFT_SUB_BCN_SPACE) 8460 #define BIT_GET_SUB_BCN_SPACE(x) \ 8461 (((x) >> BIT_SHIFT_SUB_BCN_SPACE) & BIT_MASK_SUB_BCN_SPACE) 8462 8463 /* 2 REG_MBSSID_BCN_SPACE3 (Offset 0x05BC) */ 8464 8465 #define BIT_SHIFT_BCN_SPACE_CLINT3 0 8466 #define BIT_MASK_BCN_SPACE_CLINT3 0xfff 8467 #define BIT_BCN_SPACE_CLINT3(x) \ 8468 (((x) & BIT_MASK_BCN_SPACE_CLINT3) << BIT_SHIFT_BCN_SPACE_CLINT3) 8469 #define BIT_GET_BCN_SPACE_CLINT3(x) \ 8470 (((x) >> BIT_SHIFT_BCN_SPACE_CLINT3) & BIT_MASK_BCN_SPACE_CLINT3) 8471 8472 /* 2 REG_ACMHWCTRL (Offset 0x05C0) */ 8473 8474 #define BIT_BEQ_ACM_STATUS BIT(7) 8475 #define BIT_VIQ_ACM_STATUS BIT(6) 8476 #define BIT_VOQ_ACM_STATUS BIT(5) 8477 #define BIT_BEQ_ACM_EN BIT(3) 8478 #define BIT_VIQ_ACM_EN BIT(2) 8479 #define BIT_VOQ_ACM_EN BIT(1) 8480 #define BIT_ACMHWEN BIT(0) 8481 8482 /* 2 REG_ACMRSTCTRL (Offset 0x05C1) */ 8483 8484 #define BIT_BE_ACM_RESET_USED_TIME BIT(2) 8485 #define BIT_VI_ACM_RESET_USED_TIME BIT(1) 8486 #define BIT_VO_ACM_RESET_USED_TIME BIT(0) 8487 8488 /* 2 REG_ACMAVG (Offset 0x05C2) */ 8489 8490 #define BIT_SHIFT_AVGPERIOD 0 8491 #define BIT_MASK_AVGPERIOD 0xffff 8492 #define BIT_AVGPERIOD(x) (((x) & BIT_MASK_AVGPERIOD) << BIT_SHIFT_AVGPERIOD) 8493 #define BIT_GET_AVGPERIOD(x) (((x) >> BIT_SHIFT_AVGPERIOD) & BIT_MASK_AVGPERIOD) 8494 8495 /* 2 REG_VO_ADMTIME (Offset 0x05C4) */ 8496 8497 #define BIT_SHIFT_VO_ADMITTED_TIME 0 8498 #define BIT_MASK_VO_ADMITTED_TIME 0xffff 8499 #define BIT_VO_ADMITTED_TIME(x) \ 8500 (((x) & BIT_MASK_VO_ADMITTED_TIME) << BIT_SHIFT_VO_ADMITTED_TIME) 8501 #define BIT_GET_VO_ADMITTED_TIME(x) \ 8502 (((x) >> BIT_SHIFT_VO_ADMITTED_TIME) & BIT_MASK_VO_ADMITTED_TIME) 8503 8504 /* 2 REG_VI_ADMTIME (Offset 0x05C6) */ 8505 8506 #define BIT_SHIFT_VI_ADMITTED_TIME 0 8507 #define BIT_MASK_VI_ADMITTED_TIME 0xffff 8508 #define BIT_VI_ADMITTED_TIME(x) \ 8509 (((x) & BIT_MASK_VI_ADMITTED_TIME) << BIT_SHIFT_VI_ADMITTED_TIME) 8510 #define BIT_GET_VI_ADMITTED_TIME(x) \ 8511 (((x) >> BIT_SHIFT_VI_ADMITTED_TIME) & BIT_MASK_VI_ADMITTED_TIME) 8512 8513 /* 2 REG_BE_ADMTIME (Offset 0x05C8) */ 8514 8515 #define BIT_SHIFT_BE_ADMITTED_TIME 0 8516 #define BIT_MASK_BE_ADMITTED_TIME 0xffff 8517 #define BIT_BE_ADMITTED_TIME(x) \ 8518 (((x) & BIT_MASK_BE_ADMITTED_TIME) << BIT_SHIFT_BE_ADMITTED_TIME) 8519 #define BIT_GET_BE_ADMITTED_TIME(x) \ 8520 (((x) >> BIT_SHIFT_BE_ADMITTED_TIME) & BIT_MASK_BE_ADMITTED_TIME) 8521 8522 /* 2 REG_EDCA_RANDOM_GEN (Offset 0x05CC) */ 8523 8524 #define BIT_SHIFT_RANDOM_GEN 0 8525 #define BIT_MASK_RANDOM_GEN 0xffffff 8526 #define BIT_RANDOM_GEN(x) (((x) & BIT_MASK_RANDOM_GEN) << BIT_SHIFT_RANDOM_GEN) 8527 #define BIT_GET_RANDOM_GEN(x) \ 8528 (((x) >> BIT_SHIFT_RANDOM_GEN) & BIT_MASK_RANDOM_GEN) 8529 8530 /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ 8531 8532 #define BIT_SHIFT_NOA_SEL 4 8533 #define BIT_MASK_NOA_SEL 0x7 8534 #define BIT_NOA_SEL(x) (((x) & BIT_MASK_NOA_SEL) << BIT_SHIFT_NOA_SEL) 8535 #define BIT_GET_NOA_SEL(x) (((x) >> BIT_SHIFT_NOA_SEL) & BIT_MASK_NOA_SEL) 8536 8537 /* 2 REG_TXCMD_NOA_SEL (Offset 0x05CF) */ 8538 8539 #define BIT_SHIFT_TXCMD_SEG_SEL 0 8540 #define BIT_MASK_TXCMD_SEG_SEL 0xf 8541 #define BIT_TXCMD_SEG_SEL(x) \ 8542 (((x) & BIT_MASK_TXCMD_SEG_SEL) << BIT_SHIFT_TXCMD_SEG_SEL) 8543 #define BIT_GET_TXCMD_SEG_SEL(x) \ 8544 (((x) >> BIT_SHIFT_TXCMD_SEG_SEL) & BIT_MASK_TXCMD_SEG_SEL) 8545 8546 /* 2 REG_NOA_PARAM (Offset 0x05E0) */ 8547 8548 #define BIT_SHIFT_NOA_COUNT (96 & CPU_OPT_WIDTH) 8549 #define BIT_MASK_NOA_COUNT 0xff 8550 #define BIT_NOA_COUNT(x) (((x) & BIT_MASK_NOA_COUNT) << BIT_SHIFT_NOA_COUNT) 8551 #define BIT_GET_NOA_COUNT(x) (((x) >> BIT_SHIFT_NOA_COUNT) & BIT_MASK_NOA_COUNT) 8552 8553 #define BIT_SHIFT_NOA_START_TIME (64 & CPU_OPT_WIDTH) 8554 #define BIT_MASK_NOA_START_TIME 0xffffffffL 8555 #define BIT_NOA_START_TIME(x) \ 8556 (((x) & BIT_MASK_NOA_START_TIME) << BIT_SHIFT_NOA_START_TIME) 8557 #define BIT_GET_NOA_START_TIME(x) \ 8558 (((x) >> BIT_SHIFT_NOA_START_TIME) & BIT_MASK_NOA_START_TIME) 8559 8560 #define BIT_SHIFT_NOA_INTERVAL (32 & CPU_OPT_WIDTH) 8561 #define BIT_MASK_NOA_INTERVAL 0xffffffffL 8562 #define BIT_NOA_INTERVAL(x) \ 8563 (((x) & BIT_MASK_NOA_INTERVAL) << BIT_SHIFT_NOA_INTERVAL) 8564 #define BIT_GET_NOA_INTERVAL(x) \ 8565 (((x) >> BIT_SHIFT_NOA_INTERVAL) & BIT_MASK_NOA_INTERVAL) 8566 8567 #define BIT_SHIFT_NOA_DURATION 0 8568 #define BIT_MASK_NOA_DURATION 0xffffffffL 8569 #define BIT_NOA_DURATION(x) \ 8570 (((x) & BIT_MASK_NOA_DURATION) << BIT_SHIFT_NOA_DURATION) 8571 #define BIT_GET_NOA_DURATION(x) \ 8572 (((x) >> BIT_SHIFT_NOA_DURATION) & BIT_MASK_NOA_DURATION) 8573 8574 /* 2 REG_P2P_RST (Offset 0x05F0) */ 8575 8576 #define BIT_P2P2_PWR_RST1 BIT(5) 8577 #define BIT_P2P2_PWR_RST0 BIT(4) 8578 #define BIT_P2P1_PWR_RST1 BIT(3) 8579 #define BIT_P2P1_PWR_RST0 BIT(2) 8580 #define BIT_P2P_PWR_RST1_V1 BIT(1) 8581 #define BIT_P2P_PWR_RST0_V1 BIT(0) 8582 8583 /* 2 REG_SCHEDULER_RST (Offset 0x05F1) */ 8584 8585 #define BIT_SYNC_CLI BIT(1) 8586 #define BIT_SCHEDULER_RST_V1 BIT(0) 8587 8588 /* 2 REG_SCH_TXCMD (Offset 0x05F8) */ 8589 8590 #define BIT_SHIFT_SCH_TXCMD 0 8591 #define BIT_MASK_SCH_TXCMD 0xffffffffL 8592 #define BIT_SCH_TXCMD(x) (((x) & BIT_MASK_SCH_TXCMD) << BIT_SHIFT_SCH_TXCMD) 8593 #define BIT_GET_SCH_TXCMD(x) (((x) >> BIT_SHIFT_SCH_TXCMD) & BIT_MASK_SCH_TXCMD) 8594 8595 /* 2 REG_WMAC_CR (Offset 0x0600) */ 8596 8597 #define BIT_IC_MACPHY_M BIT(0) 8598 8599 /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ 8600 8601 #define BIT_FWEN BIT(7) 8602 8603 /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ 8604 8605 #define BIT_PHYSTS_PKT_CTRL BIT(6) 8606 8607 /* 2 REG_WMAC_FWPKT_CR (Offset 0x0601) */ 8608 8609 #define BIT_APPHDR_MIDSRCH_FAIL BIT(4) 8610 #define BIT_FWPARSING_EN BIT(3) 8611 8612 #define BIT_SHIFT_APPEND_MHDR_LEN 0 8613 #define BIT_MASK_APPEND_MHDR_LEN 0x7 8614 #define BIT_APPEND_MHDR_LEN(x) \ 8615 (((x) & BIT_MASK_APPEND_MHDR_LEN) << BIT_SHIFT_APPEND_MHDR_LEN) 8616 #define BIT_GET_APPEND_MHDR_LEN(x) \ 8617 (((x) >> BIT_SHIFT_APPEND_MHDR_LEN) & BIT_MASK_APPEND_MHDR_LEN) 8618 8619 /* 2 REG_TCR (Offset 0x0604) */ 8620 8621 #define BIT_WMAC_EN_RTS_ADDR BIT(31) 8622 #define BIT_WMAC_DISABLE_CCK BIT(30) 8623 #define BIT_WMAC_RAW_LEN BIT(29) 8624 #define BIT_WMAC_NOTX_IN_RXNDP BIT(28) 8625 #define BIT_WMAC_EN_EOF BIT(27) 8626 #define BIT_WMAC_BF_SEL BIT(26) 8627 #define BIT_WMAC_ANTMODE_SEL BIT(25) 8628 8629 /* 2 REG_TCR (Offset 0x0604) */ 8630 8631 #define BIT_WMAC_TCRPWRMGT_HWCTL BIT(24) 8632 8633 /* 2 REG_TCR (Offset 0x0604) */ 8634 8635 #define BIT_WMAC_SMOOTH_VAL BIT(23) 8636 8637 /* 2 REG_TCR (Offset 0x0604) */ 8638 8639 #define BIT_FETCH_MPDU_AFTER_WSEC_RDY BIT(20) 8640 8641 /* 2 REG_TCR (Offset 0x0604) */ 8642 8643 #define BIT_WMAC_TCR_EN_20MST BIT(19) 8644 #define BIT_WMAC_DIS_SIGTA BIT(18) 8645 #define BIT_WMAC_DIS_A2B0 BIT(17) 8646 #define BIT_WMAC_MSK_SIGBCRC BIT(16) 8647 8648 /* 2 REG_TCR (Offset 0x0604) */ 8649 8650 #define BIT_WMAC_TCR_ERRSTEN_3 BIT(15) 8651 #define BIT_WMAC_TCR_ERRSTEN_2 BIT(14) 8652 #define BIT_WMAC_TCR_ERRSTEN_1 BIT(13) 8653 #define BIT_WMAC_TCR_ERRSTEN_0 BIT(12) 8654 #define BIT_WMAC_TCR_TXSK_PERPKT BIT(11) 8655 #define BIT_ICV BIT(10) 8656 #define BIT_CFEND_FORMAT BIT(9) 8657 #define BIT_CRC BIT(8) 8658 #define BIT_PWRBIT_OW_EN BIT(7) 8659 #define BIT_PWR_ST BIT(6) 8660 #define BIT_WMAC_TCR_UPD_TIMIE BIT(5) 8661 #define BIT_WMAC_TCR_UPD_HGQMD BIT(4) 8662 8663 /* 2 REG_TCR (Offset 0x0604) */ 8664 8665 #define BIT_VHTSIGA1_TXPS BIT(3) 8666 8667 /* 2 REG_TCR (Offset 0x0604) */ 8668 8669 #define BIT_PAD_SEL BIT(2) 8670 #define BIT_DIS_GCLK BIT(1) 8671 8672 /* 2 REG_RCR (Offset 0x0608) */ 8673 8674 #define BIT_APP_FCS BIT(31) 8675 #define BIT_APP_MIC BIT(30) 8676 #define BIT_APP_ICV BIT(29) 8677 #define BIT_APP_PHYSTS BIT(28) 8678 #define BIT_APP_BASSN BIT(27) 8679 8680 /* 2 REG_RCR (Offset 0x0608) */ 8681 8682 #define BIT_VHT_DACK BIT(26) 8683 8684 /* 2 REG_RCR (Offset 0x0608) */ 8685 8686 #define BIT_TCPOFLD_EN BIT(25) 8687 #define BIT_ENMBID BIT(24) 8688 #define BIT_LSIGEN BIT(23) 8689 #define BIT_MFBEN BIT(22) 8690 #define BIT_DISCHKPPDLLEN BIT(21) 8691 #define BIT_PKTCTL_DLEN BIT(20) 8692 #define BIT_TIM_PARSER_EN BIT(18) 8693 #define BIT_BC_MD_EN BIT(17) 8694 #define BIT_UC_MD_EN BIT(16) 8695 #define BIT_RXSK_PERPKT BIT(15) 8696 #define BIT_HTC_LOC_CTRL BIT(14) 8697 8698 /* 2 REG_RCR (Offset 0x0608) */ 8699 8700 #define BIT_RPFM_CAM_ENABLE BIT(12) 8701 8702 /* 2 REG_RCR (Offset 0x0608) */ 8703 8704 #define BIT_TA_BCN BIT(11) 8705 8706 /* 2 REG_RCR (Offset 0x0608) */ 8707 8708 #define BIT_DISDECMYPKT BIT(10) 8709 #define BIT_AICV BIT(9) 8710 #define BIT_ACRC32 BIT(8) 8711 #define BIT_CBSSID_BCN BIT(7) 8712 #define BIT_CBSSID_DATA BIT(6) 8713 #define BIT_APWRMGT BIT(5) 8714 #define BIT_ADD3 BIT(4) 8715 #define BIT_AB BIT(3) 8716 #define BIT_AM BIT(2) 8717 #define BIT_APM BIT(1) 8718 #define BIT_AAP BIT(0) 8719 8720 /* 2 REG_RX_PKT_LIMIT (Offset 0x060C) */ 8721 8722 #define BIT_SHIFT_RXPKTLMT 0 8723 #define BIT_MASK_RXPKTLMT 0x3f 8724 #define BIT_RXPKTLMT(x) (((x) & BIT_MASK_RXPKTLMT) << BIT_SHIFT_RXPKTLMT) 8725 #define BIT_GET_RXPKTLMT(x) (((x) >> BIT_SHIFT_RXPKTLMT) & BIT_MASK_RXPKTLMT) 8726 8727 /* 2 REG_RX_DLK_TIME (Offset 0x060D) */ 8728 8729 #define BIT_SHIFT_RX_DLK_TIME 0 8730 #define BIT_MASK_RX_DLK_TIME 0xff 8731 #define BIT_RX_DLK_TIME(x) \ 8732 (((x) & BIT_MASK_RX_DLK_TIME) << BIT_SHIFT_RX_DLK_TIME) 8733 #define BIT_GET_RX_DLK_TIME(x) \ 8734 (((x) >> BIT_SHIFT_RX_DLK_TIME) & BIT_MASK_RX_DLK_TIME) 8735 8736 /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8737 8738 #define BIT_DATA_RPFM15EN BIT(15) 8739 #define BIT_DATA_RPFM14EN BIT(14) 8740 #define BIT_DATA_RPFM13EN BIT(13) 8741 #define BIT_DATA_RPFM12EN BIT(12) 8742 #define BIT_DATA_RPFM11EN BIT(11) 8743 #define BIT_DATA_RPFM10EN BIT(10) 8744 #define BIT_DATA_RPFM9EN BIT(9) 8745 #define BIT_DATA_RPFM8EN BIT(8) 8746 8747 /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8748 8749 #define BIT_PHYSTS_PER_PKT_MODE BIT(7) 8750 #define BIT_DATA_RPFM7EN BIT(7) 8751 8752 /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8753 8754 #define BIT_DATA_RPFM6EN BIT(6) 8755 8756 /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8757 8758 #define BIT_DATA_RPFM5EN BIT(5) 8759 #define BIT_DATA_RPFM4EN BIT(4) 8760 #define BIT_DATA_RPFM3EN BIT(3) 8761 #define BIT_DATA_RPFM2EN BIT(2) 8762 #define BIT_DATA_RPFM1EN BIT(1) 8763 8764 /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8765 8766 #define BIT_SHIFT_DRVINFO_SZ_V1 0 8767 #define BIT_MASK_DRVINFO_SZ_V1 0xf 8768 #define BIT_DRVINFO_SZ_V1(x) \ 8769 (((x) & BIT_MASK_DRVINFO_SZ_V1) << BIT_SHIFT_DRVINFO_SZ_V1) 8770 #define BIT_GET_DRVINFO_SZ_V1(x) \ 8771 (((x) >> BIT_SHIFT_DRVINFO_SZ_V1) & BIT_MASK_DRVINFO_SZ_V1) 8772 8773 /* 2 REG_RX_DRVINFO_SZ (Offset 0x060F) */ 8774 8775 #define BIT_DATA_RPFM0EN BIT(0) 8776 8777 /* 2 REG_MACID (Offset 0x0610) */ 8778 8779 #define BIT_SHIFT_MACID 0 8780 #define BIT_MASK_MACID 0xffffffffffffL 8781 #define BIT_MACID(x) (((x) & BIT_MASK_MACID) << BIT_SHIFT_MACID) 8782 #define BIT_GET_MACID(x) (((x) >> BIT_SHIFT_MACID) & BIT_MASK_MACID) 8783 8784 /* 2 REG_BSSID (Offset 0x0618) */ 8785 8786 #define BIT_SHIFT_BSSID 0 8787 #define BIT_MASK_BSSID 0xffffffffffffL 8788 #define BIT_BSSID(x) (((x) & BIT_MASK_BSSID) << BIT_SHIFT_BSSID) 8789 #define BIT_GET_BSSID(x) (((x) >> BIT_SHIFT_BSSID) & BIT_MASK_BSSID) 8790 8791 /* 2 REG_MAR (Offset 0x0620) */ 8792 8793 #define BIT_SHIFT_MAR 0 8794 #define BIT_MASK_MAR 0xffffffffffffffffL 8795 #define BIT_MAR(x) (((x) & BIT_MASK_MAR) << BIT_SHIFT_MAR) 8796 #define BIT_GET_MAR(x) (((x) >> BIT_SHIFT_MAR) & BIT_MASK_MAR) 8797 8798 /* 2 REG_MBIDCAMCFG_1 (Offset 0x0628) */ 8799 8800 #define BIT_SHIFT_MBIDCAM_RWDATA_L 0 8801 #define BIT_MASK_MBIDCAM_RWDATA_L 0xffffffffL 8802 #define BIT_MBIDCAM_RWDATA_L(x) \ 8803 (((x) & BIT_MASK_MBIDCAM_RWDATA_L) << BIT_SHIFT_MBIDCAM_RWDATA_L) 8804 #define BIT_GET_MBIDCAM_RWDATA_L(x) \ 8805 (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_L) & BIT_MASK_MBIDCAM_RWDATA_L) 8806 8807 /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ 8808 8809 #define BIT_MBIDCAM_POLL BIT(31) 8810 #define BIT_MBIDCAM_WT_EN BIT(30) 8811 8812 #define BIT_SHIFT_MBIDCAM_ADDR 24 8813 #define BIT_MASK_MBIDCAM_ADDR 0x1f 8814 #define BIT_MBIDCAM_ADDR(x) \ 8815 (((x) & BIT_MASK_MBIDCAM_ADDR) << BIT_SHIFT_MBIDCAM_ADDR) 8816 #define BIT_GET_MBIDCAM_ADDR(x) \ 8817 (((x) >> BIT_SHIFT_MBIDCAM_ADDR) & BIT_MASK_MBIDCAM_ADDR) 8818 8819 #define BIT_MBIDCAM_VALID BIT(23) 8820 #define BIT_LSIC_TXOP_EN BIT(17) 8821 8822 /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ 8823 8824 #define BIT_CTS_EN BIT(16) 8825 8826 /* 2 REG_MBIDCAMCFG_2 (Offset 0x062C) */ 8827 8828 #define BIT_SHIFT_MBIDCAM_RWDATA_H 0 8829 #define BIT_MASK_MBIDCAM_RWDATA_H 0xffff 8830 #define BIT_MBIDCAM_RWDATA_H(x) \ 8831 (((x) & BIT_MASK_MBIDCAM_RWDATA_H) << BIT_SHIFT_MBIDCAM_RWDATA_H) 8832 #define BIT_GET_MBIDCAM_RWDATA_H(x) \ 8833 (((x) >> BIT_SHIFT_MBIDCAM_RWDATA_H) & BIT_MASK_MBIDCAM_RWDATA_H) 8834 8835 /* 2 REG_WMAC_TCR_TSFT_OFS (Offset 0x0630) */ 8836 8837 #define BIT_SHIFT_WMAC_TCR_TSFT_OFS 0 8838 #define BIT_MASK_WMAC_TCR_TSFT_OFS 0xffff 8839 #define BIT_WMAC_TCR_TSFT_OFS(x) \ 8840 (((x) & BIT_MASK_WMAC_TCR_TSFT_OFS) << BIT_SHIFT_WMAC_TCR_TSFT_OFS) 8841 #define BIT_GET_WMAC_TCR_TSFT_OFS(x) \ 8842 (((x) >> BIT_SHIFT_WMAC_TCR_TSFT_OFS) & BIT_MASK_WMAC_TCR_TSFT_OFS) 8843 8844 /* 2 REG_UDF_THSD (Offset 0x0632) */ 8845 8846 #define BIT_SHIFT_UDF_THSD 0 8847 #define BIT_MASK_UDF_THSD 0xff 8848 #define BIT_UDF_THSD(x) (((x) & BIT_MASK_UDF_THSD) << BIT_SHIFT_UDF_THSD) 8849 #define BIT_GET_UDF_THSD(x) (((x) >> BIT_SHIFT_UDF_THSD) & BIT_MASK_UDF_THSD) 8850 8851 /* 2 REG_ZLD_NUM (Offset 0x0633) */ 8852 8853 #define BIT_SHIFT_ZLD_NUM 0 8854 #define BIT_MASK_ZLD_NUM 0xff 8855 #define BIT_ZLD_NUM(x) (((x) & BIT_MASK_ZLD_NUM) << BIT_SHIFT_ZLD_NUM) 8856 #define BIT_GET_ZLD_NUM(x) (((x) >> BIT_SHIFT_ZLD_NUM) & BIT_MASK_ZLD_NUM) 8857 8858 /* 2 REG_STMP_THSD (Offset 0x0634) */ 8859 8860 #define BIT_SHIFT_STMP_THSD 0 8861 #define BIT_MASK_STMP_THSD 0xff 8862 #define BIT_STMP_THSD(x) (((x) & BIT_MASK_STMP_THSD) << BIT_SHIFT_STMP_THSD) 8863 #define BIT_GET_STMP_THSD(x) (((x) >> BIT_SHIFT_STMP_THSD) & BIT_MASK_STMP_THSD) 8864 8865 /* 2 REG_WMAC_TXTIMEOUT (Offset 0x0635) */ 8866 8867 #define BIT_SHIFT_WMAC_TXTIMEOUT 0 8868 #define BIT_MASK_WMAC_TXTIMEOUT 0xff 8869 #define BIT_WMAC_TXTIMEOUT(x) \ 8870 (((x) & BIT_MASK_WMAC_TXTIMEOUT) << BIT_SHIFT_WMAC_TXTIMEOUT) 8871 #define BIT_GET_WMAC_TXTIMEOUT(x) \ 8872 (((x) >> BIT_SHIFT_WMAC_TXTIMEOUT) & BIT_MASK_WMAC_TXTIMEOUT) 8873 8874 /* 2 REG_MCU_TEST_2_V1 (Offset 0x0636) */ 8875 8876 #define BIT_SHIFT_MCU_RSVD_2_V1 0 8877 #define BIT_MASK_MCU_RSVD_2_V1 0xffff 8878 #define BIT_MCU_RSVD_2_V1(x) \ 8879 (((x) & BIT_MASK_MCU_RSVD_2_V1) << BIT_SHIFT_MCU_RSVD_2_V1) 8880 #define BIT_GET_MCU_RSVD_2_V1(x) \ 8881 (((x) >> BIT_SHIFT_MCU_RSVD_2_V1) & BIT_MASK_MCU_RSVD_2_V1) 8882 8883 /* 2 REG_USTIME_EDCA (Offset 0x0638) */ 8884 8885 #define BIT_SHIFT_USTIME_EDCA_V1 0 8886 #define BIT_MASK_USTIME_EDCA_V1 0x1ff 8887 #define BIT_USTIME_EDCA_V1(x) \ 8888 (((x) & BIT_MASK_USTIME_EDCA_V1) << BIT_SHIFT_USTIME_EDCA_V1) 8889 #define BIT_GET_USTIME_EDCA_V1(x) \ 8890 (((x) >> BIT_SHIFT_USTIME_EDCA_V1) & BIT_MASK_USTIME_EDCA_V1) 8891 8892 /* 2 REG_MAC_SPEC_SIFS (Offset 0x063A) */ 8893 8894 #define BIT_SHIFT_SPEC_SIFS_OFDM 8 8895 #define BIT_MASK_SPEC_SIFS_OFDM 0xff 8896 #define BIT_SPEC_SIFS_OFDM(x) \ 8897 (((x) & BIT_MASK_SPEC_SIFS_OFDM) << BIT_SHIFT_SPEC_SIFS_OFDM) 8898 #define BIT_GET_SPEC_SIFS_OFDM(x) \ 8899 (((x) >> BIT_SHIFT_SPEC_SIFS_OFDM) & BIT_MASK_SPEC_SIFS_OFDM) 8900 8901 #define BIT_SHIFT_SPEC_SIFS_CCK 0 8902 #define BIT_MASK_SPEC_SIFS_CCK 0xff 8903 #define BIT_SPEC_SIFS_CCK(x) \ 8904 (((x) & BIT_MASK_SPEC_SIFS_CCK) << BIT_SHIFT_SPEC_SIFS_CCK) 8905 #define BIT_GET_SPEC_SIFS_CCK(x) \ 8906 (((x) >> BIT_SHIFT_SPEC_SIFS_CCK) & BIT_MASK_SPEC_SIFS_CCK) 8907 8908 /* 2 REG_RESP_SIFS_CCK (Offset 0x063C) */ 8909 8910 #define BIT_SHIFT_SIFS_R2T_CCK 8 8911 #define BIT_MASK_SIFS_R2T_CCK 0xff 8912 #define BIT_SIFS_R2T_CCK(x) \ 8913 (((x) & BIT_MASK_SIFS_R2T_CCK) << BIT_SHIFT_SIFS_R2T_CCK) 8914 #define BIT_GET_SIFS_R2T_CCK(x) \ 8915 (((x) >> BIT_SHIFT_SIFS_R2T_CCK) & BIT_MASK_SIFS_R2T_CCK) 8916 8917 #define BIT_SHIFT_SIFS_T2T_CCK 0 8918 #define BIT_MASK_SIFS_T2T_CCK 0xff 8919 #define BIT_SIFS_T2T_CCK(x) \ 8920 (((x) & BIT_MASK_SIFS_T2T_CCK) << BIT_SHIFT_SIFS_T2T_CCK) 8921 #define BIT_GET_SIFS_T2T_CCK(x) \ 8922 (((x) >> BIT_SHIFT_SIFS_T2T_CCK) & BIT_MASK_SIFS_T2T_CCK) 8923 8924 /* 2 REG_RESP_SIFS_OFDM (Offset 0x063E) */ 8925 8926 #define BIT_SHIFT_SIFS_R2T_OFDM 8 8927 #define BIT_MASK_SIFS_R2T_OFDM 0xff 8928 #define BIT_SIFS_R2T_OFDM(x) \ 8929 (((x) & BIT_MASK_SIFS_R2T_OFDM) << BIT_SHIFT_SIFS_R2T_OFDM) 8930 #define BIT_GET_SIFS_R2T_OFDM(x) \ 8931 (((x) >> BIT_SHIFT_SIFS_R2T_OFDM) & BIT_MASK_SIFS_R2T_OFDM) 8932 8933 #define BIT_SHIFT_SIFS_T2T_OFDM 0 8934 #define BIT_MASK_SIFS_T2T_OFDM 0xff 8935 #define BIT_SIFS_T2T_OFDM(x) \ 8936 (((x) & BIT_MASK_SIFS_T2T_OFDM) << BIT_SHIFT_SIFS_T2T_OFDM) 8937 #define BIT_GET_SIFS_T2T_OFDM(x) \ 8938 (((x) >> BIT_SHIFT_SIFS_T2T_OFDM) & BIT_MASK_SIFS_T2T_OFDM) 8939 8940 /* 2 REG_ACKTO (Offset 0x0640) */ 8941 8942 #define BIT_SHIFT_ACKTO 0 8943 #define BIT_MASK_ACKTO 0xff 8944 #define BIT_ACKTO(x) (((x) & BIT_MASK_ACKTO) << BIT_SHIFT_ACKTO) 8945 #define BIT_GET_ACKTO(x) (((x) >> BIT_SHIFT_ACKTO) & BIT_MASK_ACKTO) 8946 8947 /* 2 REG_CTS2TO (Offset 0x0641) */ 8948 8949 #define BIT_SHIFT_CTS2TO 0 8950 #define BIT_MASK_CTS2TO 0xff 8951 #define BIT_CTS2TO(x) (((x) & BIT_MASK_CTS2TO) << BIT_SHIFT_CTS2TO) 8952 #define BIT_GET_CTS2TO(x) (((x) >> BIT_SHIFT_CTS2TO) & BIT_MASK_CTS2TO) 8953 8954 /* 2 REG_EIFS (Offset 0x0642) */ 8955 8956 #define BIT_SHIFT_EIFS 0 8957 #define BIT_MASK_EIFS 0xffff 8958 #define BIT_EIFS(x) (((x) & BIT_MASK_EIFS) << BIT_SHIFT_EIFS) 8959 #define BIT_GET_EIFS(x) (((x) >> BIT_SHIFT_EIFS) & BIT_MASK_EIFS) 8960 8961 /* 2 REG_NAV_CTRL (Offset 0x0650) */ 8962 8963 #define BIT_SHIFT_NAV_UPPER 16 8964 #define BIT_MASK_NAV_UPPER 0xff 8965 #define BIT_NAV_UPPER(x) (((x) & BIT_MASK_NAV_UPPER) << BIT_SHIFT_NAV_UPPER) 8966 #define BIT_GET_NAV_UPPER(x) (((x) >> BIT_SHIFT_NAV_UPPER) & BIT_MASK_NAV_UPPER) 8967 8968 #define BIT_SHIFT_RXMYRTS_NAV 8 8969 #define BIT_MASK_RXMYRTS_NAV 0xf 8970 #define BIT_RXMYRTS_NAV(x) \ 8971 (((x) & BIT_MASK_RXMYRTS_NAV) << BIT_SHIFT_RXMYRTS_NAV) 8972 #define BIT_GET_RXMYRTS_NAV(x) \ 8973 (((x) >> BIT_SHIFT_RXMYRTS_NAV) & BIT_MASK_RXMYRTS_NAV) 8974 8975 #define BIT_SHIFT_RTSRST 0 8976 #define BIT_MASK_RTSRST 0xff 8977 #define BIT_RTSRST(x) (((x) & BIT_MASK_RTSRST) << BIT_SHIFT_RTSRST) 8978 #define BIT_GET_RTSRST(x) (((x) >> BIT_SHIFT_RTSRST) & BIT_MASK_RTSRST) 8979 8980 /* 2 REG_BACAMCMD (Offset 0x0654) */ 8981 8982 #define BIT_BACAM_POLL BIT(31) 8983 #define BIT_BACAM_RST BIT(17) 8984 #define BIT_BACAM_RW BIT(16) 8985 8986 #define BIT_SHIFT_TXSBM 14 8987 #define BIT_MASK_TXSBM 0x3 8988 #define BIT_TXSBM(x) (((x) & BIT_MASK_TXSBM) << BIT_SHIFT_TXSBM) 8989 #define BIT_GET_TXSBM(x) (((x) >> BIT_SHIFT_TXSBM) & BIT_MASK_TXSBM) 8990 8991 #define BIT_SHIFT_BACAM_ADDR 0 8992 #define BIT_MASK_BACAM_ADDR 0x3f 8993 #define BIT_BACAM_ADDR(x) (((x) & BIT_MASK_BACAM_ADDR) << BIT_SHIFT_BACAM_ADDR) 8994 #define BIT_GET_BACAM_ADDR(x) \ 8995 (((x) >> BIT_SHIFT_BACAM_ADDR) & BIT_MASK_BACAM_ADDR) 8996 8997 /* 2 REG_BACAMCONTENT (Offset 0x0658) */ 8998 8999 #define BIT_SHIFT_BA_CONTENT_H (32 & CPU_OPT_WIDTH) 9000 #define BIT_MASK_BA_CONTENT_H 0xffffffffL 9001 #define BIT_BA_CONTENT_H(x) \ 9002 (((x) & BIT_MASK_BA_CONTENT_H) << BIT_SHIFT_BA_CONTENT_H) 9003 #define BIT_GET_BA_CONTENT_H(x) \ 9004 (((x) >> BIT_SHIFT_BA_CONTENT_H) & BIT_MASK_BA_CONTENT_H) 9005 9006 #define BIT_SHIFT_BA_CONTENT_L 0 9007 #define BIT_MASK_BA_CONTENT_L 0xffffffffL 9008 #define BIT_BA_CONTENT_L(x) \ 9009 (((x) & BIT_MASK_BA_CONTENT_L) << BIT_SHIFT_BA_CONTENT_L) 9010 #define BIT_GET_BA_CONTENT_L(x) \ 9011 (((x) >> BIT_SHIFT_BA_CONTENT_L) & BIT_MASK_BA_CONTENT_L) 9012 9013 /* 2 REG_LBDLY (Offset 0x0660) */ 9014 9015 #define BIT_SHIFT_LBDLY 0 9016 #define BIT_MASK_LBDLY 0x1f 9017 #define BIT_LBDLY(x) (((x) & BIT_MASK_LBDLY) << BIT_SHIFT_LBDLY) 9018 #define BIT_GET_LBDLY(x) (((x) >> BIT_SHIFT_LBDLY) & BIT_MASK_LBDLY) 9019 9020 /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ 9021 9022 #define BIT_SHIFT_BITMAP_SSNBK_COUNTER 2 9023 #define BIT_MASK_BITMAP_SSNBK_COUNTER 0x3f 9024 #define BIT_BITMAP_SSNBK_COUNTER(x) \ 9025 (((x) & BIT_MASK_BITMAP_SSNBK_COUNTER) \ 9026 << BIT_SHIFT_BITMAP_SSNBK_COUNTER) 9027 #define BIT_GET_BITMAP_SSNBK_COUNTER(x) \ 9028 (((x) >> BIT_SHIFT_BITMAP_SSNBK_COUNTER) & \ 9029 BIT_MASK_BITMAP_SSNBK_COUNTER) 9030 9031 #define BIT_BITMAP_EN BIT(1) 9032 9033 /* 2 REG_WMAC_BACAM_RPMEN (Offset 0x0661) */ 9034 9035 #define BIT_WMAC_BACAM_RPMEN BIT(0) 9036 9037 /* 2 REG_TX_RX (Offset 0x0662) */ 9038 9039 #define BIT_SHIFT_RXPKT_TYPE 2 9040 #define BIT_MASK_RXPKT_TYPE 0x3f 9041 #define BIT_RXPKT_TYPE(x) (((x) & BIT_MASK_RXPKT_TYPE) << BIT_SHIFT_RXPKT_TYPE) 9042 #define BIT_GET_RXPKT_TYPE(x) \ 9043 (((x) >> BIT_SHIFT_RXPKT_TYPE) & BIT_MASK_RXPKT_TYPE) 9044 9045 #define BIT_TXACT_IND BIT(1) 9046 #define BIT_RXACT_IND BIT(0) 9047 9048 /* 2 REG_WMAC_BITMAP_CTL (Offset 0x0663) */ 9049 9050 #define BIT_BITMAP_VO BIT(7) 9051 #define BIT_BITMAP_VI BIT(6) 9052 #define BIT_BITMAP_BE BIT(5) 9053 #define BIT_BITMAP_BK BIT(4) 9054 9055 #define BIT_SHIFT_BITMAP_CONDITION 2 9056 #define BIT_MASK_BITMAP_CONDITION 0x3 9057 #define BIT_BITMAP_CONDITION(x) \ 9058 (((x) & BIT_MASK_BITMAP_CONDITION) << BIT_SHIFT_BITMAP_CONDITION) 9059 #define BIT_GET_BITMAP_CONDITION(x) \ 9060 (((x) >> BIT_SHIFT_BITMAP_CONDITION) & BIT_MASK_BITMAP_CONDITION) 9061 9062 #define BIT_BITMAP_SSNBK_COUNTER_CLR BIT(1) 9063 #define BIT_BITMAP_FORCE BIT(0) 9064 9065 /* 2 REG_RXERR_RPT (Offset 0x0664) */ 9066 9067 #define BIT_SHIFT_RXERR_RPT_SEL_V1_3_0 28 9068 #define BIT_MASK_RXERR_RPT_SEL_V1_3_0 0xf 9069 #define BIT_RXERR_RPT_SEL_V1_3_0(x) \ 9070 (((x) & BIT_MASK_RXERR_RPT_SEL_V1_3_0) \ 9071 << BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) 9072 #define BIT_GET_RXERR_RPT_SEL_V1_3_0(x) \ 9073 (((x) >> BIT_SHIFT_RXERR_RPT_SEL_V1_3_0) & \ 9074 BIT_MASK_RXERR_RPT_SEL_V1_3_0) 9075 9076 /* 2 REG_RXERR_RPT (Offset 0x0664) */ 9077 9078 #define BIT_RXERR_RPT_RST BIT(27) 9079 9080 /* 2 REG_RXERR_RPT (Offset 0x0664) */ 9081 9082 #define BIT_RXERR_RPT_SEL_V1_4 BIT(26) 9083 9084 /* 2 REG_RXERR_RPT (Offset 0x0664) */ 9085 9086 #define BIT_W1S BIT(23) 9087 9088 /* 2 REG_RXERR_RPT (Offset 0x0664) */ 9089 9090 #define BIT_UD_SELECT_BSSID BIT(22) 9091 9092 /* 2 REG_RXERR_RPT (Offset 0x0664) */ 9093 9094 #define BIT_SHIFT_UD_SUB_TYPE 18 9095 #define BIT_MASK_UD_SUB_TYPE 0xf 9096 #define BIT_UD_SUB_TYPE(x) \ 9097 (((x) & BIT_MASK_UD_SUB_TYPE) << BIT_SHIFT_UD_SUB_TYPE) 9098 #define BIT_GET_UD_SUB_TYPE(x) \ 9099 (((x) >> BIT_SHIFT_UD_SUB_TYPE) & BIT_MASK_UD_SUB_TYPE) 9100 9101 #define BIT_SHIFT_UD_TYPE 16 9102 #define BIT_MASK_UD_TYPE 0x3 9103 #define BIT_UD_TYPE(x) (((x) & BIT_MASK_UD_TYPE) << BIT_SHIFT_UD_TYPE) 9104 #define BIT_GET_UD_TYPE(x) (((x) >> BIT_SHIFT_UD_TYPE) & BIT_MASK_UD_TYPE) 9105 9106 #define BIT_SHIFT_RPT_COUNTER 0 9107 #define BIT_MASK_RPT_COUNTER 0xffff 9108 #define BIT_RPT_COUNTER(x) \ 9109 (((x) & BIT_MASK_RPT_COUNTER) << BIT_SHIFT_RPT_COUNTER) 9110 #define BIT_GET_RPT_COUNTER(x) \ 9111 (((x) >> BIT_SHIFT_RPT_COUNTER) & BIT_MASK_RPT_COUNTER) 9112 9113 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9114 9115 #define BIT_SHIFT_ACKBA_TYPSEL (60 & CPU_OPT_WIDTH) 9116 #define BIT_MASK_ACKBA_TYPSEL 0xf 9117 #define BIT_ACKBA_TYPSEL(x) \ 9118 (((x) & BIT_MASK_ACKBA_TYPSEL) << BIT_SHIFT_ACKBA_TYPSEL) 9119 #define BIT_GET_ACKBA_TYPSEL(x) \ 9120 (((x) >> BIT_SHIFT_ACKBA_TYPSEL) & BIT_MASK_ACKBA_TYPSEL) 9121 9122 #define BIT_SHIFT_ACKBA_ACKPCHK (56 & CPU_OPT_WIDTH) 9123 #define BIT_MASK_ACKBA_ACKPCHK 0xf 9124 #define BIT_ACKBA_ACKPCHK(x) \ 9125 (((x) & BIT_MASK_ACKBA_ACKPCHK) << BIT_SHIFT_ACKBA_ACKPCHK) 9126 #define BIT_GET_ACKBA_ACKPCHK(x) \ 9127 (((x) >> BIT_SHIFT_ACKBA_ACKPCHK) & BIT_MASK_ACKBA_ACKPCHK) 9128 9129 #define BIT_SHIFT_ACKBAR_TYPESEL (48 & CPU_OPT_WIDTH) 9130 #define BIT_MASK_ACKBAR_TYPESEL 0xff 9131 #define BIT_ACKBAR_TYPESEL(x) \ 9132 (((x) & BIT_MASK_ACKBAR_TYPESEL) << BIT_SHIFT_ACKBAR_TYPESEL) 9133 #define BIT_GET_ACKBAR_TYPESEL(x) \ 9134 (((x) >> BIT_SHIFT_ACKBAR_TYPESEL) & BIT_MASK_ACKBAR_TYPESEL) 9135 9136 #define BIT_SHIFT_ACKBAR_ACKPCHK (44 & CPU_OPT_WIDTH) 9137 #define BIT_MASK_ACKBAR_ACKPCHK 0xf 9138 #define BIT_ACKBAR_ACKPCHK(x) \ 9139 (((x) & BIT_MASK_ACKBAR_ACKPCHK) << BIT_SHIFT_ACKBAR_ACKPCHK) 9140 #define BIT_GET_ACKBAR_ACKPCHK(x) \ 9141 (((x) >> BIT_SHIFT_ACKBAR_ACKPCHK) & BIT_MASK_ACKBAR_ACKPCHK) 9142 9143 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9144 9145 #define BIT_RXBA_IGNOREA2 BIT(42) 9146 #define BIT_EN_SAVE_ALL_TXOPADDR BIT(41) 9147 #define BIT_EN_TXCTS_TO_TXOPOWNER_INRXNAV BIT(40) 9148 9149 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9150 9151 #define BIT_DIS_TXBA_AMPDUFCSERR BIT(39) 9152 #define BIT_DIS_TXBA_RXBARINFULL BIT(38) 9153 #define BIT_DIS_TXCFE_INFULL BIT(37) 9154 #define BIT_DIS_TXCTS_INFULL BIT(36) 9155 #define BIT_EN_TXACKBA_IN_TX_RDG BIT(35) 9156 #define BIT_EN_TXACKBA_IN_TXOP BIT(34) 9157 #define BIT_EN_TXCTS_IN_RXNAV BIT(33) 9158 #define BIT_EN_TXCTS_INTXOP BIT(32) 9159 #define BIT_BLK_EDCA_BBSLP BIT(31) 9160 #define BIT_BLK_EDCA_BBSBY BIT(30) 9161 #define BIT_ACKTO_BLOCK_SCH_EN BIT(27) 9162 #define BIT_EIFS_BLOCK_SCH_EN BIT(26) 9163 #define BIT_PLCPCHK_RST_EIFS BIT(25) 9164 #define BIT_CCA_RST_EIFS BIT(24) 9165 #define BIT_DIS_UPD_MYRXPKTNAV BIT(23) 9166 #define BIT_EARLY_TXBA BIT(22) 9167 9168 #define BIT_SHIFT_RESP_CHNBUSY 20 9169 #define BIT_MASK_RESP_CHNBUSY 0x3 9170 #define BIT_RESP_CHNBUSY(x) \ 9171 (((x) & BIT_MASK_RESP_CHNBUSY) << BIT_SHIFT_RESP_CHNBUSY) 9172 #define BIT_GET_RESP_CHNBUSY(x) \ 9173 (((x) >> BIT_SHIFT_RESP_CHNBUSY) & BIT_MASK_RESP_CHNBUSY) 9174 9175 #define BIT_RESP_DCTS_EN BIT(19) 9176 #define BIT_RESP_DCFE_EN BIT(18) 9177 #define BIT_RESP_SPLCPEN BIT(17) 9178 #define BIT_RESP_SGIEN BIT(16) 9179 9180 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9181 9182 #define BIT_RESP_LDPC_EN BIT(15) 9183 #define BIT_DIS_RESP_ACKINCCA BIT(14) 9184 #define BIT_DIS_RESP_CTSINCCA BIT(13) 9185 9186 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9187 9188 #define BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER 10 9189 #define BIT_MASK_R_WMAC_SECOND_CCA_TIMER 0x7 9190 #define BIT_R_WMAC_SECOND_CCA_TIMER(x) \ 9191 (((x) & BIT_MASK_R_WMAC_SECOND_CCA_TIMER) \ 9192 << BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) 9193 #define BIT_GET_R_WMAC_SECOND_CCA_TIMER(x) \ 9194 (((x) >> BIT_SHIFT_R_WMAC_SECOND_CCA_TIMER) & \ 9195 BIT_MASK_R_WMAC_SECOND_CCA_TIMER) 9196 9197 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9198 9199 #define BIT_SHIFT_RFMOD 7 9200 #define BIT_MASK_RFMOD 0x3 9201 #define BIT_RFMOD(x) (((x) & BIT_MASK_RFMOD) << BIT_SHIFT_RFMOD) 9202 #define BIT_GET_RFMOD(x) (((x) >> BIT_SHIFT_RFMOD) & BIT_MASK_RFMOD) 9203 9204 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9205 9206 #define BIT_SHIFT_RESP_CTS_DYNBW_SEL 5 9207 #define BIT_MASK_RESP_CTS_DYNBW_SEL 0x3 9208 #define BIT_RESP_CTS_DYNBW_SEL(x) \ 9209 (((x) & BIT_MASK_RESP_CTS_DYNBW_SEL) << BIT_SHIFT_RESP_CTS_DYNBW_SEL) 9210 #define BIT_GET_RESP_CTS_DYNBW_SEL(x) \ 9211 (((x) >> BIT_SHIFT_RESP_CTS_DYNBW_SEL) & BIT_MASK_RESP_CTS_DYNBW_SEL) 9212 9213 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9214 9215 #define BIT_DLY_TX_WAIT_RXANTSEL BIT(4) 9216 9217 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9218 9219 #define BIT_TXRESP_BY_RXANTSEL BIT(3) 9220 9221 /* 2 REG_WMAC_TRXPTCL_CTL (Offset 0x0668) */ 9222 9223 #define BIT_SHIFT_ORIG_DCTS_CHK 0 9224 #define BIT_MASK_ORIG_DCTS_CHK 0x3 9225 #define BIT_ORIG_DCTS_CHK(x) \ 9226 (((x) & BIT_MASK_ORIG_DCTS_CHK) << BIT_SHIFT_ORIG_DCTS_CHK) 9227 #define BIT_GET_ORIG_DCTS_CHK(x) \ 9228 (((x) >> BIT_SHIFT_ORIG_DCTS_CHK) & BIT_MASK_ORIG_DCTS_CHK) 9229 9230 /* 2 REG_CAMCMD (Offset 0x0670) */ 9231 9232 #define BIT_SECCAM_POLLING BIT(31) 9233 #define BIT_SECCAM_CLR BIT(30) 9234 #define BIT_MFBCAM_CLR BIT(29) 9235 9236 /* 2 REG_CAMCMD (Offset 0x0670) */ 9237 9238 #define BIT_SECCAM_WE BIT(16) 9239 9240 /* 2 REG_CAMCMD (Offset 0x0670) */ 9241 9242 #define BIT_SHIFT_SECCAM_ADDR_V2 0 9243 #define BIT_MASK_SECCAM_ADDR_V2 0x3ff 9244 #define BIT_SECCAM_ADDR_V2(x) \ 9245 (((x) & BIT_MASK_SECCAM_ADDR_V2) << BIT_SHIFT_SECCAM_ADDR_V2) 9246 #define BIT_GET_SECCAM_ADDR_V2(x) \ 9247 (((x) >> BIT_SHIFT_SECCAM_ADDR_V2) & BIT_MASK_SECCAM_ADDR_V2) 9248 9249 /* 2 REG_CAMWRITE (Offset 0x0674) */ 9250 9251 #define BIT_SHIFT_CAMW_DATA 0 9252 #define BIT_MASK_CAMW_DATA 0xffffffffL 9253 #define BIT_CAMW_DATA(x) (((x) & BIT_MASK_CAMW_DATA) << BIT_SHIFT_CAMW_DATA) 9254 #define BIT_GET_CAMW_DATA(x) (((x) >> BIT_SHIFT_CAMW_DATA) & BIT_MASK_CAMW_DATA) 9255 9256 /* 2 REG_CAMREAD (Offset 0x0678) */ 9257 9258 #define BIT_SHIFT_CAMR_DATA 0 9259 #define BIT_MASK_CAMR_DATA 0xffffffffL 9260 #define BIT_CAMR_DATA(x) (((x) & BIT_MASK_CAMR_DATA) << BIT_SHIFT_CAMR_DATA) 9261 #define BIT_GET_CAMR_DATA(x) (((x) >> BIT_SHIFT_CAMR_DATA) & BIT_MASK_CAMR_DATA) 9262 9263 /* 2 REG_CAMDBG (Offset 0x067C) */ 9264 9265 #define BIT_SECCAM_INFO BIT(31) 9266 #define BIT_SEC_KEYFOUND BIT(15) 9267 9268 #define BIT_SHIFT_CAMDBG_SEC_TYPE 12 9269 #define BIT_MASK_CAMDBG_SEC_TYPE 0x7 9270 #define BIT_CAMDBG_SEC_TYPE(x) \ 9271 (((x) & BIT_MASK_CAMDBG_SEC_TYPE) << BIT_SHIFT_CAMDBG_SEC_TYPE) 9272 #define BIT_GET_CAMDBG_SEC_TYPE(x) \ 9273 (((x) >> BIT_SHIFT_CAMDBG_SEC_TYPE) & BIT_MASK_CAMDBG_SEC_TYPE) 9274 9275 /* 2 REG_CAMDBG (Offset 0x067C) */ 9276 9277 #define BIT_CAMDBG_EXT_SECTYPE BIT(11) 9278 9279 /* 2 REG_CAMDBG (Offset 0x067C) */ 9280 9281 #define BIT_SHIFT_CAMDBG_MIC_KEY_IDX 5 9282 #define BIT_MASK_CAMDBG_MIC_KEY_IDX 0x1f 9283 #define BIT_CAMDBG_MIC_KEY_IDX(x) \ 9284 (((x) & BIT_MASK_CAMDBG_MIC_KEY_IDX) << BIT_SHIFT_CAMDBG_MIC_KEY_IDX) 9285 #define BIT_GET_CAMDBG_MIC_KEY_IDX(x) \ 9286 (((x) >> BIT_SHIFT_CAMDBG_MIC_KEY_IDX) & BIT_MASK_CAMDBG_MIC_KEY_IDX) 9287 9288 #define BIT_SHIFT_CAMDBG_SEC_KEY_IDX 0 9289 #define BIT_MASK_CAMDBG_SEC_KEY_IDX 0x1f 9290 #define BIT_CAMDBG_SEC_KEY_IDX(x) \ 9291 (((x) & BIT_MASK_CAMDBG_SEC_KEY_IDX) << BIT_SHIFT_CAMDBG_SEC_KEY_IDX) 9292 #define BIT_GET_CAMDBG_SEC_KEY_IDX(x) \ 9293 (((x) >> BIT_SHIFT_CAMDBG_SEC_KEY_IDX) & BIT_MASK_CAMDBG_SEC_KEY_IDX) 9294 9295 /* 2 REG_SECCFG (Offset 0x0680) */ 9296 9297 #define BIT_DIS_GCLK_WAPI BIT(15) 9298 #define BIT_DIS_GCLK_AES BIT(14) 9299 #define BIT_DIS_GCLK_TKIP BIT(13) 9300 9301 /* 2 REG_SECCFG (Offset 0x0680) */ 9302 9303 #define BIT_AES_SEL_QC_1 BIT(12) 9304 #define BIT_AES_SEL_QC_0 BIT(11) 9305 9306 /* 2 REG_SECCFG (Offset 0x0680) */ 9307 9308 #define BIT_CHK_BMC BIT(9) 9309 9310 /* 2 REG_SECCFG (Offset 0x0680) */ 9311 9312 #define BIT_CHK_KEYID BIT(8) 9313 #define BIT_RXBCUSEDK BIT(7) 9314 #define BIT_TXBCUSEDK BIT(6) 9315 #define BIT_NOSKMC BIT(5) 9316 #define BIT_SKBYA2 BIT(4) 9317 #define BIT_RXDEC BIT(3) 9318 #define BIT_TXENC BIT(2) 9319 #define BIT_RXUHUSEDK BIT(1) 9320 #define BIT_TXUHUSEDK BIT(0) 9321 9322 /* 2 REG_RXFILTER_CATEGORY_1 (Offset 0x0682) */ 9323 9324 #define BIT_SHIFT_RXFILTER_CATEGORY_1 0 9325 #define BIT_MASK_RXFILTER_CATEGORY_1 0xff 9326 #define BIT_RXFILTER_CATEGORY_1(x) \ 9327 (((x) & BIT_MASK_RXFILTER_CATEGORY_1) << BIT_SHIFT_RXFILTER_CATEGORY_1) 9328 #define BIT_GET_RXFILTER_CATEGORY_1(x) \ 9329 (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_1) & BIT_MASK_RXFILTER_CATEGORY_1) 9330 9331 /* 2 REG_RXFILTER_ACTION_1 (Offset 0x0683) */ 9332 9333 #define BIT_SHIFT_RXFILTER_ACTION_1 0 9334 #define BIT_MASK_RXFILTER_ACTION_1 0xff 9335 #define BIT_RXFILTER_ACTION_1(x) \ 9336 (((x) & BIT_MASK_RXFILTER_ACTION_1) << BIT_SHIFT_RXFILTER_ACTION_1) 9337 #define BIT_GET_RXFILTER_ACTION_1(x) \ 9338 (((x) >> BIT_SHIFT_RXFILTER_ACTION_1) & BIT_MASK_RXFILTER_ACTION_1) 9339 9340 /* 2 REG_RXFILTER_CATEGORY_2 (Offset 0x0684) */ 9341 9342 #define BIT_SHIFT_RXFILTER_CATEGORY_2 0 9343 #define BIT_MASK_RXFILTER_CATEGORY_2 0xff 9344 #define BIT_RXFILTER_CATEGORY_2(x) \ 9345 (((x) & BIT_MASK_RXFILTER_CATEGORY_2) << BIT_SHIFT_RXFILTER_CATEGORY_2) 9346 #define BIT_GET_RXFILTER_CATEGORY_2(x) \ 9347 (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_2) & BIT_MASK_RXFILTER_CATEGORY_2) 9348 9349 /* 2 REG_RXFILTER_ACTION_2 (Offset 0x0685) */ 9350 9351 #define BIT_SHIFT_RXFILTER_ACTION_2 0 9352 #define BIT_MASK_RXFILTER_ACTION_2 0xff 9353 #define BIT_RXFILTER_ACTION_2(x) \ 9354 (((x) & BIT_MASK_RXFILTER_ACTION_2) << BIT_SHIFT_RXFILTER_ACTION_2) 9355 #define BIT_GET_RXFILTER_ACTION_2(x) \ 9356 (((x) >> BIT_SHIFT_RXFILTER_ACTION_2) & BIT_MASK_RXFILTER_ACTION_2) 9357 9358 /* 2 REG_RXFILTER_CATEGORY_3 (Offset 0x0686) */ 9359 9360 #define BIT_SHIFT_RXFILTER_CATEGORY_3 0 9361 #define BIT_MASK_RXFILTER_CATEGORY_3 0xff 9362 #define BIT_RXFILTER_CATEGORY_3(x) \ 9363 (((x) & BIT_MASK_RXFILTER_CATEGORY_3) << BIT_SHIFT_RXFILTER_CATEGORY_3) 9364 #define BIT_GET_RXFILTER_CATEGORY_3(x) \ 9365 (((x) >> BIT_SHIFT_RXFILTER_CATEGORY_3) & BIT_MASK_RXFILTER_CATEGORY_3) 9366 9367 /* 2 REG_RXFILTER_ACTION_3 (Offset 0x0687) */ 9368 9369 #define BIT_SHIFT_RXFILTER_ACTION_3 0 9370 #define BIT_MASK_RXFILTER_ACTION_3 0xff 9371 #define BIT_RXFILTER_ACTION_3(x) \ 9372 (((x) & BIT_MASK_RXFILTER_ACTION_3) << BIT_SHIFT_RXFILTER_ACTION_3) 9373 #define BIT_GET_RXFILTER_ACTION_3(x) \ 9374 (((x) >> BIT_SHIFT_RXFILTER_ACTION_3) & BIT_MASK_RXFILTER_ACTION_3) 9375 9376 /* 2 REG_RXFLTMAP3 (Offset 0x0688) */ 9377 9378 #define BIT_MGTFLT15EN_FW BIT(15) 9379 #define BIT_MGTFLT14EN_FW BIT(14) 9380 #define BIT_MGTFLT13EN_FW BIT(13) 9381 #define BIT_MGTFLT12EN_FW BIT(12) 9382 #define BIT_MGTFLT11EN_FW BIT(11) 9383 #define BIT_MGTFLT10EN_FW BIT(10) 9384 #define BIT_MGTFLT9EN_FW BIT(9) 9385 #define BIT_MGTFLT8EN_FW BIT(8) 9386 #define BIT_MGTFLT7EN_FW BIT(7) 9387 #define BIT_MGTFLT6EN_FW BIT(6) 9388 #define BIT_MGTFLT5EN_FW BIT(5) 9389 #define BIT_MGTFLT4EN_FW BIT(4) 9390 #define BIT_MGTFLT3EN_FW BIT(3) 9391 #define BIT_MGTFLT2EN_FW BIT(2) 9392 #define BIT_MGTFLT1EN_FW BIT(1) 9393 #define BIT_MGTFLT0EN_FW BIT(0) 9394 9395 /* 2 REG_RXFLTMAP4 (Offset 0x068A) */ 9396 9397 #define BIT_CTRLFLT15EN_FW BIT(15) 9398 #define BIT_CTRLFLT14EN_FW BIT(14) 9399 #define BIT_CTRLFLT13EN_FW BIT(13) 9400 #define BIT_CTRLFLT12EN_FW BIT(12) 9401 #define BIT_CTRLFLT11EN_FW BIT(11) 9402 #define BIT_CTRLFLT10EN_FW BIT(10) 9403 #define BIT_CTRLFLT9EN_FW BIT(9) 9404 #define BIT_CTRLFLT8EN_FW BIT(8) 9405 #define BIT_CTRLFLT7EN_FW BIT(7) 9406 #define BIT_CTRLFLT6EN_FW BIT(6) 9407 #define BIT_CTRLFLT5EN_FW BIT(5) 9408 #define BIT_CTRLFLT4EN_FW BIT(4) 9409 #define BIT_CTRLFLT3EN_FW BIT(3) 9410 #define BIT_CTRLFLT2EN_FW BIT(2) 9411 #define BIT_CTRLFLT1EN_FW BIT(1) 9412 #define BIT_CTRLFLT0EN_FW BIT(0) 9413 9414 /* 2 REG_RXFLTMAP5 (Offset 0x068C) */ 9415 9416 #define BIT_DATAFLT15EN_FW BIT(15) 9417 #define BIT_DATAFLT14EN_FW BIT(14) 9418 #define BIT_DATAFLT13EN_FW BIT(13) 9419 #define BIT_DATAFLT12EN_FW BIT(12) 9420 #define BIT_DATAFLT11EN_FW BIT(11) 9421 #define BIT_DATAFLT10EN_FW BIT(10) 9422 #define BIT_DATAFLT9EN_FW BIT(9) 9423 #define BIT_DATAFLT8EN_FW BIT(8) 9424 #define BIT_DATAFLT7EN_FW BIT(7) 9425 #define BIT_DATAFLT6EN_FW BIT(6) 9426 #define BIT_DATAFLT5EN_FW BIT(5) 9427 #define BIT_DATAFLT4EN_FW BIT(4) 9428 #define BIT_DATAFLT3EN_FW BIT(3) 9429 #define BIT_DATAFLT2EN_FW BIT(2) 9430 #define BIT_DATAFLT1EN_FW BIT(1) 9431 #define BIT_DATAFLT0EN_FW BIT(0) 9432 9433 /* 2 REG_RXFLTMAP6 (Offset 0x068E) */ 9434 9435 #define BIT_ACTIONFLT15EN_FW BIT(15) 9436 #define BIT_ACTIONFLT14EN_FW BIT(14) 9437 #define BIT_ACTIONFLT13EN_FW BIT(13) 9438 #define BIT_ACTIONFLT12EN_FW BIT(12) 9439 #define BIT_ACTIONFLT11EN_FW BIT(11) 9440 #define BIT_ACTIONFLT10EN_FW BIT(10) 9441 #define BIT_ACTIONFLT9EN_FW BIT(9) 9442 #define BIT_ACTIONFLT8EN_FW BIT(8) 9443 #define BIT_ACTIONFLT7EN_FW BIT(7) 9444 #define BIT_ACTIONFLT6EN_FW BIT(6) 9445 #define BIT_ACTIONFLT5EN_FW BIT(5) 9446 #define BIT_ACTIONFLT4EN_FW BIT(4) 9447 #define BIT_ACTIONFLT3EN_FW BIT(3) 9448 #define BIT_ACTIONFLT2EN_FW BIT(2) 9449 #define BIT_ACTIONFLT1EN_FW BIT(1) 9450 #define BIT_ACTIONFLT0EN_FW BIT(0) 9451 9452 /* 2 REG_WOW_CTRL (Offset 0x0690) */ 9453 9454 #define BIT_SHIFT_PSF_BSSIDSEL_B2B1 6 9455 #define BIT_MASK_PSF_BSSIDSEL_B2B1 0x3 9456 #define BIT_PSF_BSSIDSEL_B2B1(x) \ 9457 (((x) & BIT_MASK_PSF_BSSIDSEL_B2B1) << BIT_SHIFT_PSF_BSSIDSEL_B2B1) 9458 #define BIT_GET_PSF_BSSIDSEL_B2B1(x) \ 9459 (((x) >> BIT_SHIFT_PSF_BSSIDSEL_B2B1) & BIT_MASK_PSF_BSSIDSEL_B2B1) 9460 9461 /* 2 REG_WOW_CTRL (Offset 0x0690) */ 9462 9463 #define BIT_WOWHCI BIT(5) 9464 9465 /* 2 REG_WOW_CTRL (Offset 0x0690) */ 9466 9467 #define BIT_PSF_BSSIDSEL_B0 BIT(4) 9468 9469 /* 2 REG_WOW_CTRL (Offset 0x0690) */ 9470 9471 #define BIT_UWF BIT(3) 9472 #define BIT_MAGIC BIT(2) 9473 #define BIT_WOWEN BIT(1) 9474 #define BIT_FORCE_WAKEUP BIT(0) 9475 9476 /* 2 REG_NAN_RX_TSF_FILTER (Offset 0x0691) */ 9477 9478 #define BIT_CHK_TSF_TA BIT(2) 9479 #define BIT_CHK_TSF_CBSSID BIT(1) 9480 #define BIT_CHK_TSF_EN BIT(0) 9481 9482 /* 2 REG_PS_RX_INFO (Offset 0x0692) */ 9483 9484 #define BIT_SHIFT_PORTSEL__PS_RX_INFO 5 9485 #define BIT_MASK_PORTSEL__PS_RX_INFO 0x7 9486 #define BIT_PORTSEL__PS_RX_INFO(x) \ 9487 (((x) & BIT_MASK_PORTSEL__PS_RX_INFO) << BIT_SHIFT_PORTSEL__PS_RX_INFO) 9488 #define BIT_GET_PORTSEL__PS_RX_INFO(x) \ 9489 (((x) >> BIT_SHIFT_PORTSEL__PS_RX_INFO) & BIT_MASK_PORTSEL__PS_RX_INFO) 9490 9491 /* 2 REG_PS_RX_INFO (Offset 0x0692) */ 9492 9493 #define BIT_RXCTRLIN0 BIT(4) 9494 #define BIT_RXMGTIN0 BIT(3) 9495 #define BIT_RXDATAIN2 BIT(2) 9496 #define BIT_RXDATAIN1 BIT(1) 9497 #define BIT_RXDATAIN0 BIT(0) 9498 9499 /* 2 REG_WMMPS_UAPSD_TID (Offset 0x0693) */ 9500 9501 #define BIT_WMMPS_UAPSD_TID7 BIT(7) 9502 #define BIT_WMMPS_UAPSD_TID6 BIT(6) 9503 #define BIT_WMMPS_UAPSD_TID5 BIT(5) 9504 #define BIT_WMMPS_UAPSD_TID4 BIT(4) 9505 #define BIT_WMMPS_UAPSD_TID3 BIT(3) 9506 #define BIT_WMMPS_UAPSD_TID2 BIT(2) 9507 #define BIT_WMMPS_UAPSD_TID1 BIT(1) 9508 #define BIT_WMMPS_UAPSD_TID0 BIT(0) 9509 9510 /* 2 REG_LPNAV_CTRL (Offset 0x0694) */ 9511 9512 #define BIT_LPNAV_EN BIT(31) 9513 9514 #define BIT_SHIFT_LPNAV_EARLY 16 9515 #define BIT_MASK_LPNAV_EARLY 0x7fff 9516 #define BIT_LPNAV_EARLY(x) \ 9517 (((x) & BIT_MASK_LPNAV_EARLY) << BIT_SHIFT_LPNAV_EARLY) 9518 #define BIT_GET_LPNAV_EARLY(x) \ 9519 (((x) >> BIT_SHIFT_LPNAV_EARLY) & BIT_MASK_LPNAV_EARLY) 9520 9521 #define BIT_SHIFT_LPNAV_TH 0 9522 #define BIT_MASK_LPNAV_TH 0xffff 9523 #define BIT_LPNAV_TH(x) (((x) & BIT_MASK_LPNAV_TH) << BIT_SHIFT_LPNAV_TH) 9524 #define BIT_GET_LPNAV_TH(x) (((x) >> BIT_SHIFT_LPNAV_TH) & BIT_MASK_LPNAV_TH) 9525 9526 /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ 9527 9528 #define BIT_WKFCAM_POLLING_V1 BIT(31) 9529 #define BIT_WKFCAM_CLR_V1 BIT(30) 9530 9531 /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ 9532 9533 #define BIT_WKFCAM_WE BIT(16) 9534 9535 /* 2 REG_WKFMCAM_CMD (Offset 0x0698) */ 9536 9537 #define BIT_SHIFT_WKFCAM_ADDR_V2 8 9538 #define BIT_MASK_WKFCAM_ADDR_V2 0xff 9539 #define BIT_WKFCAM_ADDR_V2(x) \ 9540 (((x) & BIT_MASK_WKFCAM_ADDR_V2) << BIT_SHIFT_WKFCAM_ADDR_V2) 9541 #define BIT_GET_WKFCAM_ADDR_V2(x) \ 9542 (((x) >> BIT_SHIFT_WKFCAM_ADDR_V2) & BIT_MASK_WKFCAM_ADDR_V2) 9543 9544 #define BIT_SHIFT_WKFCAM_CAM_NUM_V1 0 9545 #define BIT_MASK_WKFCAM_CAM_NUM_V1 0xff 9546 #define BIT_WKFCAM_CAM_NUM_V1(x) \ 9547 (((x) & BIT_MASK_WKFCAM_CAM_NUM_V1) << BIT_SHIFT_WKFCAM_CAM_NUM_V1) 9548 #define BIT_GET_WKFCAM_CAM_NUM_V1(x) \ 9549 (((x) >> BIT_SHIFT_WKFCAM_CAM_NUM_V1) & BIT_MASK_WKFCAM_CAM_NUM_V1) 9550 9551 /* 2 REG_WKFMCAM_RWD (Offset 0x069C) */ 9552 9553 #define BIT_SHIFT_WKFMCAM_RWD 0 9554 #define BIT_MASK_WKFMCAM_RWD 0xffffffffL 9555 #define BIT_WKFMCAM_RWD(x) \ 9556 (((x) & BIT_MASK_WKFMCAM_RWD) << BIT_SHIFT_WKFMCAM_RWD) 9557 #define BIT_GET_WKFMCAM_RWD(x) \ 9558 (((x) >> BIT_SHIFT_WKFMCAM_RWD) & BIT_MASK_WKFMCAM_RWD) 9559 9560 /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9561 9562 #define BIT_MGTFLT15EN BIT(15) 9563 #define BIT_MGTFLT14EN BIT(14) 9564 9565 /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9566 9567 #define BIT_MGTFLT13EN BIT(13) 9568 #define BIT_MGTFLT12EN BIT(12) 9569 #define BIT_MGTFLT11EN BIT(11) 9570 #define BIT_MGTFLT10EN BIT(10) 9571 #define BIT_MGTFLT9EN BIT(9) 9572 #define BIT_MGTFLT8EN BIT(8) 9573 9574 /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9575 9576 #define BIT_MGTFLT7EN BIT(7) 9577 #define BIT_MGTFLT6EN BIT(6) 9578 9579 /* 2 REG_RXFLTMAP0 (Offset 0x06A0) */ 9580 9581 #define BIT_MGTFLT5EN BIT(5) 9582 #define BIT_MGTFLT4EN BIT(4) 9583 #define BIT_MGTFLT3EN BIT(3) 9584 #define BIT_MGTFLT2EN BIT(2) 9585 #define BIT_MGTFLT1EN BIT(1) 9586 #define BIT_MGTFLT0EN BIT(0) 9587 9588 /* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ 9589 9590 #define BIT_CTRLFLT15EN BIT(15) 9591 #define BIT_CTRLFLT14EN BIT(14) 9592 #define BIT_CTRLFLT13EN BIT(13) 9593 #define BIT_CTRLFLT12EN BIT(12) 9594 #define BIT_CTRLFLT11EN BIT(11) 9595 #define BIT_CTRLFLT10EN BIT(10) 9596 #define BIT_CTRLFLT9EN BIT(9) 9597 #define BIT_CTRLFLT8EN BIT(8) 9598 #define BIT_CTRLFLT7EN BIT(7) 9599 #define BIT_CTRLFLT6EN BIT(6) 9600 9601 /* 2 REG_RXFLTMAP1 (Offset 0x06A2) */ 9602 9603 #define BIT_CTRLFLT5EN BIT(5) 9604 #define BIT_CTRLFLT4EN BIT(4) 9605 #define BIT_CTRLFLT3EN BIT(3) 9606 #define BIT_CTRLFLT2EN BIT(2) 9607 #define BIT_CTRLFLT1EN BIT(1) 9608 #define BIT_CTRLFLT0EN BIT(0) 9609 9610 /* 2 REG_RXFLTMAP (Offset 0x06A4) */ 9611 9612 #define BIT_DATAFLT15EN BIT(15) 9613 #define BIT_DATAFLT14EN BIT(14) 9614 #define BIT_DATAFLT13EN BIT(13) 9615 #define BIT_DATAFLT12EN BIT(12) 9616 #define BIT_DATAFLT11EN BIT(11) 9617 #define BIT_DATAFLT10EN BIT(10) 9618 #define BIT_DATAFLT9EN BIT(9) 9619 #define BIT_DATAFLT8EN BIT(8) 9620 #define BIT_DATAFLT7EN BIT(7) 9621 #define BIT_DATAFLT6EN BIT(6) 9622 #define BIT_DATAFLT5EN BIT(5) 9623 #define BIT_DATAFLT4EN BIT(4) 9624 #define BIT_DATAFLT3EN BIT(3) 9625 #define BIT_DATAFLT2EN BIT(2) 9626 #define BIT_DATAFLT1EN BIT(1) 9627 #define BIT_DATAFLT0EN BIT(0) 9628 9629 /* 2 REG_BCN_PSR_RPT (Offset 0x06A8) */ 9630 9631 #define BIT_SHIFT_DTIM_CNT 24 9632 #define BIT_MASK_DTIM_CNT 0xff 9633 #define BIT_DTIM_CNT(x) (((x) & BIT_MASK_DTIM_CNT) << BIT_SHIFT_DTIM_CNT) 9634 #define BIT_GET_DTIM_CNT(x) (((x) >> BIT_SHIFT_DTIM_CNT) & BIT_MASK_DTIM_CNT) 9635 9636 #define BIT_SHIFT_DTIM_PERIOD 16 9637 #define BIT_MASK_DTIM_PERIOD 0xff 9638 #define BIT_DTIM_PERIOD(x) \ 9639 (((x) & BIT_MASK_DTIM_PERIOD) << BIT_SHIFT_DTIM_PERIOD) 9640 #define BIT_GET_DTIM_PERIOD(x) \ 9641 (((x) >> BIT_SHIFT_DTIM_PERIOD) & BIT_MASK_DTIM_PERIOD) 9642 9643 #define BIT_DTIM BIT(15) 9644 #define BIT_TIM BIT(14) 9645 9646 #define BIT_SHIFT_PS_AID_0 0 9647 #define BIT_MASK_PS_AID_0 0x7ff 9648 #define BIT_PS_AID_0(x) (((x) & BIT_MASK_PS_AID_0) << BIT_SHIFT_PS_AID_0) 9649 #define BIT_GET_PS_AID_0(x) (((x) >> BIT_SHIFT_PS_AID_0) & BIT_MASK_PS_AID_0) 9650 9651 /* 2 REG_FLC_RPC (Offset 0x06AC) */ 9652 9653 #define BIT_SHIFT_FLC_RPC 0 9654 #define BIT_MASK_FLC_RPC 0xff 9655 #define BIT_FLC_RPC(x) (((x) & BIT_MASK_FLC_RPC) << BIT_SHIFT_FLC_RPC) 9656 #define BIT_GET_FLC_RPC(x) (((x) >> BIT_SHIFT_FLC_RPC) & BIT_MASK_FLC_RPC) 9657 9658 /* 2 REG_FLC_RPCT (Offset 0x06AD) */ 9659 9660 #define BIT_SHIFT_FLC_RPCT 0 9661 #define BIT_MASK_FLC_RPCT 0xff 9662 #define BIT_FLC_RPCT(x) (((x) & BIT_MASK_FLC_RPCT) << BIT_SHIFT_FLC_RPCT) 9663 #define BIT_GET_FLC_RPCT(x) (((x) >> BIT_SHIFT_FLC_RPCT) & BIT_MASK_FLC_RPCT) 9664 9665 /* 2 REG_FLC_PTS (Offset 0x06AE) */ 9666 9667 #define BIT_CMF BIT(2) 9668 #define BIT_CCF BIT(1) 9669 #define BIT_CDF BIT(0) 9670 9671 /* 2 REG_FLC_TRPC (Offset 0x06AF) */ 9672 9673 #define BIT_FLC_RPCT_V1 BIT(7) 9674 #define BIT_MODE BIT(6) 9675 9676 #define BIT_SHIFT_TRPCD 0 9677 #define BIT_MASK_TRPCD 0x3f 9678 #define BIT_TRPCD(x) (((x) & BIT_MASK_TRPCD) << BIT_SHIFT_TRPCD) 9679 #define BIT_GET_TRPCD(x) (((x) >> BIT_SHIFT_TRPCD) & BIT_MASK_TRPCD) 9680 9681 /* 2 REG_RXPKTMON_CTRL (Offset 0x06B0) */ 9682 9683 #define BIT_SHIFT_RXBKQPKT_SEQ 20 9684 #define BIT_MASK_RXBKQPKT_SEQ 0xf 9685 #define BIT_RXBKQPKT_SEQ(x) \ 9686 (((x) & BIT_MASK_RXBKQPKT_SEQ) << BIT_SHIFT_RXBKQPKT_SEQ) 9687 #define BIT_GET_RXBKQPKT_SEQ(x) \ 9688 (((x) >> BIT_SHIFT_RXBKQPKT_SEQ) & BIT_MASK_RXBKQPKT_SEQ) 9689 9690 #define BIT_SHIFT_RXBEQPKT_SEQ 16 9691 #define BIT_MASK_RXBEQPKT_SEQ 0xf 9692 #define BIT_RXBEQPKT_SEQ(x) \ 9693 (((x) & BIT_MASK_RXBEQPKT_SEQ) << BIT_SHIFT_RXBEQPKT_SEQ) 9694 #define BIT_GET_RXBEQPKT_SEQ(x) \ 9695 (((x) >> BIT_SHIFT_RXBEQPKT_SEQ) & BIT_MASK_RXBEQPKT_SEQ) 9696 9697 #define BIT_SHIFT_RXVIQPKT_SEQ 12 9698 #define BIT_MASK_RXVIQPKT_SEQ 0xf 9699 #define BIT_RXVIQPKT_SEQ(x) \ 9700 (((x) & BIT_MASK_RXVIQPKT_SEQ) << BIT_SHIFT_RXVIQPKT_SEQ) 9701 #define BIT_GET_RXVIQPKT_SEQ(x) \ 9702 (((x) >> BIT_SHIFT_RXVIQPKT_SEQ) & BIT_MASK_RXVIQPKT_SEQ) 9703 9704 #define BIT_SHIFT_RXVOQPKT_SEQ 8 9705 #define BIT_MASK_RXVOQPKT_SEQ 0xf 9706 #define BIT_RXVOQPKT_SEQ(x) \ 9707 (((x) & BIT_MASK_RXVOQPKT_SEQ) << BIT_SHIFT_RXVOQPKT_SEQ) 9708 #define BIT_GET_RXVOQPKT_SEQ(x) \ 9709 (((x) >> BIT_SHIFT_RXVOQPKT_SEQ) & BIT_MASK_RXVOQPKT_SEQ) 9710 9711 #define BIT_RXBKQPKT_ERR BIT(7) 9712 #define BIT_RXBEQPKT_ERR BIT(6) 9713 #define BIT_RXVIQPKT_ERR BIT(5) 9714 #define BIT_RXVOQPKT_ERR BIT(4) 9715 #define BIT_RXDMA_MON_EN BIT(2) 9716 #define BIT_RXPKT_MON_RST BIT(1) 9717 #define BIT_RXPKT_MON_EN BIT(0) 9718 9719 /* 2 REG_STATE_MON (Offset 0x06B4) */ 9720 9721 #define BIT_SHIFT_STATE_SEL 24 9722 #define BIT_MASK_STATE_SEL 0x1f 9723 #define BIT_STATE_SEL(x) (((x) & BIT_MASK_STATE_SEL) << BIT_SHIFT_STATE_SEL) 9724 #define BIT_GET_STATE_SEL(x) (((x) >> BIT_SHIFT_STATE_SEL) & BIT_MASK_STATE_SEL) 9725 9726 #define BIT_SHIFT_STATE_INFO 8 9727 #define BIT_MASK_STATE_INFO 0xff 9728 #define BIT_STATE_INFO(x) (((x) & BIT_MASK_STATE_INFO) << BIT_SHIFT_STATE_INFO) 9729 #define BIT_GET_STATE_INFO(x) \ 9730 (((x) >> BIT_SHIFT_STATE_INFO) & BIT_MASK_STATE_INFO) 9731 9732 #define BIT_UPD_NXT_STATE BIT(7) 9733 9734 /* 2 REG_STATE_MON (Offset 0x06B4) */ 9735 9736 #define BIT_SHIFT_CUR_STATE 0 9737 #define BIT_MASK_CUR_STATE 0x7f 9738 #define BIT_CUR_STATE(x) (((x) & BIT_MASK_CUR_STATE) << BIT_SHIFT_CUR_STATE) 9739 #define BIT_GET_CUR_STATE(x) (((x) >> BIT_SHIFT_CUR_STATE) & BIT_MASK_CUR_STATE) 9740 9741 /* 2 REG_ERROR_MON (Offset 0x06B8) */ 9742 9743 #define BIT_MACRX_ERR_1 BIT(17) 9744 #define BIT_MACRX_ERR_0 BIT(16) 9745 #define BIT_MACTX_ERR_3 BIT(3) 9746 #define BIT_MACTX_ERR_2 BIT(2) 9747 #define BIT_MACTX_ERR_1 BIT(1) 9748 #define BIT_MACTX_ERR_0 BIT(0) 9749 9750 /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ 9751 9752 #define BIT_EN_TXRPTBUF_CLK BIT(31) 9753 9754 #define BIT_SHIFT_INFO_INDEX_OFFSET 16 9755 #define BIT_MASK_INFO_INDEX_OFFSET 0x1fff 9756 #define BIT_INFO_INDEX_OFFSET(x) \ 9757 (((x) & BIT_MASK_INFO_INDEX_OFFSET) << BIT_SHIFT_INFO_INDEX_OFFSET) 9758 #define BIT_GET_INFO_INDEX_OFFSET(x) \ 9759 (((x) >> BIT_SHIFT_INFO_INDEX_OFFSET) & BIT_MASK_INFO_INDEX_OFFSET) 9760 9761 /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ 9762 9763 #define BIT_WMAC_SRCH_FIFOFULL BIT(15) 9764 9765 /* 2 REG_SEARCH_MACID (Offset 0x06BC) */ 9766 9767 #define BIT_DIS_INFOSRCH BIT(14) 9768 #define BIT_DISABLE_B0 BIT(13) 9769 9770 #define BIT_SHIFT_INFO_ADDR_OFFSET 0 9771 #define BIT_MASK_INFO_ADDR_OFFSET 0x1fff 9772 #define BIT_INFO_ADDR_OFFSET(x) \ 9773 (((x) & BIT_MASK_INFO_ADDR_OFFSET) << BIT_SHIFT_INFO_ADDR_OFFSET) 9774 #define BIT_GET_INFO_ADDR_OFFSET(x) \ 9775 (((x) >> BIT_SHIFT_INFO_ADDR_OFFSET) & BIT_MASK_INFO_ADDR_OFFSET) 9776 9777 /* 2 REG_BT_COEX_TABLE (Offset 0x06C0) */ 9778 9779 #define BIT_PRI_MASK_RX_RESP BIT(126) 9780 #define BIT_PRI_MASK_RXOFDM BIT(125) 9781 #define BIT_PRI_MASK_RXCCK BIT(124) 9782 9783 #define BIT_SHIFT_PRI_MASK_TXAC (117 & CPU_OPT_WIDTH) 9784 #define BIT_MASK_PRI_MASK_TXAC 0x7f 9785 #define BIT_PRI_MASK_TXAC(x) \ 9786 (((x) & BIT_MASK_PRI_MASK_TXAC) << BIT_SHIFT_PRI_MASK_TXAC) 9787 #define BIT_GET_PRI_MASK_TXAC(x) \ 9788 (((x) >> BIT_SHIFT_PRI_MASK_TXAC) & BIT_MASK_PRI_MASK_TXAC) 9789 9790 #define BIT_SHIFT_PRI_MASK_NAV (109 & CPU_OPT_WIDTH) 9791 #define BIT_MASK_PRI_MASK_NAV 0xff 9792 #define BIT_PRI_MASK_NAV(x) \ 9793 (((x) & BIT_MASK_PRI_MASK_NAV) << BIT_SHIFT_PRI_MASK_NAV) 9794 #define BIT_GET_PRI_MASK_NAV(x) \ 9795 (((x) >> BIT_SHIFT_PRI_MASK_NAV) & BIT_MASK_PRI_MASK_NAV) 9796 9797 #define BIT_PRI_MASK_CCK BIT(108) 9798 #define BIT_PRI_MASK_OFDM BIT(107) 9799 #define BIT_PRI_MASK_RTY BIT(106) 9800 9801 #define BIT_SHIFT_PRI_MASK_NUM (102 & CPU_OPT_WIDTH) 9802 #define BIT_MASK_PRI_MASK_NUM 0xf 9803 #define BIT_PRI_MASK_NUM(x) \ 9804 (((x) & BIT_MASK_PRI_MASK_NUM) << BIT_SHIFT_PRI_MASK_NUM) 9805 #define BIT_GET_PRI_MASK_NUM(x) \ 9806 (((x) >> BIT_SHIFT_PRI_MASK_NUM) & BIT_MASK_PRI_MASK_NUM) 9807 9808 #define BIT_SHIFT_PRI_MASK_TYPE (98 & CPU_OPT_WIDTH) 9809 #define BIT_MASK_PRI_MASK_TYPE 0xf 9810 #define BIT_PRI_MASK_TYPE(x) \ 9811 (((x) & BIT_MASK_PRI_MASK_TYPE) << BIT_SHIFT_PRI_MASK_TYPE) 9812 #define BIT_GET_PRI_MASK_TYPE(x) \ 9813 (((x) >> BIT_SHIFT_PRI_MASK_TYPE) & BIT_MASK_PRI_MASK_TYPE) 9814 9815 #define BIT_OOB BIT(97) 9816 #define BIT_ANT_SEL BIT(96) 9817 9818 #define BIT_SHIFT_BREAK_TABLE_2 (80 & CPU_OPT_WIDTH) 9819 #define BIT_MASK_BREAK_TABLE_2 0xffff 9820 #define BIT_BREAK_TABLE_2(x) \ 9821 (((x) & BIT_MASK_BREAK_TABLE_2) << BIT_SHIFT_BREAK_TABLE_2) 9822 #define BIT_GET_BREAK_TABLE_2(x) \ 9823 (((x) >> BIT_SHIFT_BREAK_TABLE_2) & BIT_MASK_BREAK_TABLE_2) 9824 9825 #define BIT_SHIFT_BREAK_TABLE_1 (64 & CPU_OPT_WIDTH) 9826 #define BIT_MASK_BREAK_TABLE_1 0xffff 9827 #define BIT_BREAK_TABLE_1(x) \ 9828 (((x) & BIT_MASK_BREAK_TABLE_1) << BIT_SHIFT_BREAK_TABLE_1) 9829 #define BIT_GET_BREAK_TABLE_1(x) \ 9830 (((x) >> BIT_SHIFT_BREAK_TABLE_1) & BIT_MASK_BREAK_TABLE_1) 9831 9832 #define BIT_SHIFT_COEX_TABLE_2 (32 & CPU_OPT_WIDTH) 9833 #define BIT_MASK_COEX_TABLE_2 0xffffffffL 9834 #define BIT_COEX_TABLE_2(x) \ 9835 (((x) & BIT_MASK_COEX_TABLE_2) << BIT_SHIFT_COEX_TABLE_2) 9836 #define BIT_GET_COEX_TABLE_2(x) \ 9837 (((x) >> BIT_SHIFT_COEX_TABLE_2) & BIT_MASK_COEX_TABLE_2) 9838 9839 #define BIT_SHIFT_COEX_TABLE_1 0 9840 #define BIT_MASK_COEX_TABLE_1 0xffffffffL 9841 #define BIT_COEX_TABLE_1(x) \ 9842 (((x) & BIT_MASK_COEX_TABLE_1) << BIT_SHIFT_COEX_TABLE_1) 9843 #define BIT_GET_COEX_TABLE_1(x) \ 9844 (((x) >> BIT_SHIFT_COEX_TABLE_1) & BIT_MASK_COEX_TABLE_1) 9845 9846 /* 2 REG_RXCMD_0 (Offset 0x06D0) */ 9847 9848 #define BIT_RXCMD_EN BIT(31) 9849 9850 #define BIT_SHIFT_RXCMD_INFO 0 9851 #define BIT_MASK_RXCMD_INFO 0x7fffffffL 9852 #define BIT_RXCMD_INFO(x) (((x) & BIT_MASK_RXCMD_INFO) << BIT_SHIFT_RXCMD_INFO) 9853 #define BIT_GET_RXCMD_INFO(x) \ 9854 (((x) >> BIT_SHIFT_RXCMD_INFO) & BIT_MASK_RXCMD_INFO) 9855 9856 /* 2 REG_RXCMD_1 (Offset 0x06D4) */ 9857 9858 #define BIT_SHIFT_RXCMD_PRD 0 9859 #define BIT_MASK_RXCMD_PRD 0xffff 9860 #define BIT_RXCMD_PRD(x) (((x) & BIT_MASK_RXCMD_PRD) << BIT_SHIFT_RXCMD_PRD) 9861 #define BIT_GET_RXCMD_PRD(x) (((x) >> BIT_SHIFT_RXCMD_PRD) & BIT_MASK_RXCMD_PRD) 9862 9863 /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ 9864 9865 #define BIT_SHIFT_WMAC_RESP_MFB 25 9866 #define BIT_MASK_WMAC_RESP_MFB 0x7f 9867 #define BIT_WMAC_RESP_MFB(x) \ 9868 (((x) & BIT_MASK_WMAC_RESP_MFB) << BIT_SHIFT_WMAC_RESP_MFB) 9869 #define BIT_GET_WMAC_RESP_MFB(x) \ 9870 (((x) >> BIT_SHIFT_WMAC_RESP_MFB) & BIT_MASK_WMAC_RESP_MFB) 9871 9872 #define BIT_SHIFT_WMAC_ANTINF_SEL 23 9873 #define BIT_MASK_WMAC_ANTINF_SEL 0x3 9874 #define BIT_WMAC_ANTINF_SEL(x) \ 9875 (((x) & BIT_MASK_WMAC_ANTINF_SEL) << BIT_SHIFT_WMAC_ANTINF_SEL) 9876 #define BIT_GET_WMAC_ANTINF_SEL(x) \ 9877 (((x) >> BIT_SHIFT_WMAC_ANTINF_SEL) & BIT_MASK_WMAC_ANTINF_SEL) 9878 9879 #define BIT_SHIFT_WMAC_ANTSEL_SEL 21 9880 #define BIT_MASK_WMAC_ANTSEL_SEL 0x3 9881 #define BIT_WMAC_ANTSEL_SEL(x) \ 9882 (((x) & BIT_MASK_WMAC_ANTSEL_SEL) << BIT_SHIFT_WMAC_ANTSEL_SEL) 9883 #define BIT_GET_WMAC_ANTSEL_SEL(x) \ 9884 (((x) >> BIT_SHIFT_WMAC_ANTSEL_SEL) & BIT_MASK_WMAC_ANTSEL_SEL) 9885 9886 /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ 9887 9888 #define BIT_SHIFT_R_WMAC_RESP_TXPOWER 18 9889 #define BIT_MASK_R_WMAC_RESP_TXPOWER 0x7 9890 #define BIT_R_WMAC_RESP_TXPOWER(x) \ 9891 (((x) & BIT_MASK_R_WMAC_RESP_TXPOWER) << BIT_SHIFT_R_WMAC_RESP_TXPOWER) 9892 #define BIT_GET_R_WMAC_RESP_TXPOWER(x) \ 9893 (((x) >> BIT_SHIFT_R_WMAC_RESP_TXPOWER) & BIT_MASK_R_WMAC_RESP_TXPOWER) 9894 9895 /* 2 REG_WMAC_RESP_TXINFO (Offset 0x06D8) */ 9896 9897 #define BIT_SHIFT_WMAC_RESP_TXANT 0 9898 #define BIT_MASK_WMAC_RESP_TXANT 0x3ffff 9899 #define BIT_WMAC_RESP_TXANT(x) \ 9900 (((x) & BIT_MASK_WMAC_RESP_TXANT) << BIT_SHIFT_WMAC_RESP_TXANT) 9901 #define BIT_GET_WMAC_RESP_TXANT(x) \ 9902 (((x) >> BIT_SHIFT_WMAC_RESP_TXANT) & BIT_MASK_WMAC_RESP_TXANT) 9903 9904 /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9905 9906 #define BIT_CTL_IDLE_CLR_CSI_RPT BIT(31) 9907 9908 /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9909 9910 #define BIT_WMAC_USE_NDPARATE BIT(30) 9911 9912 #define BIT_SHIFT_WMAC_CSI_RATE 24 9913 #define BIT_MASK_WMAC_CSI_RATE 0x3f 9914 #define BIT_WMAC_CSI_RATE(x) \ 9915 (((x) & BIT_MASK_WMAC_CSI_RATE) << BIT_SHIFT_WMAC_CSI_RATE) 9916 #define BIT_GET_WMAC_CSI_RATE(x) \ 9917 (((x) >> BIT_SHIFT_WMAC_CSI_RATE) & BIT_MASK_WMAC_CSI_RATE) 9918 9919 #define BIT_SHIFT_WMAC_RESP_TXRATE 16 9920 #define BIT_MASK_WMAC_RESP_TXRATE 0xff 9921 #define BIT_WMAC_RESP_TXRATE(x) \ 9922 (((x) & BIT_MASK_WMAC_RESP_TXRATE) << BIT_SHIFT_WMAC_RESP_TXRATE) 9923 #define BIT_GET_WMAC_RESP_TXRATE(x) \ 9924 (((x) >> BIT_SHIFT_WMAC_RESP_TXRATE) & BIT_MASK_WMAC_RESP_TXRATE) 9925 9926 /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9927 9928 #define BIT_BBPSF_MPDUCHKEN BIT(5) 9929 9930 /* 2 REG_BBPSF_CTRL (Offset 0x06DC) */ 9931 9932 #define BIT_BBPSF_MHCHKEN BIT(4) 9933 #define BIT_BBPSF_ERRCHKEN BIT(3) 9934 9935 #define BIT_SHIFT_BBPSF_ERRTHR 0 9936 #define BIT_MASK_BBPSF_ERRTHR 0x7 9937 #define BIT_BBPSF_ERRTHR(x) \ 9938 (((x) & BIT_MASK_BBPSF_ERRTHR) << BIT_SHIFT_BBPSF_ERRTHR) 9939 #define BIT_GET_BBPSF_ERRTHR(x) \ 9940 (((x) >> BIT_SHIFT_BBPSF_ERRTHR) & BIT_MASK_BBPSF_ERRTHR) 9941 9942 /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ 9943 9944 #define BIT_NOA_PARSER_EN BIT(15) 9945 9946 /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ 9947 9948 #define BIT_BSSID_SEL BIT(14) 9949 9950 /* 2 REG_P2P_RX_BCN_NOA (Offset 0x06E0) */ 9951 9952 #define BIT_SHIFT_P2P_OUI_TYPE 0 9953 #define BIT_MASK_P2P_OUI_TYPE 0xff 9954 #define BIT_P2P_OUI_TYPE(x) \ 9955 (((x) & BIT_MASK_P2P_OUI_TYPE) << BIT_SHIFT_P2P_OUI_TYPE) 9956 #define BIT_GET_P2P_OUI_TYPE(x) \ 9957 (((x) >> BIT_SHIFT_P2P_OUI_TYPE) & BIT_MASK_P2P_OUI_TYPE) 9958 9959 /* 2 REG_ASSOCIATED_BFMER0_INFO (Offset 0x06E4) */ 9960 9961 #define BIT_SHIFT_R_WMAC_TXCSI_AID0 (48 & CPU_OPT_WIDTH) 9962 #define BIT_MASK_R_WMAC_TXCSI_AID0 0x1ff 9963 #define BIT_R_WMAC_TXCSI_AID0(x) \ 9964 (((x) & BIT_MASK_R_WMAC_TXCSI_AID0) << BIT_SHIFT_R_WMAC_TXCSI_AID0) 9965 #define BIT_GET_R_WMAC_TXCSI_AID0(x) \ 9966 (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID0) & BIT_MASK_R_WMAC_TXCSI_AID0) 9967 9968 #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0 0 9969 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R0 0xffffffffffffL 9970 #define BIT_R_WMAC_SOUNDING_RXADD_R0(x) \ 9971 (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) \ 9972 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) 9973 #define BIT_GET_R_WMAC_SOUNDING_RXADD_R0(x) \ 9974 (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R0) & \ 9975 BIT_MASK_R_WMAC_SOUNDING_RXADD_R0) 9976 9977 /* 2 REG_ASSOCIATED_BFMER1_INFO (Offset 0x06EC) */ 9978 9979 #define BIT_SHIFT_R_WMAC_TXCSI_AID1 (48 & CPU_OPT_WIDTH) 9980 #define BIT_MASK_R_WMAC_TXCSI_AID1 0x1ff 9981 #define BIT_R_WMAC_TXCSI_AID1(x) \ 9982 (((x) & BIT_MASK_R_WMAC_TXCSI_AID1) << BIT_SHIFT_R_WMAC_TXCSI_AID1) 9983 #define BIT_GET_R_WMAC_TXCSI_AID1(x) \ 9984 (((x) >> BIT_SHIFT_R_WMAC_TXCSI_AID1) & BIT_MASK_R_WMAC_TXCSI_AID1) 9985 9986 #define BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1 0 9987 #define BIT_MASK_R_WMAC_SOUNDING_RXADD_R1 0xffffffffffffL 9988 #define BIT_R_WMAC_SOUNDING_RXADD_R1(x) \ 9989 (((x) & BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) \ 9990 << BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) 9991 #define BIT_GET_R_WMAC_SOUNDING_RXADD_R1(x) \ 9992 (((x) >> BIT_SHIFT_R_WMAC_SOUNDING_RXADD_R1) & \ 9993 BIT_MASK_R_WMAC_SOUNDING_RXADD_R1) 9994 9995 /* 2 REG_TX_CSI_RPT_PARAM_BW20 (Offset 0x06F4) */ 9996 9997 #define BIT_SHIFT_R_WMAC_BFINFO_20M_1 16 9998 #define BIT_MASK_R_WMAC_BFINFO_20M_1 0xfff 9999 #define BIT_R_WMAC_BFINFO_20M_1(x) \ 10000 (((x) & BIT_MASK_R_WMAC_BFINFO_20M_1) << BIT_SHIFT_R_WMAC_BFINFO_20M_1) 10001 #define BIT_GET_R_WMAC_BFINFO_20M_1(x) \ 10002 (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_1) & BIT_MASK_R_WMAC_BFINFO_20M_1) 10003 10004 #define BIT_SHIFT_R_WMAC_BFINFO_20M_0 0 10005 #define BIT_MASK_R_WMAC_BFINFO_20M_0 0xfff 10006 #define BIT_R_WMAC_BFINFO_20M_0(x) \ 10007 (((x) & BIT_MASK_R_WMAC_BFINFO_20M_0) << BIT_SHIFT_R_WMAC_BFINFO_20M_0) 10008 #define BIT_GET_R_WMAC_BFINFO_20M_0(x) \ 10009 (((x) >> BIT_SHIFT_R_WMAC_BFINFO_20M_0) & BIT_MASK_R_WMAC_BFINFO_20M_0) 10010 10011 /* 2 REG_TX_CSI_RPT_PARAM_BW40 (Offset 0x06F8) */ 10012 10013 #define BIT_SHIFT_WMAC_RESP_ANTCD 0 10014 #define BIT_MASK_WMAC_RESP_ANTCD 0xf 10015 #define BIT_WMAC_RESP_ANTCD(x) \ 10016 (((x) & BIT_MASK_WMAC_RESP_ANTCD) << BIT_SHIFT_WMAC_RESP_ANTCD) 10017 #define BIT_GET_WMAC_RESP_ANTCD(x) \ 10018 (((x) >> BIT_SHIFT_WMAC_RESP_ANTCD) & BIT_MASK_WMAC_RESP_ANTCD) 10019 10020 /* 2 REG_MACID1 (Offset 0x0700) */ 10021 10022 #define BIT_SHIFT_MACID1 0 10023 #define BIT_MASK_MACID1 0xffffffffffffL 10024 #define BIT_MACID1(x) (((x) & BIT_MASK_MACID1) << BIT_SHIFT_MACID1) 10025 #define BIT_GET_MACID1(x) (((x) >> BIT_SHIFT_MACID1) & BIT_MASK_MACID1) 10026 10027 /* 2 REG_BSSID1 (Offset 0x0708) */ 10028 10029 #define BIT_SHIFT_BSSID1 0 10030 #define BIT_MASK_BSSID1 0xffffffffffffL 10031 #define BIT_BSSID1(x) (((x) & BIT_MASK_BSSID1) << BIT_SHIFT_BSSID1) 10032 #define BIT_GET_BSSID1(x) (((x) >> BIT_SHIFT_BSSID1) & BIT_MASK_BSSID1) 10033 10034 /* 2 REG_BCN_PSR_RPT1 (Offset 0x0710) */ 10035 10036 #define BIT_SHIFT_DTIM_CNT1 24 10037 #define BIT_MASK_DTIM_CNT1 0xff 10038 #define BIT_DTIM_CNT1(x) (((x) & BIT_MASK_DTIM_CNT1) << BIT_SHIFT_DTIM_CNT1) 10039 #define BIT_GET_DTIM_CNT1(x) (((x) >> BIT_SHIFT_DTIM_CNT1) & BIT_MASK_DTIM_CNT1) 10040 10041 #define BIT_SHIFT_DTIM_PERIOD1 16 10042 #define BIT_MASK_DTIM_PERIOD1 0xff 10043 #define BIT_DTIM_PERIOD1(x) \ 10044 (((x) & BIT_MASK_DTIM_PERIOD1) << BIT_SHIFT_DTIM_PERIOD1) 10045 #define BIT_GET_DTIM_PERIOD1(x) \ 10046 (((x) >> BIT_SHIFT_DTIM_PERIOD1) & BIT_MASK_DTIM_PERIOD1) 10047 10048 #define BIT_DTIM1 BIT(15) 10049 #define BIT_TIM1 BIT(14) 10050 10051 #define BIT_SHIFT_PS_AID_1 0 10052 #define BIT_MASK_PS_AID_1 0x7ff 10053 #define BIT_PS_AID_1(x) (((x) & BIT_MASK_PS_AID_1) << BIT_SHIFT_PS_AID_1) 10054 #define BIT_GET_PS_AID_1(x) (((x) >> BIT_SHIFT_PS_AID_1) & BIT_MASK_PS_AID_1) 10055 10056 /* 2 REG_ASSOCIATED_BFMEE_SEL (Offset 0x0714) */ 10057 10058 #define BIT_TXUSER_ID1 BIT(25) 10059 10060 #define BIT_SHIFT_AID1 16 10061 #define BIT_MASK_AID1 0x1ff 10062 #define BIT_AID1(x) (((x) & BIT_MASK_AID1) << BIT_SHIFT_AID1) 10063 #define BIT_GET_AID1(x) (((x) >> BIT_SHIFT_AID1) & BIT_MASK_AID1) 10064 10065 #define BIT_TXUSER_ID0 BIT(9) 10066 10067 #define BIT_SHIFT_AID0 0 10068 #define BIT_MASK_AID0 0x1ff 10069 #define BIT_AID0(x) (((x) & BIT_MASK_AID0) << BIT_SHIFT_AID0) 10070 #define BIT_GET_AID0(x) (((x) >> BIT_SHIFT_AID0) & BIT_MASK_AID0) 10071 10072 /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ 10073 10074 #define BIT_SHIFT_NDP_RX_STANDBY_TIMER 24 10075 #define BIT_MASK_NDP_RX_STANDBY_TIMER 0xff 10076 #define BIT_NDP_RX_STANDBY_TIMER(x) \ 10077 (((x) & BIT_MASK_NDP_RX_STANDBY_TIMER) \ 10078 << BIT_SHIFT_NDP_RX_STANDBY_TIMER) 10079 #define BIT_GET_NDP_RX_STANDBY_TIMER(x) \ 10080 (((x) >> BIT_SHIFT_NDP_RX_STANDBY_TIMER) & \ 10081 BIT_MASK_NDP_RX_STANDBY_TIMER) 10082 10083 #define BIT_SHIFT_CSI_RPT_OFFSET_HT 16 10084 #define BIT_MASK_CSI_RPT_OFFSET_HT 0xff 10085 #define BIT_CSI_RPT_OFFSET_HT(x) \ 10086 (((x) & BIT_MASK_CSI_RPT_OFFSET_HT) << BIT_SHIFT_CSI_RPT_OFFSET_HT) 10087 #define BIT_GET_CSI_RPT_OFFSET_HT(x) \ 10088 (((x) >> BIT_SHIFT_CSI_RPT_OFFSET_HT) & BIT_MASK_CSI_RPT_OFFSET_HT) 10089 10090 /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ 10091 10092 #define BIT_SHIFT_R_WMAC_VHT_CATEGORY 8 10093 #define BIT_MASK_R_WMAC_VHT_CATEGORY 0xff 10094 #define BIT_R_WMAC_VHT_CATEGORY(x) \ 10095 (((x) & BIT_MASK_R_WMAC_VHT_CATEGORY) << BIT_SHIFT_R_WMAC_VHT_CATEGORY) 10096 #define BIT_GET_R_WMAC_VHT_CATEGORY(x) \ 10097 (((x) >> BIT_SHIFT_R_WMAC_VHT_CATEGORY) & BIT_MASK_R_WMAC_VHT_CATEGORY) 10098 10099 /* 2 REG_SND_PTCL_CTRL (Offset 0x0718) */ 10100 10101 #define BIT_R_WMAC_USE_NSTS BIT(7) 10102 #define BIT_R_DISABLE_CHECK_VHTSIGB_CRC BIT(6) 10103 #define BIT_R_DISABLE_CHECK_VHTSIGA_CRC BIT(5) 10104 #define BIT_R_WMAC_BFPARAM_SEL BIT(4) 10105 #define BIT_R_WMAC_CSISEQ_SEL BIT(3) 10106 #define BIT_R_WMAC_CSI_WITHHTC_EN BIT(2) 10107 #define BIT_R_WMAC_HT_NDPA_EN BIT(1) 10108 #define BIT_R_WMAC_VHT_NDPA_EN BIT(0) 10109 10110 /* 2 REG_NS_ARP_CTRL (Offset 0x0720) */ 10111 10112 #define BIT_R_WMAC_NSARP_RSPEN BIT(15) 10113 #define BIT_R_WMAC_NSARP_RARP BIT(9) 10114 #define BIT_R_WMAC_NSARP_RIPV6 BIT(8) 10115 10116 #define BIT_SHIFT_R_WMAC_NSARP_MODEN 6 10117 #define BIT_MASK_R_WMAC_NSARP_MODEN 0x3 10118 #define BIT_R_WMAC_NSARP_MODEN(x) \ 10119 (((x) & BIT_MASK_R_WMAC_NSARP_MODEN) << BIT_SHIFT_R_WMAC_NSARP_MODEN) 10120 #define BIT_GET_R_WMAC_NSARP_MODEN(x) \ 10121 (((x) >> BIT_SHIFT_R_WMAC_NSARP_MODEN) & BIT_MASK_R_WMAC_NSARP_MODEN) 10122 10123 #define BIT_SHIFT_R_WMAC_NSARP_RSPFTP 4 10124 #define BIT_MASK_R_WMAC_NSARP_RSPFTP 0x3 10125 #define BIT_R_WMAC_NSARP_RSPFTP(x) \ 10126 (((x) & BIT_MASK_R_WMAC_NSARP_RSPFTP) << BIT_SHIFT_R_WMAC_NSARP_RSPFTP) 10127 #define BIT_GET_R_WMAC_NSARP_RSPFTP(x) \ 10128 (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPFTP) & BIT_MASK_R_WMAC_NSARP_RSPFTP) 10129 10130 #define BIT_SHIFT_R_WMAC_NSARP_RSPSEC 0 10131 #define BIT_MASK_R_WMAC_NSARP_RSPSEC 0xf 10132 #define BIT_R_WMAC_NSARP_RSPSEC(x) \ 10133 (((x) & BIT_MASK_R_WMAC_NSARP_RSPSEC) << BIT_SHIFT_R_WMAC_NSARP_RSPSEC) 10134 #define BIT_GET_R_WMAC_NSARP_RSPSEC(x) \ 10135 (((x) >> BIT_SHIFT_R_WMAC_NSARP_RSPSEC) & BIT_MASK_R_WMAC_NSARP_RSPSEC) 10136 10137 /* 2 REG_NS_ARP_INFO (Offset 0x0724) */ 10138 10139 #define BIT_REQ_IS_MCNS BIT(23) 10140 #define BIT_REQ_IS_UCNS BIT(22) 10141 #define BIT_REQ_IS_USNS BIT(21) 10142 #define BIT_REQ_IS_ARP BIT(20) 10143 #define BIT_EXPRSP_MH_WITHQC BIT(19) 10144 10145 #define BIT_SHIFT_EXPRSP_SECTYPE 16 10146 #define BIT_MASK_EXPRSP_SECTYPE 0x7 10147 #define BIT_EXPRSP_SECTYPE(x) \ 10148 (((x) & BIT_MASK_EXPRSP_SECTYPE) << BIT_SHIFT_EXPRSP_SECTYPE) 10149 #define BIT_GET_EXPRSP_SECTYPE(x) \ 10150 (((x) >> BIT_SHIFT_EXPRSP_SECTYPE) & BIT_MASK_EXPRSP_SECTYPE) 10151 10152 #define BIT_SHIFT_EXPRSP_CHKSM_7_TO_0 8 10153 #define BIT_MASK_EXPRSP_CHKSM_7_TO_0 0xff 10154 #define BIT_EXPRSP_CHKSM_7_TO_0(x) \ 10155 (((x) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) << BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) 10156 #define BIT_GET_EXPRSP_CHKSM_7_TO_0(x) \ 10157 (((x) >> BIT_SHIFT_EXPRSP_CHKSM_7_TO_0) & BIT_MASK_EXPRSP_CHKSM_7_TO_0) 10158 10159 #define BIT_SHIFT_EXPRSP_CHKSM_15_TO_8 0 10160 #define BIT_MASK_EXPRSP_CHKSM_15_TO_8 0xff 10161 #define BIT_EXPRSP_CHKSM_15_TO_8(x) \ 10162 (((x) & BIT_MASK_EXPRSP_CHKSM_15_TO_8) \ 10163 << BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) 10164 #define BIT_GET_EXPRSP_CHKSM_15_TO_8(x) \ 10165 (((x) >> BIT_SHIFT_EXPRSP_CHKSM_15_TO_8) & \ 10166 BIT_MASK_EXPRSP_CHKSM_15_TO_8) 10167 10168 /* 2 REG_BEAMFORMING_INFO_NSARP_V1 (Offset 0x0728) */ 10169 10170 #define BIT_SHIFT_WMAC_ARPIP 0 10171 #define BIT_MASK_WMAC_ARPIP 0xffffffffL 10172 #define BIT_WMAC_ARPIP(x) (((x) & BIT_MASK_WMAC_ARPIP) << BIT_SHIFT_WMAC_ARPIP) 10173 #define BIT_GET_WMAC_ARPIP(x) \ 10174 (((x) >> BIT_SHIFT_WMAC_ARPIP) & BIT_MASK_WMAC_ARPIP) 10175 10176 /* 2 REG_BEAMFORMING_INFO_NSARP (Offset 0x072C) */ 10177 10178 #define BIT_SHIFT_BEAMFORMING_INFO 0 10179 #define BIT_MASK_BEAMFORMING_INFO 0xffffffffL 10180 #define BIT_BEAMFORMING_INFO(x) \ 10181 (((x) & BIT_MASK_BEAMFORMING_INFO) << BIT_SHIFT_BEAMFORMING_INFO) 10182 #define BIT_GET_BEAMFORMING_INFO(x) \ 10183 (((x) >> BIT_SHIFT_BEAMFORMING_INFO) & BIT_MASK_BEAMFORMING_INFO) 10184 10185 /* 2 REG_WMAC_RTX_CTX_SUBTYPE_CFG (Offset 0x0750) */ 10186 10187 #define BIT_SHIFT_R_WMAC_CTX_SUBTYPE 4 10188 #define BIT_MASK_R_WMAC_CTX_SUBTYPE 0xf 10189 #define BIT_R_WMAC_CTX_SUBTYPE(x) \ 10190 (((x) & BIT_MASK_R_WMAC_CTX_SUBTYPE) << BIT_SHIFT_R_WMAC_CTX_SUBTYPE) 10191 #define BIT_GET_R_WMAC_CTX_SUBTYPE(x) \ 10192 (((x) >> BIT_SHIFT_R_WMAC_CTX_SUBTYPE) & BIT_MASK_R_WMAC_CTX_SUBTYPE) 10193 10194 #define BIT_SHIFT_R_WMAC_RTX_SUBTYPE 0 10195 #define BIT_MASK_R_WMAC_RTX_SUBTYPE 0xf 10196 #define BIT_R_WMAC_RTX_SUBTYPE(x) \ 10197 (((x) & BIT_MASK_R_WMAC_RTX_SUBTYPE) << BIT_SHIFT_R_WMAC_RTX_SUBTYPE) 10198 #define BIT_GET_R_WMAC_RTX_SUBTYPE(x) \ 10199 (((x) >> BIT_SHIFT_R_WMAC_RTX_SUBTYPE) & BIT_MASK_R_WMAC_RTX_SUBTYPE) 10200 10201 /* 2 REG_BT_COEX_V2 (Offset 0x0762) */ 10202 10203 #define BIT_GNT_BT_POLARITY BIT(12) 10204 #define BIT_GNT_BT_BYPASS_PRIORITY BIT(8) 10205 10206 #define BIT_SHIFT_TIMER 0 10207 #define BIT_MASK_TIMER 0xff 10208 #define BIT_TIMER(x) (((x) & BIT_MASK_TIMER) << BIT_SHIFT_TIMER) 10209 #define BIT_GET_TIMER(x) (((x) >> BIT_SHIFT_TIMER) & BIT_MASK_TIMER) 10210 10211 /* 2 REG_BT_COEX (Offset 0x0764) */ 10212 10213 #define BIT_R_GNT_BT_RFC_SW BIT(12) 10214 #define BIT_R_GNT_BT_RFC_SW_EN BIT(11) 10215 #define BIT_R_GNT_BT_BB_SW BIT(10) 10216 #define BIT_R_GNT_BT_BB_SW_EN BIT(9) 10217 #define BIT_R_BT_CNT_THREN BIT(8) 10218 10219 #define BIT_SHIFT_R_BT_CNT_THR 0 10220 #define BIT_MASK_R_BT_CNT_THR 0xff 10221 #define BIT_R_BT_CNT_THR(x) \ 10222 (((x) & BIT_MASK_R_BT_CNT_THR) << BIT_SHIFT_R_BT_CNT_THR) 10223 #define BIT_GET_R_BT_CNT_THR(x) \ 10224 (((x) >> BIT_SHIFT_R_BT_CNT_THR) & BIT_MASK_R_BT_CNT_THR) 10225 10226 /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ 10227 10228 #define BIT_WLRX_TER_BY_CTL BIT(43) 10229 #define BIT_WLRX_TER_BY_AD BIT(42) 10230 #define BIT_ANT_DIVERSITY_SEL BIT(41) 10231 #define BIT_ANTSEL_FOR_BT_CTRL_EN BIT(40) 10232 #define BIT_WLACT_LOW_GNTWL_EN BIT(34) 10233 #define BIT_WLACT_HIGH_GNTBT_EN BIT(33) 10234 10235 /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ 10236 10237 #define BIT_NAV_UPPER_V1 BIT(32) 10238 10239 /* 2 REG_WLAN_ACT_MASK_CTRL (Offset 0x0768) */ 10240 10241 #define BIT_SHIFT_RXMYRTS_NAV_V1 8 10242 #define BIT_MASK_RXMYRTS_NAV_V1 0xff 10243 #define BIT_RXMYRTS_NAV_V1(x) \ 10244 (((x) & BIT_MASK_RXMYRTS_NAV_V1) << BIT_SHIFT_RXMYRTS_NAV_V1) 10245 #define BIT_GET_RXMYRTS_NAV_V1(x) \ 10246 (((x) >> BIT_SHIFT_RXMYRTS_NAV_V1) & BIT_MASK_RXMYRTS_NAV_V1) 10247 10248 #define BIT_SHIFT_RTSRST_V1 0 10249 #define BIT_MASK_RTSRST_V1 0xff 10250 #define BIT_RTSRST_V1(x) (((x) & BIT_MASK_RTSRST_V1) << BIT_SHIFT_RTSRST_V1) 10251 #define BIT_GET_RTSRST_V1(x) (((x) >> BIT_SHIFT_RTSRST_V1) & BIT_MASK_RTSRST_V1) 10252 10253 /* 2 REG_BT_COEX_ENHANCED_INTR_CTRL (Offset 0x076E) */ 10254 10255 #define BIT_SHIFT_BT_STAT_DELAY 12 10256 #define BIT_MASK_BT_STAT_DELAY 0xf 10257 #define BIT_BT_STAT_DELAY(x) \ 10258 (((x) & BIT_MASK_BT_STAT_DELAY) << BIT_SHIFT_BT_STAT_DELAY) 10259 #define BIT_GET_BT_STAT_DELAY(x) \ 10260 (((x) >> BIT_SHIFT_BT_STAT_DELAY) & BIT_MASK_BT_STAT_DELAY) 10261 10262 #define BIT_SHIFT_BT_TRX_INIT_DETECT 8 10263 #define BIT_MASK_BT_TRX_INIT_DETECT 0xf 10264 #define BIT_BT_TRX_INIT_DETECT(x) \ 10265 (((x) & BIT_MASK_BT_TRX_INIT_DETECT) << BIT_SHIFT_BT_TRX_INIT_DETECT) 10266 #define BIT_GET_BT_TRX_INIT_DETECT(x) \ 10267 (((x) >> BIT_SHIFT_BT_TRX_INIT_DETECT) & BIT_MASK_BT_TRX_INIT_DETECT) 10268 10269 #define BIT_SHIFT_BT_PRI_DETECT_TO 4 10270 #define BIT_MASK_BT_PRI_DETECT_TO 0xf 10271 #define BIT_BT_PRI_DETECT_TO(x) \ 10272 (((x) & BIT_MASK_BT_PRI_DETECT_TO) << BIT_SHIFT_BT_PRI_DETECT_TO) 10273 #define BIT_GET_BT_PRI_DETECT_TO(x) \ 10274 (((x) >> BIT_SHIFT_BT_PRI_DETECT_TO) & BIT_MASK_BT_PRI_DETECT_TO) 10275 10276 #define BIT_R_GRANTALL_WLMASK BIT(3) 10277 #define BIT_STATIS_BT_EN BIT(2) 10278 #define BIT_WL_ACT_MASK_ENABLE BIT(1) 10279 #define BIT_ENHANCED_BT BIT(0) 10280 10281 /* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ 10282 10283 #define BIT_SHIFT_STATIS_BT_LO_RX (48 & CPU_OPT_WIDTH) 10284 #define BIT_MASK_STATIS_BT_LO_RX 0xffff 10285 #define BIT_STATIS_BT_LO_RX(x) \ 10286 (((x) & BIT_MASK_STATIS_BT_LO_RX) << BIT_SHIFT_STATIS_BT_LO_RX) 10287 #define BIT_GET_STATIS_BT_LO_RX(x) \ 10288 (((x) >> BIT_SHIFT_STATIS_BT_LO_RX) & BIT_MASK_STATIS_BT_LO_RX) 10289 10290 #define BIT_SHIFT_STATIS_BT_LO_TX (32 & CPU_OPT_WIDTH) 10291 #define BIT_MASK_STATIS_BT_LO_TX 0xffff 10292 #define BIT_STATIS_BT_LO_TX(x) \ 10293 (((x) & BIT_MASK_STATIS_BT_LO_TX) << BIT_SHIFT_STATIS_BT_LO_TX) 10294 #define BIT_GET_STATIS_BT_LO_TX(x) \ 10295 (((x) >> BIT_SHIFT_STATIS_BT_LO_TX) & BIT_MASK_STATIS_BT_LO_TX) 10296 10297 /* 2 REG_BT_ACT_STATISTICS (Offset 0x0770) */ 10298 10299 #define BIT_SHIFT_STATIS_BT_HI_RX 16 10300 #define BIT_MASK_STATIS_BT_HI_RX 0xffff 10301 #define BIT_STATIS_BT_HI_RX(x) \ 10302 (((x) & BIT_MASK_STATIS_BT_HI_RX) << BIT_SHIFT_STATIS_BT_HI_RX) 10303 #define BIT_GET_STATIS_BT_HI_RX(x) \ 10304 (((x) >> BIT_SHIFT_STATIS_BT_HI_RX) & BIT_MASK_STATIS_BT_HI_RX) 10305 10306 #define BIT_SHIFT_STATIS_BT_HI_TX 0 10307 #define BIT_MASK_STATIS_BT_HI_TX 0xffff 10308 #define BIT_STATIS_BT_HI_TX(x) \ 10309 (((x) & BIT_MASK_STATIS_BT_HI_TX) << BIT_SHIFT_STATIS_BT_HI_TX) 10310 #define BIT_GET_STATIS_BT_HI_TX(x) \ 10311 (((x) >> BIT_SHIFT_STATIS_BT_HI_TX) & BIT_MASK_STATIS_BT_HI_TX) 10312 10313 /* 2 REG_BT_STATISTICS_CONTROL_REGISTER (Offset 0x0778) */ 10314 10315 #define BIT_SHIFT_R_BT_CMD_RPT 16 10316 #define BIT_MASK_R_BT_CMD_RPT 0xffff 10317 #define BIT_R_BT_CMD_RPT(x) \ 10318 (((x) & BIT_MASK_R_BT_CMD_RPT) << BIT_SHIFT_R_BT_CMD_RPT) 10319 #define BIT_GET_R_BT_CMD_RPT(x) \ 10320 (((x) >> BIT_SHIFT_R_BT_CMD_RPT) & BIT_MASK_R_BT_CMD_RPT) 10321 10322 #define BIT_SHIFT_R_RPT_FROM_BT 8 10323 #define BIT_MASK_R_RPT_FROM_BT 0xff 10324 #define BIT_R_RPT_FROM_BT(x) \ 10325 (((x) & BIT_MASK_R_RPT_FROM_BT) << BIT_SHIFT_R_RPT_FROM_BT) 10326 #define BIT_GET_R_RPT_FROM_BT(x) \ 10327 (((x) >> BIT_SHIFT_R_RPT_FROM_BT) & BIT_MASK_R_RPT_FROM_BT) 10328 10329 #define BIT_SHIFT_BT_HID_ISR_SET 6 10330 #define BIT_MASK_BT_HID_ISR_SET 0x3 10331 #define BIT_BT_HID_ISR_SET(x) \ 10332 (((x) & BIT_MASK_BT_HID_ISR_SET) << BIT_SHIFT_BT_HID_ISR_SET) 10333 #define BIT_GET_BT_HID_ISR_SET(x) \ 10334 (((x) >> BIT_SHIFT_BT_HID_ISR_SET) & BIT_MASK_BT_HID_ISR_SET) 10335 10336 #define BIT_TDMA_BT_START_NOTIFY BIT(5) 10337 #define BIT_ENABLE_TDMA_FW_MODE BIT(4) 10338 #define BIT_ENABLE_PTA_TDMA_MODE BIT(3) 10339 #define BIT_ENABLE_COEXIST_TAB_IN_TDMA BIT(2) 10340 #define BIT_GPIO2_GPIO3_EXANGE_OR_NO_BT_CCA BIT(1) 10341 #define BIT_RTK_BT_ENABLE BIT(0) 10342 10343 /* 2 REG_BT_STATUS_REPORT_REGISTER (Offset 0x077C) */ 10344 10345 #define BIT_SHIFT_BT_PROFILE 24 10346 #define BIT_MASK_BT_PROFILE 0xff 10347 #define BIT_BT_PROFILE(x) (((x) & BIT_MASK_BT_PROFILE) << BIT_SHIFT_BT_PROFILE) 10348 #define BIT_GET_BT_PROFILE(x) \ 10349 (((x) >> BIT_SHIFT_BT_PROFILE) & BIT_MASK_BT_PROFILE) 10350 10351 #define BIT_SHIFT_BT_POWER 16 10352 #define BIT_MASK_BT_POWER 0xff 10353 #define BIT_BT_POWER(x) (((x) & BIT_MASK_BT_POWER) << BIT_SHIFT_BT_POWER) 10354 #define BIT_GET_BT_POWER(x) (((x) >> BIT_SHIFT_BT_POWER) & BIT_MASK_BT_POWER) 10355 10356 #define BIT_SHIFT_BT_PREDECT_STATUS 8 10357 #define BIT_MASK_BT_PREDECT_STATUS 0xff 10358 #define BIT_BT_PREDECT_STATUS(x) \ 10359 (((x) & BIT_MASK_BT_PREDECT_STATUS) << BIT_SHIFT_BT_PREDECT_STATUS) 10360 #define BIT_GET_BT_PREDECT_STATUS(x) \ 10361 (((x) >> BIT_SHIFT_BT_PREDECT_STATUS) & BIT_MASK_BT_PREDECT_STATUS) 10362 10363 #define BIT_SHIFT_BT_CMD_INFO 0 10364 #define BIT_MASK_BT_CMD_INFO 0xff 10365 #define BIT_BT_CMD_INFO(x) \ 10366 (((x) & BIT_MASK_BT_CMD_INFO) << BIT_SHIFT_BT_CMD_INFO) 10367 #define BIT_GET_BT_CMD_INFO(x) \ 10368 (((x) >> BIT_SHIFT_BT_CMD_INFO) & BIT_MASK_BT_CMD_INFO) 10369 10370 /* 2 REG_BT_INTERRUPT_CONTROL_REGISTER (Offset 0x0780) */ 10371 10372 #define BIT_EN_MAC_NULL_PKT_NOTIFY BIT(31) 10373 #define BIT_EN_WLAN_RPT_AND_BT_QUERY BIT(30) 10374 #define BIT_EN_BT_STSTUS_RPT BIT(29) 10375 #define BIT_EN_BT_POWER BIT(28) 10376 #define BIT_EN_BT_CHANNEL BIT(27) 10377 #define BIT_EN_BT_SLOT_CHANGE BIT(26) 10378 #define BIT_EN_BT_PROFILE_OR_HID BIT(25) 10379 #define BIT_WLAN_RPT_NOTIFY BIT(24) 10380 10381 #define BIT_SHIFT_WLAN_RPT_DATA 16 10382 #define BIT_MASK_WLAN_RPT_DATA 0xff 10383 #define BIT_WLAN_RPT_DATA(x) \ 10384 (((x) & BIT_MASK_WLAN_RPT_DATA) << BIT_SHIFT_WLAN_RPT_DATA) 10385 #define BIT_GET_WLAN_RPT_DATA(x) \ 10386 (((x) >> BIT_SHIFT_WLAN_RPT_DATA) & BIT_MASK_WLAN_RPT_DATA) 10387 10388 #define BIT_SHIFT_CMD_ID 8 10389 #define BIT_MASK_CMD_ID 0xff 10390 #define BIT_CMD_ID(x) (((x) & BIT_MASK_CMD_ID) << BIT_SHIFT_CMD_ID) 10391 #define BIT_GET_CMD_ID(x) (((x) >> BIT_SHIFT_CMD_ID) & BIT_MASK_CMD_ID) 10392 10393 #define BIT_SHIFT_BT_DATA 0 10394 #define BIT_MASK_BT_DATA 0xff 10395 #define BIT_BT_DATA(x) (((x) & BIT_MASK_BT_DATA) << BIT_SHIFT_BT_DATA) 10396 #define BIT_GET_BT_DATA(x) (((x) >> BIT_SHIFT_BT_DATA) & BIT_MASK_BT_DATA) 10397 10398 /* 2 REG_WLAN_REPORT_TIME_OUT_CONTROL_REGISTER (Offset 0x0784) */ 10399 10400 #define BIT_SHIFT_WLAN_RPT_TO 0 10401 #define BIT_MASK_WLAN_RPT_TO 0xff 10402 #define BIT_WLAN_RPT_TO(x) \ 10403 (((x) & BIT_MASK_WLAN_RPT_TO) << BIT_SHIFT_WLAN_RPT_TO) 10404 #define BIT_GET_WLAN_RPT_TO(x) \ 10405 (((x) >> BIT_SHIFT_WLAN_RPT_TO) & BIT_MASK_WLAN_RPT_TO) 10406 10407 /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ 10408 10409 #define BIT_SHIFT_ISOLATION_CHK 1 10410 #define BIT_MASK_ISOLATION_CHK 0x7fffffffffffffffffffL 10411 #define BIT_ISOLATION_CHK(x) \ 10412 (((x) & BIT_MASK_ISOLATION_CHK) << BIT_SHIFT_ISOLATION_CHK) 10413 #define BIT_GET_ISOLATION_CHK(x) \ 10414 (((x) >> BIT_SHIFT_ISOLATION_CHK) & BIT_MASK_ISOLATION_CHK) 10415 10416 /* 2 REG_BT_ISOLATION_TABLE_REGISTER_REGISTER (Offset 0x0785) */ 10417 10418 #define BIT_ISOLATION_EN BIT(0) 10419 10420 /* 2 REG_BT_INTERRUPT_STATUS_REGISTER (Offset 0x078F) */ 10421 10422 #define BIT_BT_HID_ISR BIT(7) 10423 #define BIT_BT_QUERY_ISR BIT(6) 10424 #define BIT_MAC_NULL_PKT_NOTIFY_ISR BIT(5) 10425 #define BIT_WLAN_RPT_ISR BIT(4) 10426 #define BIT_BT_POWER_ISR BIT(3) 10427 #define BIT_BT_CHANNEL_ISR BIT(2) 10428 #define BIT_BT_SLOT_CHANGE_ISR BIT(1) 10429 #define BIT_BT_PROFILE_ISR BIT(0) 10430 10431 /* 2 REG_BT_TDMA_TIME_REGISTER (Offset 0x0790) */ 10432 10433 #define BIT_SHIFT_BT_TIME 6 10434 #define BIT_MASK_BT_TIME 0x3ffffff 10435 #define BIT_BT_TIME(x) (((x) & BIT_MASK_BT_TIME) << BIT_SHIFT_BT_TIME) 10436 #define BIT_GET_BT_TIME(x) (((x) >> BIT_SHIFT_BT_TIME) & BIT_MASK_BT_TIME) 10437 10438 #define BIT_SHIFT_BT_RPT_SAMPLE_RATE 0 10439 #define BIT_MASK_BT_RPT_SAMPLE_RATE 0x3f 10440 #define BIT_BT_RPT_SAMPLE_RATE(x) \ 10441 (((x) & BIT_MASK_BT_RPT_SAMPLE_RATE) << BIT_SHIFT_BT_RPT_SAMPLE_RATE) 10442 #define BIT_GET_BT_RPT_SAMPLE_RATE(x) \ 10443 (((x) >> BIT_SHIFT_BT_RPT_SAMPLE_RATE) & BIT_MASK_BT_RPT_SAMPLE_RATE) 10444 10445 /* 2 REG_BT_ACT_REGISTER (Offset 0x0794) */ 10446 10447 #define BIT_SHIFT_BT_EISR_EN 16 10448 #define BIT_MASK_BT_EISR_EN 0xff 10449 #define BIT_BT_EISR_EN(x) (((x) & BIT_MASK_BT_EISR_EN) << BIT_SHIFT_BT_EISR_EN) 10450 #define BIT_GET_BT_EISR_EN(x) \ 10451 (((x) >> BIT_SHIFT_BT_EISR_EN) & BIT_MASK_BT_EISR_EN) 10452 10453 #define BIT_BT_ACT_FALLING_ISR BIT(10) 10454 #define BIT_BT_ACT_RISING_ISR BIT(9) 10455 #define BIT_TDMA_TO_ISR BIT(8) 10456 10457 #define BIT_SHIFT_BT_CH 0 10458 #define BIT_MASK_BT_CH 0xff 10459 #define BIT_BT_CH(x) (((x) & BIT_MASK_BT_CH) << BIT_SHIFT_BT_CH) 10460 #define BIT_GET_BT_CH(x) (((x) >> BIT_SHIFT_BT_CH) & BIT_MASK_BT_CH) 10461 10462 /* 2 REG_OBFF_CTRL_BASIC (Offset 0x0798) */ 10463 10464 #define BIT_OBFF_EN_V1 BIT(31) 10465 10466 #define BIT_SHIFT_OBFF_STATE_V1 28 10467 #define BIT_MASK_OBFF_STATE_V1 0x3 10468 #define BIT_OBFF_STATE_V1(x) \ 10469 (((x) & BIT_MASK_OBFF_STATE_V1) << BIT_SHIFT_OBFF_STATE_V1) 10470 #define BIT_GET_OBFF_STATE_V1(x) \ 10471 (((x) >> BIT_SHIFT_OBFF_STATE_V1) & BIT_MASK_OBFF_STATE_V1) 10472 10473 #define BIT_OBFF_ACT_RXDMA_EN BIT(27) 10474 #define BIT_OBFF_BLOCK_INT_EN BIT(26) 10475 #define BIT_OBFF_AUTOACT_EN BIT(25) 10476 #define BIT_OBFF_AUTOIDLE_EN BIT(24) 10477 10478 #define BIT_SHIFT_WAKE_MAX_PLS 20 10479 #define BIT_MASK_WAKE_MAX_PLS 0x7 10480 #define BIT_WAKE_MAX_PLS(x) \ 10481 (((x) & BIT_MASK_WAKE_MAX_PLS) << BIT_SHIFT_WAKE_MAX_PLS) 10482 #define BIT_GET_WAKE_MAX_PLS(x) \ 10483 (((x) >> BIT_SHIFT_WAKE_MAX_PLS) & BIT_MASK_WAKE_MAX_PLS) 10484 10485 #define BIT_SHIFT_WAKE_MIN_PLS 16 10486 #define BIT_MASK_WAKE_MIN_PLS 0x7 10487 #define BIT_WAKE_MIN_PLS(x) \ 10488 (((x) & BIT_MASK_WAKE_MIN_PLS) << BIT_SHIFT_WAKE_MIN_PLS) 10489 #define BIT_GET_WAKE_MIN_PLS(x) \ 10490 (((x) >> BIT_SHIFT_WAKE_MIN_PLS) & BIT_MASK_WAKE_MIN_PLS) 10491 10492 #define BIT_SHIFT_WAKE_MAX_F2F 12 10493 #define BIT_MASK_WAKE_MAX_F2F 0x7 10494 #define BIT_WAKE_MAX_F2F(x) \ 10495 (((x) & BIT_MASK_WAKE_MAX_F2F) << BIT_SHIFT_WAKE_MAX_F2F) 10496 #define BIT_GET_WAKE_MAX_F2F(x) \ 10497 (((x) >> BIT_SHIFT_WAKE_MAX_F2F) & BIT_MASK_WAKE_MAX_F2F) 10498 10499 #define BIT_SHIFT_WAKE_MIN_F2F 8 10500 #define BIT_MASK_WAKE_MIN_F2F 0x7 10501 #define BIT_WAKE_MIN_F2F(x) \ 10502 (((x) & BIT_MASK_WAKE_MIN_F2F) << BIT_SHIFT_WAKE_MIN_F2F) 10503 #define BIT_GET_WAKE_MIN_F2F(x) \ 10504 (((x) >> BIT_SHIFT_WAKE_MIN_F2F) & BIT_MASK_WAKE_MIN_F2F) 10505 10506 #define BIT_APP_CPU_ACT_V1 BIT(3) 10507 #define BIT_APP_OBFF_V1 BIT(2) 10508 #define BIT_APP_IDLE_V1 BIT(1) 10509 #define BIT_APP_INIT_V1 BIT(0) 10510 10511 /* 2 REG_OBFF_CTRL2_TIMER (Offset 0x079C) */ 10512 10513 #define BIT_SHIFT_RX_HIGH_TIMER_IDX 24 10514 #define BIT_MASK_RX_HIGH_TIMER_IDX 0x7 10515 #define BIT_RX_HIGH_TIMER_IDX(x) \ 10516 (((x) & BIT_MASK_RX_HIGH_TIMER_IDX) << BIT_SHIFT_RX_HIGH_TIMER_IDX) 10517 #define BIT_GET_RX_HIGH_TIMER_IDX(x) \ 10518 (((x) >> BIT_SHIFT_RX_HIGH_TIMER_IDX) & BIT_MASK_RX_HIGH_TIMER_IDX) 10519 10520 #define BIT_SHIFT_RX_MED_TIMER_IDX 16 10521 #define BIT_MASK_RX_MED_TIMER_IDX 0x7 10522 #define BIT_RX_MED_TIMER_IDX(x) \ 10523 (((x) & BIT_MASK_RX_MED_TIMER_IDX) << BIT_SHIFT_RX_MED_TIMER_IDX) 10524 #define BIT_GET_RX_MED_TIMER_IDX(x) \ 10525 (((x) >> BIT_SHIFT_RX_MED_TIMER_IDX) & BIT_MASK_RX_MED_TIMER_IDX) 10526 10527 #define BIT_SHIFT_RX_LOW_TIMER_IDX 8 10528 #define BIT_MASK_RX_LOW_TIMER_IDX 0x7 10529 #define BIT_RX_LOW_TIMER_IDX(x) \ 10530 (((x) & BIT_MASK_RX_LOW_TIMER_IDX) << BIT_SHIFT_RX_LOW_TIMER_IDX) 10531 #define BIT_GET_RX_LOW_TIMER_IDX(x) \ 10532 (((x) >> BIT_SHIFT_RX_LOW_TIMER_IDX) & BIT_MASK_RX_LOW_TIMER_IDX) 10533 10534 #define BIT_SHIFT_OBFF_INT_TIMER_IDX 0 10535 #define BIT_MASK_OBFF_INT_TIMER_IDX 0x7 10536 #define BIT_OBFF_INT_TIMER_IDX(x) \ 10537 (((x) & BIT_MASK_OBFF_INT_TIMER_IDX) << BIT_SHIFT_OBFF_INT_TIMER_IDX) 10538 #define BIT_GET_OBFF_INT_TIMER_IDX(x) \ 10539 (((x) >> BIT_SHIFT_OBFF_INT_TIMER_IDX) & BIT_MASK_OBFF_INT_TIMER_IDX) 10540 10541 /* 2 REG_LTR_CTRL_BASIC (Offset 0x07A0) */ 10542 10543 #define BIT_LTR_EN_V1 BIT(31) 10544 #define BIT_LTR_HW_EN_V1 BIT(30) 10545 #define BIT_LRT_ACT_CTS_EN BIT(29) 10546 #define BIT_LTR_ACT_RXPKT_EN BIT(28) 10547 #define BIT_LTR_ACT_RXDMA_EN BIT(27) 10548 #define BIT_LTR_IDLE_NO_SNOOP BIT(26) 10549 #define BIT_SPDUP_MGTPKT BIT(25) 10550 #define BIT_RX_AGG_EN BIT(24) 10551 #define BIT_APP_LTR_ACT BIT(23) 10552 #define BIT_APP_LTR_IDLE BIT(22) 10553 10554 #define BIT_SHIFT_HIGH_RATE_TRIG_SEL 20 10555 #define BIT_MASK_HIGH_RATE_TRIG_SEL 0x3 10556 #define BIT_HIGH_RATE_TRIG_SEL(x) \ 10557 (((x) & BIT_MASK_HIGH_RATE_TRIG_SEL) << BIT_SHIFT_HIGH_RATE_TRIG_SEL) 10558 #define BIT_GET_HIGH_RATE_TRIG_SEL(x) \ 10559 (((x) >> BIT_SHIFT_HIGH_RATE_TRIG_SEL) & BIT_MASK_HIGH_RATE_TRIG_SEL) 10560 10561 #define BIT_SHIFT_MED_RATE_TRIG_SEL 18 10562 #define BIT_MASK_MED_RATE_TRIG_SEL 0x3 10563 #define BIT_MED_RATE_TRIG_SEL(x) \ 10564 (((x) & BIT_MASK_MED_RATE_TRIG_SEL) << BIT_SHIFT_MED_RATE_TRIG_SEL) 10565 #define BIT_GET_MED_RATE_TRIG_SEL(x) \ 10566 (((x) >> BIT_SHIFT_MED_RATE_TRIG_SEL) & BIT_MASK_MED_RATE_TRIG_SEL) 10567 10568 #define BIT_SHIFT_LOW_RATE_TRIG_SEL 16 10569 #define BIT_MASK_LOW_RATE_TRIG_SEL 0x3 10570 #define BIT_LOW_RATE_TRIG_SEL(x) \ 10571 (((x) & BIT_MASK_LOW_RATE_TRIG_SEL) << BIT_SHIFT_LOW_RATE_TRIG_SEL) 10572 #define BIT_GET_LOW_RATE_TRIG_SEL(x) \ 10573 (((x) >> BIT_SHIFT_LOW_RATE_TRIG_SEL) & BIT_MASK_LOW_RATE_TRIG_SEL) 10574 10575 #define BIT_SHIFT_HIGH_RATE_BD_IDX 8 10576 #define BIT_MASK_HIGH_RATE_BD_IDX 0x7f 10577 #define BIT_HIGH_RATE_BD_IDX(x) \ 10578 (((x) & BIT_MASK_HIGH_RATE_BD_IDX) << BIT_SHIFT_HIGH_RATE_BD_IDX) 10579 #define BIT_GET_HIGH_RATE_BD_IDX(x) \ 10580 (((x) >> BIT_SHIFT_HIGH_RATE_BD_IDX) & BIT_MASK_HIGH_RATE_BD_IDX) 10581 10582 #define BIT_SHIFT_LOW_RATE_BD_IDX 0 10583 #define BIT_MASK_LOW_RATE_BD_IDX 0x7f 10584 #define BIT_LOW_RATE_BD_IDX(x) \ 10585 (((x) & BIT_MASK_LOW_RATE_BD_IDX) << BIT_SHIFT_LOW_RATE_BD_IDX) 10586 #define BIT_GET_LOW_RATE_BD_IDX(x) \ 10587 (((x) >> BIT_SHIFT_LOW_RATE_BD_IDX) & BIT_MASK_LOW_RATE_BD_IDX) 10588 10589 /* 2 REG_LTR_CTRL2_TIMER_THRESHOLD (Offset 0x07A4) */ 10590 10591 #define BIT_SHIFT_RX_EMPTY_TIMER_IDX 24 10592 #define BIT_MASK_RX_EMPTY_TIMER_IDX 0x7 10593 #define BIT_RX_EMPTY_TIMER_IDX(x) \ 10594 (((x) & BIT_MASK_RX_EMPTY_TIMER_IDX) << BIT_SHIFT_RX_EMPTY_TIMER_IDX) 10595 #define BIT_GET_RX_EMPTY_TIMER_IDX(x) \ 10596 (((x) >> BIT_SHIFT_RX_EMPTY_TIMER_IDX) & BIT_MASK_RX_EMPTY_TIMER_IDX) 10597 10598 #define BIT_SHIFT_RX_AFULL_TH_IDX 20 10599 #define BIT_MASK_RX_AFULL_TH_IDX 0x7 10600 #define BIT_RX_AFULL_TH_IDX(x) \ 10601 (((x) & BIT_MASK_RX_AFULL_TH_IDX) << BIT_SHIFT_RX_AFULL_TH_IDX) 10602 #define BIT_GET_RX_AFULL_TH_IDX(x) \ 10603 (((x) >> BIT_SHIFT_RX_AFULL_TH_IDX) & BIT_MASK_RX_AFULL_TH_IDX) 10604 10605 #define BIT_SHIFT_RX_HIGH_TH_IDX 16 10606 #define BIT_MASK_RX_HIGH_TH_IDX 0x7 10607 #define BIT_RX_HIGH_TH_IDX(x) \ 10608 (((x) & BIT_MASK_RX_HIGH_TH_IDX) << BIT_SHIFT_RX_HIGH_TH_IDX) 10609 #define BIT_GET_RX_HIGH_TH_IDX(x) \ 10610 (((x) >> BIT_SHIFT_RX_HIGH_TH_IDX) & BIT_MASK_RX_HIGH_TH_IDX) 10611 10612 #define BIT_SHIFT_RX_MED_TH_IDX 12 10613 #define BIT_MASK_RX_MED_TH_IDX 0x7 10614 #define BIT_RX_MED_TH_IDX(x) \ 10615 (((x) & BIT_MASK_RX_MED_TH_IDX) << BIT_SHIFT_RX_MED_TH_IDX) 10616 #define BIT_GET_RX_MED_TH_IDX(x) \ 10617 (((x) >> BIT_SHIFT_RX_MED_TH_IDX) & BIT_MASK_RX_MED_TH_IDX) 10618 10619 #define BIT_SHIFT_RX_LOW_TH_IDX 8 10620 #define BIT_MASK_RX_LOW_TH_IDX 0x7 10621 #define BIT_RX_LOW_TH_IDX(x) \ 10622 (((x) & BIT_MASK_RX_LOW_TH_IDX) << BIT_SHIFT_RX_LOW_TH_IDX) 10623 #define BIT_GET_RX_LOW_TH_IDX(x) \ 10624 (((x) >> BIT_SHIFT_RX_LOW_TH_IDX) & BIT_MASK_RX_LOW_TH_IDX) 10625 10626 #define BIT_SHIFT_LTR_SPACE_IDX 4 10627 #define BIT_MASK_LTR_SPACE_IDX 0x3 10628 #define BIT_LTR_SPACE_IDX(x) \ 10629 (((x) & BIT_MASK_LTR_SPACE_IDX) << BIT_SHIFT_LTR_SPACE_IDX) 10630 #define BIT_GET_LTR_SPACE_IDX(x) \ 10631 (((x) >> BIT_SHIFT_LTR_SPACE_IDX) & BIT_MASK_LTR_SPACE_IDX) 10632 10633 #define BIT_SHIFT_LTR_IDLE_TIMER_IDX 0 10634 #define BIT_MASK_LTR_IDLE_TIMER_IDX 0x7 10635 #define BIT_LTR_IDLE_TIMER_IDX(x) \ 10636 (((x) & BIT_MASK_LTR_IDLE_TIMER_IDX) << BIT_SHIFT_LTR_IDLE_TIMER_IDX) 10637 #define BIT_GET_LTR_IDLE_TIMER_IDX(x) \ 10638 (((x) >> BIT_SHIFT_LTR_IDLE_TIMER_IDX) & BIT_MASK_LTR_IDLE_TIMER_IDX) 10639 10640 /* 2 REG_LTR_IDLE_LATENCY_V1 (Offset 0x07A8) */ 10641 10642 #define BIT_SHIFT_LTR_IDLE_L 0 10643 #define BIT_MASK_LTR_IDLE_L 0xffffffffL 10644 #define BIT_LTR_IDLE_L(x) (((x) & BIT_MASK_LTR_IDLE_L) << BIT_SHIFT_LTR_IDLE_L) 10645 #define BIT_GET_LTR_IDLE_L(x) \ 10646 (((x) >> BIT_SHIFT_LTR_IDLE_L) & BIT_MASK_LTR_IDLE_L) 10647 10648 /* 2 REG_LTR_ACTIVE_LATENCY_V1 (Offset 0x07AC) */ 10649 10650 #define BIT_SHIFT_LTR_ACT_L 0 10651 #define BIT_MASK_LTR_ACT_L 0xffffffffL 10652 #define BIT_LTR_ACT_L(x) (((x) & BIT_MASK_LTR_ACT_L) << BIT_SHIFT_LTR_ACT_L) 10653 #define BIT_GET_LTR_ACT_L(x) (((x) >> BIT_SHIFT_LTR_ACT_L) & BIT_MASK_LTR_ACT_L) 10654 10655 /* 2 REG_ANTENNA_TRAINING_CONTROL_REGISTER (Offset 0x07B0) */ 10656 10657 #define BIT_APPEND_MACID_IN_RESP_EN BIT(50) 10658 #define BIT_ADDR2_MATCH_EN BIT(49) 10659 #define BIT_ANTTRN_EN BIT(48) 10660 10661 #define BIT_SHIFT_TRAIN_STA_ADDR 0 10662 #define BIT_MASK_TRAIN_STA_ADDR 0xffffffffffffL 10663 #define BIT_TRAIN_STA_ADDR(x) \ 10664 (((x) & BIT_MASK_TRAIN_STA_ADDR) << BIT_SHIFT_TRAIN_STA_ADDR) 10665 #define BIT_GET_TRAIN_STA_ADDR(x) \ 10666 (((x) >> BIT_SHIFT_TRAIN_STA_ADDR) & BIT_MASK_TRAIN_STA_ADDR) 10667 10668 /* 2 REG_WMAC_PKTCNT_RWD (Offset 0x07B8) */ 10669 10670 #define BIT_SHIFT_PKTCNT_BSSIDMAP 4 10671 #define BIT_MASK_PKTCNT_BSSIDMAP 0xf 10672 #define BIT_PKTCNT_BSSIDMAP(x) \ 10673 (((x) & BIT_MASK_PKTCNT_BSSIDMAP) << BIT_SHIFT_PKTCNT_BSSIDMAP) 10674 #define BIT_GET_PKTCNT_BSSIDMAP(x) \ 10675 (((x) >> BIT_SHIFT_PKTCNT_BSSIDMAP) & BIT_MASK_PKTCNT_BSSIDMAP) 10676 10677 #define BIT_PKTCNT_CNTRST BIT(1) 10678 #define BIT_PKTCNT_CNTEN BIT(0) 10679 10680 /* 2 REG_WMAC_PKTCNT_CTRL (Offset 0x07BC) */ 10681 10682 #define BIT_WMAC_PKTCNT_TRST BIT(9) 10683 #define BIT_WMAC_PKTCNT_FEN BIT(8) 10684 10685 #define BIT_SHIFT_WMAC_PKTCNT_CFGAD 0 10686 #define BIT_MASK_WMAC_PKTCNT_CFGAD 0xff 10687 #define BIT_WMAC_PKTCNT_CFGAD(x) \ 10688 (((x) & BIT_MASK_WMAC_PKTCNT_CFGAD) << BIT_SHIFT_WMAC_PKTCNT_CFGAD) 10689 #define BIT_GET_WMAC_PKTCNT_CFGAD(x) \ 10690 (((x) >> BIT_SHIFT_WMAC_PKTCNT_CFGAD) & BIT_MASK_WMAC_PKTCNT_CFGAD) 10691 10692 /* 2 REG_IQ_DUMP (Offset 0x07C0) */ 10693 10694 #define BIT_SHIFT_R_WMAC_MATCH_REF_MAC (64 & CPU_OPT_WIDTH) 10695 #define BIT_MASK_R_WMAC_MATCH_REF_MAC 0xffffffffL 10696 #define BIT_R_WMAC_MATCH_REF_MAC(x) \ 10697 (((x) & BIT_MASK_R_WMAC_MATCH_REF_MAC) \ 10698 << BIT_SHIFT_R_WMAC_MATCH_REF_MAC) 10699 #define BIT_GET_R_WMAC_MATCH_REF_MAC(x) \ 10700 (((x) >> BIT_SHIFT_R_WMAC_MATCH_REF_MAC) & \ 10701 BIT_MASK_R_WMAC_MATCH_REF_MAC) 10702 10703 #define BIT_SHIFT_R_WMAC_RX_FIL_LEN (64 & CPU_OPT_WIDTH) 10704 #define BIT_MASK_R_WMAC_RX_FIL_LEN 0xffff 10705 #define BIT_R_WMAC_RX_FIL_LEN(x) \ 10706 (((x) & BIT_MASK_R_WMAC_RX_FIL_LEN) << BIT_SHIFT_R_WMAC_RX_FIL_LEN) 10707 #define BIT_GET_R_WMAC_RX_FIL_LEN(x) \ 10708 (((x) >> BIT_SHIFT_R_WMAC_RX_FIL_LEN) & BIT_MASK_R_WMAC_RX_FIL_LEN) 10709 10710 #define BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH (56 & CPU_OPT_WIDTH) 10711 #define BIT_MASK_R_WMAC_RXFIFO_FULL_TH 0xff 10712 #define BIT_R_WMAC_RXFIFO_FULL_TH(x) \ 10713 (((x) & BIT_MASK_R_WMAC_RXFIFO_FULL_TH) \ 10714 << BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) 10715 #define BIT_GET_R_WMAC_RXFIFO_FULL_TH(x) \ 10716 (((x) >> BIT_SHIFT_R_WMAC_RXFIFO_FULL_TH) & \ 10717 BIT_MASK_R_WMAC_RXFIFO_FULL_TH) 10718 10719 #define BIT_R_WMAC_SRCH_TXRPT_TYPE BIT(51) 10720 #define BIT_R_WMAC_NDP_RST BIT(50) 10721 #define BIT_R_WMAC_POWINT_EN BIT(49) 10722 #define BIT_R_WMAC_SRCH_TXRPT_PERPKT BIT(48) 10723 #define BIT_R_WMAC_SRCH_TXRPT_MID BIT(47) 10724 #define BIT_R_WMAC_PFIN_TOEN BIT(46) 10725 #define BIT_R_WMAC_FIL_SECERR BIT(45) 10726 #define BIT_R_WMAC_FIL_CTLPKTLEN BIT(44) 10727 #define BIT_R_WMAC_FIL_FCTYPE BIT(43) 10728 #define BIT_R_WMAC_FIL_FCPROVER BIT(42) 10729 #define BIT_R_WMAC_PHYSTS_SNIF BIT(41) 10730 #define BIT_R_WMAC_PHYSTS_PLCP BIT(40) 10731 #define BIT_R_MAC_TCR_VBONF_RD BIT(39) 10732 #define BIT_R_WMAC_TCR_MPAR_NDP BIT(38) 10733 #define BIT_R_WMAC_NDP_FILTER BIT(37) 10734 #define BIT_R_WMAC_RXLEN_SEL BIT(36) 10735 #define BIT_R_WMAC_RXLEN_SEL1 BIT(35) 10736 #define BIT_R_OFDM_FILTER BIT(34) 10737 #define BIT_R_WMAC_CHK_OFDM_LEN BIT(33) 10738 10739 #define BIT_SHIFT_R_WMAC_MASK_LA_MAC (32 & CPU_OPT_WIDTH) 10740 #define BIT_MASK_R_WMAC_MASK_LA_MAC 0xffffffffL 10741 #define BIT_R_WMAC_MASK_LA_MAC(x) \ 10742 (((x) & BIT_MASK_R_WMAC_MASK_LA_MAC) << BIT_SHIFT_R_WMAC_MASK_LA_MAC) 10743 #define BIT_GET_R_WMAC_MASK_LA_MAC(x) \ 10744 (((x) >> BIT_SHIFT_R_WMAC_MASK_LA_MAC) & BIT_MASK_R_WMAC_MASK_LA_MAC) 10745 10746 #define BIT_R_WMAC_CHK_CCK_LEN BIT(32) 10747 10748 /* 2 REG_IQ_DUMP (Offset 0x07C0) */ 10749 10750 #define BIT_SHIFT_R_OFDM_LEN 26 10751 #define BIT_MASK_R_OFDM_LEN 0x3f 10752 #define BIT_R_OFDM_LEN(x) (((x) & BIT_MASK_R_OFDM_LEN) << BIT_SHIFT_R_OFDM_LEN) 10753 #define BIT_GET_R_OFDM_LEN(x) \ 10754 (((x) >> BIT_SHIFT_R_OFDM_LEN) & BIT_MASK_R_OFDM_LEN) 10755 10756 #define BIT_SHIFT_DUMP_OK_ADDR 15 10757 #define BIT_MASK_DUMP_OK_ADDR 0x1ffff 10758 #define BIT_DUMP_OK_ADDR(x) \ 10759 (((x) & BIT_MASK_DUMP_OK_ADDR) << BIT_SHIFT_DUMP_OK_ADDR) 10760 #define BIT_GET_DUMP_OK_ADDR(x) \ 10761 (((x) >> BIT_SHIFT_DUMP_OK_ADDR) & BIT_MASK_DUMP_OK_ADDR) 10762 10763 #define BIT_SHIFT_R_TRIG_TIME_SEL 8 10764 #define BIT_MASK_R_TRIG_TIME_SEL 0x7f 10765 #define BIT_R_TRIG_TIME_SEL(x) \ 10766 (((x) & BIT_MASK_R_TRIG_TIME_SEL) << BIT_SHIFT_R_TRIG_TIME_SEL) 10767 #define BIT_GET_R_TRIG_TIME_SEL(x) \ 10768 (((x) >> BIT_SHIFT_R_TRIG_TIME_SEL) & BIT_MASK_R_TRIG_TIME_SEL) 10769 10770 #define BIT_SHIFT_R_MAC_TRIG_SEL 6 10771 #define BIT_MASK_R_MAC_TRIG_SEL 0x3 10772 #define BIT_R_MAC_TRIG_SEL(x) \ 10773 (((x) & BIT_MASK_R_MAC_TRIG_SEL) << BIT_SHIFT_R_MAC_TRIG_SEL) 10774 #define BIT_GET_R_MAC_TRIG_SEL(x) \ 10775 (((x) >> BIT_SHIFT_R_MAC_TRIG_SEL) & BIT_MASK_R_MAC_TRIG_SEL) 10776 10777 #define BIT_MAC_TRIG_REG BIT(5) 10778 10779 #define BIT_SHIFT_R_LEVEL_PULSE_SEL 3 10780 #define BIT_MASK_R_LEVEL_PULSE_SEL 0x3 10781 #define BIT_R_LEVEL_PULSE_SEL(x) \ 10782 (((x) & BIT_MASK_R_LEVEL_PULSE_SEL) << BIT_SHIFT_R_LEVEL_PULSE_SEL) 10783 #define BIT_GET_R_LEVEL_PULSE_SEL(x) \ 10784 (((x) >> BIT_SHIFT_R_LEVEL_PULSE_SEL) & BIT_MASK_R_LEVEL_PULSE_SEL) 10785 10786 #define BIT_EN_LA_MAC BIT(2) 10787 #define BIT_R_EN_IQDUMP BIT(1) 10788 #define BIT_R_IQDATA_DUMP BIT(0) 10789 10790 #define BIT_SHIFT_R_CCK_LEN 0 10791 #define BIT_MASK_R_CCK_LEN 0xffff 10792 #define BIT_R_CCK_LEN(x) (((x) & BIT_MASK_R_CCK_LEN) << BIT_SHIFT_R_CCK_LEN) 10793 #define BIT_GET_R_CCK_LEN(x) (((x) >> BIT_SHIFT_R_CCK_LEN) & BIT_MASK_R_CCK_LEN) 10794 10795 /* 2 REG_WMAC_FTM_CTL (Offset 0x07CC) */ 10796 10797 #define BIT_RXFTM_TXACK_SC BIT(6) 10798 #define BIT_RXFTM_TXACK_BW BIT(5) 10799 #define BIT_RXFTM_EN BIT(3) 10800 #define BIT_RXFTMREQ_BYDRV BIT(2) 10801 #define BIT_RXFTMREQ_EN BIT(1) 10802 #define BIT_FTM_EN BIT(0) 10803 10804 /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10805 10806 #define BIT_R_WMAC_MHRDDY_LATCH BIT(14) 10807 10808 /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10809 10810 #define BIT_R_WMAC_MHRDDY_CLR BIT(13) 10811 10812 /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10813 10814 #define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY1 BIT(12) 10815 10816 /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10817 10818 #define BIT_WMAC_DIS_VHT_PLCP_CHK_MU BIT(11) 10819 10820 /* 2 REG_RX_FILTER_FUNCTION (Offset 0x07DA) */ 10821 10822 #define BIT_R_CHK_DELIMIT_LEN BIT(10) 10823 #define BIT_R_REAPTER_ADDR_MATCH BIT(9) 10824 #define BIT_R_RXPKTCTL_FSM_BASED_MPDURDY BIT(8) 10825 #define BIT_R_LATCH_MACHRDY BIT(7) 10826 #define BIT_R_WMAC_RXFIL_REND BIT(6) 10827 #define BIT_R_WMAC_MPDURDY_CLR BIT(5) 10828 #define BIT_R_WMAC_CLRRXSEC BIT(4) 10829 #define BIT_R_WMAC_RXFIL_RDEL BIT(3) 10830 #define BIT_R_WMAC_RXFIL_FCSE BIT(2) 10831 #define BIT_R_WMAC_RXFIL_MESH_DEL BIT(1) 10832 #define BIT_R_WMAC_RXFIL_MASKM BIT(0) 10833 10834 /* 2 REG_NDP_SIG (Offset 0x07E0) */ 10835 10836 #define BIT_SHIFT_R_WMAC_TXNDP_SIGB 0 10837 #define BIT_MASK_R_WMAC_TXNDP_SIGB 0x1fffff 10838 #define BIT_R_WMAC_TXNDP_SIGB(x) \ 10839 (((x) & BIT_MASK_R_WMAC_TXNDP_SIGB) << BIT_SHIFT_R_WMAC_TXNDP_SIGB) 10840 #define BIT_GET_R_WMAC_TXNDP_SIGB(x) \ 10841 (((x) >> BIT_SHIFT_R_WMAC_TXNDP_SIGB) & BIT_MASK_R_WMAC_TXNDP_SIGB) 10842 10843 /* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ 10844 10845 #define BIT_SHIFT_R_MAC_DEBUG (32 & CPU_OPT_WIDTH) 10846 #define BIT_MASK_R_MAC_DEBUG 0xffffffffL 10847 #define BIT_R_MAC_DEBUG(x) \ 10848 (((x) & BIT_MASK_R_MAC_DEBUG) << BIT_SHIFT_R_MAC_DEBUG) 10849 #define BIT_GET_R_MAC_DEBUG(x) \ 10850 (((x) >> BIT_SHIFT_R_MAC_DEBUG) & BIT_MASK_R_MAC_DEBUG) 10851 10852 /* 2 REG_TXCMD_INFO_FOR_RSP_PKT (Offset 0x07E4) */ 10853 10854 #define BIT_SHIFT_R_MAC_DBG_SHIFT 8 10855 #define BIT_MASK_R_MAC_DBG_SHIFT 0x7 10856 #define BIT_R_MAC_DBG_SHIFT(x) \ 10857 (((x) & BIT_MASK_R_MAC_DBG_SHIFT) << BIT_SHIFT_R_MAC_DBG_SHIFT) 10858 #define BIT_GET_R_MAC_DBG_SHIFT(x) \ 10859 (((x) >> BIT_SHIFT_R_MAC_DBG_SHIFT) & BIT_MASK_R_MAC_DBG_SHIFT) 10860 10861 #define BIT_SHIFT_R_MAC_DBG_SEL 0 10862 #define BIT_MASK_R_MAC_DBG_SEL 0x3 10863 #define BIT_R_MAC_DBG_SEL(x) \ 10864 (((x) & BIT_MASK_R_MAC_DBG_SEL) << BIT_SHIFT_R_MAC_DBG_SEL) 10865 #define BIT_GET_R_MAC_DBG_SEL(x) \ 10866 (((x) >> BIT_SHIFT_R_MAC_DBG_SEL) & BIT_MASK_R_MAC_DBG_SEL) 10867 10868 /* 2 REG_SYS_CFG3 (Offset 0x1000) */ 10869 10870 #define BIT_PWC_MA33V BIT(15) 10871 10872 /* 2 REG_SYS_CFG3 (Offset 0x1000) */ 10873 10874 #define BIT_PWC_MA12V BIT(14) 10875 #define BIT_PWC_MD12V BIT(13) 10876 #define BIT_PWC_PD12V BIT(12) 10877 #define BIT_PWC_UD12V BIT(11) 10878 #define BIT_ISO_MA2MD BIT(1) 10879 10880 /* 2 REG_SYS_CFG5 (Offset 0x1070) */ 10881 10882 #define BIT_LPS_STATUS BIT(3) 10883 #define BIT_HCI_TXDMA_BUSY BIT(2) 10884 #define BIT_HCI_TXDMA_ALLOW BIT(1) 10885 #define BIT_FW_CTRL_HCI_TXDMA_EN BIT(0) 10886 10887 /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ 10888 10889 #define BIT_WDT_OPT_IOWRAPPER BIT(19) 10890 10891 /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ 10892 10893 #define BIT_ANA_PORT_IDLE BIT(18) 10894 #define BIT_MAC_PORT_IDLE BIT(17) 10895 #define BIT_WL_PLATFORM_RST BIT(16) 10896 #define BIT_WL_SECURITY_CLK BIT(15) 10897 10898 /* 2 REG_CPU_DMEM_CON (Offset 0x1080) */ 10899 10900 #define BIT_SHIFT_CPU_DMEM_CON 0 10901 #define BIT_MASK_CPU_DMEM_CON 0xff 10902 #define BIT_CPU_DMEM_CON(x) \ 10903 (((x) & BIT_MASK_CPU_DMEM_CON) << BIT_SHIFT_CPU_DMEM_CON) 10904 #define BIT_GET_CPU_DMEM_CON(x) \ 10905 (((x) >> BIT_SHIFT_CPU_DMEM_CON) & BIT_MASK_CPU_DMEM_CON) 10906 10907 /* 2 REG_BOOT_REASON (Offset 0x1088) */ 10908 10909 #define BIT_SHIFT_BOOT_REASON 0 10910 #define BIT_MASK_BOOT_REASON 0x7 10911 #define BIT_BOOT_REASON(x) \ 10912 (((x) & BIT_MASK_BOOT_REASON) << BIT_SHIFT_BOOT_REASON) 10913 #define BIT_GET_BOOT_REASON(x) \ 10914 (((x) >> BIT_SHIFT_BOOT_REASON) & BIT_MASK_BOOT_REASON) 10915 10916 /* 2 REG_NFCPAD_CTRL (Offset 0x10A8) */ 10917 10918 #define BIT_PAD_SHUTDW BIT(18) 10919 #define BIT_SYSON_NFC_PAD BIT(17) 10920 #define BIT_NFC_INT_PAD_CTRL BIT(16) 10921 #define BIT_NFC_RFDIS_PAD_CTRL BIT(15) 10922 #define BIT_NFC_CLK_PAD_CTRL BIT(14) 10923 #define BIT_NFC_DATA_PAD_CTRL BIT(13) 10924 #define BIT_NFC_PAD_PULL_CTRL BIT(12) 10925 10926 #define BIT_SHIFT_NFCPAD_IO_SEL 8 10927 #define BIT_MASK_NFCPAD_IO_SEL 0xf 10928 #define BIT_NFCPAD_IO_SEL(x) \ 10929 (((x) & BIT_MASK_NFCPAD_IO_SEL) << BIT_SHIFT_NFCPAD_IO_SEL) 10930 #define BIT_GET_NFCPAD_IO_SEL(x) \ 10931 (((x) >> BIT_SHIFT_NFCPAD_IO_SEL) & BIT_MASK_NFCPAD_IO_SEL) 10932 10933 #define BIT_SHIFT_NFCPAD_OUT 4 10934 #define BIT_MASK_NFCPAD_OUT 0xf 10935 #define BIT_NFCPAD_OUT(x) (((x) & BIT_MASK_NFCPAD_OUT) << BIT_SHIFT_NFCPAD_OUT) 10936 #define BIT_GET_NFCPAD_OUT(x) \ 10937 (((x) >> BIT_SHIFT_NFCPAD_OUT) & BIT_MASK_NFCPAD_OUT) 10938 10939 #define BIT_SHIFT_NFCPAD_IN 0 10940 #define BIT_MASK_NFCPAD_IN 0xf 10941 #define BIT_NFCPAD_IN(x) (((x) & BIT_MASK_NFCPAD_IN) << BIT_SHIFT_NFCPAD_IN) 10942 #define BIT_GET_NFCPAD_IN(x) (((x) >> BIT_SHIFT_NFCPAD_IN) & BIT_MASK_NFCPAD_IN) 10943 10944 /* 2 REG_HIMR2 (Offset 0x10B0) */ 10945 10946 #define BIT_BCNDMAINT_P4_MSK BIT(31) 10947 #define BIT_BCNDMAINT_P3_MSK BIT(30) 10948 #define BIT_BCNDMAINT_P2_MSK BIT(29) 10949 #define BIT_BCNDMAINT_P1_MSK BIT(28) 10950 #define BIT_ATIMEND7_MSK BIT(22) 10951 #define BIT_ATIMEND6_MSK BIT(21) 10952 #define BIT_ATIMEND5_MSK BIT(20) 10953 #define BIT_ATIMEND4_MSK BIT(19) 10954 #define BIT_ATIMEND3_MSK BIT(18) 10955 #define BIT_ATIMEND2_MSK BIT(17) 10956 #define BIT_ATIMEND1_MSK BIT(16) 10957 #define BIT_TXBCN7OK_MSK BIT(14) 10958 #define BIT_TXBCN6OK_MSK BIT(13) 10959 #define BIT_TXBCN5OK_MSK BIT(12) 10960 #define BIT_TXBCN4OK_MSK BIT(11) 10961 #define BIT_TXBCN3OK_MSK BIT(10) 10962 #define BIT_TXBCN2OK_MSK BIT(9) 10963 #define BIT_TXBCN1OK_MSK_V1 BIT(8) 10964 #define BIT_TXBCN7ERR_MSK BIT(6) 10965 #define BIT_TXBCN6ERR_MSK BIT(5) 10966 #define BIT_TXBCN5ERR_MSK BIT(4) 10967 #define BIT_TXBCN4ERR_MSK BIT(3) 10968 #define BIT_TXBCN3ERR_MSK BIT(2) 10969 #define BIT_TXBCN2ERR_MSK BIT(1) 10970 #define BIT_TXBCN1ERR_MSK_V1 BIT(0) 10971 10972 /* 2 REG_HISR2 (Offset 0x10B4) */ 10973 10974 #define BIT_BCNDMAINT_P4 BIT(31) 10975 #define BIT_BCNDMAINT_P3 BIT(30) 10976 #define BIT_BCNDMAINT_P2 BIT(29) 10977 #define BIT_BCNDMAINT_P1 BIT(28) 10978 #define BIT_ATIMEND7 BIT(22) 10979 #define BIT_ATIMEND6 BIT(21) 10980 #define BIT_ATIMEND5 BIT(20) 10981 #define BIT_ATIMEND4 BIT(19) 10982 #define BIT_ATIMEND3 BIT(18) 10983 #define BIT_ATIMEND2 BIT(17) 10984 #define BIT_ATIMEND1 BIT(16) 10985 #define BIT_TXBCN7OK BIT(14) 10986 #define BIT_TXBCN6OK BIT(13) 10987 #define BIT_TXBCN5OK BIT(12) 10988 #define BIT_TXBCN4OK BIT(11) 10989 #define BIT_TXBCN3OK BIT(10) 10990 #define BIT_TXBCN2OK BIT(9) 10991 #define BIT_TXBCN1OK BIT(8) 10992 #define BIT_TXBCN7ERR BIT(6) 10993 #define BIT_TXBCN6ERR BIT(5) 10994 #define BIT_TXBCN5ERR BIT(4) 10995 #define BIT_TXBCN4ERR BIT(3) 10996 #define BIT_TXBCN3ERR BIT(2) 10997 #define BIT_TXBCN2ERR BIT(1) 10998 #define BIT_TXBCN1ERR BIT(0) 10999 11000 /* 2 REG_HIMR3 (Offset 0x10B8) */ 11001 11002 #define BIT_WDT_PLATFORM_INT_MSK BIT(18) 11003 #define BIT_WDT_CPU_INT_MSK BIT(17) 11004 11005 /* 2 REG_HIMR3 (Offset 0x10B8) */ 11006 11007 #define BIT_SETH2CDOK_MASK BIT(16) 11008 #define BIT_H2C_CMD_FULL_MASK BIT(15) 11009 #define BIT_PWR_INT_127_MASK BIT(14) 11010 #define BIT_TXSHORTCUT_TXDESUPDATEOK_MASK BIT(13) 11011 #define BIT_TXSHORTCUT_BKUPDATEOK_MASK BIT(12) 11012 #define BIT_TXSHORTCUT_BEUPDATEOK_MASK BIT(11) 11013 #define BIT_TXSHORTCUT_VIUPDATEOK_MAS BIT(10) 11014 #define BIT_TXSHORTCUT_VOUPDATEOK_MASK BIT(9) 11015 #define BIT_PWR_INT_127_MASK_V1 BIT(8) 11016 #define BIT_PWR_INT_126TO96_MASK BIT(7) 11017 #define BIT_PWR_INT_95TO64_MASK BIT(6) 11018 #define BIT_PWR_INT_63TO32_MASK BIT(5) 11019 #define BIT_PWR_INT_31TO0_MASK BIT(4) 11020 #define BIT_DDMA0_LP_INT_MSK BIT(1) 11021 #define BIT_DDMA0_HP_INT_MSK BIT(0) 11022 11023 /* 2 REG_HISR3 (Offset 0x10BC) */ 11024 11025 #define BIT_WDT_PLATFORM_INT BIT(18) 11026 #define BIT_WDT_CPU_INT BIT(17) 11027 11028 /* 2 REG_HISR3 (Offset 0x10BC) */ 11029 11030 #define BIT_SETH2CDOK BIT(16) 11031 #define BIT_H2C_CMD_FULL BIT(15) 11032 #define BIT_PWR_INT_127 BIT(14) 11033 #define BIT_TXSHORTCUT_TXDESUPDATEOK BIT(13) 11034 #define BIT_TXSHORTCUT_BKUPDATEOK BIT(12) 11035 #define BIT_TXSHORTCUT_BEUPDATEOK BIT(11) 11036 #define BIT_TXSHORTCUT_VIUPDATEOK BIT(10) 11037 #define BIT_TXSHORTCUT_VOUPDATEOK BIT(9) 11038 #define BIT_PWR_INT_127_V1 BIT(8) 11039 #define BIT_PWR_INT_126TO96 BIT(7) 11040 #define BIT_PWR_INT_95TO64 BIT(6) 11041 #define BIT_PWR_INT_63TO32 BIT(5) 11042 #define BIT_PWR_INT_31TO0 BIT(4) 11043 #define BIT_DDMA0_LP_INT BIT(1) 11044 #define BIT_DDMA0_HP_INT BIT(0) 11045 11046 /* 2 REG_SW_MDIO (Offset 0x10C0) */ 11047 11048 #define BIT_DIS_TIMEOUT_IO BIT(24) 11049 11050 /* 2 REG_SW_FLUSH (Offset 0x10C4) */ 11051 11052 #define BIT_FLUSH_HOLDN_EN BIT(25) 11053 #define BIT_FLUSH_WR_EN BIT(24) 11054 #define BIT_SW_FLASH_CONTROL BIT(23) 11055 #define BIT_SW_FLASH_WEN_E BIT(19) 11056 #define BIT_SW_FLASH_HOLDN_E BIT(18) 11057 #define BIT_SW_FLASH_SO_E BIT(17) 11058 #define BIT_SW_FLASH_SI_E BIT(16) 11059 #define BIT_SW_FLASH_SK_O BIT(13) 11060 #define BIT_SW_FLASH_CEN_O BIT(12) 11061 #define BIT_SW_FLASH_WEN_O BIT(11) 11062 #define BIT_SW_FLASH_HOLDN_O BIT(10) 11063 #define BIT_SW_FLASH_SO_O BIT(9) 11064 #define BIT_SW_FLASH_SI_O BIT(8) 11065 #define BIT_SW_FLASH_WEN_I BIT(3) 11066 #define BIT_SW_FLASH_HOLDN_I BIT(2) 11067 #define BIT_SW_FLASH_SO_I BIT(1) 11068 #define BIT_SW_FLASH_SI_I BIT(0) 11069 11070 /* 2 REG_H2C_PKT_READADDR (Offset 0x10D0) */ 11071 11072 #define BIT_SHIFT_H2C_PKT_READADDR 0 11073 #define BIT_MASK_H2C_PKT_READADDR 0x3ffff 11074 #define BIT_H2C_PKT_READADDR(x) \ 11075 (((x) & BIT_MASK_H2C_PKT_READADDR) << BIT_SHIFT_H2C_PKT_READADDR) 11076 #define BIT_GET_H2C_PKT_READADDR(x) \ 11077 (((x) >> BIT_SHIFT_H2C_PKT_READADDR) & BIT_MASK_H2C_PKT_READADDR) 11078 11079 /* 2 REG_H2C_PKT_WRITEADDR (Offset 0x10D4) */ 11080 11081 #define BIT_SHIFT_H2C_PKT_WRITEADDR 0 11082 #define BIT_MASK_H2C_PKT_WRITEADDR 0x3ffff 11083 #define BIT_H2C_PKT_WRITEADDR(x) \ 11084 (((x) & BIT_MASK_H2C_PKT_WRITEADDR) << BIT_SHIFT_H2C_PKT_WRITEADDR) 11085 #define BIT_GET_H2C_PKT_WRITEADDR(x) \ 11086 (((x) >> BIT_SHIFT_H2C_PKT_WRITEADDR) & BIT_MASK_H2C_PKT_WRITEADDR) 11087 11088 /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ 11089 11090 #define BIT_MEM_BB_SD BIT(17) 11091 #define BIT_MEM_BB_DS BIT(16) 11092 #define BIT_MEM_BT_DS BIT(10) 11093 #define BIT_MEM_SDIO_LS BIT(9) 11094 #define BIT_MEM_SDIO_DS BIT(8) 11095 #define BIT_MEM_USB_LS BIT(7) 11096 #define BIT_MEM_USB_DS BIT(6) 11097 #define BIT_MEM_PCI_LS BIT(5) 11098 #define BIT_MEM_PCI_DS BIT(4) 11099 #define BIT_MEM_WLMAC_LS BIT(3) 11100 #define BIT_MEM_WLMAC_DS BIT(2) 11101 #define BIT_MEM_WLMCU_LS BIT(1) 11102 11103 /* 2 REG_MEM_PWR_CRTL (Offset 0x10D8) */ 11104 11105 #define BIT_MEM_WLMCU_DS BIT(0) 11106 11107 /* 2 REG_FW_DBG0 (Offset 0x10E0) */ 11108 11109 #define BIT_SHIFT_FW_DBG0 0 11110 #define BIT_MASK_FW_DBG0 0xffffffffL 11111 #define BIT_FW_DBG0(x) (((x) & BIT_MASK_FW_DBG0) << BIT_SHIFT_FW_DBG0) 11112 #define BIT_GET_FW_DBG0(x) (((x) >> BIT_SHIFT_FW_DBG0) & BIT_MASK_FW_DBG0) 11113 11114 /* 2 REG_FW_DBG1 (Offset 0x10E4) */ 11115 11116 #define BIT_SHIFT_FW_DBG1 0 11117 #define BIT_MASK_FW_DBG1 0xffffffffL 11118 #define BIT_FW_DBG1(x) (((x) & BIT_MASK_FW_DBG1) << BIT_SHIFT_FW_DBG1) 11119 #define BIT_GET_FW_DBG1(x) (((x) >> BIT_SHIFT_FW_DBG1) & BIT_MASK_FW_DBG1) 11120 11121 /* 2 REG_FW_DBG2 (Offset 0x10E8) */ 11122 11123 #define BIT_SHIFT_FW_DBG2 0 11124 #define BIT_MASK_FW_DBG2 0xffffffffL 11125 #define BIT_FW_DBG2(x) (((x) & BIT_MASK_FW_DBG2) << BIT_SHIFT_FW_DBG2) 11126 #define BIT_GET_FW_DBG2(x) (((x) >> BIT_SHIFT_FW_DBG2) & BIT_MASK_FW_DBG2) 11127 11128 /* 2 REG_FW_DBG3 (Offset 0x10EC) */ 11129 11130 #define BIT_SHIFT_FW_DBG3 0 11131 #define BIT_MASK_FW_DBG3 0xffffffffL 11132 #define BIT_FW_DBG3(x) (((x) & BIT_MASK_FW_DBG3) << BIT_SHIFT_FW_DBG3) 11133 #define BIT_GET_FW_DBG3(x) (((x) >> BIT_SHIFT_FW_DBG3) & BIT_MASK_FW_DBG3) 11134 11135 /* 2 REG_FW_DBG4 (Offset 0x10F0) */ 11136 11137 #define BIT_SHIFT_FW_DBG4 0 11138 #define BIT_MASK_FW_DBG4 0xffffffffL 11139 #define BIT_FW_DBG4(x) (((x) & BIT_MASK_FW_DBG4) << BIT_SHIFT_FW_DBG4) 11140 #define BIT_GET_FW_DBG4(x) (((x) >> BIT_SHIFT_FW_DBG4) & BIT_MASK_FW_DBG4) 11141 11142 /* 2 REG_FW_DBG5 (Offset 0x10F4) */ 11143 11144 #define BIT_SHIFT_FW_DBG5 0 11145 #define BIT_MASK_FW_DBG5 0xffffffffL 11146 #define BIT_FW_DBG5(x) (((x) & BIT_MASK_FW_DBG5) << BIT_SHIFT_FW_DBG5) 11147 #define BIT_GET_FW_DBG5(x) (((x) >> BIT_SHIFT_FW_DBG5) & BIT_MASK_FW_DBG5) 11148 11149 /* 2 REG_FW_DBG6 (Offset 0x10F8) */ 11150 11151 #define BIT_SHIFT_FW_DBG6 0 11152 #define BIT_MASK_FW_DBG6 0xffffffffL 11153 #define BIT_FW_DBG6(x) (((x) & BIT_MASK_FW_DBG6) << BIT_SHIFT_FW_DBG6) 11154 #define BIT_GET_FW_DBG6(x) (((x) >> BIT_SHIFT_FW_DBG6) & BIT_MASK_FW_DBG6) 11155 11156 /* 2 REG_FW_DBG7 (Offset 0x10FC) */ 11157 11158 #define BIT_SHIFT_FW_DBG7 0 11159 #define BIT_MASK_FW_DBG7 0xffffffffL 11160 #define BIT_FW_DBG7(x) (((x) & BIT_MASK_FW_DBG7) << BIT_SHIFT_FW_DBG7) 11161 #define BIT_GET_FW_DBG7(x) (((x) >> BIT_SHIFT_FW_DBG7) & BIT_MASK_FW_DBG7) 11162 11163 /* 2 REG_CR_EXT (Offset 0x1100) */ 11164 11165 #define BIT_SHIFT_PHY_REQ_DELAY 24 11166 #define BIT_MASK_PHY_REQ_DELAY 0xf 11167 #define BIT_PHY_REQ_DELAY(x) \ 11168 (((x) & BIT_MASK_PHY_REQ_DELAY) << BIT_SHIFT_PHY_REQ_DELAY) 11169 #define BIT_GET_PHY_REQ_DELAY(x) \ 11170 (((x) >> BIT_SHIFT_PHY_REQ_DELAY) & BIT_MASK_PHY_REQ_DELAY) 11171 11172 #define BIT_SPD_DOWN BIT(16) 11173 11174 #define BIT_SHIFT_NETYPE4 4 11175 #define BIT_MASK_NETYPE4 0x3 11176 #define BIT_NETYPE4(x) (((x) & BIT_MASK_NETYPE4) << BIT_SHIFT_NETYPE4) 11177 #define BIT_GET_NETYPE4(x) (((x) >> BIT_SHIFT_NETYPE4) & BIT_MASK_NETYPE4) 11178 11179 #define BIT_SHIFT_NETYPE3 2 11180 #define BIT_MASK_NETYPE3 0x3 11181 #define BIT_NETYPE3(x) (((x) & BIT_MASK_NETYPE3) << BIT_SHIFT_NETYPE3) 11182 #define BIT_GET_NETYPE3(x) (((x) >> BIT_SHIFT_NETYPE3) & BIT_MASK_NETYPE3) 11183 11184 #define BIT_SHIFT_NETYPE2 0 11185 #define BIT_MASK_NETYPE2 0x3 11186 #define BIT_NETYPE2(x) (((x) & BIT_MASK_NETYPE2) << BIT_SHIFT_NETYPE2) 11187 #define BIT_GET_NETYPE2(x) (((x) >> BIT_SHIFT_NETYPE2) & BIT_MASK_NETYPE2) 11188 11189 /* 2 REG_FWFF (Offset 0x1114) */ 11190 11191 #define BIT_SHIFT_PKTNUM_TH_V1 24 11192 #define BIT_MASK_PKTNUM_TH_V1 0xff 11193 #define BIT_PKTNUM_TH_V1(x) \ 11194 (((x) & BIT_MASK_PKTNUM_TH_V1) << BIT_SHIFT_PKTNUM_TH_V1) 11195 #define BIT_GET_PKTNUM_TH_V1(x) \ 11196 (((x) >> BIT_SHIFT_PKTNUM_TH_V1) & BIT_MASK_PKTNUM_TH_V1) 11197 11198 /* 2 REG_FWFF (Offset 0x1114) */ 11199 11200 #define BIT_SHIFT_TIMER_TH 16 11201 #define BIT_MASK_TIMER_TH 0xff 11202 #define BIT_TIMER_TH(x) (((x) & BIT_MASK_TIMER_TH) << BIT_SHIFT_TIMER_TH) 11203 #define BIT_GET_TIMER_TH(x) (((x) >> BIT_SHIFT_TIMER_TH) & BIT_MASK_TIMER_TH) 11204 11205 /* 2 REG_FWFF (Offset 0x1114) */ 11206 11207 #define BIT_SHIFT_RXPKT1ENADDR 0 11208 #define BIT_MASK_RXPKT1ENADDR 0xffff 11209 #define BIT_RXPKT1ENADDR(x) \ 11210 (((x) & BIT_MASK_RXPKT1ENADDR) << BIT_SHIFT_RXPKT1ENADDR) 11211 #define BIT_GET_RXPKT1ENADDR(x) \ 11212 (((x) >> BIT_SHIFT_RXPKT1ENADDR) & BIT_MASK_RXPKT1ENADDR) 11213 11214 /* 2 REG_FE2IMR (Offset 0x1120) */ 11215 11216 #define BIT__FE4ISR__IND_MSK BIT(29) 11217 11218 /* 2 REG_FE2IMR (Offset 0x1120) */ 11219 11220 #define BIT_FS_TXSC_DESC_DONE_INT_EN BIT(28) 11221 #define BIT_FS_TXSC_BKDONE_INT_EN BIT(27) 11222 #define BIT_FS_TXSC_BEDONE_INT_EN BIT(26) 11223 #define BIT_FS_TXSC_VIDONE_INT_EN BIT(25) 11224 #define BIT_FS_TXSC_VODONE_INT_EN BIT(24) 11225 11226 /* 2 REG_FE2IMR (Offset 0x1120) */ 11227 11228 #define BIT_FS_ATIM_MB7_INT_EN BIT(23) 11229 #define BIT_FS_ATIM_MB6_INT_EN BIT(22) 11230 #define BIT_FS_ATIM_MB5_INT_EN BIT(21) 11231 #define BIT_FS_ATIM_MB4_INT_EN BIT(20) 11232 #define BIT_FS_ATIM_MB3_INT_EN BIT(19) 11233 #define BIT_FS_ATIM_MB2_INT_EN BIT(18) 11234 #define BIT_FS_ATIM_MB1_INT_EN BIT(17) 11235 #define BIT_FS_ATIM_MB0_INT_EN BIT(16) 11236 #define BIT_FS_TBTT4INT_EN BIT(11) 11237 #define BIT_FS_TBTT3INT_EN BIT(10) 11238 #define BIT_FS_TBTT2INT_EN BIT(9) 11239 #define BIT_FS_TBTT1INT_EN BIT(8) 11240 #define BIT_FS_TBTT0_MB7INT_EN BIT(7) 11241 #define BIT_FS_TBTT0_MB6INT_EN BIT(6) 11242 #define BIT_FS_TBTT0_MB5INT_EN BIT(5) 11243 #define BIT_FS_TBTT0_MB4INT_EN BIT(4) 11244 #define BIT_FS_TBTT0_MB3INT_EN BIT(3) 11245 #define BIT_FS_TBTT0_MB2INT_EN BIT(2) 11246 #define BIT_FS_TBTT0_MB1INT_EN BIT(1) 11247 #define BIT_FS_TBTT0_INT_EN BIT(0) 11248 11249 /* 2 REG_FE2ISR (Offset 0x1124) */ 11250 11251 #define BIT__FE4ISR__IND_INT BIT(29) 11252 11253 /* 2 REG_FE2ISR (Offset 0x1124) */ 11254 11255 #define BIT_FS_TXSC_DESC_DONE_INT BIT(28) 11256 #define BIT_FS_TXSC_BKDONE_INT BIT(27) 11257 #define BIT_FS_TXSC_BEDONE_INT BIT(26) 11258 #define BIT_FS_TXSC_VIDONE_INT BIT(25) 11259 #define BIT_FS_TXSC_VODONE_INT BIT(24) 11260 11261 /* 2 REG_FE2ISR (Offset 0x1124) */ 11262 11263 #define BIT_FS_ATIM_MB7_INT BIT(23) 11264 #define BIT_FS_ATIM_MB6_INT BIT(22) 11265 #define BIT_FS_ATIM_MB5_INT BIT(21) 11266 #define BIT_FS_ATIM_MB4_INT BIT(20) 11267 #define BIT_FS_ATIM_MB3_INT BIT(19) 11268 #define BIT_FS_ATIM_MB2_INT BIT(18) 11269 #define BIT_FS_ATIM_MB1_INT BIT(17) 11270 #define BIT_FS_ATIM_MB0_INT BIT(16) 11271 #define BIT_FS_TBTT4INT BIT(11) 11272 #define BIT_FS_TBTT3INT BIT(10) 11273 #define BIT_FS_TBTT2INT BIT(9) 11274 #define BIT_FS_TBTT1INT BIT(8) 11275 #define BIT_FS_TBTT0_MB7INT BIT(7) 11276 #define BIT_FS_TBTT0_MB6INT BIT(6) 11277 #define BIT_FS_TBTT0_MB5INT BIT(5) 11278 #define BIT_FS_TBTT0_MB4INT BIT(4) 11279 #define BIT_FS_TBTT0_MB3INT BIT(3) 11280 #define BIT_FS_TBTT0_MB2INT BIT(2) 11281 #define BIT_FS_TBTT0_MB1INT BIT(1) 11282 #define BIT_FS_TBTT0_INT BIT(0) 11283 11284 /* 2 REG_FE3IMR (Offset 0x1128) */ 11285 11286 #define BIT_FS_CLI3_MTI_BCNIVLEAR_INT__EN BIT(31) 11287 11288 /* 2 REG_FE3IMR (Offset 0x1128) */ 11289 11290 #define BIT_FS_CLI2_MTI_BCNIVLEAR_INT__EN BIT(30) 11291 11292 /* 2 REG_FE3IMR (Offset 0x1128) */ 11293 11294 #define BIT_FS_CLI1_MTI_BCNIVLEAR_INT__EN BIT(29) 11295 11296 /* 2 REG_FE3IMR (Offset 0x1128) */ 11297 11298 #define BIT_FS_CLI0_MTI_BCNIVLEAR_INT__EN BIT(28) 11299 11300 /* 2 REG_FE3IMR (Offset 0x1128) */ 11301 11302 #define BIT_FS_BCNDMA4_INT_EN BIT(27) 11303 #define BIT_FS_BCNDMA3_INT_EN BIT(26) 11304 #define BIT_FS_BCNDMA2_INT_EN BIT(25) 11305 #define BIT_FS_BCNDMA1_INT_EN BIT(24) 11306 #define BIT_FS_BCNDMA0_MB7_INT_EN BIT(23) 11307 #define BIT_FS_BCNDMA0_MB6_INT_EN BIT(22) 11308 #define BIT_FS_BCNDMA0_MB5_INT_EN BIT(21) 11309 #define BIT_FS_BCNDMA0_MB4_INT_EN BIT(20) 11310 #define BIT_FS_BCNDMA0_MB3_INT_EN BIT(19) 11311 #define BIT_FS_BCNDMA0_MB2_INT_EN BIT(18) 11312 #define BIT_FS_BCNDMA0_MB1_INT_EN BIT(17) 11313 #define BIT_FS_BCNDMA0_INT_EN BIT(16) 11314 #define BIT_FS_MTI_BCNIVLEAR_INT__EN BIT(15) 11315 #define BIT_FS_BCNERLY4_INT_EN BIT(11) 11316 #define BIT_FS_BCNERLY3_INT_EN BIT(10) 11317 #define BIT_FS_BCNERLY2_INT_EN BIT(9) 11318 #define BIT_FS_BCNERLY1_INT_EN BIT(8) 11319 #define BIT_FS_BCNERLY0_MB7INT_EN BIT(7) 11320 #define BIT_FS_BCNERLY0_MB6INT_EN BIT(6) 11321 #define BIT_FS_BCNERLY0_MB5INT_EN BIT(5) 11322 #define BIT_FS_BCNERLY0_MB4INT_EN BIT(4) 11323 #define BIT_FS_BCNERLY0_MB3INT_EN BIT(3) 11324 #define BIT_FS_BCNERLY0_MB2INT_EN BIT(2) 11325 #define BIT_FS_BCNERLY0_MB1INT_EN BIT(1) 11326 #define BIT_FS_BCNERLY0_INT_EN BIT(0) 11327 11328 /* 2 REG_FE3ISR (Offset 0x112C) */ 11329 11330 #define BIT_FS_CLI3_MTI_BCNIVLEAR_INT BIT(31) 11331 11332 /* 2 REG_FE3ISR (Offset 0x112C) */ 11333 11334 #define BIT_FS_CLI2_MTI_BCNIVLEAR_INT BIT(30) 11335 11336 /* 2 REG_FE3ISR (Offset 0x112C) */ 11337 11338 #define BIT_FS_CLI1_MTI_BCNIVLEAR_INT BIT(29) 11339 11340 /* 2 REG_FE3ISR (Offset 0x112C) */ 11341 11342 #define BIT_FS_CLI0_MTI_BCNIVLEAR_INT BIT(28) 11343 11344 /* 2 REG_FE3ISR (Offset 0x112C) */ 11345 11346 #define BIT_FS_BCNDMA4_INT BIT(27) 11347 #define BIT_FS_BCNDMA3_INT BIT(26) 11348 #define BIT_FS_BCNDMA2_INT BIT(25) 11349 #define BIT_FS_BCNDMA1_INT BIT(24) 11350 #define BIT_FS_BCNDMA0_MB7_INT BIT(23) 11351 #define BIT_FS_BCNDMA0_MB6_INT BIT(22) 11352 #define BIT_FS_BCNDMA0_MB5_INT BIT(21) 11353 #define BIT_FS_BCNDMA0_MB4_INT BIT(20) 11354 #define BIT_FS_BCNDMA0_MB3_INT BIT(19) 11355 #define BIT_FS_BCNDMA0_MB2_INT BIT(18) 11356 #define BIT_FS_BCNDMA0_MB1_INT BIT(17) 11357 #define BIT_FS_BCNDMA0_INT BIT(16) 11358 #define BIT_FS_MTI_BCNIVLEAR_INT BIT(15) 11359 #define BIT_FS_BCNERLY4_INT BIT(11) 11360 #define BIT_FS_BCNERLY3_INT BIT(10) 11361 #define BIT_FS_BCNERLY2_INT BIT(9) 11362 #define BIT_FS_BCNERLY1_INT BIT(8) 11363 #define BIT_FS_BCNERLY0_MB7INT BIT(7) 11364 #define BIT_FS_BCNERLY0_MB6INT BIT(6) 11365 #define BIT_FS_BCNERLY0_MB5INT BIT(5) 11366 #define BIT_FS_BCNERLY0_MB4INT BIT(4) 11367 #define BIT_FS_BCNERLY0_MB3INT BIT(3) 11368 #define BIT_FS_BCNERLY0_MB2INT BIT(2) 11369 #define BIT_FS_BCNERLY0_MB1INT BIT(1) 11370 #define BIT_FS_BCNERLY0_INT BIT(0) 11371 11372 /* 2 REG_FE4IMR (Offset 0x1130) */ 11373 11374 #define BIT_FS_CLI3_TXPKTIN_INT_EN BIT(19) 11375 11376 /* 2 REG_FE4IMR (Offset 0x1130) */ 11377 11378 #define BIT_FS_CLI2_TXPKTIN_INT_EN BIT(18) 11379 11380 /* 2 REG_FE4IMR (Offset 0x1130) */ 11381 11382 #define BIT_FS_CLI1_TXPKTIN_INT_EN BIT(17) 11383 11384 /* 2 REG_FE4IMR (Offset 0x1130) */ 11385 11386 #define BIT_FS_CLI0_TXPKTIN_INT_EN BIT(16) 11387 11388 /* 2 REG_FE4IMR (Offset 0x1130) */ 11389 11390 #define BIT_FS_CLI3_RX_UMD0_INT_EN BIT(15) 11391 11392 /* 2 REG_FE4IMR (Offset 0x1130) */ 11393 11394 #define BIT_FS_CLI3_RX_UMD1_INT_EN BIT(14) 11395 11396 /* 2 REG_FE4IMR (Offset 0x1130) */ 11397 11398 #define BIT_FS_CLI3_RX_BMD0_INT_EN BIT(13) 11399 11400 /* 2 REG_FE4IMR (Offset 0x1130) */ 11401 11402 #define BIT_FS_CLI3_RX_BMD1_INT_EN BIT(12) 11403 11404 /* 2 REG_FE4IMR (Offset 0x1130) */ 11405 11406 #define BIT_FS_CLI2_RX_UMD0_INT_EN BIT(11) 11407 11408 /* 2 REG_FE4IMR (Offset 0x1130) */ 11409 11410 #define BIT_FS_CLI2_RX_UMD1_INT_EN BIT(10) 11411 11412 /* 2 REG_FE4IMR (Offset 0x1130) */ 11413 11414 #define BIT_FS_CLI2_RX_BMD0_INT_EN BIT(9) 11415 11416 /* 2 REG_FE4IMR (Offset 0x1130) */ 11417 11418 #define BIT_FS_CLI2_RX_BMD1_INT_EN BIT(8) 11419 11420 /* 2 REG_FE4IMR (Offset 0x1130) */ 11421 11422 #define BIT_FS_CLI1_RX_UMD0_INT_EN BIT(7) 11423 11424 /* 2 REG_FE4IMR (Offset 0x1130) */ 11425 11426 #define BIT_FS_CLI1_RX_UMD1_INT_EN BIT(6) 11427 11428 /* 2 REG_FE4IMR (Offset 0x1130) */ 11429 11430 #define BIT_FS_CLI1_RX_BMD0_INT_EN BIT(5) 11431 11432 /* 2 REG_FE4IMR (Offset 0x1130) */ 11433 11434 #define BIT_FS_CLI1_RX_BMD1_INT_EN BIT(4) 11435 11436 /* 2 REG_FE4IMR (Offset 0x1130) */ 11437 11438 #define BIT_FS_CLI0_RX_UMD0_INT_EN BIT(3) 11439 11440 /* 2 REG_FE4IMR (Offset 0x1130) */ 11441 11442 #define BIT_FS_CLI0_RX_UMD1_INT_EN BIT(2) 11443 11444 /* 2 REG_FE4IMR (Offset 0x1130) */ 11445 11446 #define BIT_FS_CLI0_RX_BMD0_INT_EN BIT(1) 11447 11448 /* 2 REG_FE4IMR (Offset 0x1130) */ 11449 11450 #define BIT_FS_CLI0_RX_BMD1_INT_EN BIT(0) 11451 11452 /* 2 REG_FE4ISR (Offset 0x1134) */ 11453 11454 #define BIT_FS_CLI3_TXPKTIN_INT BIT(19) 11455 11456 /* 2 REG_FE4ISR (Offset 0x1134) */ 11457 11458 #define BIT_FS_CLI2_TXPKTIN_INT BIT(18) 11459 11460 /* 2 REG_FE4ISR (Offset 0x1134) */ 11461 11462 #define BIT_FS_CLI1_TXPKTIN_INT BIT(17) 11463 11464 /* 2 REG_FE4ISR (Offset 0x1134) */ 11465 11466 #define BIT_FS_CLI0_TXPKTIN_INT BIT(16) 11467 11468 /* 2 REG_FE4ISR (Offset 0x1134) */ 11469 11470 #define BIT_FS_CLI3_RX_UMD0_INT BIT(15) 11471 11472 /* 2 REG_FE4ISR (Offset 0x1134) */ 11473 11474 #define BIT_FS_CLI3_RX_UMD1_INT BIT(14) 11475 11476 /* 2 REG_FE4ISR (Offset 0x1134) */ 11477 11478 #define BIT_FS_CLI3_RX_BMD0_INT BIT(13) 11479 11480 /* 2 REG_FE4ISR (Offset 0x1134) */ 11481 11482 #define BIT_FS_CLI3_RX_BMD1_INT BIT(12) 11483 11484 /* 2 REG_FE4ISR (Offset 0x1134) */ 11485 11486 #define BIT_FS_CLI2_RX_UMD0_INT BIT(11) 11487 11488 /* 2 REG_FE4ISR (Offset 0x1134) */ 11489 11490 #define BIT_FS_CLI2_RX_UMD1_INT BIT(10) 11491 11492 /* 2 REG_FE4ISR (Offset 0x1134) */ 11493 11494 #define BIT_FS_CLI2_RX_BMD0_INT BIT(9) 11495 11496 /* 2 REG_FE4ISR (Offset 0x1134) */ 11497 11498 #define BIT_FS_CLI2_RX_BMD1_INT BIT(8) 11499 11500 /* 2 REG_FE4ISR (Offset 0x1134) */ 11501 11502 #define BIT_FS_CLI1_RX_UMD0_INT BIT(7) 11503 11504 /* 2 REG_FE4ISR (Offset 0x1134) */ 11505 11506 #define BIT_FS_CLI1_RX_UMD1_INT BIT(6) 11507 11508 /* 2 REG_FE4ISR (Offset 0x1134) */ 11509 11510 #define BIT_FS_CLI1_RX_BMD0_INT BIT(5) 11511 11512 /* 2 REG_FE4ISR (Offset 0x1134) */ 11513 11514 #define BIT_FS_CLI1_RX_BMD1_INT BIT(4) 11515 11516 /* 2 REG_FE4ISR (Offset 0x1134) */ 11517 11518 #define BIT_FS_CLI0_RX_UMD0_INT BIT(3) 11519 11520 /* 2 REG_FE4ISR (Offset 0x1134) */ 11521 11522 #define BIT_FS_CLI0_RX_UMD1_INT BIT(2) 11523 11524 /* 2 REG_FE4ISR (Offset 0x1134) */ 11525 11526 #define BIT_FS_CLI0_RX_BMD0_INT BIT(1) 11527 11528 /* 2 REG_FE4ISR (Offset 0x1134) */ 11529 11530 #define BIT_FS_CLI0_RX_BMD1_INT BIT(0) 11531 11532 /* 2 REG_FT1IMR (Offset 0x1138) */ 11533 11534 #define BIT__FT2ISR__IND_MSK BIT(30) 11535 #define BIT_FTM_PTT_INT_EN BIT(29) 11536 #define BIT_RXFTMREQ_INT_EN BIT(28) 11537 #define BIT_RXFTM_INT_EN BIT(27) 11538 #define BIT_TXFTM_INT_EN BIT(26) 11539 11540 /* 2 REG_FT1IMR (Offset 0x1138) */ 11541 11542 #define BIT_FS_H2C_CMD_OK_INT_EN BIT(25) 11543 #define BIT_FS_H2C_CMD_FULL_INT_EN BIT(24) 11544 11545 /* 2 REG_FT1IMR (Offset 0x1138) */ 11546 11547 #define BIT_FS_MACID_PWRCHANGE5_INT_EN BIT(23) 11548 #define BIT_FS_MACID_PWRCHANGE4_INT_EN BIT(22) 11549 #define BIT_FS_MACID_PWRCHANGE3_INT_EN BIT(21) 11550 #define BIT_FS_MACID_PWRCHANGE2_INT_EN BIT(20) 11551 #define BIT_FS_MACID_PWRCHANGE1_INT_EN BIT(19) 11552 #define BIT_FS_MACID_PWRCHANGE0_INT_EN BIT(18) 11553 #define BIT_FS_CTWEND2_INT_EN BIT(17) 11554 #define BIT_FS_CTWEND1_INT_EN BIT(16) 11555 #define BIT_FS_CTWEND0_INT_EN BIT(15) 11556 #define BIT_FS_TX_NULL1_INT_EN BIT(14) 11557 #define BIT_FS_TX_NULL0_INT_EN BIT(13) 11558 #define BIT_FS_TSF_BIT32_TOGGLE_EN BIT(12) 11559 #define BIT_FS_P2P_RFON2_INT_EN BIT(11) 11560 #define BIT_FS_P2P_RFOFF2_INT_EN BIT(10) 11561 #define BIT_FS_P2P_RFON1_INT_EN BIT(9) 11562 #define BIT_FS_P2P_RFOFF1_INT_EN BIT(8) 11563 #define BIT_FS_P2P_RFON0_INT_EN BIT(7) 11564 #define BIT_FS_P2P_RFOFF0_INT_EN BIT(6) 11565 #define BIT_FS_RX_UAPSDMD1_EN BIT(5) 11566 #define BIT_FS_RX_UAPSDMD0_EN BIT(4) 11567 #define BIT_FS_TRIGGER_PKT_EN BIT(3) 11568 #define BIT_FS_EOSP_INT_EN BIT(2) 11569 #define BIT_FS_RPWM2_INT_EN BIT(1) 11570 #define BIT_FS_RPWM_INT_EN BIT(0) 11571 11572 /* 2 REG_FT1ISR (Offset 0x113C) */ 11573 11574 #define BIT__FT2ISR__IND_INT BIT(30) 11575 #define BIT_FTM_PTT_INT BIT(29) 11576 #define BIT_RXFTMREQ_INT BIT(28) 11577 #define BIT_RXFTM_INT BIT(27) 11578 #define BIT_TXFTM_INT BIT(26) 11579 11580 /* 2 REG_FT1ISR (Offset 0x113C) */ 11581 11582 #define BIT_FS_H2C_CMD_OK_INT BIT(25) 11583 #define BIT_FS_H2C_CMD_FULL_INT BIT(24) 11584 11585 /* 2 REG_FT1ISR (Offset 0x113C) */ 11586 11587 #define BIT_FS_MACID_PWRCHANGE5_INT BIT(23) 11588 #define BIT_FS_MACID_PWRCHANGE4_INT BIT(22) 11589 #define BIT_FS_MACID_PWRCHANGE3_INT BIT(21) 11590 #define BIT_FS_MACID_PWRCHANGE2_INT BIT(20) 11591 #define BIT_FS_MACID_PWRCHANGE1_INT BIT(19) 11592 #define BIT_FS_MACID_PWRCHANGE0_INT BIT(18) 11593 #define BIT_FS_CTWEND2_INT BIT(17) 11594 #define BIT_FS_CTWEND1_INT BIT(16) 11595 #define BIT_FS_CTWEND0_INT BIT(15) 11596 #define BIT_FS_TX_NULL1_INT BIT(14) 11597 #define BIT_FS_TX_NULL0_INT BIT(13) 11598 #define BIT_FS_TSF_BIT32_TOGGLE_INT BIT(12) 11599 #define BIT_FS_P2P_RFON2_INT BIT(11) 11600 #define BIT_FS_P2P_RFOFF2_INT BIT(10) 11601 #define BIT_FS_P2P_RFON1_INT BIT(9) 11602 #define BIT_FS_P2P_RFOFF1_INT BIT(8) 11603 #define BIT_FS_P2P_RFON0_INT BIT(7) 11604 #define BIT_FS_P2P_RFOFF0_INT BIT(6) 11605 #define BIT_FS_RX_UAPSDMD1_INT BIT(5) 11606 #define BIT_FS_RX_UAPSDMD0_INT BIT(4) 11607 #define BIT_FS_TRIGGER_PKT_INT BIT(3) 11608 #define BIT_FS_EOSP_INT BIT(2) 11609 #define BIT_FS_RPWM2_INT BIT(1) 11610 #define BIT_FS_RPWM_INT BIT(0) 11611 11612 /* 2 REG_SPWR0 (Offset 0x1140) */ 11613 11614 #define BIT_SHIFT_MID_31TO0 0 11615 #define BIT_MASK_MID_31TO0 0xffffffffL 11616 #define BIT_MID_31TO0(x) (((x) & BIT_MASK_MID_31TO0) << BIT_SHIFT_MID_31TO0) 11617 #define BIT_GET_MID_31TO0(x) (((x) >> BIT_SHIFT_MID_31TO0) & BIT_MASK_MID_31TO0) 11618 11619 /* 2 REG_SPWR1 (Offset 0x1144) */ 11620 11621 #define BIT_SHIFT_MID_63TO32 0 11622 #define BIT_MASK_MID_63TO32 0xffffffffL 11623 #define BIT_MID_63TO32(x) (((x) & BIT_MASK_MID_63TO32) << BIT_SHIFT_MID_63TO32) 11624 #define BIT_GET_MID_63TO32(x) \ 11625 (((x) >> BIT_SHIFT_MID_63TO32) & BIT_MASK_MID_63TO32) 11626 11627 /* 2 REG_SPWR2 (Offset 0x1148) */ 11628 11629 #define BIT_SHIFT_MID_95O64 0 11630 #define BIT_MASK_MID_95O64 0xffffffffL 11631 #define BIT_MID_95O64(x) (((x) & BIT_MASK_MID_95O64) << BIT_SHIFT_MID_95O64) 11632 #define BIT_GET_MID_95O64(x) (((x) >> BIT_SHIFT_MID_95O64) & BIT_MASK_MID_95O64) 11633 11634 /* 2 REG_SPWR3 (Offset 0x114C) */ 11635 11636 #define BIT_SHIFT_MID_127TO96 0 11637 #define BIT_MASK_MID_127TO96 0xffffffffL 11638 #define BIT_MID_127TO96(x) \ 11639 (((x) & BIT_MASK_MID_127TO96) << BIT_SHIFT_MID_127TO96) 11640 #define BIT_GET_MID_127TO96(x) \ 11641 (((x) >> BIT_SHIFT_MID_127TO96) & BIT_MASK_MID_127TO96) 11642 11643 /* 2 REG_POWSEQ (Offset 0x1150) */ 11644 11645 #define BIT_SHIFT_SEQNUM_MID 16 11646 #define BIT_MASK_SEQNUM_MID 0xffff 11647 #define BIT_SEQNUM_MID(x) (((x) & BIT_MASK_SEQNUM_MID) << BIT_SHIFT_SEQNUM_MID) 11648 #define BIT_GET_SEQNUM_MID(x) \ 11649 (((x) >> BIT_SHIFT_SEQNUM_MID) & BIT_MASK_SEQNUM_MID) 11650 11651 #define BIT_SHIFT_REF_MID 0 11652 #define BIT_MASK_REF_MID 0x7f 11653 #define BIT_REF_MID(x) (((x) & BIT_MASK_REF_MID) << BIT_SHIFT_REF_MID) 11654 #define BIT_GET_REF_MID(x) (((x) >> BIT_SHIFT_REF_MID) & BIT_MASK_REF_MID) 11655 11656 /* 2 REG_TC7_CTRL_V1 (Offset 0x1158) */ 11657 11658 #define BIT_TC7INT_EN BIT(26) 11659 #define BIT_TC7MODE BIT(25) 11660 #define BIT_TC7EN BIT(24) 11661 11662 #define BIT_SHIFT_TC7DATA 0 11663 #define BIT_MASK_TC7DATA 0xffffff 11664 #define BIT_TC7DATA(x) (((x) & BIT_MASK_TC7DATA) << BIT_SHIFT_TC7DATA) 11665 #define BIT_GET_TC7DATA(x) (((x) >> BIT_SHIFT_TC7DATA) & BIT_MASK_TC7DATA) 11666 11667 /* 2 REG_TC8_CTRL_V1 (Offset 0x115C) */ 11668 11669 #define BIT_TC8INT_EN BIT(26) 11670 #define BIT_TC8MODE BIT(25) 11671 #define BIT_TC8EN BIT(24) 11672 11673 #define BIT_SHIFT_TC8DATA 0 11674 #define BIT_MASK_TC8DATA 0xffffff 11675 #define BIT_TC8DATA(x) (((x) & BIT_MASK_TC8DATA) << BIT_SHIFT_TC8DATA) 11676 #define BIT_GET_TC8DATA(x) (((x) >> BIT_SHIFT_TC8DATA) & BIT_MASK_TC8DATA) 11677 11678 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11679 11680 #define BIT_FS_CLI3_RX_UAPSDMD1_EN BIT(31) 11681 11682 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11683 11684 #define BIT_FS_CLI3_RX_UAPSDMD0_EN BIT(30) 11685 11686 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11687 11688 #define BIT_FS_CLI3_TRIGGER_PKT_EN BIT(29) 11689 11690 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11691 11692 #define BIT_FS_CLI3_EOSP_INT_EN BIT(28) 11693 11694 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11695 11696 #define BIT_FS_CLI2_RX_UAPSDMD1_EN BIT(27) 11697 11698 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11699 11700 #define BIT_FS_CLI2_RX_UAPSDMD0_EN BIT(26) 11701 11702 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11703 11704 #define BIT_FS_CLI2_TRIGGER_PKT_EN BIT(25) 11705 11706 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11707 11708 #define BIT_FS_CLI2_EOSP_INT_EN BIT(24) 11709 11710 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11711 11712 #define BIT_FS_CLI1_RX_UAPSDMD1_EN BIT(23) 11713 11714 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11715 11716 #define BIT_FS_CLI1_RX_UAPSDMD0_EN BIT(22) 11717 11718 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11719 11720 #define BIT_FS_CLI1_TRIGGER_PKT_EN BIT(21) 11721 11722 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11723 11724 #define BIT_FS_CLI1_EOSP_INT_EN BIT(20) 11725 11726 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11727 11728 #define BIT_FS_CLI0_RX_UAPSDMD1_EN BIT(19) 11729 11730 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11731 11732 #define BIT_FS_CLI0_RX_UAPSDMD0_EN BIT(18) 11733 11734 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11735 11736 #define BIT_FS_CLI0_TRIGGER_PKT_EN BIT(17) 11737 11738 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11739 11740 #define BIT_FS_CLI0_EOSP_INT_EN BIT(16) 11741 11742 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11743 11744 #define BIT_FS_TSF_BIT32_TOGGLE_P2P2_EN BIT(9) 11745 11746 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11747 11748 #define BIT_FS_TSF_BIT32_TOGGLE_P2P1_EN BIT(8) 11749 11750 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11751 11752 #define BIT_FS_CLI3_TX_NULL1_INT_EN BIT(7) 11753 11754 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11755 11756 #define BIT_FS_CLI3_TX_NULL0_INT_EN BIT(6) 11757 11758 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11759 11760 #define BIT_FS_CLI2_TX_NULL1_INT_EN BIT(5) 11761 11762 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11763 11764 #define BIT_FS_CLI2_TX_NULL0_INT_EN BIT(4) 11765 11766 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11767 11768 #define BIT_FS_CLI1_TX_NULL1_INT_EN BIT(3) 11769 11770 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11771 11772 #define BIT_FS_CLI1_TX_NULL0_INT_EN BIT(2) 11773 11774 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11775 11776 #define BIT_FS_CLI0_TX_NULL1_INT_EN BIT(1) 11777 11778 /* 2 REG_FT2IMR (Offset 0x11E0) */ 11779 11780 #define BIT_FS_CLI0_TX_NULL0_INT_EN BIT(0) 11781 11782 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11783 11784 #define BIT_FS_CLI3_RX_UAPSDMD1_INT BIT(31) 11785 11786 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11787 11788 #define BIT_FS_CLI3_RX_UAPSDMD0_INT BIT(30) 11789 11790 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11791 11792 #define BIT_FS_CLI3_TRIGGER_PKT_INT BIT(29) 11793 11794 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11795 11796 #define BIT_FS_CLI3_EOSP_INT BIT(28) 11797 11798 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11799 11800 #define BIT_FS_CLI2_RX_UAPSDMD1_INT BIT(27) 11801 11802 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11803 11804 #define BIT_FS_CLI2_RX_UAPSDMD0_INT BIT(26) 11805 11806 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11807 11808 #define BIT_FS_CLI2_TRIGGER_PKT_INT BIT(25) 11809 11810 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11811 11812 #define BIT_FS_CLI2_EOSP_INT BIT(24) 11813 11814 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11815 11816 #define BIT_FS_CLI1_RX_UAPSDMD1_INT BIT(23) 11817 11818 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11819 11820 #define BIT_FS_CLI1_RX_UAPSDMD0_INT BIT(22) 11821 11822 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11823 11824 #define BIT_FS_CLI1_TRIGGER_PKT_INT BIT(21) 11825 11826 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11827 11828 #define BIT_FS_CLI1_EOSP_INT BIT(20) 11829 11830 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11831 11832 #define BIT_FS_CLI0_RX_UAPSDMD1_INT BIT(19) 11833 11834 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11835 11836 #define BIT_FS_CLI0_RX_UAPSDMD0_INT BIT(18) 11837 11838 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11839 11840 #define BIT_FS_CLI0_TRIGGER_PKT_INT BIT(17) 11841 11842 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11843 11844 #define BIT_FS_CLI0_EOSP_INT BIT(16) 11845 11846 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11847 11848 #define BIT_FS_TSF_BIT32_TOGGLE_P2P2_INT BIT(9) 11849 11850 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11851 11852 #define BIT_FS_TSF_BIT32_TOGGLE_P2P1_INT BIT(8) 11853 11854 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11855 11856 #define BIT_FS_CLI3_TX_NULL1_INT BIT(7) 11857 11858 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11859 11860 #define BIT_FS_CLI3_TX_NULL0_INT BIT(6) 11861 11862 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11863 11864 #define BIT_FS_CLI2_TX_NULL1_INT BIT(5) 11865 11866 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11867 11868 #define BIT_FS_CLI2_TX_NULL0_INT BIT(4) 11869 11870 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11871 11872 #define BIT_FS_CLI1_TX_NULL1_INT BIT(3) 11873 11874 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11875 11876 #define BIT_FS_CLI1_TX_NULL0_INT BIT(2) 11877 11878 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11879 11880 #define BIT_FS_CLI0_TX_NULL1_INT BIT(1) 11881 11882 /* 2 REG_FT2ISR (Offset 0x11E4) */ 11883 11884 #define BIT_FS_CLI0_TX_NULL0_INT BIT(0) 11885 11886 /* 2 REG_MSG2 (Offset 0x11F0) */ 11887 11888 #define BIT_SHIFT_FW_MSG2 0 11889 #define BIT_MASK_FW_MSG2 0xffffffffL 11890 #define BIT_FW_MSG2(x) (((x) & BIT_MASK_FW_MSG2) << BIT_SHIFT_FW_MSG2) 11891 #define BIT_GET_FW_MSG2(x) (((x) >> BIT_SHIFT_FW_MSG2) & BIT_MASK_FW_MSG2) 11892 11893 /* 2 REG_MSG3 (Offset 0x11F4) */ 11894 11895 #define BIT_SHIFT_FW_MSG3 0 11896 #define BIT_MASK_FW_MSG3 0xffffffffL 11897 #define BIT_FW_MSG3(x) (((x) & BIT_MASK_FW_MSG3) << BIT_SHIFT_FW_MSG3) 11898 #define BIT_GET_FW_MSG3(x) (((x) >> BIT_SHIFT_FW_MSG3) & BIT_MASK_FW_MSG3) 11899 11900 /* 2 REG_MSG4 (Offset 0x11F8) */ 11901 11902 #define BIT_SHIFT_FW_MSG4 0 11903 #define BIT_MASK_FW_MSG4 0xffffffffL 11904 #define BIT_FW_MSG4(x) (((x) & BIT_MASK_FW_MSG4) << BIT_SHIFT_FW_MSG4) 11905 #define BIT_GET_FW_MSG4(x) (((x) >> BIT_SHIFT_FW_MSG4) & BIT_MASK_FW_MSG4) 11906 11907 /* 2 REG_MSG5 (Offset 0x11FC) */ 11908 11909 #define BIT_SHIFT_FW_MSG5 0 11910 #define BIT_MASK_FW_MSG5 0xffffffffL 11911 #define BIT_FW_MSG5(x) (((x) & BIT_MASK_FW_MSG5) << BIT_SHIFT_FW_MSG5) 11912 #define BIT_GET_FW_MSG5(x) (((x) >> BIT_SHIFT_FW_MSG5) & BIT_MASK_FW_MSG5) 11913 11914 /* 2 REG_DDMA_CH0SA (Offset 0x1200) */ 11915 11916 #define BIT_SHIFT_DDMACH0_SA 0 11917 #define BIT_MASK_DDMACH0_SA 0xffffffffL 11918 #define BIT_DDMACH0_SA(x) (((x) & BIT_MASK_DDMACH0_SA) << BIT_SHIFT_DDMACH0_SA) 11919 #define BIT_GET_DDMACH0_SA(x) \ 11920 (((x) >> BIT_SHIFT_DDMACH0_SA) & BIT_MASK_DDMACH0_SA) 11921 11922 /* 2 REG_DDMA_CH0DA (Offset 0x1204) */ 11923 11924 #define BIT_SHIFT_DDMACH0_DA 0 11925 #define BIT_MASK_DDMACH0_DA 0xffffffffL 11926 #define BIT_DDMACH0_DA(x) (((x) & BIT_MASK_DDMACH0_DA) << BIT_SHIFT_DDMACH0_DA) 11927 #define BIT_GET_DDMACH0_DA(x) \ 11928 (((x) >> BIT_SHIFT_DDMACH0_DA) & BIT_MASK_DDMACH0_DA) 11929 11930 /* 2 REG_DDMA_CH0CTRL (Offset 0x1208) */ 11931 11932 #define BIT_DDMACH0_OWN BIT(31) 11933 #define BIT_DDMACH0_CHKSUM_EN BIT(29) 11934 #define BIT_DDMACH0_DA_W_DISABLE BIT(28) 11935 #define BIT_DDMACH0_CHKSUM_STS BIT(27) 11936 #define BIT_DDMACH0_DDMA_MODE BIT(26) 11937 #define BIT_DDMACH0_RESET_CHKSUM_STS BIT(25) 11938 #define BIT_DDMACH0_CHKSUM_CONT BIT(24) 11939 11940 #define BIT_SHIFT_DDMACH0_DLEN 0 11941 #define BIT_MASK_DDMACH0_DLEN 0x3ffff 11942 #define BIT_DDMACH0_DLEN(x) \ 11943 (((x) & BIT_MASK_DDMACH0_DLEN) << BIT_SHIFT_DDMACH0_DLEN) 11944 #define BIT_GET_DDMACH0_DLEN(x) \ 11945 (((x) >> BIT_SHIFT_DDMACH0_DLEN) & BIT_MASK_DDMACH0_DLEN) 11946 11947 /* 2 REG_DDMA_CH1SA (Offset 0x1210) */ 11948 11949 #define BIT_SHIFT_DDMACH1_SA 0 11950 #define BIT_MASK_DDMACH1_SA 0xffffffffL 11951 #define BIT_DDMACH1_SA(x) (((x) & BIT_MASK_DDMACH1_SA) << BIT_SHIFT_DDMACH1_SA) 11952 #define BIT_GET_DDMACH1_SA(x) \ 11953 (((x) >> BIT_SHIFT_DDMACH1_SA) & BIT_MASK_DDMACH1_SA) 11954 11955 /* 2 REG_DDMA_CH1DA (Offset 0x1214) */ 11956 11957 #define BIT_SHIFT_DDMACH1_DA 0 11958 #define BIT_MASK_DDMACH1_DA 0xffffffffL 11959 #define BIT_DDMACH1_DA(x) (((x) & BIT_MASK_DDMACH1_DA) << BIT_SHIFT_DDMACH1_DA) 11960 #define BIT_GET_DDMACH1_DA(x) \ 11961 (((x) >> BIT_SHIFT_DDMACH1_DA) & BIT_MASK_DDMACH1_DA) 11962 11963 /* 2 REG_DDMA_CH1CTRL (Offset 0x1218) */ 11964 11965 #define BIT_DDMACH1_OWN BIT(31) 11966 #define BIT_DDMACH1_CHKSUM_EN BIT(29) 11967 #define BIT_DDMACH1_DA_W_DISABLE BIT(28) 11968 #define BIT_DDMACH1_CHKSUM_STS BIT(27) 11969 #define BIT_DDMACH1_DDMA_MODE BIT(26) 11970 #define BIT_DDMACH1_RESET_CHKSUM_STS BIT(25) 11971 #define BIT_DDMACH1_CHKSUM_CONT BIT(24) 11972 11973 #define BIT_SHIFT_DDMACH1_DLEN 0 11974 #define BIT_MASK_DDMACH1_DLEN 0x3ffff 11975 #define BIT_DDMACH1_DLEN(x) \ 11976 (((x) & BIT_MASK_DDMACH1_DLEN) << BIT_SHIFT_DDMACH1_DLEN) 11977 #define BIT_GET_DDMACH1_DLEN(x) \ 11978 (((x) >> BIT_SHIFT_DDMACH1_DLEN) & BIT_MASK_DDMACH1_DLEN) 11979 11980 /* 2 REG_DDMA_CH2SA (Offset 0x1220) */ 11981 11982 #define BIT_SHIFT_DDMACH2_SA 0 11983 #define BIT_MASK_DDMACH2_SA 0xffffffffL 11984 #define BIT_DDMACH2_SA(x) (((x) & BIT_MASK_DDMACH2_SA) << BIT_SHIFT_DDMACH2_SA) 11985 #define BIT_GET_DDMACH2_SA(x) \ 11986 (((x) >> BIT_SHIFT_DDMACH2_SA) & BIT_MASK_DDMACH2_SA) 11987 11988 /* 2 REG_DDMA_CH2DA (Offset 0x1224) */ 11989 11990 #define BIT_SHIFT_DDMACH2_DA 0 11991 #define BIT_MASK_DDMACH2_DA 0xffffffffL 11992 #define BIT_DDMACH2_DA(x) (((x) & BIT_MASK_DDMACH2_DA) << BIT_SHIFT_DDMACH2_DA) 11993 #define BIT_GET_DDMACH2_DA(x) \ 11994 (((x) >> BIT_SHIFT_DDMACH2_DA) & BIT_MASK_DDMACH2_DA) 11995 11996 /* 2 REG_DDMA_CH2CTRL (Offset 0x1228) */ 11997 11998 #define BIT_DDMACH2_OWN BIT(31) 11999 #define BIT_DDMACH2_CHKSUM_EN BIT(29) 12000 #define BIT_DDMACH2_DA_W_DISABLE BIT(28) 12001 #define BIT_DDMACH2_CHKSUM_STS BIT(27) 12002 #define BIT_DDMACH2_DDMA_MODE BIT(26) 12003 #define BIT_DDMACH2_RESET_CHKSUM_STS BIT(25) 12004 #define BIT_DDMACH2_CHKSUM_CONT BIT(24) 12005 12006 #define BIT_SHIFT_DDMACH2_DLEN 0 12007 #define BIT_MASK_DDMACH2_DLEN 0x3ffff 12008 #define BIT_DDMACH2_DLEN(x) \ 12009 (((x) & BIT_MASK_DDMACH2_DLEN) << BIT_SHIFT_DDMACH2_DLEN) 12010 #define BIT_GET_DDMACH2_DLEN(x) \ 12011 (((x) >> BIT_SHIFT_DDMACH2_DLEN) & BIT_MASK_DDMACH2_DLEN) 12012 12013 /* 2 REG_DDMA_CH3SA (Offset 0x1230) */ 12014 12015 #define BIT_SHIFT_DDMACH3_SA 0 12016 #define BIT_MASK_DDMACH3_SA 0xffffffffL 12017 #define BIT_DDMACH3_SA(x) (((x) & BIT_MASK_DDMACH3_SA) << BIT_SHIFT_DDMACH3_SA) 12018 #define BIT_GET_DDMACH3_SA(x) \ 12019 (((x) >> BIT_SHIFT_DDMACH3_SA) & BIT_MASK_DDMACH3_SA) 12020 12021 /* 2 REG_DDMA_CH3DA (Offset 0x1234) */ 12022 12023 #define BIT_SHIFT_DDMACH3_DA 0 12024 #define BIT_MASK_DDMACH3_DA 0xffffffffL 12025 #define BIT_DDMACH3_DA(x) (((x) & BIT_MASK_DDMACH3_DA) << BIT_SHIFT_DDMACH3_DA) 12026 #define BIT_GET_DDMACH3_DA(x) \ 12027 (((x) >> BIT_SHIFT_DDMACH3_DA) & BIT_MASK_DDMACH3_DA) 12028 12029 /* 2 REG_DDMA_CH3CTRL (Offset 0x1238) */ 12030 12031 #define BIT_DDMACH3_OWN BIT(31) 12032 #define BIT_DDMACH3_CHKSUM_EN BIT(29) 12033 #define BIT_DDMACH3_DA_W_DISABLE BIT(28) 12034 #define BIT_DDMACH3_CHKSUM_STS BIT(27) 12035 #define BIT_DDMACH3_DDMA_MODE BIT(26) 12036 #define BIT_DDMACH3_RESET_CHKSUM_STS BIT(25) 12037 #define BIT_DDMACH3_CHKSUM_CONT BIT(24) 12038 12039 #define BIT_SHIFT_DDMACH3_DLEN 0 12040 #define BIT_MASK_DDMACH3_DLEN 0x3ffff 12041 #define BIT_DDMACH3_DLEN(x) \ 12042 (((x) & BIT_MASK_DDMACH3_DLEN) << BIT_SHIFT_DDMACH3_DLEN) 12043 #define BIT_GET_DDMACH3_DLEN(x) \ 12044 (((x) >> BIT_SHIFT_DDMACH3_DLEN) & BIT_MASK_DDMACH3_DLEN) 12045 12046 /* 2 REG_DDMA_CH4SA (Offset 0x1240) */ 12047 12048 #define BIT_SHIFT_DDMACH4_SA 0 12049 #define BIT_MASK_DDMACH4_SA 0xffffffffL 12050 #define BIT_DDMACH4_SA(x) (((x) & BIT_MASK_DDMACH4_SA) << BIT_SHIFT_DDMACH4_SA) 12051 #define BIT_GET_DDMACH4_SA(x) \ 12052 (((x) >> BIT_SHIFT_DDMACH4_SA) & BIT_MASK_DDMACH4_SA) 12053 12054 /* 2 REG_DDMA_CH4DA (Offset 0x1244) */ 12055 12056 #define BIT_SHIFT_DDMACH4_DA 0 12057 #define BIT_MASK_DDMACH4_DA 0xffffffffL 12058 #define BIT_DDMACH4_DA(x) (((x) & BIT_MASK_DDMACH4_DA) << BIT_SHIFT_DDMACH4_DA) 12059 #define BIT_GET_DDMACH4_DA(x) \ 12060 (((x) >> BIT_SHIFT_DDMACH4_DA) & BIT_MASK_DDMACH4_DA) 12061 12062 /* 2 REG_DDMA_CH4CTRL (Offset 0x1248) */ 12063 12064 #define BIT_DDMACH4_OWN BIT(31) 12065 #define BIT_DDMACH4_CHKSUM_EN BIT(29) 12066 #define BIT_DDMACH4_DA_W_DISABLE BIT(28) 12067 #define BIT_DDMACH4_CHKSUM_STS BIT(27) 12068 #define BIT_DDMACH4_DDMA_MODE BIT(26) 12069 #define BIT_DDMACH4_RESET_CHKSUM_STS BIT(25) 12070 #define BIT_DDMACH4_CHKSUM_CONT BIT(24) 12071 12072 #define BIT_SHIFT_DDMACH4_DLEN 0 12073 #define BIT_MASK_DDMACH4_DLEN 0x3ffff 12074 #define BIT_DDMACH4_DLEN(x) \ 12075 (((x) & BIT_MASK_DDMACH4_DLEN) << BIT_SHIFT_DDMACH4_DLEN) 12076 #define BIT_GET_DDMACH4_DLEN(x) \ 12077 (((x) >> BIT_SHIFT_DDMACH4_DLEN) & BIT_MASK_DDMACH4_DLEN) 12078 12079 /* 2 REG_DDMA_CH5SA (Offset 0x1250) */ 12080 12081 #define BIT_SHIFT_DDMACH5_SA 0 12082 #define BIT_MASK_DDMACH5_SA 0xffffffffL 12083 #define BIT_DDMACH5_SA(x) (((x) & BIT_MASK_DDMACH5_SA) << BIT_SHIFT_DDMACH5_SA) 12084 #define BIT_GET_DDMACH5_SA(x) \ 12085 (((x) >> BIT_SHIFT_DDMACH5_SA) & BIT_MASK_DDMACH5_SA) 12086 12087 /* 2 REG_DDMA_CH5DA (Offset 0x1254) */ 12088 12089 #define BIT_DDMACH5_OWN BIT(31) 12090 #define BIT_DDMACH5_CHKSUM_EN BIT(29) 12091 #define BIT_DDMACH5_DA_W_DISABLE BIT(28) 12092 #define BIT_DDMACH5_CHKSUM_STS BIT(27) 12093 #define BIT_DDMACH5_DDMA_MODE BIT(26) 12094 #define BIT_DDMACH5_RESET_CHKSUM_STS BIT(25) 12095 #define BIT_DDMACH5_CHKSUM_CONT BIT(24) 12096 12097 #define BIT_SHIFT_DDMACH5_DA 0 12098 #define BIT_MASK_DDMACH5_DA 0xffffffffL 12099 #define BIT_DDMACH5_DA(x) (((x) & BIT_MASK_DDMACH5_DA) << BIT_SHIFT_DDMACH5_DA) 12100 #define BIT_GET_DDMACH5_DA(x) \ 12101 (((x) >> BIT_SHIFT_DDMACH5_DA) & BIT_MASK_DDMACH5_DA) 12102 12103 #define BIT_SHIFT_DDMACH5_DLEN 0 12104 #define BIT_MASK_DDMACH5_DLEN 0x3ffff 12105 #define BIT_DDMACH5_DLEN(x) \ 12106 (((x) & BIT_MASK_DDMACH5_DLEN) << BIT_SHIFT_DDMACH5_DLEN) 12107 #define BIT_GET_DDMACH5_DLEN(x) \ 12108 (((x) >> BIT_SHIFT_DDMACH5_DLEN) & BIT_MASK_DDMACH5_DLEN) 12109 12110 /* 2 REG_DDMA_INT_MSK (Offset 0x12E0) */ 12111 12112 #define BIT_DDMACH5_MSK BIT(5) 12113 #define BIT_DDMACH4_MSK BIT(4) 12114 #define BIT_DDMACH3_MSK BIT(3) 12115 #define BIT_DDMACH2_MSK BIT(2) 12116 #define BIT_DDMACH1_MSK BIT(1) 12117 #define BIT_DDMACH0_MSK BIT(0) 12118 12119 /* 2 REG_DDMA_CHSTATUS (Offset 0x12E8) */ 12120 12121 #define BIT_DDMACH5_BUSY BIT(5) 12122 #define BIT_DDMACH4_BUSY BIT(4) 12123 #define BIT_DDMACH3_BUSY BIT(3) 12124 #define BIT_DDMACH2_BUSY BIT(2) 12125 #define BIT_DDMACH1_BUSY BIT(1) 12126 #define BIT_DDMACH0_BUSY BIT(0) 12127 12128 /* 2 REG_DDMA_CHKSUM (Offset 0x12F0) */ 12129 12130 #define BIT_SHIFT_IDDMA0_CHKSUM 0 12131 #define BIT_MASK_IDDMA0_CHKSUM 0xffff 12132 #define BIT_IDDMA0_CHKSUM(x) \ 12133 (((x) & BIT_MASK_IDDMA0_CHKSUM) << BIT_SHIFT_IDDMA0_CHKSUM) 12134 #define BIT_GET_IDDMA0_CHKSUM(x) \ 12135 (((x) >> BIT_SHIFT_IDDMA0_CHKSUM) & BIT_MASK_IDDMA0_CHKSUM) 12136 12137 /* 2 REG_DDMA_MONITOR (Offset 0x12FC) */ 12138 12139 #define BIT_IDDMA0_PERMU_UNDERFLOW BIT(14) 12140 #define BIT_IDDMA0_FIFO_UNDERFLOW BIT(13) 12141 #define BIT_IDDMA0_FIFO_OVERFLOW BIT(12) 12142 #define BIT_ECRC_EN_V1 BIT(7) 12143 #define BIT_MDIO_RFLAG_V1 BIT(6) 12144 #define BIT_CH5_ERR BIT(5) 12145 #define BIT_MDIO_WFLAG_V1 BIT(5) 12146 #define BIT_CH4_ERR BIT(4) 12147 #define BIT_CH3_ERR BIT(3) 12148 #define BIT_CH2_ERR BIT(2) 12149 #define BIT_CH1_ERR BIT(1) 12150 #define BIT_CH0_ERR BIT(0) 12151 12152 /* 2 REG_STC_INT_CS (Offset 0x1300) */ 12153 12154 #define BIT_STC_INT_EN BIT(31) 12155 12156 #define BIT_SHIFT_STC_INT_FLAG 16 12157 #define BIT_MASK_STC_INT_FLAG 0xff 12158 #define BIT_STC_INT_FLAG(x) \ 12159 (((x) & BIT_MASK_STC_INT_FLAG) << BIT_SHIFT_STC_INT_FLAG) 12160 #define BIT_GET_STC_INT_FLAG(x) \ 12161 (((x) >> BIT_SHIFT_STC_INT_FLAG) & BIT_MASK_STC_INT_FLAG) 12162 12163 #define BIT_SHIFT_STC_INT_IDX 8 12164 #define BIT_MASK_STC_INT_IDX 0x7 12165 #define BIT_STC_INT_IDX(x) \ 12166 (((x) & BIT_MASK_STC_INT_IDX) << BIT_SHIFT_STC_INT_IDX) 12167 #define BIT_GET_STC_INT_IDX(x) \ 12168 (((x) >> BIT_SHIFT_STC_INT_IDX) & BIT_MASK_STC_INT_IDX) 12169 12170 #define BIT_SHIFT_STC_INT_REALTIME_CS 0 12171 #define BIT_MASK_STC_INT_REALTIME_CS 0x3f 12172 #define BIT_STC_INT_REALTIME_CS(x) \ 12173 (((x) & BIT_MASK_STC_INT_REALTIME_CS) << BIT_SHIFT_STC_INT_REALTIME_CS) 12174 #define BIT_GET_STC_INT_REALTIME_CS(x) \ 12175 (((x) >> BIT_SHIFT_STC_INT_REALTIME_CS) & BIT_MASK_STC_INT_REALTIME_CS) 12176 12177 /* 2 REG_ST_INT_CFG (Offset 0x1304) */ 12178 12179 #define BIT_STC_INT_GRP_EN BIT(31) 12180 12181 #define BIT_SHIFT_STC_INT_EXPECT_LS 8 12182 #define BIT_MASK_STC_INT_EXPECT_LS 0x3f 12183 #define BIT_STC_INT_EXPECT_LS(x) \ 12184 (((x) & BIT_MASK_STC_INT_EXPECT_LS) << BIT_SHIFT_STC_INT_EXPECT_LS) 12185 #define BIT_GET_STC_INT_EXPECT_LS(x) \ 12186 (((x) >> BIT_SHIFT_STC_INT_EXPECT_LS) & BIT_MASK_STC_INT_EXPECT_LS) 12187 12188 #define BIT_SHIFT_STC_INT_EXPECT_CS 0 12189 #define BIT_MASK_STC_INT_EXPECT_CS 0x3f 12190 #define BIT_STC_INT_EXPECT_CS(x) \ 12191 (((x) & BIT_MASK_STC_INT_EXPECT_CS) << BIT_SHIFT_STC_INT_EXPECT_CS) 12192 #define BIT_GET_STC_INT_EXPECT_CS(x) \ 12193 (((x) >> BIT_SHIFT_STC_INT_EXPECT_CS) & BIT_MASK_STC_INT_EXPECT_CS) 12194 12195 /* 2 REG_CMU_DLY_CTRL (Offset 0x1310) */ 12196 12197 #define BIT_CMU_DLY_EN BIT(31) 12198 #define BIT_CMU_DLY_MODE BIT(30) 12199 12200 #define BIT_SHIFT_CMU_DLY_PRE_DIV 0 12201 #define BIT_MASK_CMU_DLY_PRE_DIV 0xff 12202 #define BIT_CMU_DLY_PRE_DIV(x) \ 12203 (((x) & BIT_MASK_CMU_DLY_PRE_DIV) << BIT_SHIFT_CMU_DLY_PRE_DIV) 12204 #define BIT_GET_CMU_DLY_PRE_DIV(x) \ 12205 (((x) >> BIT_SHIFT_CMU_DLY_PRE_DIV) & BIT_MASK_CMU_DLY_PRE_DIV) 12206 12207 /* 2 REG_CMU_DLY_CFG (Offset 0x1314) */ 12208 12209 #define BIT_SHIFT_CMU_DLY_LTR_A2I 24 12210 #define BIT_MASK_CMU_DLY_LTR_A2I 0xff 12211 #define BIT_CMU_DLY_LTR_A2I(x) \ 12212 (((x) & BIT_MASK_CMU_DLY_LTR_A2I) << BIT_SHIFT_CMU_DLY_LTR_A2I) 12213 #define BIT_GET_CMU_DLY_LTR_A2I(x) \ 12214 (((x) >> BIT_SHIFT_CMU_DLY_LTR_A2I) & BIT_MASK_CMU_DLY_LTR_A2I) 12215 12216 #define BIT_SHIFT_CMU_DLY_LTR_I2A 16 12217 #define BIT_MASK_CMU_DLY_LTR_I2A 0xff 12218 #define BIT_CMU_DLY_LTR_I2A(x) \ 12219 (((x) & BIT_MASK_CMU_DLY_LTR_I2A) << BIT_SHIFT_CMU_DLY_LTR_I2A) 12220 #define BIT_GET_CMU_DLY_LTR_I2A(x) \ 12221 (((x) >> BIT_SHIFT_CMU_DLY_LTR_I2A) & BIT_MASK_CMU_DLY_LTR_I2A) 12222 12223 #define BIT_SHIFT_CMU_DLY_LTR_IDLE 8 12224 #define BIT_MASK_CMU_DLY_LTR_IDLE 0xff 12225 #define BIT_CMU_DLY_LTR_IDLE(x) \ 12226 (((x) & BIT_MASK_CMU_DLY_LTR_IDLE) << BIT_SHIFT_CMU_DLY_LTR_IDLE) 12227 #define BIT_GET_CMU_DLY_LTR_IDLE(x) \ 12228 (((x) >> BIT_SHIFT_CMU_DLY_LTR_IDLE) & BIT_MASK_CMU_DLY_LTR_IDLE) 12229 12230 #define BIT_SHIFT_CMU_DLY_LTR_ACT 0 12231 #define BIT_MASK_CMU_DLY_LTR_ACT 0xff 12232 #define BIT_CMU_DLY_LTR_ACT(x) \ 12233 (((x) & BIT_MASK_CMU_DLY_LTR_ACT) << BIT_SHIFT_CMU_DLY_LTR_ACT) 12234 #define BIT_GET_CMU_DLY_LTR_ACT(x) \ 12235 (((x) >> BIT_SHIFT_CMU_DLY_LTR_ACT) & BIT_MASK_CMU_DLY_LTR_ACT) 12236 12237 /* 2 REG_H2CQ_TXBD_DESA (Offset 0x1320) */ 12238 12239 #define BIT_SHIFT_H2CQ_TXBD_DESA 0 12240 #define BIT_MASK_H2CQ_TXBD_DESA 0xffffffffffffffffL 12241 #define BIT_H2CQ_TXBD_DESA(x) \ 12242 (((x) & BIT_MASK_H2CQ_TXBD_DESA) << BIT_SHIFT_H2CQ_TXBD_DESA) 12243 #define BIT_GET_H2CQ_TXBD_DESA(x) \ 12244 (((x) >> BIT_SHIFT_H2CQ_TXBD_DESA) & BIT_MASK_H2CQ_TXBD_DESA) 12245 12246 /* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ 12247 12248 #define BIT_PCIE_H2CQ_FLAG BIT(14) 12249 12250 /* 2 REG_H2CQ_TXBD_NUM (Offset 0x1328) */ 12251 12252 #define BIT_SHIFT_H2CQ_DESC_MODE 12 12253 #define BIT_MASK_H2CQ_DESC_MODE 0x3 12254 #define BIT_H2CQ_DESC_MODE(x) \ 12255 (((x) & BIT_MASK_H2CQ_DESC_MODE) << BIT_SHIFT_H2CQ_DESC_MODE) 12256 #define BIT_GET_H2CQ_DESC_MODE(x) \ 12257 (((x) >> BIT_SHIFT_H2CQ_DESC_MODE) & BIT_MASK_H2CQ_DESC_MODE) 12258 12259 #define BIT_SHIFT_H2CQ_DESC_NUM 0 12260 #define BIT_MASK_H2CQ_DESC_NUM 0xfff 12261 #define BIT_H2CQ_DESC_NUM(x) \ 12262 (((x) & BIT_MASK_H2CQ_DESC_NUM) << BIT_SHIFT_H2CQ_DESC_NUM) 12263 #define BIT_GET_H2CQ_DESC_NUM(x) \ 12264 (((x) >> BIT_SHIFT_H2CQ_DESC_NUM) & BIT_MASK_H2CQ_DESC_NUM) 12265 12266 /* 2 REG_H2CQ_TXBD_IDX (Offset 0x132C) */ 12267 12268 #define BIT_SHIFT_H2CQ_HW_IDX 16 12269 #define BIT_MASK_H2CQ_HW_IDX 0xfff 12270 #define BIT_H2CQ_HW_IDX(x) \ 12271 (((x) & BIT_MASK_H2CQ_HW_IDX) << BIT_SHIFT_H2CQ_HW_IDX) 12272 #define BIT_GET_H2CQ_HW_IDX(x) \ 12273 (((x) >> BIT_SHIFT_H2CQ_HW_IDX) & BIT_MASK_H2CQ_HW_IDX) 12274 12275 #define BIT_SHIFT_H2CQ_HOST_IDX 0 12276 #define BIT_MASK_H2CQ_HOST_IDX 0xfff 12277 #define BIT_H2CQ_HOST_IDX(x) \ 12278 (((x) & BIT_MASK_H2CQ_HOST_IDX) << BIT_SHIFT_H2CQ_HOST_IDX) 12279 #define BIT_GET_H2CQ_HOST_IDX(x) \ 12280 (((x) >> BIT_SHIFT_H2CQ_HOST_IDX) & BIT_MASK_H2CQ_HOST_IDX) 12281 12282 /* 2 REG_H2CQ_CSR (Offset 0x1330) */ 12283 12284 #define BIT_H2CQ_FULL BIT(31) 12285 #define BIT_CLR_H2CQ_HOST_IDX BIT(16) 12286 #define BIT_CLR_H2CQ_HW_IDX BIT(8) 12287 12288 /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ 12289 12290 #define BIT_CHANGE_PCIE_SPEED BIT(18) 12291 12292 /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ 12293 12294 #define BIT_SHIFT_GEN1_GEN2 16 12295 #define BIT_MASK_GEN1_GEN2 0x3 12296 #define BIT_GEN1_GEN2(x) (((x) & BIT_MASK_GEN1_GEN2) << BIT_SHIFT_GEN1_GEN2) 12297 #define BIT_GET_GEN1_GEN2(x) (((x) >> BIT_SHIFT_GEN1_GEN2) & BIT_MASK_GEN1_GEN2) 12298 12299 /* 2 REG_CHANGE_PCIE_SPEED (Offset 0x1350) */ 12300 12301 #define BIT_SHIFT_AUTO_HANG_RELEASE 0 12302 #define BIT_MASK_AUTO_HANG_RELEASE 0x7 12303 #define BIT_AUTO_HANG_RELEASE(x) \ 12304 (((x) & BIT_MASK_AUTO_HANG_RELEASE) << BIT_SHIFT_AUTO_HANG_RELEASE) 12305 #define BIT_GET_AUTO_HANG_RELEASE(x) \ 12306 (((x) >> BIT_SHIFT_AUTO_HANG_RELEASE) & BIT_MASK_AUTO_HANG_RELEASE) 12307 12308 /* 2 REG_OLD_DEHANG (Offset 0x13F4) */ 12309 12310 #define BIT_OLD_DEHANG BIT(1) 12311 12312 /* 2 REG_Q0_Q1_INFO (Offset 0x1400) */ 12313 12314 #define BIT_SHIFT_AC1_PKT_INFO 16 12315 #define BIT_MASK_AC1_PKT_INFO 0xfff 12316 #define BIT_AC1_PKT_INFO(x) \ 12317 (((x) & BIT_MASK_AC1_PKT_INFO) << BIT_SHIFT_AC1_PKT_INFO) 12318 #define BIT_GET_AC1_PKT_INFO(x) \ 12319 (((x) >> BIT_SHIFT_AC1_PKT_INFO) & BIT_MASK_AC1_PKT_INFO) 12320 12321 #define BIT_SHIFT_AC0_PKT_INFO 0 12322 #define BIT_MASK_AC0_PKT_INFO 0xfff 12323 #define BIT_AC0_PKT_INFO(x) \ 12324 (((x) & BIT_MASK_AC0_PKT_INFO) << BIT_SHIFT_AC0_PKT_INFO) 12325 #define BIT_GET_AC0_PKT_INFO(x) \ 12326 (((x) >> BIT_SHIFT_AC0_PKT_INFO) & BIT_MASK_AC0_PKT_INFO) 12327 12328 /* 2 REG_Q2_Q3_INFO (Offset 0x1404) */ 12329 12330 #define BIT_SHIFT_AC3_PKT_INFO 16 12331 #define BIT_MASK_AC3_PKT_INFO 0xfff 12332 #define BIT_AC3_PKT_INFO(x) \ 12333 (((x) & BIT_MASK_AC3_PKT_INFO) << BIT_SHIFT_AC3_PKT_INFO) 12334 #define BIT_GET_AC3_PKT_INFO(x) \ 12335 (((x) >> BIT_SHIFT_AC3_PKT_INFO) & BIT_MASK_AC3_PKT_INFO) 12336 12337 #define BIT_SHIFT_AC2_PKT_INFO 0 12338 #define BIT_MASK_AC2_PKT_INFO 0xfff 12339 #define BIT_AC2_PKT_INFO(x) \ 12340 (((x) & BIT_MASK_AC2_PKT_INFO) << BIT_SHIFT_AC2_PKT_INFO) 12341 #define BIT_GET_AC2_PKT_INFO(x) \ 12342 (((x) >> BIT_SHIFT_AC2_PKT_INFO) & BIT_MASK_AC2_PKT_INFO) 12343 12344 /* 2 REG_Q4_Q5_INFO (Offset 0x1408) */ 12345 12346 #define BIT_SHIFT_AC5_PKT_INFO 16 12347 #define BIT_MASK_AC5_PKT_INFO 0xfff 12348 #define BIT_AC5_PKT_INFO(x) \ 12349 (((x) & BIT_MASK_AC5_PKT_INFO) << BIT_SHIFT_AC5_PKT_INFO) 12350 #define BIT_GET_AC5_PKT_INFO(x) \ 12351 (((x) >> BIT_SHIFT_AC5_PKT_INFO) & BIT_MASK_AC5_PKT_INFO) 12352 12353 #define BIT_SHIFT_AC4_PKT_INFO 0 12354 #define BIT_MASK_AC4_PKT_INFO 0xfff 12355 #define BIT_AC4_PKT_INFO(x) \ 12356 (((x) & BIT_MASK_AC4_PKT_INFO) << BIT_SHIFT_AC4_PKT_INFO) 12357 #define BIT_GET_AC4_PKT_INFO(x) \ 12358 (((x) >> BIT_SHIFT_AC4_PKT_INFO) & BIT_MASK_AC4_PKT_INFO) 12359 12360 /* 2 REG_Q6_Q7_INFO (Offset 0x140C) */ 12361 12362 #define BIT_SHIFT_AC7_PKT_INFO 16 12363 #define BIT_MASK_AC7_PKT_INFO 0xfff 12364 #define BIT_AC7_PKT_INFO(x) \ 12365 (((x) & BIT_MASK_AC7_PKT_INFO) << BIT_SHIFT_AC7_PKT_INFO) 12366 #define BIT_GET_AC7_PKT_INFO(x) \ 12367 (((x) >> BIT_SHIFT_AC7_PKT_INFO) & BIT_MASK_AC7_PKT_INFO) 12368 12369 #define BIT_SHIFT_AC6_PKT_INFO 0 12370 #define BIT_MASK_AC6_PKT_INFO 0xfff 12371 #define BIT_AC6_PKT_INFO(x) \ 12372 (((x) & BIT_MASK_AC6_PKT_INFO) << BIT_SHIFT_AC6_PKT_INFO) 12373 #define BIT_GET_AC6_PKT_INFO(x) \ 12374 (((x) >> BIT_SHIFT_AC6_PKT_INFO) & BIT_MASK_AC6_PKT_INFO) 12375 12376 /* 2 REG_MGQ_HIQ_INFO (Offset 0x1410) */ 12377 12378 #define BIT_SHIFT_HIQ_PKT_INFO 16 12379 #define BIT_MASK_HIQ_PKT_INFO 0xfff 12380 #define BIT_HIQ_PKT_INFO(x) \ 12381 (((x) & BIT_MASK_HIQ_PKT_INFO) << BIT_SHIFT_HIQ_PKT_INFO) 12382 #define BIT_GET_HIQ_PKT_INFO(x) \ 12383 (((x) >> BIT_SHIFT_HIQ_PKT_INFO) & BIT_MASK_HIQ_PKT_INFO) 12384 12385 #define BIT_SHIFT_MGQ_PKT_INFO 0 12386 #define BIT_MASK_MGQ_PKT_INFO 0xfff 12387 #define BIT_MGQ_PKT_INFO(x) \ 12388 (((x) & BIT_MASK_MGQ_PKT_INFO) << BIT_SHIFT_MGQ_PKT_INFO) 12389 #define BIT_GET_MGQ_PKT_INFO(x) \ 12390 (((x) >> BIT_SHIFT_MGQ_PKT_INFO) & BIT_MASK_MGQ_PKT_INFO) 12391 12392 /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ 12393 12394 #define BIT_SHIFT_CMDQ_PKT_INFO 16 12395 #define BIT_MASK_CMDQ_PKT_INFO 0xfff 12396 #define BIT_CMDQ_PKT_INFO(x) \ 12397 (((x) & BIT_MASK_CMDQ_PKT_INFO) << BIT_SHIFT_CMDQ_PKT_INFO) 12398 #define BIT_GET_CMDQ_PKT_INFO(x) \ 12399 (((x) >> BIT_SHIFT_CMDQ_PKT_INFO) & BIT_MASK_CMDQ_PKT_INFO) 12400 12401 /* 2 REG_CMDQ_BCNQ_INFO (Offset 0x1414) */ 12402 12403 #define BIT_SHIFT_BCNQ_PKT_INFO 0 12404 #define BIT_MASK_BCNQ_PKT_INFO 0xfff 12405 #define BIT_BCNQ_PKT_INFO(x) \ 12406 (((x) & BIT_MASK_BCNQ_PKT_INFO) << BIT_SHIFT_BCNQ_PKT_INFO) 12407 #define BIT_GET_BCNQ_PKT_INFO(x) \ 12408 (((x) >> BIT_SHIFT_BCNQ_PKT_INFO) & BIT_MASK_BCNQ_PKT_INFO) 12409 12410 /* 2 REG_USEREG_SETTING (Offset 0x1420) */ 12411 12412 #define BIT_NDPA_USEREG BIT(21) 12413 12414 #define BIT_SHIFT_RETRY_USEREG 19 12415 #define BIT_MASK_RETRY_USEREG 0x3 12416 #define BIT_RETRY_USEREG(x) \ 12417 (((x) & BIT_MASK_RETRY_USEREG) << BIT_SHIFT_RETRY_USEREG) 12418 #define BIT_GET_RETRY_USEREG(x) \ 12419 (((x) >> BIT_SHIFT_RETRY_USEREG) & BIT_MASK_RETRY_USEREG) 12420 12421 #define BIT_SHIFT_TRYPKT_USEREG 17 12422 #define BIT_MASK_TRYPKT_USEREG 0x3 12423 #define BIT_TRYPKT_USEREG(x) \ 12424 (((x) & BIT_MASK_TRYPKT_USEREG) << BIT_SHIFT_TRYPKT_USEREG) 12425 #define BIT_GET_TRYPKT_USEREG(x) \ 12426 (((x) >> BIT_SHIFT_TRYPKT_USEREG) & BIT_MASK_TRYPKT_USEREG) 12427 12428 #define BIT_CTLPKT_USEREG BIT(16) 12429 12430 /* 2 REG_AESIV_SETTING (Offset 0x1424) */ 12431 12432 #define BIT_SHIFT_AESIV_OFFSET 0 12433 #define BIT_MASK_AESIV_OFFSET 0xfff 12434 #define BIT_AESIV_OFFSET(x) \ 12435 (((x) & BIT_MASK_AESIV_OFFSET) << BIT_SHIFT_AESIV_OFFSET) 12436 #define BIT_GET_AESIV_OFFSET(x) \ 12437 (((x) >> BIT_SHIFT_AESIV_OFFSET) & BIT_MASK_AESIV_OFFSET) 12438 12439 /* 2 REG_BF0_TIME_SETTING (Offset 0x1428) */ 12440 12441 #define BIT_BF0_TIMER_SET BIT(31) 12442 #define BIT_BF0_TIMER_CLR BIT(30) 12443 #define BIT_BF0_UPDATE_EN BIT(29) 12444 #define BIT_BF0_TIMER_EN BIT(28) 12445 12446 #define BIT_SHIFT_BF0_PRETIME_OVER 16 12447 #define BIT_MASK_BF0_PRETIME_OVER 0xfff 12448 #define BIT_BF0_PRETIME_OVER(x) \ 12449 (((x) & BIT_MASK_BF0_PRETIME_OVER) << BIT_SHIFT_BF0_PRETIME_OVER) 12450 #define BIT_GET_BF0_PRETIME_OVER(x) \ 12451 (((x) >> BIT_SHIFT_BF0_PRETIME_OVER) & BIT_MASK_BF0_PRETIME_OVER) 12452 12453 #define BIT_SHIFT_BF0_LIFETIME 0 12454 #define BIT_MASK_BF0_LIFETIME 0xffff 12455 #define BIT_BF0_LIFETIME(x) \ 12456 (((x) & BIT_MASK_BF0_LIFETIME) << BIT_SHIFT_BF0_LIFETIME) 12457 #define BIT_GET_BF0_LIFETIME(x) \ 12458 (((x) >> BIT_SHIFT_BF0_LIFETIME) & BIT_MASK_BF0_LIFETIME) 12459 12460 /* 2 REG_BF1_TIME_SETTING (Offset 0x142C) */ 12461 12462 #define BIT_BF1_TIMER_SET BIT(31) 12463 #define BIT_BF1_TIMER_CLR BIT(30) 12464 #define BIT_BF1_UPDATE_EN BIT(29) 12465 #define BIT_BF1_TIMER_EN BIT(28) 12466 12467 #define BIT_SHIFT_BF1_PRETIME_OVER 16 12468 #define BIT_MASK_BF1_PRETIME_OVER 0xfff 12469 #define BIT_BF1_PRETIME_OVER(x) \ 12470 (((x) & BIT_MASK_BF1_PRETIME_OVER) << BIT_SHIFT_BF1_PRETIME_OVER) 12471 #define BIT_GET_BF1_PRETIME_OVER(x) \ 12472 (((x) >> BIT_SHIFT_BF1_PRETIME_OVER) & BIT_MASK_BF1_PRETIME_OVER) 12473 12474 #define BIT_SHIFT_BF1_LIFETIME 0 12475 #define BIT_MASK_BF1_LIFETIME 0xffff 12476 #define BIT_BF1_LIFETIME(x) \ 12477 (((x) & BIT_MASK_BF1_LIFETIME) << BIT_SHIFT_BF1_LIFETIME) 12478 #define BIT_GET_BF1_LIFETIME(x) \ 12479 (((x) >> BIT_SHIFT_BF1_LIFETIME) & BIT_MASK_BF1_LIFETIME) 12480 12481 /* 2 REG_BF_TIMEOUT_EN (Offset 0x1430) */ 12482 12483 #define BIT_EN_VHT_LDPC BIT(9) 12484 #define BIT_EN_HT_LDPC BIT(8) 12485 #define BIT_BF1_TIMEOUT_EN BIT(1) 12486 #define BIT_BF0_TIMEOUT_EN BIT(0) 12487 12488 /* 2 REG_MACID_RELEASE0 (Offset 0x1434) */ 12489 12490 #define BIT_SHIFT_MACID31_0_RELEASE 0 12491 #define BIT_MASK_MACID31_0_RELEASE 0xffffffffL 12492 #define BIT_MACID31_0_RELEASE(x) \ 12493 (((x) & BIT_MASK_MACID31_0_RELEASE) << BIT_SHIFT_MACID31_0_RELEASE) 12494 #define BIT_GET_MACID31_0_RELEASE(x) \ 12495 (((x) >> BIT_SHIFT_MACID31_0_RELEASE) & BIT_MASK_MACID31_0_RELEASE) 12496 12497 /* 2 REG_MACID_RELEASE1 (Offset 0x1438) */ 12498 12499 #define BIT_SHIFT_MACID63_32_RELEASE 0 12500 #define BIT_MASK_MACID63_32_RELEASE 0xffffffffL 12501 #define BIT_MACID63_32_RELEASE(x) \ 12502 (((x) & BIT_MASK_MACID63_32_RELEASE) << BIT_SHIFT_MACID63_32_RELEASE) 12503 #define BIT_GET_MACID63_32_RELEASE(x) \ 12504 (((x) >> BIT_SHIFT_MACID63_32_RELEASE) & BIT_MASK_MACID63_32_RELEASE) 12505 12506 /* 2 REG_MACID_RELEASE2 (Offset 0x143C) */ 12507 12508 #define BIT_SHIFT_MACID95_64_RELEASE 0 12509 #define BIT_MASK_MACID95_64_RELEASE 0xffffffffL 12510 #define BIT_MACID95_64_RELEASE(x) \ 12511 (((x) & BIT_MASK_MACID95_64_RELEASE) << BIT_SHIFT_MACID95_64_RELEASE) 12512 #define BIT_GET_MACID95_64_RELEASE(x) \ 12513 (((x) >> BIT_SHIFT_MACID95_64_RELEASE) & BIT_MASK_MACID95_64_RELEASE) 12514 12515 /* 2 REG_MACID_RELEASE3 (Offset 0x1440) */ 12516 12517 #define BIT_SHIFT_MACID127_96_RELEASE 0 12518 #define BIT_MASK_MACID127_96_RELEASE 0xffffffffL 12519 #define BIT_MACID127_96_RELEASE(x) \ 12520 (((x) & BIT_MASK_MACID127_96_RELEASE) << BIT_SHIFT_MACID127_96_RELEASE) 12521 #define BIT_GET_MACID127_96_RELEASE(x) \ 12522 (((x) >> BIT_SHIFT_MACID127_96_RELEASE) & BIT_MASK_MACID127_96_RELEASE) 12523 12524 /* 2 REG_MACID_RELEASE_SETTING (Offset 0x1444) */ 12525 12526 #define BIT_MACID_VALUE BIT(7) 12527 12528 #define BIT_SHIFT_MACID_OFFSET 0 12529 #define BIT_MASK_MACID_OFFSET 0x7f 12530 #define BIT_MACID_OFFSET(x) \ 12531 (((x) & BIT_MASK_MACID_OFFSET) << BIT_SHIFT_MACID_OFFSET) 12532 #define BIT_GET_MACID_OFFSET(x) \ 12533 (((x) >> BIT_SHIFT_MACID_OFFSET) & BIT_MASK_MACID_OFFSET) 12534 12535 /* 2 REG_FAST_EDCA_VOVI_SETTING (Offset 0x1448) */ 12536 12537 #define BIT_SHIFT_VI_FAST_EDCA_TO 24 12538 #define BIT_MASK_VI_FAST_EDCA_TO 0xff 12539 #define BIT_VI_FAST_EDCA_TO(x) \ 12540 (((x) & BIT_MASK_VI_FAST_EDCA_TO) << BIT_SHIFT_VI_FAST_EDCA_TO) 12541 #define BIT_GET_VI_FAST_EDCA_TO(x) \ 12542 (((x) >> BIT_SHIFT_VI_FAST_EDCA_TO) & BIT_MASK_VI_FAST_EDCA_TO) 12543 12544 #define BIT_VI_THRESHOLD_SEL BIT(23) 12545 12546 #define BIT_SHIFT_VI_FAST_EDCA_PKT_TH 16 12547 #define BIT_MASK_VI_FAST_EDCA_PKT_TH 0x7f 12548 #define BIT_VI_FAST_EDCA_PKT_TH(x) \ 12549 (((x) & BIT_MASK_VI_FAST_EDCA_PKT_TH) << BIT_SHIFT_VI_FAST_EDCA_PKT_TH) 12550 #define BIT_GET_VI_FAST_EDCA_PKT_TH(x) \ 12551 (((x) >> BIT_SHIFT_VI_FAST_EDCA_PKT_TH) & BIT_MASK_VI_FAST_EDCA_PKT_TH) 12552 12553 #define BIT_SHIFT_VO_FAST_EDCA_TO 8 12554 #define BIT_MASK_VO_FAST_EDCA_TO 0xff 12555 #define BIT_VO_FAST_EDCA_TO(x) \ 12556 (((x) & BIT_MASK_VO_FAST_EDCA_TO) << BIT_SHIFT_VO_FAST_EDCA_TO) 12557 #define BIT_GET_VO_FAST_EDCA_TO(x) \ 12558 (((x) >> BIT_SHIFT_VO_FAST_EDCA_TO) & BIT_MASK_VO_FAST_EDCA_TO) 12559 12560 #define BIT_VO_THRESHOLD_SEL BIT(7) 12561 12562 #define BIT_SHIFT_VO_FAST_EDCA_PKT_TH 0 12563 #define BIT_MASK_VO_FAST_EDCA_PKT_TH 0x7f 12564 #define BIT_VO_FAST_EDCA_PKT_TH(x) \ 12565 (((x) & BIT_MASK_VO_FAST_EDCA_PKT_TH) << BIT_SHIFT_VO_FAST_EDCA_PKT_TH) 12566 #define BIT_GET_VO_FAST_EDCA_PKT_TH(x) \ 12567 (((x) >> BIT_SHIFT_VO_FAST_EDCA_PKT_TH) & BIT_MASK_VO_FAST_EDCA_PKT_TH) 12568 12569 /* 2 REG_FAST_EDCA_BEBK_SETTING (Offset 0x144C) */ 12570 12571 #define BIT_SHIFT_BK_FAST_EDCA_TO 24 12572 #define BIT_MASK_BK_FAST_EDCA_TO 0xff 12573 #define BIT_BK_FAST_EDCA_TO(x) \ 12574 (((x) & BIT_MASK_BK_FAST_EDCA_TO) << BIT_SHIFT_BK_FAST_EDCA_TO) 12575 #define BIT_GET_BK_FAST_EDCA_TO(x) \ 12576 (((x) >> BIT_SHIFT_BK_FAST_EDCA_TO) & BIT_MASK_BK_FAST_EDCA_TO) 12577 12578 #define BIT_BK_THRESHOLD_SEL BIT(23) 12579 12580 #define BIT_SHIFT_BK_FAST_EDCA_PKT_TH 16 12581 #define BIT_MASK_BK_FAST_EDCA_PKT_TH 0x7f 12582 #define BIT_BK_FAST_EDCA_PKT_TH(x) \ 12583 (((x) & BIT_MASK_BK_FAST_EDCA_PKT_TH) << BIT_SHIFT_BK_FAST_EDCA_PKT_TH) 12584 #define BIT_GET_BK_FAST_EDCA_PKT_TH(x) \ 12585 (((x) >> BIT_SHIFT_BK_FAST_EDCA_PKT_TH) & BIT_MASK_BK_FAST_EDCA_PKT_TH) 12586 12587 #define BIT_SHIFT_BE_FAST_EDCA_TO 8 12588 #define BIT_MASK_BE_FAST_EDCA_TO 0xff 12589 #define BIT_BE_FAST_EDCA_TO(x) \ 12590 (((x) & BIT_MASK_BE_FAST_EDCA_TO) << BIT_SHIFT_BE_FAST_EDCA_TO) 12591 #define BIT_GET_BE_FAST_EDCA_TO(x) \ 12592 (((x) >> BIT_SHIFT_BE_FAST_EDCA_TO) & BIT_MASK_BE_FAST_EDCA_TO) 12593 12594 #define BIT_BE_THRESHOLD_SEL BIT(7) 12595 12596 #define BIT_SHIFT_BE_FAST_EDCA_PKT_TH 0 12597 #define BIT_MASK_BE_FAST_EDCA_PKT_TH 0x7f 12598 #define BIT_BE_FAST_EDCA_PKT_TH(x) \ 12599 (((x) & BIT_MASK_BE_FAST_EDCA_PKT_TH) << BIT_SHIFT_BE_FAST_EDCA_PKT_TH) 12600 #define BIT_GET_BE_FAST_EDCA_PKT_TH(x) \ 12601 (((x) >> BIT_SHIFT_BE_FAST_EDCA_PKT_TH) & BIT_MASK_BE_FAST_EDCA_PKT_TH) 12602 12603 /* 2 REG_MACID_DROP0 (Offset 0x1450) */ 12604 12605 #define BIT_SHIFT_MACID31_0_DROP 0 12606 #define BIT_MASK_MACID31_0_DROP 0xffffffffL 12607 #define BIT_MACID31_0_DROP(x) \ 12608 (((x) & BIT_MASK_MACID31_0_DROP) << BIT_SHIFT_MACID31_0_DROP) 12609 #define BIT_GET_MACID31_0_DROP(x) \ 12610 (((x) >> BIT_SHIFT_MACID31_0_DROP) & BIT_MASK_MACID31_0_DROP) 12611 12612 /* 2 REG_MACID_DROP1 (Offset 0x1454) */ 12613 12614 #define BIT_SHIFT_MACID63_32_DROP 0 12615 #define BIT_MASK_MACID63_32_DROP 0xffffffffL 12616 #define BIT_MACID63_32_DROP(x) \ 12617 (((x) & BIT_MASK_MACID63_32_DROP) << BIT_SHIFT_MACID63_32_DROP) 12618 #define BIT_GET_MACID63_32_DROP(x) \ 12619 (((x) >> BIT_SHIFT_MACID63_32_DROP) & BIT_MASK_MACID63_32_DROP) 12620 12621 /* 2 REG_MACID_DROP2 (Offset 0x1458) */ 12622 12623 #define BIT_SHIFT_MACID95_64_DROP 0 12624 #define BIT_MASK_MACID95_64_DROP 0xffffffffL 12625 #define BIT_MACID95_64_DROP(x) \ 12626 (((x) & BIT_MASK_MACID95_64_DROP) << BIT_SHIFT_MACID95_64_DROP) 12627 #define BIT_GET_MACID95_64_DROP(x) \ 12628 (((x) >> BIT_SHIFT_MACID95_64_DROP) & BIT_MASK_MACID95_64_DROP) 12629 12630 /* 2 REG_MACID_DROP3 (Offset 0x145C) */ 12631 12632 #define BIT_SHIFT_MACID127_96_DROP 0 12633 #define BIT_MASK_MACID127_96_DROP 0xffffffffL 12634 #define BIT_MACID127_96_DROP(x) \ 12635 (((x) & BIT_MASK_MACID127_96_DROP) << BIT_SHIFT_MACID127_96_DROP) 12636 #define BIT_GET_MACID127_96_DROP(x) \ 12637 (((x) >> BIT_SHIFT_MACID127_96_DROP) & BIT_MASK_MACID127_96_DROP) 12638 12639 /* 2 REG_R_MACID_RELEASE_SUCCESS_0 (Offset 0x1460) */ 12640 12641 #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0 0 12642 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_0 0xffffffffL 12643 #define BIT_R_MACID_RELEASE_SUCCESS_0(x) \ 12644 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_0) \ 12645 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) 12646 #define BIT_GET_R_MACID_RELEASE_SUCCESS_0(x) \ 12647 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_0) & \ 12648 BIT_MASK_R_MACID_RELEASE_SUCCESS_0) 12649 12650 /* 2 REG_R_MACID_RELEASE_SUCCESS_1 (Offset 0x1464) */ 12651 12652 #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1 0 12653 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_1 0xffffffffL 12654 #define BIT_R_MACID_RELEASE_SUCCESS_1(x) \ 12655 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_1) \ 12656 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) 12657 #define BIT_GET_R_MACID_RELEASE_SUCCESS_1(x) \ 12658 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_1) & \ 12659 BIT_MASK_R_MACID_RELEASE_SUCCESS_1) 12660 12661 /* 2 REG_R_MACID_RELEASE_SUCCESS_2 (Offset 0x1468) */ 12662 12663 #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2 0 12664 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_2 0xffffffffL 12665 #define BIT_R_MACID_RELEASE_SUCCESS_2(x) \ 12666 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_2) \ 12667 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) 12668 #define BIT_GET_R_MACID_RELEASE_SUCCESS_2(x) \ 12669 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_2) & \ 12670 BIT_MASK_R_MACID_RELEASE_SUCCESS_2) 12671 12672 /* 2 REG_R_MACID_RELEASE_SUCCESS_3 (Offset 0x146C) */ 12673 12674 #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3 0 12675 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_3 0xffffffffL 12676 #define BIT_R_MACID_RELEASE_SUCCESS_3(x) \ 12677 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_3) \ 12678 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) 12679 #define BIT_GET_R_MACID_RELEASE_SUCCESS_3(x) \ 12680 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_3) & \ 12681 BIT_MASK_R_MACID_RELEASE_SUCCESS_3) 12682 12683 /* 2 REG_MGG_FIFO_CRTL (Offset 0x1470) */ 12684 12685 #define BIT_R_MGG_FIFO_EN BIT(31) 12686 12687 #define BIT_SHIFT_R_MGG_FIFO_PG_SIZE 28 12688 #define BIT_MASK_R_MGG_FIFO_PG_SIZE 0x7 12689 #define BIT_R_MGG_FIFO_PG_SIZE(x) \ 12690 (((x) & BIT_MASK_R_MGG_FIFO_PG_SIZE) << BIT_SHIFT_R_MGG_FIFO_PG_SIZE) 12691 #define BIT_GET_R_MGG_FIFO_PG_SIZE(x) \ 12692 (((x) >> BIT_SHIFT_R_MGG_FIFO_PG_SIZE) & BIT_MASK_R_MGG_FIFO_PG_SIZE) 12693 12694 #define BIT_SHIFT_R_MGG_FIFO_START_PG 16 12695 #define BIT_MASK_R_MGG_FIFO_START_PG 0xfff 12696 #define BIT_R_MGG_FIFO_START_PG(x) \ 12697 (((x) & BIT_MASK_R_MGG_FIFO_START_PG) << BIT_SHIFT_R_MGG_FIFO_START_PG) 12698 #define BIT_GET_R_MGG_FIFO_START_PG(x) \ 12699 (((x) >> BIT_SHIFT_R_MGG_FIFO_START_PG) & BIT_MASK_R_MGG_FIFO_START_PG) 12700 12701 #define BIT_SHIFT_R_MGG_FIFO_SIZE 14 12702 #define BIT_MASK_R_MGG_FIFO_SIZE 0x3 12703 #define BIT_R_MGG_FIFO_SIZE(x) \ 12704 (((x) & BIT_MASK_R_MGG_FIFO_SIZE) << BIT_SHIFT_R_MGG_FIFO_SIZE) 12705 #define BIT_GET_R_MGG_FIFO_SIZE(x) \ 12706 (((x) >> BIT_SHIFT_R_MGG_FIFO_SIZE) & BIT_MASK_R_MGG_FIFO_SIZE) 12707 12708 #define BIT_R_MGG_FIFO_PAUSE BIT(13) 12709 12710 #define BIT_SHIFT_R_MGG_FIFO_RPTR 8 12711 #define BIT_MASK_R_MGG_FIFO_RPTR 0x1f 12712 #define BIT_R_MGG_FIFO_RPTR(x) \ 12713 (((x) & BIT_MASK_R_MGG_FIFO_RPTR) << BIT_SHIFT_R_MGG_FIFO_RPTR) 12714 #define BIT_GET_R_MGG_FIFO_RPTR(x) \ 12715 (((x) >> BIT_SHIFT_R_MGG_FIFO_RPTR) & BIT_MASK_R_MGG_FIFO_RPTR) 12716 12717 #define BIT_R_MGG_FIFO_OV BIT(7) 12718 #define BIT_R_MGG_FIFO_WPTR_ERROR BIT(6) 12719 #define BIT_R_EN_CPU_LIFETIME BIT(5) 12720 12721 #define BIT_SHIFT_R_MGG_FIFO_WPTR 0 12722 #define BIT_MASK_R_MGG_FIFO_WPTR 0x1f 12723 #define BIT_R_MGG_FIFO_WPTR(x) \ 12724 (((x) & BIT_MASK_R_MGG_FIFO_WPTR) << BIT_SHIFT_R_MGG_FIFO_WPTR) 12725 #define BIT_GET_R_MGG_FIFO_WPTR(x) \ 12726 (((x) >> BIT_SHIFT_R_MGG_FIFO_WPTR) & BIT_MASK_R_MGG_FIFO_WPTR) 12727 12728 /* 2 REG_MGG_FIFO_INT (Offset 0x1474) */ 12729 12730 #define BIT_SHIFT_R_MGG_FIFO_INT_FLAG 16 12731 #define BIT_MASK_R_MGG_FIFO_INT_FLAG 0xffff 12732 #define BIT_R_MGG_FIFO_INT_FLAG(x) \ 12733 (((x) & BIT_MASK_R_MGG_FIFO_INT_FLAG) << BIT_SHIFT_R_MGG_FIFO_INT_FLAG) 12734 #define BIT_GET_R_MGG_FIFO_INT_FLAG(x) \ 12735 (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_FLAG) & BIT_MASK_R_MGG_FIFO_INT_FLAG) 12736 12737 #define BIT_SHIFT_R_MGG_FIFO_INT_MASK 0 12738 #define BIT_MASK_R_MGG_FIFO_INT_MASK 0xffff 12739 #define BIT_R_MGG_FIFO_INT_MASK(x) \ 12740 (((x) & BIT_MASK_R_MGG_FIFO_INT_MASK) << BIT_SHIFT_R_MGG_FIFO_INT_MASK) 12741 #define BIT_GET_R_MGG_FIFO_INT_MASK(x) \ 12742 (((x) >> BIT_SHIFT_R_MGG_FIFO_INT_MASK) & BIT_MASK_R_MGG_FIFO_INT_MASK) 12743 12744 /* 2 REG_MGG_FIFO_LIFETIME (Offset 0x1478) */ 12745 12746 #define BIT_SHIFT_R_MGG_FIFO_LIFETIME 16 12747 #define BIT_MASK_R_MGG_FIFO_LIFETIME 0xffff 12748 #define BIT_R_MGG_FIFO_LIFETIME(x) \ 12749 (((x) & BIT_MASK_R_MGG_FIFO_LIFETIME) << BIT_SHIFT_R_MGG_FIFO_LIFETIME) 12750 #define BIT_GET_R_MGG_FIFO_LIFETIME(x) \ 12751 (((x) >> BIT_SHIFT_R_MGG_FIFO_LIFETIME) & BIT_MASK_R_MGG_FIFO_LIFETIME) 12752 12753 #define BIT_SHIFT_R_MGG_FIFO_VALID_MAP 0 12754 #define BIT_MASK_R_MGG_FIFO_VALID_MAP 0xffff 12755 #define BIT_R_MGG_FIFO_VALID_MAP(x) \ 12756 (((x) & BIT_MASK_R_MGG_FIFO_VALID_MAP) \ 12757 << BIT_SHIFT_R_MGG_FIFO_VALID_MAP) 12758 #define BIT_GET_R_MGG_FIFO_VALID_MAP(x) \ 12759 (((x) >> BIT_SHIFT_R_MGG_FIFO_VALID_MAP) & \ 12760 BIT_MASK_R_MGG_FIFO_VALID_MAP) 12761 12762 /* 2 REG_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET (Offset 0x147C) */ 12763 12764 #define BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0 12765 #define BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET 0x7f 12766 #define BIT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ 12767 (((x) & BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) \ 12768 << BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) 12769 #define BIT_GET_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET(x) \ 12770 (((x) >> BIT_SHIFT_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) & \ 12771 BIT_MASK_R_MACID_RELEASE_SUCCESS_CLEAR_OFFSET) 12772 12773 #define BIT_SHIFT_P2PON_DIS_TXTIME 0 12774 #define BIT_MASK_P2PON_DIS_TXTIME 0xff 12775 #define BIT_P2PON_DIS_TXTIME(x) \ 12776 (((x) & BIT_MASK_P2PON_DIS_TXTIME) << BIT_SHIFT_P2PON_DIS_TXTIME) 12777 #define BIT_GET_P2PON_DIS_TXTIME(x) \ 12778 (((x) >> BIT_SHIFT_P2PON_DIS_TXTIME) & BIT_MASK_P2PON_DIS_TXTIME) 12779 12780 /* 2 REG_MACID_SHCUT_OFFSET (Offset 0x1480) */ 12781 12782 #define BIT_SHIFT_MACID_SHCUT_OFFSET_V1 0 12783 #define BIT_MASK_MACID_SHCUT_OFFSET_V1 0xff 12784 #define BIT_MACID_SHCUT_OFFSET_V1(x) \ 12785 (((x) & BIT_MASK_MACID_SHCUT_OFFSET_V1) \ 12786 << BIT_SHIFT_MACID_SHCUT_OFFSET_V1) 12787 #define BIT_GET_MACID_SHCUT_OFFSET_V1(x) \ 12788 (((x) >> BIT_SHIFT_MACID_SHCUT_OFFSET_V1) & \ 12789 BIT_MASK_MACID_SHCUT_OFFSET_V1) 12790 12791 /* 2 REG_MU_TX_CTL (Offset 0x14C0) */ 12792 12793 #define BIT_R_EN_REVERS_GTAB BIT(6) 12794 12795 #define BIT_SHIFT_R_MU_TABLE_VALID 0 12796 #define BIT_MASK_R_MU_TABLE_VALID 0x3f 12797 #define BIT_R_MU_TABLE_VALID(x) \ 12798 (((x) & BIT_MASK_R_MU_TABLE_VALID) << BIT_SHIFT_R_MU_TABLE_VALID) 12799 #define BIT_GET_R_MU_TABLE_VALID(x) \ 12800 (((x) >> BIT_SHIFT_R_MU_TABLE_VALID) & BIT_MASK_R_MU_TABLE_VALID) 12801 12802 #define BIT_SHIFT_R_MU_STA_GTAB_VALID 0 12803 #define BIT_MASK_R_MU_STA_GTAB_VALID 0xffffffffL 12804 #define BIT_R_MU_STA_GTAB_VALID(x) \ 12805 (((x) & BIT_MASK_R_MU_STA_GTAB_VALID) << BIT_SHIFT_R_MU_STA_GTAB_VALID) 12806 #define BIT_GET_R_MU_STA_GTAB_VALID(x) \ 12807 (((x) >> BIT_SHIFT_R_MU_STA_GTAB_VALID) & BIT_MASK_R_MU_STA_GTAB_VALID) 12808 12809 #define BIT_SHIFT_R_MU_STA_GTAB_POSITION 0 12810 #define BIT_MASK_R_MU_STA_GTAB_POSITION 0xffffffffffffffffL 12811 #define BIT_R_MU_STA_GTAB_POSITION(x) \ 12812 (((x) & BIT_MASK_R_MU_STA_GTAB_POSITION) \ 12813 << BIT_SHIFT_R_MU_STA_GTAB_POSITION) 12814 #define BIT_GET_R_MU_STA_GTAB_POSITION(x) \ 12815 (((x) >> BIT_SHIFT_R_MU_STA_GTAB_POSITION) & \ 12816 BIT_MASK_R_MU_STA_GTAB_POSITION) 12817 12818 /* 2 REG_MU_TRX_DBG_CNT (Offset 0x14D0) */ 12819 12820 #define BIT_MU_DNGCNT_RST BIT(20) 12821 12822 #define BIT_SHIFT_MU_DBGCNT_SEL 16 12823 #define BIT_MASK_MU_DBGCNT_SEL 0xf 12824 #define BIT_MU_DBGCNT_SEL(x) \ 12825 (((x) & BIT_MASK_MU_DBGCNT_SEL) << BIT_SHIFT_MU_DBGCNT_SEL) 12826 #define BIT_GET_MU_DBGCNT_SEL(x) \ 12827 (((x) >> BIT_SHIFT_MU_DBGCNT_SEL) & BIT_MASK_MU_DBGCNT_SEL) 12828 12829 #define BIT_SHIFT_MU_DNGCNT 0 12830 #define BIT_MASK_MU_DNGCNT 0xffff 12831 #define BIT_MU_DNGCNT(x) (((x) & BIT_MASK_MU_DNGCNT) << BIT_SHIFT_MU_DNGCNT) 12832 #define BIT_GET_MU_DNGCNT(x) (((x) >> BIT_SHIFT_MU_DNGCNT) & BIT_MASK_MU_DNGCNT) 12833 12834 /* 2 REG_CPUMGQ_TX_TIMER (Offset 0x1500) */ 12835 12836 #define BIT_SHIFT_CPUMGQ_TX_TIMER_V1 0 12837 #define BIT_MASK_CPUMGQ_TX_TIMER_V1 0xffffffffL 12838 #define BIT_CPUMGQ_TX_TIMER_V1(x) \ 12839 (((x) & BIT_MASK_CPUMGQ_TX_TIMER_V1) << BIT_SHIFT_CPUMGQ_TX_TIMER_V1) 12840 #define BIT_GET_CPUMGQ_TX_TIMER_V1(x) \ 12841 (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_V1) & BIT_MASK_CPUMGQ_TX_TIMER_V1) 12842 12843 /* 2 REG_PS_TIMER_A (Offset 0x1504) */ 12844 12845 #define BIT_SHIFT_PS_TIMER_A_V1 0 12846 #define BIT_MASK_PS_TIMER_A_V1 0xffffffffL 12847 #define BIT_PS_TIMER_A_V1(x) \ 12848 (((x) & BIT_MASK_PS_TIMER_A_V1) << BIT_SHIFT_PS_TIMER_A_V1) 12849 #define BIT_GET_PS_TIMER_A_V1(x) \ 12850 (((x) >> BIT_SHIFT_PS_TIMER_A_V1) & BIT_MASK_PS_TIMER_A_V1) 12851 12852 /* 2 REG_PS_TIMER_B (Offset 0x1508) */ 12853 12854 #define BIT_SHIFT_PS_TIMER_B_V1 0 12855 #define BIT_MASK_PS_TIMER_B_V1 0xffffffffL 12856 #define BIT_PS_TIMER_B_V1(x) \ 12857 (((x) & BIT_MASK_PS_TIMER_B_V1) << BIT_SHIFT_PS_TIMER_B_V1) 12858 #define BIT_GET_PS_TIMER_B_V1(x) \ 12859 (((x) >> BIT_SHIFT_PS_TIMER_B_V1) & BIT_MASK_PS_TIMER_B_V1) 12860 12861 /* 2 REG_PS_TIMER_C (Offset 0x150C) */ 12862 12863 #define BIT_SHIFT_PS_TIMER_C_V1 0 12864 #define BIT_MASK_PS_TIMER_C_V1 0xffffffffL 12865 #define BIT_PS_TIMER_C_V1(x) \ 12866 (((x) & BIT_MASK_PS_TIMER_C_V1) << BIT_SHIFT_PS_TIMER_C_V1) 12867 #define BIT_GET_PS_TIMER_C_V1(x) \ 12868 (((x) >> BIT_SHIFT_PS_TIMER_C_V1) & BIT_MASK_PS_TIMER_C_V1) 12869 12870 /* 2 REG_PS_TIMER_ABC_CPUMGQ_TIMER_CRTL (Offset 0x1510) */ 12871 12872 #define BIT_CPUMGQ_TIMER_EN BIT(31) 12873 #define BIT_CPUMGQ_TX_EN BIT(28) 12874 12875 #define BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL 24 12876 #define BIT_MASK_CPUMGQ_TIMER_TSF_SEL 0x7 12877 #define BIT_CPUMGQ_TIMER_TSF_SEL(x) \ 12878 (((x) & BIT_MASK_CPUMGQ_TIMER_TSF_SEL) \ 12879 << BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) 12880 #define BIT_GET_CPUMGQ_TIMER_TSF_SEL(x) \ 12881 (((x) >> BIT_SHIFT_CPUMGQ_TIMER_TSF_SEL) & \ 12882 BIT_MASK_CPUMGQ_TIMER_TSF_SEL) 12883 12884 #define BIT_PS_TIMER_C_EN BIT(23) 12885 12886 #define BIT_SHIFT_PS_TIMER_C_TSF_SEL 16 12887 #define BIT_MASK_PS_TIMER_C_TSF_SEL 0x7 12888 #define BIT_PS_TIMER_C_TSF_SEL(x) \ 12889 (((x) & BIT_MASK_PS_TIMER_C_TSF_SEL) << BIT_SHIFT_PS_TIMER_C_TSF_SEL) 12890 #define BIT_GET_PS_TIMER_C_TSF_SEL(x) \ 12891 (((x) >> BIT_SHIFT_PS_TIMER_C_TSF_SEL) & BIT_MASK_PS_TIMER_C_TSF_SEL) 12892 12893 #define BIT_PS_TIMER_B_EN BIT(15) 12894 12895 #define BIT_SHIFT_PS_TIMER_B_TSF_SEL 8 12896 #define BIT_MASK_PS_TIMER_B_TSF_SEL 0x7 12897 #define BIT_PS_TIMER_B_TSF_SEL(x) \ 12898 (((x) & BIT_MASK_PS_TIMER_B_TSF_SEL) << BIT_SHIFT_PS_TIMER_B_TSF_SEL) 12899 #define BIT_GET_PS_TIMER_B_TSF_SEL(x) \ 12900 (((x) >> BIT_SHIFT_PS_TIMER_B_TSF_SEL) & BIT_MASK_PS_TIMER_B_TSF_SEL) 12901 12902 #define BIT_PS_TIMER_A_EN BIT(7) 12903 12904 #define BIT_SHIFT_PS_TIMER_A_TSF_SEL 0 12905 #define BIT_MASK_PS_TIMER_A_TSF_SEL 0x7 12906 #define BIT_PS_TIMER_A_TSF_SEL(x) \ 12907 (((x) & BIT_MASK_PS_TIMER_A_TSF_SEL) << BIT_SHIFT_PS_TIMER_A_TSF_SEL) 12908 #define BIT_GET_PS_TIMER_A_TSF_SEL(x) \ 12909 (((x) >> BIT_SHIFT_PS_TIMER_A_TSF_SEL) & BIT_MASK_PS_TIMER_A_TSF_SEL) 12910 12911 /* 2 REG_CPUMGQ_TX_TIMER_EARLY (Offset 0x1514) */ 12912 12913 #define BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY 0 12914 #define BIT_MASK_CPUMGQ_TX_TIMER_EARLY 0xff 12915 #define BIT_CPUMGQ_TX_TIMER_EARLY(x) \ 12916 (((x) & BIT_MASK_CPUMGQ_TX_TIMER_EARLY) \ 12917 << BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) 12918 #define BIT_GET_CPUMGQ_TX_TIMER_EARLY(x) \ 12919 (((x) >> BIT_SHIFT_CPUMGQ_TX_TIMER_EARLY) & \ 12920 BIT_MASK_CPUMGQ_TX_TIMER_EARLY) 12921 12922 /* 2 REG_PS_TIMER_A_EARLY (Offset 0x1515) */ 12923 12924 #define BIT_SHIFT_PS_TIMER_A_EARLY 0 12925 #define BIT_MASK_PS_TIMER_A_EARLY 0xff 12926 #define BIT_PS_TIMER_A_EARLY(x) \ 12927 (((x) & BIT_MASK_PS_TIMER_A_EARLY) << BIT_SHIFT_PS_TIMER_A_EARLY) 12928 #define BIT_GET_PS_TIMER_A_EARLY(x) \ 12929 (((x) >> BIT_SHIFT_PS_TIMER_A_EARLY) & BIT_MASK_PS_TIMER_A_EARLY) 12930 12931 /* 2 REG_PS_TIMER_B_EARLY (Offset 0x1516) */ 12932 12933 #define BIT_SHIFT_PS_TIMER_B_EARLY 0 12934 #define BIT_MASK_PS_TIMER_B_EARLY 0xff 12935 #define BIT_PS_TIMER_B_EARLY(x) \ 12936 (((x) & BIT_MASK_PS_TIMER_B_EARLY) << BIT_SHIFT_PS_TIMER_B_EARLY) 12937 #define BIT_GET_PS_TIMER_B_EARLY(x) \ 12938 (((x) >> BIT_SHIFT_PS_TIMER_B_EARLY) & BIT_MASK_PS_TIMER_B_EARLY) 12939 12940 /* 2 REG_PS_TIMER_C_EARLY (Offset 0x1517) */ 12941 12942 #define BIT_SHIFT_PS_TIMER_C_EARLY 0 12943 #define BIT_MASK_PS_TIMER_C_EARLY 0xff 12944 #define BIT_PS_TIMER_C_EARLY(x) \ 12945 (((x) & BIT_MASK_PS_TIMER_C_EARLY) << BIT_SHIFT_PS_TIMER_C_EARLY) 12946 #define BIT_GET_PS_TIMER_C_EARLY(x) \ 12947 (((x) >> BIT_SHIFT_PS_TIMER_C_EARLY) & BIT_MASK_PS_TIMER_C_EARLY) 12948 12949 /* 2 REG_BCN_PSR_RPT2 (Offset 0x1600) */ 12950 12951 #define BIT_SHIFT_DTIM_CNT2 24 12952 #define BIT_MASK_DTIM_CNT2 0xff 12953 #define BIT_DTIM_CNT2(x) (((x) & BIT_MASK_DTIM_CNT2) << BIT_SHIFT_DTIM_CNT2) 12954 #define BIT_GET_DTIM_CNT2(x) (((x) >> BIT_SHIFT_DTIM_CNT2) & BIT_MASK_DTIM_CNT2) 12955 12956 #define BIT_SHIFT_DTIM_PERIOD2 16 12957 #define BIT_MASK_DTIM_PERIOD2 0xff 12958 #define BIT_DTIM_PERIOD2(x) \ 12959 (((x) & BIT_MASK_DTIM_PERIOD2) << BIT_SHIFT_DTIM_PERIOD2) 12960 #define BIT_GET_DTIM_PERIOD2(x) \ 12961 (((x) >> BIT_SHIFT_DTIM_PERIOD2) & BIT_MASK_DTIM_PERIOD2) 12962 12963 #define BIT_DTIM2 BIT(15) 12964 #define BIT_TIM2 BIT(14) 12965 12966 #define BIT_SHIFT_PS_AID_2 0 12967 #define BIT_MASK_PS_AID_2 0x7ff 12968 #define BIT_PS_AID_2(x) (((x) & BIT_MASK_PS_AID_2) << BIT_SHIFT_PS_AID_2) 12969 #define BIT_GET_PS_AID_2(x) (((x) >> BIT_SHIFT_PS_AID_2) & BIT_MASK_PS_AID_2) 12970 12971 /* 2 REG_BCN_PSR_RPT3 (Offset 0x1604) */ 12972 12973 #define BIT_SHIFT_DTIM_CNT3 24 12974 #define BIT_MASK_DTIM_CNT3 0xff 12975 #define BIT_DTIM_CNT3(x) (((x) & BIT_MASK_DTIM_CNT3) << BIT_SHIFT_DTIM_CNT3) 12976 #define BIT_GET_DTIM_CNT3(x) (((x) >> BIT_SHIFT_DTIM_CNT3) & BIT_MASK_DTIM_CNT3) 12977 12978 #define BIT_SHIFT_DTIM_PERIOD3 16 12979 #define BIT_MASK_DTIM_PERIOD3 0xff 12980 #define BIT_DTIM_PERIOD3(x) \ 12981 (((x) & BIT_MASK_DTIM_PERIOD3) << BIT_SHIFT_DTIM_PERIOD3) 12982 #define BIT_GET_DTIM_PERIOD3(x) \ 12983 (((x) >> BIT_SHIFT_DTIM_PERIOD3) & BIT_MASK_DTIM_PERIOD3) 12984 12985 #define BIT_DTIM3 BIT(15) 12986 #define BIT_TIM3 BIT(14) 12987 12988 #define BIT_SHIFT_PS_AID_3 0 12989 #define BIT_MASK_PS_AID_3 0x7ff 12990 #define BIT_PS_AID_3(x) (((x) & BIT_MASK_PS_AID_3) << BIT_SHIFT_PS_AID_3) 12991 #define BIT_GET_PS_AID_3(x) (((x) >> BIT_SHIFT_PS_AID_3) & BIT_MASK_PS_AID_3) 12992 12993 /* 2 REG_BCN_PSR_RPT4 (Offset 0x1608) */ 12994 12995 #define BIT_SHIFT_DTIM_CNT4 24 12996 #define BIT_MASK_DTIM_CNT4 0xff 12997 #define BIT_DTIM_CNT4(x) (((x) & BIT_MASK_DTIM_CNT4) << BIT_SHIFT_DTIM_CNT4) 12998 #define BIT_GET_DTIM_CNT4(x) (((x) >> BIT_SHIFT_DTIM_CNT4) & BIT_MASK_DTIM_CNT4) 12999 13000 #define BIT_SHIFT_DTIM_PERIOD4 16 13001 #define BIT_MASK_DTIM_PERIOD4 0xff 13002 #define BIT_DTIM_PERIOD4(x) \ 13003 (((x) & BIT_MASK_DTIM_PERIOD4) << BIT_SHIFT_DTIM_PERIOD4) 13004 #define BIT_GET_DTIM_PERIOD4(x) \ 13005 (((x) >> BIT_SHIFT_DTIM_PERIOD4) & BIT_MASK_DTIM_PERIOD4) 13006 13007 #define BIT_DTIM4 BIT(15) 13008 #define BIT_TIM4 BIT(14) 13009 13010 #define BIT_SHIFT_PS_AID_4 0 13011 #define BIT_MASK_PS_AID_4 0x7ff 13012 #define BIT_PS_AID_4(x) (((x) & BIT_MASK_PS_AID_4) << BIT_SHIFT_PS_AID_4) 13013 #define BIT_GET_PS_AID_4(x) (((x) >> BIT_SHIFT_PS_AID_4) & BIT_MASK_PS_AID_4) 13014 13015 /* 2 REG_A1_ADDR_MASK (Offset 0x160C) */ 13016 13017 #define BIT_SHIFT_A1_ADDR_MASK 0 13018 #define BIT_MASK_A1_ADDR_MASK 0xffffffffL 13019 #define BIT_A1_ADDR_MASK(x) \ 13020 (((x) & BIT_MASK_A1_ADDR_MASK) << BIT_SHIFT_A1_ADDR_MASK) 13021 #define BIT_GET_A1_ADDR_MASK(x) \ 13022 (((x) >> BIT_SHIFT_A1_ADDR_MASK) & BIT_MASK_A1_ADDR_MASK) 13023 13024 /* 2 REG_MACID2 (Offset 0x1620) */ 13025 13026 #define BIT_SHIFT_MACID2 0 13027 #define BIT_MASK_MACID2 0xffffffffffffL 13028 #define BIT_MACID2(x) (((x) & BIT_MASK_MACID2) << BIT_SHIFT_MACID2) 13029 #define BIT_GET_MACID2(x) (((x) >> BIT_SHIFT_MACID2) & BIT_MASK_MACID2) 13030 13031 /* 2 REG_BSSID2 (Offset 0x1628) */ 13032 13033 #define BIT_SHIFT_BSSID2 0 13034 #define BIT_MASK_BSSID2 0xffffffffffffL 13035 #define BIT_BSSID2(x) (((x) & BIT_MASK_BSSID2) << BIT_SHIFT_BSSID2) 13036 #define BIT_GET_BSSID2(x) (((x) >> BIT_SHIFT_BSSID2) & BIT_MASK_BSSID2) 13037 13038 /* 2 REG_MACID3 (Offset 0x1630) */ 13039 13040 #define BIT_SHIFT_MACID3 0 13041 #define BIT_MASK_MACID3 0xffffffffffffL 13042 #define BIT_MACID3(x) (((x) & BIT_MASK_MACID3) << BIT_SHIFT_MACID3) 13043 #define BIT_GET_MACID3(x) (((x) >> BIT_SHIFT_MACID3) & BIT_MASK_MACID3) 13044 13045 /* 2 REG_BSSID3 (Offset 0x1638) */ 13046 13047 #define BIT_SHIFT_BSSID3 0 13048 #define BIT_MASK_BSSID3 0xffffffffffffL 13049 #define BIT_BSSID3(x) (((x) & BIT_MASK_BSSID3) << BIT_SHIFT_BSSID3) 13050 #define BIT_GET_BSSID3(x) (((x) >> BIT_SHIFT_BSSID3) & BIT_MASK_BSSID3) 13051 13052 /* 2 REG_MACID4 (Offset 0x1640) */ 13053 13054 #define BIT_SHIFT_MACID4 0 13055 #define BIT_MASK_MACID4 0xffffffffffffL 13056 #define BIT_MACID4(x) (((x) & BIT_MASK_MACID4) << BIT_SHIFT_MACID4) 13057 #define BIT_GET_MACID4(x) (((x) >> BIT_SHIFT_MACID4) & BIT_MASK_MACID4) 13058 13059 /* 2 REG_BSSID4 (Offset 0x1648) */ 13060 13061 #define BIT_SHIFT_BSSID4 0 13062 #define BIT_MASK_BSSID4 0xffffffffffffL 13063 #define BIT_BSSID4(x) (((x) & BIT_MASK_BSSID4) << BIT_SHIFT_BSSID4) 13064 #define BIT_GET_BSSID4(x) (((x) >> BIT_SHIFT_BSSID4) & BIT_MASK_BSSID4) 13065 13066 /* 2 REG_PWRBIT_SETTING (Offset 0x1660) */ 13067 13068 #define BIT_CLI3_PWRBIT_OW_EN BIT(7) 13069 #define BIT_CLI3_PWR_ST BIT(6) 13070 #define BIT_CLI2_PWRBIT_OW_EN BIT(5) 13071 #define BIT_CLI2_PWR_ST BIT(4) 13072 #define BIT_CLI1_PWRBIT_OW_EN BIT(3) 13073 #define BIT_CLI1_PWR_ST BIT(2) 13074 #define BIT_CLI0_PWRBIT_OW_EN BIT(1) 13075 #define BIT_CLI0_PWR_ST BIT(0) 13076 13077 /* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ 13078 13079 #define BIT_WMAC_RESP_NONSTA1_DIS BIT(7) 13080 13081 /* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ 13082 13083 #define BIT_BIT_WMAC_TXMU_ACKPOLICY_EN BIT(6) 13084 13085 /* 2 REG_WMAC_MU_BF_OPTION (Offset 0x167C) */ 13086 13087 #define BIT_SHIFT_WMAC_TXMU_ACKPOLICY 4 13088 #define BIT_MASK_WMAC_TXMU_ACKPOLICY 0x3 13089 #define BIT_WMAC_TXMU_ACKPOLICY(x) \ 13090 (((x) & BIT_MASK_WMAC_TXMU_ACKPOLICY) << BIT_SHIFT_WMAC_TXMU_ACKPOLICY) 13091 #define BIT_GET_WMAC_TXMU_ACKPOLICY(x) \ 13092 (((x) >> BIT_SHIFT_WMAC_TXMU_ACKPOLICY) & BIT_MASK_WMAC_TXMU_ACKPOLICY) 13093 13094 #define BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL 1 13095 #define BIT_MASK_WMAC_MU_BFEE_PORT_SEL 0x7 13096 #define BIT_WMAC_MU_BFEE_PORT_SEL(x) \ 13097 (((x) & BIT_MASK_WMAC_MU_BFEE_PORT_SEL) \ 13098 << BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) 13099 #define BIT_GET_WMAC_MU_BFEE_PORT_SEL(x) \ 13100 (((x) >> BIT_SHIFT_WMAC_MU_BFEE_PORT_SEL) & \ 13101 BIT_MASK_WMAC_MU_BFEE_PORT_SEL) 13102 13103 #define BIT_WMAC_MU_BFEE_DIS BIT(0) 13104 13105 /* 2 REG_WMAC_PAUSE_BB_CLR_TH (Offset 0x167D) */ 13106 13107 #define BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH 0 13108 #define BIT_MASK_WMAC_PAUSE_BB_CLR_TH 0xff 13109 #define BIT_WMAC_PAUSE_BB_CLR_TH(x) \ 13110 (((x) & BIT_MASK_WMAC_PAUSE_BB_CLR_TH) \ 13111 << BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) 13112 #define BIT_GET_WMAC_PAUSE_BB_CLR_TH(x) \ 13113 (((x) >> BIT_SHIFT_WMAC_PAUSE_BB_CLR_TH) & \ 13114 BIT_MASK_WMAC_PAUSE_BB_CLR_TH) 13115 13116 /* 2 REG_WMAC_MU_ARB (Offset 0x167E) */ 13117 13118 #define BIT_WMAC_ARB_HW_ADAPT_EN BIT(7) 13119 #define BIT_WMAC_ARB_SW_EN BIT(6) 13120 13121 #define BIT_SHIFT_WMAC_ARB_SW_STATE 0 13122 #define BIT_MASK_WMAC_ARB_SW_STATE 0x3f 13123 #define BIT_WMAC_ARB_SW_STATE(x) \ 13124 (((x) & BIT_MASK_WMAC_ARB_SW_STATE) << BIT_SHIFT_WMAC_ARB_SW_STATE) 13125 #define BIT_GET_WMAC_ARB_SW_STATE(x) \ 13126 (((x) >> BIT_SHIFT_WMAC_ARB_SW_STATE) & BIT_MASK_WMAC_ARB_SW_STATE) 13127 13128 /* 2 REG_WMAC_MU_OPTION (Offset 0x167F) */ 13129 13130 #define BIT_SHIFT_WMAC_MU_DBGSEL 5 13131 #define BIT_MASK_WMAC_MU_DBGSEL 0x3 13132 #define BIT_WMAC_MU_DBGSEL(x) \ 13133 (((x) & BIT_MASK_WMAC_MU_DBGSEL) << BIT_SHIFT_WMAC_MU_DBGSEL) 13134 #define BIT_GET_WMAC_MU_DBGSEL(x) \ 13135 (((x) >> BIT_SHIFT_WMAC_MU_DBGSEL) & BIT_MASK_WMAC_MU_DBGSEL) 13136 13137 #define BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT 0 13138 #define BIT_MASK_WMAC_MU_CPRD_TIMEOUT 0x1f 13139 #define BIT_WMAC_MU_CPRD_TIMEOUT(x) \ 13140 (((x) & BIT_MASK_WMAC_MU_CPRD_TIMEOUT) \ 13141 << BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) 13142 #define BIT_GET_WMAC_MU_CPRD_TIMEOUT(x) \ 13143 (((x) >> BIT_SHIFT_WMAC_MU_CPRD_TIMEOUT) & \ 13144 BIT_MASK_WMAC_MU_CPRD_TIMEOUT) 13145 13146 /* 2 REG_WMAC_MU_BF_CTL (Offset 0x1680) */ 13147 13148 #define BIT_WMAC_INVLD_BFPRT_CHK BIT(15) 13149 #define BIT_WMAC_RETXBFRPTSEQ_UPD BIT(14) 13150 13151 #define BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL 12 13152 #define BIT_MASK_WMAC_MU_BFRPTSEG_SEL 0x3 13153 #define BIT_WMAC_MU_BFRPTSEG_SEL(x) \ 13154 (((x) & BIT_MASK_WMAC_MU_BFRPTSEG_SEL) \ 13155 << BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) 13156 #define BIT_GET_WMAC_MU_BFRPTSEG_SEL(x) \ 13157 (((x) >> BIT_SHIFT_WMAC_MU_BFRPTSEG_SEL) & \ 13158 BIT_MASK_WMAC_MU_BFRPTSEG_SEL) 13159 13160 #define BIT_SHIFT_WMAC_MU_BF_MYAID 0 13161 #define BIT_MASK_WMAC_MU_BF_MYAID 0xfff 13162 #define BIT_WMAC_MU_BF_MYAID(x) \ 13163 (((x) & BIT_MASK_WMAC_MU_BF_MYAID) << BIT_SHIFT_WMAC_MU_BF_MYAID) 13164 #define BIT_GET_WMAC_MU_BF_MYAID(x) \ 13165 (((x) >> BIT_SHIFT_WMAC_MU_BF_MYAID) & BIT_MASK_WMAC_MU_BF_MYAID) 13166 13167 #define BIT_SHIFT_BFRPT_PARA 0 13168 #define BIT_MASK_BFRPT_PARA 0xfff 13169 #define BIT_BFRPT_PARA(x) (((x) & BIT_MASK_BFRPT_PARA) << BIT_SHIFT_BFRPT_PARA) 13170 #define BIT_GET_BFRPT_PARA(x) \ 13171 (((x) >> BIT_SHIFT_BFRPT_PARA) & BIT_MASK_BFRPT_PARA) 13172 13173 /* 2 REG_WMAC_MU_BFRPT_PARA (Offset 0x1682) */ 13174 13175 #define BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL 12 13176 #define BIT_MASK_BIT_BFRPT_PARA_USERID_SEL 0x7 13177 #define BIT_BIT_BFRPT_PARA_USERID_SEL(x) \ 13178 (((x) & BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) \ 13179 << BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) 13180 #define BIT_GET_BIT_BFRPT_PARA_USERID_SEL(x) \ 13181 (((x) >> BIT_SHIFT_BIT_BFRPT_PARA_USERID_SEL) & \ 13182 BIT_MASK_BIT_BFRPT_PARA_USERID_SEL) 13183 13184 /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE2 (Offset 0x1684) */ 13185 13186 #define BIT_STATUS_BFEE2 BIT(10) 13187 #define BIT_WMAC_MU_BFEE2_EN BIT(9) 13188 13189 #define BIT_SHIFT_WMAC_MU_BFEE2_AID 0 13190 #define BIT_MASK_WMAC_MU_BFEE2_AID 0x1ff 13191 #define BIT_WMAC_MU_BFEE2_AID(x) \ 13192 (((x) & BIT_MASK_WMAC_MU_BFEE2_AID) << BIT_SHIFT_WMAC_MU_BFEE2_AID) 13193 #define BIT_GET_WMAC_MU_BFEE2_AID(x) \ 13194 (((x) >> BIT_SHIFT_WMAC_MU_BFEE2_AID) & BIT_MASK_WMAC_MU_BFEE2_AID) 13195 13196 /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE3 (Offset 0x1686) */ 13197 13198 #define BIT_STATUS_BFEE3 BIT(10) 13199 #define BIT_WMAC_MU_BFEE3_EN BIT(9) 13200 13201 #define BIT_SHIFT_WMAC_MU_BFEE3_AID 0 13202 #define BIT_MASK_WMAC_MU_BFEE3_AID 0x1ff 13203 #define BIT_WMAC_MU_BFEE3_AID(x) \ 13204 (((x) & BIT_MASK_WMAC_MU_BFEE3_AID) << BIT_SHIFT_WMAC_MU_BFEE3_AID) 13205 #define BIT_GET_WMAC_MU_BFEE3_AID(x) \ 13206 (((x) >> BIT_SHIFT_WMAC_MU_BFEE3_AID) & BIT_MASK_WMAC_MU_BFEE3_AID) 13207 13208 /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE4 (Offset 0x1688) */ 13209 13210 #define BIT_STATUS_BFEE4 BIT(10) 13211 #define BIT_WMAC_MU_BFEE4_EN BIT(9) 13212 13213 #define BIT_SHIFT_WMAC_MU_BFEE4_AID 0 13214 #define BIT_MASK_WMAC_MU_BFEE4_AID 0x1ff 13215 #define BIT_WMAC_MU_BFEE4_AID(x) \ 13216 (((x) & BIT_MASK_WMAC_MU_BFEE4_AID) << BIT_SHIFT_WMAC_MU_BFEE4_AID) 13217 #define BIT_GET_WMAC_MU_BFEE4_AID(x) \ 13218 (((x) >> BIT_SHIFT_WMAC_MU_BFEE4_AID) & BIT_MASK_WMAC_MU_BFEE4_AID) 13219 13220 /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ 13221 13222 #define BIT_R_WMAC_RX_SYNCFIFO_SYNC BIT(55) 13223 #define BIT_R_WMAC_RXRST_DLY BIT(54) 13224 #define BIT_R_WMAC_SRCH_TXRPT_REF_DROP BIT(53) 13225 #define BIT_R_WMAC_SRCH_TXRPT_UA1 BIT(52) 13226 #define BIT_STATUS_BFEE5 BIT(10) 13227 13228 /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE5 (Offset 0x168A) */ 13229 13230 #define BIT_WMAC_MU_BFEE5_EN BIT(9) 13231 13232 #define BIT_SHIFT_WMAC_MU_BFEE5_AID 0 13233 #define BIT_MASK_WMAC_MU_BFEE5_AID 0x1ff 13234 #define BIT_WMAC_MU_BFEE5_AID(x) \ 13235 (((x) & BIT_MASK_WMAC_MU_BFEE5_AID) << BIT_SHIFT_WMAC_MU_BFEE5_AID) 13236 #define BIT_GET_WMAC_MU_BFEE5_AID(x) \ 13237 (((x) >> BIT_SHIFT_WMAC_MU_BFEE5_AID) & BIT_MASK_WMAC_MU_BFEE5_AID) 13238 13239 /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE6 (Offset 0x168C) */ 13240 13241 #define BIT_STATUS_BFEE6 BIT(10) 13242 #define BIT_WMAC_MU_BFEE6_EN BIT(9) 13243 13244 #define BIT_SHIFT_WMAC_MU_BFEE6_AID 0 13245 #define BIT_MASK_WMAC_MU_BFEE6_AID 0x1ff 13246 #define BIT_WMAC_MU_BFEE6_AID(x) \ 13247 (((x) & BIT_MASK_WMAC_MU_BFEE6_AID) << BIT_SHIFT_WMAC_MU_BFEE6_AID) 13248 #define BIT_GET_WMAC_MU_BFEE6_AID(x) \ 13249 (((x) >> BIT_SHIFT_WMAC_MU_BFEE6_AID) & BIT_MASK_WMAC_MU_BFEE6_AID) 13250 13251 /* 2 REG_WMAC_ASSOCIATED_MU_BFMEE7 (Offset 0x168E) */ 13252 13253 #define BIT_BIT_STATUS_BFEE4 BIT(10) 13254 #define BIT_WMAC_MU_BFEE7_EN BIT(9) 13255 13256 #define BIT_SHIFT_WMAC_MU_BFEE7_AID 0 13257 #define BIT_MASK_WMAC_MU_BFEE7_AID 0x1ff 13258 #define BIT_WMAC_MU_BFEE7_AID(x) \ 13259 (((x) & BIT_MASK_WMAC_MU_BFEE7_AID) << BIT_SHIFT_WMAC_MU_BFEE7_AID) 13260 #define BIT_GET_WMAC_MU_BFEE7_AID(x) \ 13261 (((x) >> BIT_SHIFT_WMAC_MU_BFEE7_AID) & BIT_MASK_WMAC_MU_BFEE7_AID) 13262 13263 /* 2 REG_WMAC_BB_STOP_RX_COUNTER (Offset 0x1690) */ 13264 13265 #define BIT_RST_ALL_COUNTER BIT(31) 13266 13267 #define BIT_SHIFT_ABORT_RX_VBON_COUNTER 16 13268 #define BIT_MASK_ABORT_RX_VBON_COUNTER 0xff 13269 #define BIT_ABORT_RX_VBON_COUNTER(x) \ 13270 (((x) & BIT_MASK_ABORT_RX_VBON_COUNTER) \ 13271 << BIT_SHIFT_ABORT_RX_VBON_COUNTER) 13272 #define BIT_GET_ABORT_RX_VBON_COUNTER(x) \ 13273 (((x) >> BIT_SHIFT_ABORT_RX_VBON_COUNTER) & \ 13274 BIT_MASK_ABORT_RX_VBON_COUNTER) 13275 13276 #define BIT_SHIFT_ABORT_RX_RDRDY_COUNTER 8 13277 #define BIT_MASK_ABORT_RX_RDRDY_COUNTER 0xff 13278 #define BIT_ABORT_RX_RDRDY_COUNTER(x) \ 13279 (((x) & BIT_MASK_ABORT_RX_RDRDY_COUNTER) \ 13280 << BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) 13281 #define BIT_GET_ABORT_RX_RDRDY_COUNTER(x) \ 13282 (((x) >> BIT_SHIFT_ABORT_RX_RDRDY_COUNTER) & \ 13283 BIT_MASK_ABORT_RX_RDRDY_COUNTER) 13284 13285 #define BIT_SHIFT_VBON_EARLY_FALLING_COUNTER 0 13286 #define BIT_MASK_VBON_EARLY_FALLING_COUNTER 0xff 13287 #define BIT_VBON_EARLY_FALLING_COUNTER(x) \ 13288 (((x) & BIT_MASK_VBON_EARLY_FALLING_COUNTER) \ 13289 << BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) 13290 #define BIT_GET_VBON_EARLY_FALLING_COUNTER(x) \ 13291 (((x) >> BIT_SHIFT_VBON_EARLY_FALLING_COUNTER) & \ 13292 BIT_MASK_VBON_EARLY_FALLING_COUNTER) 13293 13294 /* 2 REG_WMAC_PLCP_MONITOR (Offset 0x1694) */ 13295 13296 #define BIT_WMAC_PLCP_TRX_SEL BIT(31) 13297 13298 #define BIT_SHIFT_WMAC_PLCP_RDSIG_SEL 28 13299 #define BIT_MASK_WMAC_PLCP_RDSIG_SEL 0x7 13300 #define BIT_WMAC_PLCP_RDSIG_SEL(x) \ 13301 (((x) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) << BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) 13302 #define BIT_GET_WMAC_PLCP_RDSIG_SEL(x) \ 13303 (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG_SEL) & BIT_MASK_WMAC_PLCP_RDSIG_SEL) 13304 13305 #define BIT_SHIFT_WMAC_RATE_IDX 24 13306 #define BIT_MASK_WMAC_RATE_IDX 0xf 13307 #define BIT_WMAC_RATE_IDX(x) \ 13308 (((x) & BIT_MASK_WMAC_RATE_IDX) << BIT_SHIFT_WMAC_RATE_IDX) 13309 #define BIT_GET_WMAC_RATE_IDX(x) \ 13310 (((x) >> BIT_SHIFT_WMAC_RATE_IDX) & BIT_MASK_WMAC_RATE_IDX) 13311 13312 #define BIT_SHIFT_WMAC_PLCP_RDSIG 0 13313 #define BIT_MASK_WMAC_PLCP_RDSIG 0xffffff 13314 #define BIT_WMAC_PLCP_RDSIG(x) \ 13315 (((x) & BIT_MASK_WMAC_PLCP_RDSIG) << BIT_SHIFT_WMAC_PLCP_RDSIG) 13316 #define BIT_GET_WMAC_PLCP_RDSIG(x) \ 13317 (((x) >> BIT_SHIFT_WMAC_PLCP_RDSIG) & BIT_MASK_WMAC_PLCP_RDSIG) 13318 13319 /* 2 REG_WMAC_PLCP_MONITOR_MUTX (Offset 0x1698) */ 13320 13321 #define BIT_WMAC_MUTX_IDX BIT(24) 13322 13323 /* 2 REG_TRANSMIT_ADDRSS_0 (Offset 0x16A0) */ 13324 13325 #define BIT_SHIFT_TA0 0 13326 #define BIT_MASK_TA0 0xffffffffffffL 13327 #define BIT_TA0(x) (((x) & BIT_MASK_TA0) << BIT_SHIFT_TA0) 13328 #define BIT_GET_TA0(x) (((x) >> BIT_SHIFT_TA0) & BIT_MASK_TA0) 13329 13330 /* 2 REG_TRANSMIT_ADDRSS_1 (Offset 0x16A8) */ 13331 13332 #define BIT_SHIFT_TA1 0 13333 #define BIT_MASK_TA1 0xffffffffffffL 13334 #define BIT_TA1(x) (((x) & BIT_MASK_TA1) << BIT_SHIFT_TA1) 13335 #define BIT_GET_TA1(x) (((x) >> BIT_SHIFT_TA1) & BIT_MASK_TA1) 13336 13337 /* 2 REG_TRANSMIT_ADDRSS_2 (Offset 0x16B0) */ 13338 13339 #define BIT_SHIFT_TA2 0 13340 #define BIT_MASK_TA2 0xffffffffffffL 13341 #define BIT_TA2(x) (((x) & BIT_MASK_TA2) << BIT_SHIFT_TA2) 13342 #define BIT_GET_TA2(x) (((x) >> BIT_SHIFT_TA2) & BIT_MASK_TA2) 13343 13344 /* 2 REG_TRANSMIT_ADDRSS_3 (Offset 0x16B8) */ 13345 13346 #define BIT_SHIFT_TA3 0 13347 #define BIT_MASK_TA3 0xffffffffffffL 13348 #define BIT_TA3(x) (((x) & BIT_MASK_TA3) << BIT_SHIFT_TA3) 13349 #define BIT_GET_TA3(x) (((x) >> BIT_SHIFT_TA3) & BIT_MASK_TA3) 13350 13351 /* 2 REG_TRANSMIT_ADDRSS_4 (Offset 0x16C0) */ 13352 13353 #define BIT_SHIFT_TA4 0 13354 #define BIT_MASK_TA4 0xffffffffffffL 13355 #define BIT_TA4(x) (((x) & BIT_MASK_TA4) << BIT_SHIFT_TA4) 13356 #define BIT_GET_TA4(x) (((x) >> BIT_SHIFT_TA4) & BIT_MASK_TA4) 13357 13358 /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_CTRL_V1 (Offset 0x1700) */ 13359 13360 #define BIT_LTECOEX_ACCESS_START_V1 BIT(31) 13361 #define BIT_LTECOEX_WRITE_MODE_V1 BIT(30) 13362 #define BIT_LTECOEX_READY_BIT_V1 BIT(29) 13363 13364 #define BIT_SHIFT_WRITE_BYTE_EN_V1 16 13365 #define BIT_MASK_WRITE_BYTE_EN_V1 0xf 13366 #define BIT_WRITE_BYTE_EN_V1(x) \ 13367 (((x) & BIT_MASK_WRITE_BYTE_EN_V1) << BIT_SHIFT_WRITE_BYTE_EN_V1) 13368 #define BIT_GET_WRITE_BYTE_EN_V1(x) \ 13369 (((x) >> BIT_SHIFT_WRITE_BYTE_EN_V1) & BIT_MASK_WRITE_BYTE_EN_V1) 13370 13371 #define BIT_SHIFT_LTECOEX_REG_ADDR_V1 0 13372 #define BIT_MASK_LTECOEX_REG_ADDR_V1 0xffff 13373 #define BIT_LTECOEX_REG_ADDR_V1(x) \ 13374 (((x) & BIT_MASK_LTECOEX_REG_ADDR_V1) << BIT_SHIFT_LTECOEX_REG_ADDR_V1) 13375 #define BIT_GET_LTECOEX_REG_ADDR_V1(x) \ 13376 (((x) >> BIT_SHIFT_LTECOEX_REG_ADDR_V1) & BIT_MASK_LTECOEX_REG_ADDR_V1) 13377 13378 /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_WRITE_DATA_V1 (Offset 0x1704) */ 13379 13380 #define BIT_SHIFT_LTECOEX_W_DATA_V1 0 13381 #define BIT_MASK_LTECOEX_W_DATA_V1 0xffffffffL 13382 #define BIT_LTECOEX_W_DATA_V1(x) \ 13383 (((x) & BIT_MASK_LTECOEX_W_DATA_V1) << BIT_SHIFT_LTECOEX_W_DATA_V1) 13384 #define BIT_GET_LTECOEX_W_DATA_V1(x) \ 13385 (((x) >> BIT_SHIFT_LTECOEX_W_DATA_V1) & BIT_MASK_LTECOEX_W_DATA_V1) 13386 13387 /* 2 REG_WL2LTECOEX_INDIRECT_ACCESS_READ_DATA_V1 (Offset 0x1708) */ 13388 13389 #define BIT_SHIFT_LTECOEX_R_DATA_V1 0 13390 #define BIT_MASK_LTECOEX_R_DATA_V1 0xffffffffL 13391 #define BIT_LTECOEX_R_DATA_V1(x) \ 13392 (((x) & BIT_MASK_LTECOEX_R_DATA_V1) << BIT_SHIFT_LTECOEX_R_DATA_V1) 13393 #define BIT_GET_LTECOEX_R_DATA_V1(x) \ 13394 (((x) >> BIT_SHIFT_LTECOEX_R_DATA_V1) & BIT_MASK_LTECOEX_R_DATA_V1) 13395 13396 #endif /* __RTL_WLAN_BITDEF_H__ */ 13397