1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * bdc.h - header for the BRCM BDC USB3.0 device controller
4 *
5 * Copyright (C) 2014 Broadcom Corporation
6 *
7 * Author: Ashwini Pahuja
8 */
9
10 #ifndef __LINUX_BDC_H__
11 #define __LINUX_BDC_H__
12
13 #include <linux/kernel.h>
14 #include <linux/usb.h>
15 #include <linux/device.h>
16 #include <linux/spinlock.h>
17 #include <linux/list.h>
18 #include <linux/dma-mapping.h>
19 #include <linux/mm.h>
20 #include <linux/debugfs.h>
21 #include <linux/usb/ch9.h>
22 #include <linux/usb/gadget.h>
23 #include <asm/unaligned.h>
24
25 #define BRCM_BDC_NAME "bdc"
26 #define BRCM_BDC_DESC "Broadcom USB Device Controller driver"
27
28 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
29
30 /* BDC command operation timeout in usec*/
31 #define BDC_CMD_TIMEOUT 1000
32 /* BDC controller operation timeout in usec*/
33 #define BDC_COP_TIMEOUT 500
34
35 /*
36 * Maximum size of ep0 response buffer for ch9 requests,
37 * the set_sel request uses 6 so far, the max.
38 */
39 #define EP0_RESPONSE_BUFF 6
40 /* Start with SS as default */
41 #define EP0_MAX_PKT_SIZE 512
42
43 /* 64 entries in a SRR */
44 #define NUM_SR_ENTRIES 64
45
46 /* Num of bds per table */
47 #define NUM_BDS_PER_TABLE 32
48
49 /* Num of tables in bd list for control,bulk and Int ep */
50 #define NUM_TABLES 2
51
52 /* Num of tables in bd list for Isoch ep */
53 #define NUM_TABLES_ISOCH 6
54
55 /* U1 Timeout default: 248usec */
56 #define U1_TIMEOUT 0xf8
57
58 /* Interrupt coalescence in usec */
59 #define INT_CLS 500
60
61 /* Register offsets */
62 /* Configuration and Capability registers */
63 #define BDC_BDCCFG0 0x00
64 #define BDC_BDCCFG1 0x04
65 #define BDC_BDCCAP0 0x08
66 #define BDC_BDCCAP1 0x0c
67 #define BDC_CMDPAR0 0x10
68 #define BDC_CMDPAR1 0x14
69 #define BDC_CMDPAR2 0x18
70 #define BDC_CMDSC 0x1c
71 #define BDC_USPC 0x20
72 #define BDC_USPPMS 0x28
73 #define BDC_USPPM2 0x2c
74 #define BDC_SPBBAL 0x38
75 #define BDC_SPBBAH 0x3c
76 #define BDC_BDCSC 0x40
77 #define BDC_XSFNTF 0x4c
78
79 #define BDC_DVCSA 0x50
80 #define BDC_DVCSB 0x54
81 #define BDC_EPSTS0 0x60
82 #define BDC_EPSTS1 0x64
83 #define BDC_EPSTS2 0x68
84 #define BDC_EPSTS3 0x6c
85 #define BDC_EPSTS4 0x70
86 #define BDC_EPSTS5 0x74
87 #define BDC_EPSTS6 0x78
88 #define BDC_EPSTS7 0x7c
89 #define BDC_SRRBAL(n) (0x200 + (n * 0x10))
90 #define BDC_SRRBAH(n) (0x204 + (n * 0x10))
91 #define BDC_SRRINT(n) (0x208 + (n * 0x10))
92 #define BDC_INTCTLS(n) (0x20c + (n * 0x10))
93
94 /* Extended capability regs */
95 #define BDC_FSCNOC 0xcd4
96 #define BDC_FSCNIC 0xce4
97 #define NUM_NCS(p) (p >> 28)
98
99 /* Register bit fields and Masks */
100 /* BDC Configuration 0 */
101 #define BDC_PGS(p) (((p) & (0x7 << 8)) >> 8)
102 #define BDC_SPB(p) (p & 0x7)
103
104 /* BDC Capability1 */
105 #define BDC_P64 (1 << 0)
106
107 /* BDC Command register */
108 #define BDC_CMD_FH 0xe
109 #define BDC_CMD_DNC 0x6
110 #define BDC_CMD_EPO 0x4
111 #define BDC_CMD_BLA 0x3
112 #define BDC_CMD_EPC 0x2
113 #define BDC_CMD_DVC 0x1
114 #define BDC_CMD_CWS (0x1 << 5)
115 #define BDC_CMD_CST(p) (((p) & (0xf << 6))>>6)
116 #define BDC_CMD_EPN(p) ((p & 0x1f) << 10)
117 #define BDC_SUB_CMD_ADD (0x1 << 17)
118 #define BDC_SUB_CMD_FWK (0x4 << 17)
119 /* Reset sequence number */
120 #define BDC_CMD_EPO_RST_SN (0x1 << 16)
121 #define BDC_CMD_EP0_XSD (0x1 << 16)
122 #define BDC_SUB_CMD_ADD_EP (0x1 << 17)
123 #define BDC_SUB_CMD_DRP_EP (0x2 << 17)
124 #define BDC_SUB_CMD_EP_STP (0x2 << 17)
125 #define BDC_SUB_CMD_EP_STL (0x4 << 17)
126 #define BDC_SUB_CMD_EP_RST (0x1 << 17)
127 #define BDC_CMD_SRD (1 << 27)
128
129 /* CMD completion status */
130 #define BDC_CMDS_SUCC 0x1
131 #define BDC_CMDS_PARA 0x3
132 #define BDC_CMDS_STAT 0x4
133 #define BDC_CMDS_FAIL 0x5
134 #define BDC_CMDS_INTL 0x6
135 #define BDC_CMDS_BUSY 0xf
136
137 /* CMDSC Param 2 shifts */
138 #define EPT_SHIFT 22
139 #define MP_SHIFT 10
140 #define MB_SHIFT 6
141 #define EPM_SHIFT 4
142
143 /* BDC USPSC */
144 #define BDC_VBC (1 << 31)
145 #define BDC_PRC (1 << 30)
146 #define BDC_PCE (1 << 29)
147 #define BDC_CFC (1 << 28)
148 #define BDC_PCC (1 << 27)
149 #define BDC_PSC (1 << 26)
150 #define BDC_VBS (1 << 25)
151 #define BDC_PRS (1 << 24)
152 #define BDC_PCS (1 << 23)
153 #define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
154 #define BDC_SCN (1 << 8)
155 #define BDC_SDC (1 << 7)
156 #define BDC_SWS (1 << 4)
157
158 #define BDC_USPSC_RW (BDC_SCN|BDC_SDC|BDC_SWS|0xf)
159 #define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
160
161 #define BDC_SPEED_FS 0x1
162 #define BDC_SPEED_LS 0x2
163 #define BDC_SPEED_HS 0x3
164 #define BDC_SPEED_SS 0x4
165
166 #define BDC_PST(p) (p & 0xf)
167 #define BDC_PST_MASK 0xf
168
169 /* USPPMS */
170 #define BDC_U2E (0x1 << 31)
171 #define BDC_U1E (0x1 << 30)
172 #define BDC_U2A (0x1 << 29)
173 #define BDC_PORT_W1S (0x1 << 17)
174 #define BDC_U1T(p) ((p) & 0xff)
175 #define BDC_U2T(p) (((p) & 0xff) << 8)
176 #define BDC_U1T_MASK 0xff
177
178 /* USBPM2 */
179 /* Hardware LPM Enable */
180 #define BDC_HLE (1 << 16)
181
182 /* BDC Status and Control */
183 #define BDC_COP_RST (1 << 29)
184 #define BDC_COP_RUN (2 << 29)
185 #define BDC_COP_STP (4 << 29)
186
187 #define BDC_COP_MASK (BDC_COP_RST|BDC_COP_RUN|BDC_COP_STP)
188
189 #define BDC_COS (1 << 28)
190 #define BDC_CSTS(p) (((p) & (0x7 << 20)) >> 20)
191 #define BDC_MASK_MCW (1 << 7)
192 #define BDC_GIE (1 << 1)
193 #define BDC_GIP (1 << 0)
194
195 #define BDC_HLT 1
196 #define BDC_NOR 2
197 #define BDC_OIP 7
198
199 /* Buffer descriptor and Status report bit fields and masks */
200 #define BD_TYPE_BITMASK (0xf)
201 #define BD_CHAIN 0xf
202
203 #define BD_TFS_SHIFT 4
204 #define BD_SOT (1 << 26)
205 #define BD_EOT (1 << 27)
206 #define BD_ISP (1 << 29)
207 #define BD_IOC (1 << 30)
208 #define BD_SBF (1 << 31)
209
210 #define BD_INTR_TARGET(p) (((p) & 0x1f) << 27)
211
212 #define BDC_SRR_RWS (1 << 4)
213 #define BDC_SRR_RST (1 << 3)
214 #define BDC_SRR_ISR (1 << 2)
215 #define BDC_SRR_IE (1 << 1)
216 #define BDC_SRR_IP (1 << 0)
217 #define BDC_SRR_EPI(p) (((p) & (0xff << 24)) >> 24)
218 #define BDC_SRR_DPI(p) (((p) & (0xff << 16)) >> 16)
219 #define BDC_SRR_DPI_MASK 0x00ff0000
220
221 #define MARK_CHAIN_BD (BD_CHAIN|BD_EOT|BD_SOT)
222
223 /* Control transfer BD specific fields */
224 #define BD_DIR_IN (1 << 25)
225
226 #define BDC_PTC_MASK 0xf0000000
227
228 /* status report defines */
229 #define SR_XSF 0
230 #define SR_USPC 4
231 #define SR_BD_LEN(p) (p & 0xffffff)
232
233 #define XSF_SUCC 0x1
234 #define XSF_SHORT 0x3
235 #define XSF_BABB 0x4
236 #define XSF_SETUP_RECV 0x6
237 #define XSF_DATA_START 0x7
238 #define XSF_STATUS_START 0x8
239
240 #define XSF_STS(p) (((p) >> 28) & 0xf)
241
242 /* Transfer BD fields */
243 #define BD_LEN(p) ((p) & 0x1ffff)
244 #define BD_LTF (1 << 25)
245 #define BD_TYPE_DS 0x1
246 #define BD_TYPE_SS 0x2
247
248 #define BDC_EP_ENABLED (1 << 0)
249 #define BDC_EP_STALL (1 << 1)
250 #define BDC_EP_STOP (1 << 2)
251
252 /* One BD can transfer max 65536 bytes */
253 #define BD_MAX_BUFF_SIZE (1 << 16)
254 /* Maximum bytes in one XFR, Refer to BDC spec */
255 #define MAX_XFR_LEN 16777215
256
257 /* defines for Force Header command */
258 #define DEV_NOTF_TYPE 6
259 #define FWK_SUBTYPE 1
260 #define TRA_PACKET 4
261
262 #define to_bdc_ep(e) container_of(e, struct bdc_ep, usb_ep)
263 #define to_bdc_req(r) container_of(r, struct bdc_req, usb_req)
264 #define gadget_to_bdc(g) container_of(g, struct bdc, gadget)
265
266 /* FUNCTION WAKE DEV NOTIFICATION interval, USB3 spec table 8.13 */
267 #define BDC_TNOTIFY 2500 /*in ms*/
268 /* Devstatus bitfields */
269 #define REMOTE_WAKEUP_ISSUED (1 << 16)
270 #define DEVICE_SUSPENDED (1 << 17)
271 #define FUNC_WAKE_ISSUED (1 << 18)
272 #define REMOTE_WAKE_ENABLE (1 << USB_DEVICE_REMOTE_WAKEUP)
273
274 /* On disconnect, preserve these bits and clear rest */
275 #define DEVSTATUS_CLEAR (1 << USB_DEVICE_SELF_POWERED)
276 /* Hardware and software Data structures */
277
278 /* Endpoint bd: buffer descriptor */
279 struct bdc_bd {
280 __le32 offset[4];
281 };
282
283 /* Status report in Status report ring(srr) */
284 struct bdc_sr {
285 __le32 offset[4];
286 };
287
288 /* bd_table: contiguous bd's in a table */
289 struct bd_table {
290 struct bdc_bd *start_bd;
291 /* dma address of start bd of table*/
292 dma_addr_t dma;
293 };
294
295 /*
296 * Each endpoint has a bdl(buffer descriptor list), bdl consists of 1 or more bd
297 * table's chained to each other through a chain bd, every table has equal
298 * number of bds. the software uses bdi(bd index) to refer to particular bd in
299 * the list.
300 */
301 struct bd_list {
302 /* Array of bd table pointers*/
303 struct bd_table **bd_table_array;
304 /* How many tables chained to each other */
305 int num_tabs;
306 /* Max_bdi = num_tabs * num_bds_table - 1 */
307 int max_bdi;
308 /* current enq bdi from sw point of view */
309 int eqp_bdi;
310 /* current deq bdi from sw point of view */
311 int hwd_bdi;
312 /* numbers of bds per table */
313 int num_bds_table;
314 };
315
316 struct bdc_req;
317
318 /* Representation of a transfer, one transfer can have multiple bd's */
319 struct bd_transfer {
320 struct bdc_req *req;
321 /* start bd index */
322 int start_bdi;
323 /* this will be the next hw dqp when this transfer completes */
324 int next_hwd_bdi;
325 /* number of bds in this transfer */
326 int num_bds;
327 };
328
329 /*
330 * Representation of a gadget request, every gadget request is contained
331 * by 1 bd_transfer.
332 */
333 struct bdc_req {
334 struct usb_request usb_req;
335 struct list_head queue;
336 struct bdc_ep *ep;
337 /* only one Transfer per request */
338 struct bd_transfer bd_xfr;
339 int epnum;
340 };
341
342 /* scratchpad buffer needed by bdc hardware */
343 struct bdc_scratchpad {
344 dma_addr_t sp_dma;
345 void *buff;
346 u32 size;
347 };
348
349 /* endpoint representation */
350 struct bdc_ep {
351 struct usb_ep usb_ep;
352 struct list_head queue;
353 struct bdc *bdc;
354 u8 ep_type;
355 u8 dir;
356 u8 ep_num;
357 const struct usb_ss_ep_comp_descriptor *comp_desc;
358 const struct usb_endpoint_descriptor *desc;
359 unsigned int flags;
360 char name[20];
361 /* endpoint bd list*/
362 struct bd_list bd_list;
363 /*
364 * HW generates extra event for multi bd tranfers, this flag helps in
365 * ignoring the extra event
366 */
367 bool ignore_next_sr;
368 };
369
370 /* bdc cmmand parameter structure */
371 struct bdc_cmd_params {
372 u32 param2;
373 u32 param1;
374 u32 param0;
375 };
376
377 /* status report ring(srr), currently one srr is supported for entire system */
378 struct srr {
379 struct bdc_sr *sr_bds;
380 u16 eqp_index;
381 u16 dqp_index;
382 dma_addr_t dma_addr;
383 };
384
385 /* EP0 states */
386 enum bdc_ep0_state {
387 WAIT_FOR_SETUP = 0,
388 WAIT_FOR_DATA_START,
389 WAIT_FOR_DATA_XMIT,
390 WAIT_FOR_STATUS_START,
391 WAIT_FOR_STATUS_XMIT,
392 STATUS_PENDING
393 };
394
395 /* Link states */
396 enum bdc_link_state {
397 BDC_LINK_STATE_U0 = 0x00,
398 BDC_LINK_STATE_U3 = 0x03,
399 BDC_LINK_STATE_RX_DET = 0x05,
400 BDC_LINK_STATE_RESUME = 0x0f
401 };
402
403 /* representation of bdc */
404 struct bdc {
405 struct usb_gadget gadget;
406 struct usb_gadget_driver *gadget_driver;
407 struct device *dev;
408 /* device lock */
409 spinlock_t lock;
410
411 /* generic phy */
412 struct phy **phys;
413 int num_phys;
414 /* num of endpoints for a particular instantiation of IP */
415 unsigned int num_eps;
416 /*
417 * Array of ep's, it uses the same index covention as bdc hw i.e.
418 * 1 for ep0, 2 for 1out,3 for 1in ....
419 */
420 struct bdc_ep **bdc_ep_array;
421 void __iomem *regs;
422 struct bdc_scratchpad scratchpad;
423 u32 sp_buff_size;
424 /* current driver supports 1 status ring */
425 struct srr srr;
426 /* Last received setup packet */
427 struct usb_ctrlrequest setup_pkt;
428 struct bdc_req ep0_req;
429 struct bdc_req status_req;
430 enum bdc_ep0_state ep0_state;
431 bool delayed_status;
432 bool zlp_needed;
433 bool reinit;
434 bool pullup;
435 /* Bits 0-15 are standard and 16-31 for proprietary information */
436 u32 devstatus;
437 int irq;
438 void *mem;
439 u32 dev_addr;
440 /* DMA pools */
441 struct dma_pool *bd_table_pool;
442 u8 test_mode;
443 /* array of callbacks for various status report handlers */
444 void (*sr_handler[2])(struct bdc *, struct bdc_sr *);
445 /* ep0 callback handlers */
446 void (*sr_xsf_ep0[3])(struct bdc *, struct bdc_sr *);
447 /* ep0 response buffer for ch9 requests like GET_STATUS and SET_SEL */
448 unsigned char ep0_response_buff[EP0_RESPONSE_BUFF];
449 /*
450 * Timer to check if host resumed transfer after bdc sent Func wake
451 * notification packet after a remote wakeup. if not, then resend the
452 * Func Wake packet every 2.5 secs. Refer to USB3 spec section 8.5.6.4
453 */
454 struct delayed_work func_wake_notify;
455 struct clk *clk;
456 };
457
bdc_readl(void __iomem * base,u32 offset)458 static inline u32 bdc_readl(void __iomem *base, u32 offset)
459 {
460 return readl(base + offset);
461 }
462
bdc_writel(void __iomem * base,u32 offset,u32 value)463 static inline void bdc_writel(void __iomem *base, u32 offset, u32 value)
464 {
465 writel(value, base + offset);
466 }
467
468 /* Buffer descriptor list operations */
469 void bdc_notify_xfr(struct bdc *, u32);
470 void bdc_softconn(struct bdc *);
471 void bdc_softdisconn(struct bdc *);
472 int bdc_run(struct bdc *);
473 int bdc_stop(struct bdc *);
474 int bdc_reset(struct bdc *);
475 int bdc_udc_init(struct bdc *);
476 void bdc_udc_exit(struct bdc *);
477 int bdc_reinit(struct bdc *);
478
479 /* Status report handlers */
480 /* Upstream port status change sr */
481 void bdc_sr_uspc(struct bdc *, struct bdc_sr *);
482 /* transfer sr */
483 void bdc_sr_xsf(struct bdc *, struct bdc_sr *);
484 /* EP0 XSF handlers */
485 void bdc_xsf_ep0_setup_recv(struct bdc *, struct bdc_sr *);
486 void bdc_xsf_ep0_data_start(struct bdc *, struct bdc_sr *);
487 void bdc_xsf_ep0_status_start(struct bdc *, struct bdc_sr *);
488
489 #endif /* __LINUX_BDC_H__ */
490
