1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (c) 2018 BayLibre, SAS. 4 * Author: Jerome Brunet <jbrunet@baylibre.com> 5 */ 6 7 #ifndef __AXG_AUDIO_CLKC_H 8 #define __AXG_AUDIO_CLKC_H 9 10 /* 11 * Audio Clock register offsets 12 * 13 * Register offsets from the datasheet must be multiplied by 4 before 14 * to get the right offset 15 */ 16 #define AUDIO_CLK_GATE_EN 0x000 17 #define AUDIO_MCLK_A_CTRL 0x004 18 #define AUDIO_MCLK_B_CTRL 0x008 19 #define AUDIO_MCLK_C_CTRL 0x00C 20 #define AUDIO_MCLK_D_CTRL 0x010 21 #define AUDIO_MCLK_E_CTRL 0x014 22 #define AUDIO_MCLK_F_CTRL 0x018 23 #define AUDIO_MST_A_SCLK_CTRL0 0x040 24 #define AUDIO_MST_A_SCLK_CTRL1 0x044 25 #define AUDIO_MST_B_SCLK_CTRL0 0x048 26 #define AUDIO_MST_B_SCLK_CTRL1 0x04C 27 #define AUDIO_MST_C_SCLK_CTRL0 0x050 28 #define AUDIO_MST_C_SCLK_CTRL1 0x054 29 #define AUDIO_MST_D_SCLK_CTRL0 0x058 30 #define AUDIO_MST_D_SCLK_CTRL1 0x05C 31 #define AUDIO_MST_E_SCLK_CTRL0 0x060 32 #define AUDIO_MST_E_SCLK_CTRL1 0x064 33 #define AUDIO_MST_F_SCLK_CTRL0 0x068 34 #define AUDIO_MST_F_SCLK_CTRL1 0x06C 35 #define AUDIO_CLK_TDMIN_A_CTRL 0x080 36 #define AUDIO_CLK_TDMIN_B_CTRL 0x084 37 #define AUDIO_CLK_TDMIN_C_CTRL 0x088 38 #define AUDIO_CLK_TDMIN_LB_CTRL 0x08C 39 #define AUDIO_CLK_TDMOUT_A_CTRL 0x090 40 #define AUDIO_CLK_TDMOUT_B_CTRL 0x094 41 #define AUDIO_CLK_TDMOUT_C_CTRL 0x098 42 #define AUDIO_CLK_SPDIFIN_CTRL 0x09C 43 #define AUDIO_CLK_SPDIFOUT_CTRL 0x0A0 44 #define AUDIO_CLK_RESAMPLE_CTRL 0x0A4 45 #define AUDIO_CLK_LOCKER_CTRL 0x0A8 46 #define AUDIO_CLK_PDMIN_CTRL0 0x0AC 47 #define AUDIO_CLK_PDMIN_CTRL1 0x0B0 48 49 /* 50 * CLKID index values 51 * These indices are entirely contrived and do not map onto the hardware. 52 */ 53 54 #define AUD_CLKID_PCLK 0 55 #define AUD_CLKID_MST0 1 56 #define AUD_CLKID_MST1 2 57 #define AUD_CLKID_MST2 3 58 #define AUD_CLKID_MST3 4 59 #define AUD_CLKID_MST4 5 60 #define AUD_CLKID_MST5 6 61 #define AUD_CLKID_MST6 7 62 #define AUD_CLKID_MST7 8 63 #define AUD_CLKID_MST_A_MCLK_SEL 59 64 #define AUD_CLKID_MST_B_MCLK_SEL 60 65 #define AUD_CLKID_MST_C_MCLK_SEL 61 66 #define AUD_CLKID_MST_D_MCLK_SEL 62 67 #define AUD_CLKID_MST_E_MCLK_SEL 63 68 #define AUD_CLKID_MST_F_MCLK_SEL 64 69 #define AUD_CLKID_MST_A_MCLK_DIV 65 70 #define AUD_CLKID_MST_B_MCLK_DIV 66 71 #define AUD_CLKID_MST_C_MCLK_DIV 67 72 #define AUD_CLKID_MST_D_MCLK_DIV 68 73 #define AUD_CLKID_MST_E_MCLK_DIV 69 74 #define AUD_CLKID_MST_F_MCLK_DIV 70 75 #define AUD_CLKID_SPDIFOUT_CLK_SEL 71 76 #define AUD_CLKID_SPDIFOUT_CLK_DIV 72 77 #define AUD_CLKID_SPDIFIN_CLK_SEL 73 78 #define AUD_CLKID_SPDIFIN_CLK_DIV 74 79 #define AUD_CLKID_PDM_DCLK_SEL 75 80 #define AUD_CLKID_PDM_DCLK_DIV 76 81 #define AUD_CLKID_PDM_SYSCLK_SEL 77 82 #define AUD_CLKID_PDM_SYSCLK_DIV 78 83 #define AUD_CLKID_MST_A_SCLK_PRE_EN 92 84 #define AUD_CLKID_MST_B_SCLK_PRE_EN 93 85 #define AUD_CLKID_MST_C_SCLK_PRE_EN 94 86 #define AUD_CLKID_MST_D_SCLK_PRE_EN 95 87 #define AUD_CLKID_MST_E_SCLK_PRE_EN 96 88 #define AUD_CLKID_MST_F_SCLK_PRE_EN 97 89 #define AUD_CLKID_MST_A_SCLK_DIV 98 90 #define AUD_CLKID_MST_B_SCLK_DIV 99 91 #define AUD_CLKID_MST_C_SCLK_DIV 100 92 #define AUD_CLKID_MST_D_SCLK_DIV 101 93 #define AUD_CLKID_MST_E_SCLK_DIV 102 94 #define AUD_CLKID_MST_F_SCLK_DIV 103 95 #define AUD_CLKID_MST_A_SCLK_POST_EN 104 96 #define AUD_CLKID_MST_B_SCLK_POST_EN 105 97 #define AUD_CLKID_MST_C_SCLK_POST_EN 106 98 #define AUD_CLKID_MST_D_SCLK_POST_EN 107 99 #define AUD_CLKID_MST_E_SCLK_POST_EN 108 100 #define AUD_CLKID_MST_F_SCLK_POST_EN 109 101 #define AUD_CLKID_MST_A_LRCLK_DIV 110 102 #define AUD_CLKID_MST_B_LRCLK_DIV 111 103 #define AUD_CLKID_MST_C_LRCLK_DIV 112 104 #define AUD_CLKID_MST_D_LRCLK_DIV 113 105 #define AUD_CLKID_MST_E_LRCLK_DIV 114 106 #define AUD_CLKID_MST_F_LRCLK_DIV 115 107 #define AUD_CLKID_TDMIN_A_SCLK_PRE_EN 137 108 #define AUD_CLKID_TDMIN_B_SCLK_PRE_EN 138 109 #define AUD_CLKID_TDMIN_C_SCLK_PRE_EN 139 110 #define AUD_CLKID_TDMIN_LB_SCLK_PRE_EN 140 111 #define AUD_CLKID_TDMOUT_A_SCLK_PRE_EN 141 112 #define AUD_CLKID_TDMOUT_B_SCLK_PRE_EN 142 113 #define AUD_CLKID_TDMOUT_C_SCLK_PRE_EN 143 114 #define AUD_CLKID_TDMIN_A_SCLK_POST_EN 144 115 #define AUD_CLKID_TDMIN_B_SCLK_POST_EN 145 116 #define AUD_CLKID_TDMIN_C_SCLK_POST_EN 146 117 #define AUD_CLKID_TDMIN_LB_SCLK_POST_EN 147 118 #define AUD_CLKID_TDMOUT_A_SCLK_POST_EN 148 119 #define AUD_CLKID_TDMOUT_B_SCLK_POST_EN 149 120 #define AUD_CLKID_TDMOUT_C_SCLK_POST_EN 150 121 122 /* include the CLKIDs which are part of the DT bindings */ 123 #include <dt-bindings/clock/axg-audio-clkc.h> 124 125 #define NR_CLKS 151 126 127 #endif /*__AXG_AUDIO_CLKC_H */ 128
