1 /****************************************************************************\ 2 * 3 * File Name atomfirmware.h 4 * Project This is an interface header file between atombios and OS GPU drivers for SoC15 products 5 * 6 * Description header file of general definitions for OS nd pre-OS video drivers 7 * 8 * Copyright 2014 Advanced Micro Devices, Inc. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software 11 * and associated documentation files (the "Software"), to deal in the Software without restriction, 12 * including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, 13 * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, 14 * subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 25 * OTHER DEALINGS IN THE SOFTWARE. 26 * 27 \****************************************************************************/ 28 29 /*IMPORTANT NOTES 30 * If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file. 31 * If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file. 32 * If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h. 33 */ 34 35 #ifndef _ATOMFIRMWARE_H_ 36 #define _ATOMFIRMWARE_H_ 37 38 enum atom_bios_header_version_def{ 39 ATOM_MAJOR_VERSION =0x0003, 40 ATOM_MINOR_VERSION =0x0003, 41 }; 42 43 #ifdef _H2INC 44 #ifndef uint32_t 45 typedef unsigned long uint32_t; 46 #endif 47 48 #ifndef uint16_t 49 typedef unsigned short uint16_t; 50 #endif 51 52 #ifndef uint8_t 53 typedef unsigned char uint8_t; 54 #endif 55 #endif 56 57 enum atom_crtc_def{ 58 ATOM_CRTC1 =0, 59 ATOM_CRTC2 =1, 60 ATOM_CRTC3 =2, 61 ATOM_CRTC4 =3, 62 ATOM_CRTC5 =4, 63 ATOM_CRTC6 =5, 64 ATOM_CRTC_INVALID =0xff, 65 }; 66 67 enum atom_ppll_def{ 68 ATOM_PPLL0 =2, 69 ATOM_GCK_DFS =8, 70 ATOM_FCH_CLK =9, 71 ATOM_DP_DTO =11, 72 ATOM_COMBOPHY_PLL0 =20, 73 ATOM_COMBOPHY_PLL1 =21, 74 ATOM_COMBOPHY_PLL2 =22, 75 ATOM_COMBOPHY_PLL3 =23, 76 ATOM_COMBOPHY_PLL4 =24, 77 ATOM_COMBOPHY_PLL5 =25, 78 ATOM_PPLL_INVALID =0xff, 79 }; 80 81 // define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel 82 enum atom_dig_def{ 83 ASIC_INT_DIG1_ENCODER_ID =0x03, 84 ASIC_INT_DIG2_ENCODER_ID =0x09, 85 ASIC_INT_DIG3_ENCODER_ID =0x0a, 86 ASIC_INT_DIG4_ENCODER_ID =0x0b, 87 ASIC_INT_DIG5_ENCODER_ID =0x0c, 88 ASIC_INT_DIG6_ENCODER_ID =0x0d, 89 ASIC_INT_DIG7_ENCODER_ID =0x0e, 90 }; 91 92 //ucEncoderMode 93 enum atom_encode_mode_def 94 { 95 ATOM_ENCODER_MODE_DP =0, 96 ATOM_ENCODER_MODE_DP_SST =0, 97 ATOM_ENCODER_MODE_LVDS =1, 98 ATOM_ENCODER_MODE_DVI =2, 99 ATOM_ENCODER_MODE_HDMI =3, 100 ATOM_ENCODER_MODE_DP_AUDIO =5, 101 ATOM_ENCODER_MODE_DP_MST =5, 102 ATOM_ENCODER_MODE_CRT =15, 103 ATOM_ENCODER_MODE_DVO =16, 104 }; 105 106 enum atom_encoder_refclk_src_def{ 107 ENCODER_REFCLK_SRC_P1PLL =0, 108 ENCODER_REFCLK_SRC_P2PLL =1, 109 ENCODER_REFCLK_SRC_P3PLL =2, 110 ENCODER_REFCLK_SRC_EXTCLK =3, 111 ENCODER_REFCLK_SRC_INVALID =0xff, 112 }; 113 114 enum atom_scaler_def{ 115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/ 116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication 117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/ 118 }; 119 120 enum atom_operation_def{ 121 ATOM_DISABLE = 0, 122 ATOM_ENABLE = 1, 123 ATOM_INIT = 7, 124 ATOM_GET_STATUS = 8, 125 }; 126 127 enum atom_embedded_display_op_def{ 128 ATOM_LCD_BL_OFF = 2, 129 ATOM_LCD_BL_OM = 3, 130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4, 131 ATOM_LCD_SELFTEST_START = 5, 132 ATOM_LCD_SELFTEST_STOP = 6, 133 }; 134 135 enum atom_spread_spectrum_mode{ 136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01, 137 ATOM_SS_DOWN_SPREAD_MODE = 0x00, 138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01, 139 ATOM_INT_OR_EXT_SS_MASK = 0x02, 140 ATOM_INTERNAL_SS_MASK = 0x00, 141 ATOM_EXTERNAL_SS_MASK = 0x02, 142 }; 143 144 /* define panel bit per color */ 145 enum atom_panel_bit_per_color{ 146 PANEL_BPC_UNDEFINE =0x00, 147 PANEL_6BIT_PER_COLOR =0x01, 148 PANEL_8BIT_PER_COLOR =0x02, 149 PANEL_10BIT_PER_COLOR =0x03, 150 PANEL_12BIT_PER_COLOR =0x04, 151 PANEL_16BIT_PER_COLOR =0x05, 152 }; 153 154 //ucVoltageType 155 enum atom_voltage_type 156 { 157 VOLTAGE_TYPE_VDDC = 1, 158 VOLTAGE_TYPE_MVDDC = 2, 159 VOLTAGE_TYPE_MVDDQ = 3, 160 VOLTAGE_TYPE_VDDCI = 4, 161 VOLTAGE_TYPE_VDDGFX = 5, 162 VOLTAGE_TYPE_PCC = 6, 163 VOLTAGE_TYPE_MVPP = 7, 164 VOLTAGE_TYPE_LEDDPM = 8, 165 VOLTAGE_TYPE_PCC_MVDD = 9, 166 VOLTAGE_TYPE_PCIE_VDDC = 10, 167 VOLTAGE_TYPE_PCIE_VDDR = 11, 168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11, 169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12, 170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13, 171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14, 172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15, 173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16, 174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17, 175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18, 176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19, 177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A, 178 }; 179 180 enum atom_dgpu_vram_type { 181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50, 182 ATOM_DGPU_VRAM_TYPE_HBM2 = 0x60, 183 ATOM_DGPU_VRAM_TYPE_GDDR6 = 0x70, 184 }; 185 186 enum atom_dp_vs_preemph_def{ 187 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00, 188 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01, 189 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02, 190 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03, 191 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08, 192 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09, 193 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a, 194 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10, 195 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11, 196 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18, 197 }; 198 199 200 /* 201 enum atom_string_def{ 202 asic_bus_type_pcie_string = "PCI_EXPRESS", 203 atom_fire_gl_string = "FGL", 204 atom_bios_string = "ATOM" 205 }; 206 */ 207 208 #pragma pack(1) /* BIOS data must use byte aligment*/ 209 210 enum atombios_image_offset{ 211 OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048, 212 OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002, 213 OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94, 214 MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/ 215 OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f, 216 OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e, 217 }; 218 219 /**************************************************************************** 220 * Common header for all tables (Data table, Command function). 221 * Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header. 222 * And the pointer actually points to this header. 223 ****************************************************************************/ 224 225 struct atom_common_table_header 226 { 227 uint16_t structuresize; 228 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible 229 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change 230 }; 231 232 /**************************************************************************** 233 * Structure stores the ROM header. 234 ****************************************************************************/ 235 struct atom_rom_header_v2_2 236 { 237 struct atom_common_table_header table_header; 238 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios, 239 uint16_t bios_segment_address; 240 uint16_t protectedmodeoffset; 241 uint16_t configfilenameoffset; 242 uint16_t crc_block_offset; 243 uint16_t vbios_bootupmessageoffset; 244 uint16_t int10_offset; 245 uint16_t pcibusdevinitcode; 246 uint16_t iobaseaddress; 247 uint16_t subsystem_vendor_id; 248 uint16_t subsystem_id; 249 uint16_t pci_info_offset; 250 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position 251 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position 252 uint16_t reserved; 253 uint32_t pspdirtableoffset; 254 }; 255 256 /*==============================hw function portion======================================================================*/ 257 258 259 /**************************************************************************** 260 * Structures used in Command.mtb, each function name is not given here since those function could change from time to time 261 * The real functionality of each function is associated with the parameter structure version when defined 262 * For all internal cmd function definitions, please reference to atomstruct.h 263 ****************************************************************************/ 264 struct atom_master_list_of_command_functions_v2_1{ 265 uint16_t asic_init; //Function 266 uint16_t cmd_function1; //used as an internal one 267 uint16_t cmd_function2; //used as an internal one 268 uint16_t cmd_function3; //used as an internal one 269 uint16_t digxencodercontrol; //Function 270 uint16_t cmd_function5; //used as an internal one 271 uint16_t cmd_function6; //used as an internal one 272 uint16_t cmd_function7; //used as an internal one 273 uint16_t cmd_function8; //used as an internal one 274 uint16_t cmd_function9; //used as an internal one 275 uint16_t setengineclock; //Function 276 uint16_t setmemoryclock; //Function 277 uint16_t setpixelclock; //Function 278 uint16_t enabledisppowergating; //Function 279 uint16_t cmd_function14; //used as an internal one 280 uint16_t cmd_function15; //used as an internal one 281 uint16_t cmd_function16; //used as an internal one 282 uint16_t cmd_function17; //used as an internal one 283 uint16_t cmd_function18; //used as an internal one 284 uint16_t cmd_function19; //used as an internal one 285 uint16_t cmd_function20; //used as an internal one 286 uint16_t cmd_function21; //used as an internal one 287 uint16_t cmd_function22; //used as an internal one 288 uint16_t cmd_function23; //used as an internal one 289 uint16_t cmd_function24; //used as an internal one 290 uint16_t cmd_function25; //used as an internal one 291 uint16_t cmd_function26; //used as an internal one 292 uint16_t cmd_function27; //used as an internal one 293 uint16_t cmd_function28; //used as an internal one 294 uint16_t cmd_function29; //used as an internal one 295 uint16_t cmd_function30; //used as an internal one 296 uint16_t cmd_function31; //used as an internal one 297 uint16_t cmd_function32; //used as an internal one 298 uint16_t cmd_function33; //used as an internal one 299 uint16_t blankcrtc; //Function 300 uint16_t enablecrtc; //Function 301 uint16_t cmd_function36; //used as an internal one 302 uint16_t cmd_function37; //used as an internal one 303 uint16_t cmd_function38; //used as an internal one 304 uint16_t cmd_function39; //used as an internal one 305 uint16_t cmd_function40; //used as an internal one 306 uint16_t getsmuclockinfo; //Function 307 uint16_t selectcrtc_source; //Function 308 uint16_t cmd_function43; //used as an internal one 309 uint16_t cmd_function44; //used as an internal one 310 uint16_t cmd_function45; //used as an internal one 311 uint16_t setdceclock; //Function 312 uint16_t getmemoryclock; //Function 313 uint16_t getengineclock; //Function 314 uint16_t setcrtc_usingdtdtiming; //Function 315 uint16_t externalencodercontrol; //Function 316 uint16_t cmd_function51; //used as an internal one 317 uint16_t cmd_function52; //used as an internal one 318 uint16_t cmd_function53; //used as an internal one 319 uint16_t processi2cchanneltransaction;//Function 320 uint16_t cmd_function55; //used as an internal one 321 uint16_t cmd_function56; //used as an internal one 322 uint16_t cmd_function57; //used as an internal one 323 uint16_t cmd_function58; //used as an internal one 324 uint16_t cmd_function59; //used as an internal one 325 uint16_t computegpuclockparam; //Function 326 uint16_t cmd_function61; //used as an internal one 327 uint16_t cmd_function62; //used as an internal one 328 uint16_t dynamicmemorysettings; //Function function 329 uint16_t memorytraining; //Function function 330 uint16_t cmd_function65; //used as an internal one 331 uint16_t cmd_function66; //used as an internal one 332 uint16_t setvoltage; //Function 333 uint16_t cmd_function68; //used as an internal one 334 uint16_t readefusevalue; //Function 335 uint16_t cmd_function70; //used as an internal one 336 uint16_t cmd_function71; //used as an internal one 337 uint16_t cmd_function72; //used as an internal one 338 uint16_t cmd_function73; //used as an internal one 339 uint16_t cmd_function74; //used as an internal one 340 uint16_t cmd_function75; //used as an internal one 341 uint16_t dig1transmittercontrol; //Function 342 uint16_t cmd_function77; //used as an internal one 343 uint16_t processauxchanneltransaction;//Function 344 uint16_t cmd_function79; //used as an internal one 345 uint16_t getvoltageinfo; //Function 346 }; 347 348 struct atom_master_command_function_v2_1 349 { 350 struct atom_common_table_header table_header; 351 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions; 352 }; 353 354 /**************************************************************************** 355 * Structures used in every command function 356 ****************************************************************************/ 357 struct atom_function_attribute 358 { 359 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword), 360 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword), 361 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util 362 }; 363 364 365 /**************************************************************************** 366 * Common header for all hw functions. 367 * Every function pointed by _master_list_of_hw_function has this common header. 368 * And the pointer actually points to this header. 369 ****************************************************************************/ 370 struct atom_rom_hw_function_header 371 { 372 struct atom_common_table_header func_header; 373 struct atom_function_attribute func_attrib; 374 }; 375 376 377 /*==============================sw data table portion======================================================================*/ 378 /**************************************************************************** 379 * Structures used in data.mtb, each data table name is not given here since those data table could change from time to time 380 * The real name of each table is given when its data structure version is defined 381 ****************************************************************************/ 382 struct atom_master_list_of_data_tables_v2_1{ 383 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/ 384 uint16_t multimedia_info; 385 uint16_t smc_dpm_info; 386 uint16_t sw_datatable3; 387 uint16_t firmwareinfo; /* Shared by various SW components */ 388 uint16_t sw_datatable5; 389 uint16_t lcd_info; /* Shared by various SW components */ 390 uint16_t sw_datatable7; 391 uint16_t smu_info; 392 uint16_t sw_datatable9; 393 uint16_t sw_datatable10; 394 uint16_t vram_usagebyfirmware; /* Shared by various SW components */ 395 uint16_t gpio_pin_lut; /* Shared by various SW components */ 396 uint16_t sw_datatable13; 397 uint16_t gfx_info; 398 uint16_t powerplayinfo; /* Shared by various SW components */ 399 uint16_t sw_datatable16; 400 uint16_t sw_datatable17; 401 uint16_t sw_datatable18; 402 uint16_t sw_datatable19; 403 uint16_t sw_datatable20; 404 uint16_t sw_datatable21; 405 uint16_t displayobjectinfo; /* Shared by various SW components */ 406 uint16_t indirectioaccess; /* used as an internal one */ 407 uint16_t umc_info; /* Shared by various SW components */ 408 uint16_t sw_datatable25; 409 uint16_t sw_datatable26; 410 uint16_t dce_info; /* Shared by various SW components */ 411 uint16_t vram_info; /* Shared by various SW components */ 412 uint16_t sw_datatable29; 413 uint16_t integratedsysteminfo; /* Shared by various SW components */ 414 uint16_t asic_profiling_info; /* Shared by various SW components */ 415 uint16_t voltageobject_info; /* shared by various SW components */ 416 uint16_t sw_datatable33; 417 uint16_t sw_datatable34; 418 }; 419 420 421 struct atom_master_data_table_v2_1 422 { 423 struct atom_common_table_header table_header; 424 struct atom_master_list_of_data_tables_v2_1 listOfdatatables; 425 }; 426 427 428 struct atom_dtd_format 429 { 430 uint16_t pixclk; 431 uint16_t h_active; 432 uint16_t h_blanking_time; 433 uint16_t v_active; 434 uint16_t v_blanking_time; 435 uint16_t h_sync_offset; 436 uint16_t h_sync_width; 437 uint16_t v_sync_offset; 438 uint16_t v_syncwidth; 439 uint16_t reserved; 440 uint16_t reserved0; 441 uint8_t h_border; 442 uint8_t v_border; 443 uint16_t miscinfo; 444 uint8_t atom_mode_id; 445 uint8_t refreshrate; 446 }; 447 448 /* atom_dtd_format.modemiscinfo defintion */ 449 enum atom_dtd_format_modemiscinfo{ 450 ATOM_HSYNC_POLARITY = 0x0002, 451 ATOM_VSYNC_POLARITY = 0x0004, 452 ATOM_H_REPLICATIONBY2 = 0x0010, 453 ATOM_V_REPLICATIONBY2 = 0x0020, 454 ATOM_INTERLACE = 0x0080, 455 ATOM_COMPOSITESYNC = 0x0040, 456 }; 457 458 459 /* utilitypipeline 460 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it. 461 * the location of it can't change 462 */ 463 464 465 /* 466 *************************************************************************** 467 Data Table firmwareinfo structure 468 *************************************************************************** 469 */ 470 471 struct atom_firmware_info_v3_1 472 { 473 struct atom_common_table_header table_header; 474 uint32_t firmware_revision; 475 uint32_t bootup_sclk_in10khz; 476 uint32_t bootup_mclk_in10khz; 477 uint32_t firmware_capability; // enum atombios_firmware_capability 478 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 479 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 480 uint16_t bootup_vddc_mv; 481 uint16_t bootup_vddci_mv; 482 uint16_t bootup_mvddc_mv; 483 uint16_t bootup_vddgfx_mv; 484 uint8_t mem_module_id; 485 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 486 uint8_t reserved1[2]; 487 uint32_t mc_baseaddr_high; 488 uint32_t mc_baseaddr_low; 489 uint32_t reserved2[6]; 490 }; 491 492 /* Total 32bit cap indication */ 493 enum atombios_firmware_capability 494 { 495 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001, 496 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002, 497 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040, 498 ATOM_FIRMWARE_CAP_HWEMU_ENABLE = 0x00000080, 499 ATOM_FIRMWARE_CAP_HWEMU_UMC_CFG = 0x00000100, 500 ATOM_FIRMWARE_CAP_SRAM_ECC = 0x00000200, 501 }; 502 503 enum atom_cooling_solution_id{ 504 AIR_COOLING = 0x00, 505 LIQUID_COOLING = 0x01 506 }; 507 508 struct atom_firmware_info_v3_2 { 509 struct atom_common_table_header table_header; 510 uint32_t firmware_revision; 511 uint32_t bootup_sclk_in10khz; 512 uint32_t bootup_mclk_in10khz; 513 uint32_t firmware_capability; // enum atombios_firmware_capability 514 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 515 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 516 uint16_t bootup_vddc_mv; 517 uint16_t bootup_vddci_mv; 518 uint16_t bootup_mvddc_mv; 519 uint16_t bootup_vddgfx_mv; 520 uint8_t mem_module_id; 521 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 522 uint8_t reserved1[2]; 523 uint32_t mc_baseaddr_high; 524 uint32_t mc_baseaddr_low; 525 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 526 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 527 uint8_t board_i2c_feature_slave_addr; 528 uint8_t reserved3; 529 uint16_t bootup_mvddq_mv; 530 uint16_t bootup_mvpp_mv; 531 uint32_t zfbstartaddrin16mb; 532 uint32_t reserved2[3]; 533 }; 534 535 struct atom_firmware_info_v3_3 536 { 537 struct atom_common_table_header table_header; 538 uint32_t firmware_revision; 539 uint32_t bootup_sclk_in10khz; 540 uint32_t bootup_mclk_in10khz; 541 uint32_t firmware_capability; // enum atombios_firmware_capability 542 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */ 543 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address 544 uint16_t bootup_vddc_mv; 545 uint16_t bootup_vddci_mv; 546 uint16_t bootup_mvddc_mv; 547 uint16_t bootup_vddgfx_mv; 548 uint8_t mem_module_id; 549 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */ 550 uint8_t reserved1[2]; 551 uint32_t mc_baseaddr_high; 552 uint32_t mc_baseaddr_low; 553 uint8_t board_i2c_feature_id; // enum of atom_board_i2c_feature_id_def 554 uint8_t board_i2c_feature_gpio_id; // i2c id find in gpio_lut data table gpio_id 555 uint8_t board_i2c_feature_slave_addr; 556 uint8_t reserved3; 557 uint16_t bootup_mvddq_mv; 558 uint16_t bootup_mvpp_mv; 559 uint32_t zfbstartaddrin16mb; 560 uint32_t pplib_pptable_id; // if pplib_pptable_id!=0, pplib get powerplay table inside driver instead of from VBIOS 561 uint32_t reserved2[2]; 562 }; 563 564 /* 565 *************************************************************************** 566 Data Table lcd_info structure 567 *************************************************************************** 568 */ 569 570 struct lcd_info_v2_1 571 { 572 struct atom_common_table_header table_header; 573 struct atom_dtd_format lcd_timing; 574 uint16_t backlight_pwm; 575 uint16_t special_handle_cap; 576 uint16_t panel_misc; 577 uint16_t lvds_max_slink_pclk; 578 uint16_t lvds_ss_percentage; 579 uint16_t lvds_ss_rate_10hz; 580 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/ 581 uint8_t pwr_on_de_to_vary_bl; 582 uint8_t pwr_down_vary_bloff_to_de; 583 uint8_t pwr_down_de_to_digoff; 584 uint8_t pwr_off_delay; 585 uint8_t pwr_on_vary_bl_to_blon; 586 uint8_t pwr_down_bloff_to_vary_bloff; 587 uint8_t panel_bpc; 588 uint8_t dpcd_edp_config_cap; 589 uint8_t dpcd_max_link_rate; 590 uint8_t dpcd_max_lane_count; 591 uint8_t dpcd_max_downspread; 592 uint8_t min_allowed_bl_level; 593 uint8_t max_allowed_bl_level; 594 uint8_t bootup_bl_level; 595 uint8_t dplvdsrxid; 596 uint32_t reserved1[8]; 597 }; 598 599 /* lcd_info_v2_1.panel_misc defintion */ 600 enum atom_lcd_info_panel_misc{ 601 ATOM_PANEL_MISC_FPDI =0x0002, 602 }; 603 604 //uceDPToLVDSRxId 605 enum atom_lcd_info_dptolvds_rx_id 606 { 607 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip 608 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init 609 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init 610 }; 611 612 613 /* 614 *************************************************************************** 615 Data Table gpio_pin_lut structure 616 *************************************************************************** 617 */ 618 619 struct atom_gpio_pin_assignment 620 { 621 uint32_t data_a_reg_index; 622 uint8_t gpio_bitshift; 623 uint8_t gpio_mask_bitshift; 624 uint8_t gpio_id; 625 uint8_t reserved; 626 }; 627 628 /* atom_gpio_pin_assignment.gpio_id definition */ 629 enum atom_gpio_pin_assignment_gpio_id { 630 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */ 631 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */ 632 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */ 633 634 /* gpio_id pre-define id for multiple usage */ 635 /* GPIO use to control PCIE_VDDC in certain SLT board */ 636 PCIE_VDDC_CONTROL_GPIO_PINID = 56, 637 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */ 638 PP_AC_DC_SWITCH_GPIO_PINID = 60, 639 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */ 640 VDDC_VRHOT_GPIO_PINID = 61, 641 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */ 642 VDDC_PCC_GPIO_PINID = 62, 643 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */ 644 EFUSE_CUT_ENABLE_GPIO_PINID = 63, 645 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */ 646 DRAM_SELF_REFRESH_GPIO_PINID = 64, 647 /* Thermal interrupt output->system thermal chip GPIO pin */ 648 THERMAL_INT_OUTPUT_GPIO_PINID =65, 649 }; 650 651 652 struct atom_gpio_pin_lut_v2_1 653 { 654 struct atom_common_table_header table_header; 655 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */ 656 struct atom_gpio_pin_assignment gpio_pin[8]; 657 }; 658 659 660 /* 661 *************************************************************************** 662 Data Table vram_usagebyfirmware structure 663 *************************************************************************** 664 */ 665 666 struct vram_usagebyfirmware_v2_1 667 { 668 struct atom_common_table_header table_header; 669 uint32_t start_address_in_kb; 670 uint16_t used_by_firmware_in_kb; 671 uint16_t used_by_driver_in_kb; 672 }; 673 674 675 /* 676 *************************************************************************** 677 Data Table displayobjectinfo structure 678 *************************************************************************** 679 */ 680 681 enum atom_object_record_type_id 682 { 683 ATOM_I2C_RECORD_TYPE =1, 684 ATOM_HPD_INT_RECORD_TYPE =2, 685 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9, 686 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16, 687 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17, 688 ATOM_ENCODER_CAP_RECORD_TYPE=20, 689 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21, 690 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22, 691 ATOM_RECORD_END_TYPE =0xFF, 692 }; 693 694 struct atom_common_record_header 695 { 696 uint8_t record_type; //An emun to indicate the record type 697 uint8_t record_size; //The size of the whole record in byte 698 }; 699 700 struct atom_i2c_record 701 { 702 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE 703 uint8_t i2c_id; 704 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC 705 }; 706 707 struct atom_hpd_int_record 708 { 709 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE 710 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info 711 uint8_t plugin_pin_state; 712 }; 713 714 // Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap 715 enum atom_encoder_caps_def 716 { 717 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN 718 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not. 719 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled 720 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not. 721 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board. 722 ATOM_ENCODER_CAP_RECORD_USB_C_TYPE =0x100, // the DP connector is a USB-C type. 723 }; 724 725 struct atom_encoder_caps_record 726 { 727 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE 728 uint32_t encodercaps; 729 }; 730 731 enum atom_connector_caps_def 732 { 733 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display 734 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq 735 }; 736 737 struct atom_disp_connector_caps_record 738 { 739 struct atom_common_record_header record_header; 740 uint32_t connectcaps; 741 }; 742 743 //The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually 744 struct atom_gpio_pin_control_pair 745 { 746 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table 747 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin 748 }; 749 750 struct atom_object_gpio_cntl_record 751 { 752 struct atom_common_record_header record_header; 753 uint8_t flag; // Future expnadibility 754 uint8_t number_of_pins; // Number of GPIO pins used to control the object 755 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins 756 }; 757 758 //Definitions for GPIO pin state 759 enum atom_gpio_pin_control_pinstate_def 760 { 761 GPIO_PIN_TYPE_INPUT = 0x00, 762 GPIO_PIN_TYPE_OUTPUT = 0x10, 763 GPIO_PIN_TYPE_HW_CONTROL = 0x20, 764 765 //For GPIO_PIN_TYPE_OUTPUT the following is defined 766 GPIO_PIN_OUTPUT_STATE_MASK = 0x01, 767 GPIO_PIN_OUTPUT_STATE_SHIFT = 0, 768 GPIO_PIN_STATE_ACTIVE_LOW = 0x0, 769 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1, 770 }; 771 772 // Indexes to GPIO array in GLSync record 773 // GLSync record is for Frame Lock/Gen Lock feature. 774 enum atom_glsync_record_gpio_index_def 775 { 776 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0, 777 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1, 778 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2, 779 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3, 780 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4, 781 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5, 782 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6, 783 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7, 784 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8, 785 ATOM_GPIO_INDEX_GLSYNC_MAX = 9, 786 }; 787 788 789 struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE 790 { 791 struct atom_common_record_header record_header; 792 uint8_t hpd_pin_map[8]; 793 }; 794 795 struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE 796 { 797 struct atom_common_record_header record_header; 798 uint8_t aux_ddc_map[8]; 799 }; 800 801 struct atom_connector_forced_tmds_cap_record 802 { 803 struct atom_common_record_header record_header; 804 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5 805 uint8_t maxtmdsclkrate_in2_5mhz; 806 uint8_t reserved; 807 }; 808 809 struct atom_connector_layout_info 810 { 811 uint16_t connectorobjid; 812 uint8_t connector_type; 813 uint8_t position; 814 }; 815 816 // define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size 817 enum atom_connector_layout_info_connector_type_def 818 { 819 CONNECTOR_TYPE_DVI_D = 1, 820 821 CONNECTOR_TYPE_HDMI = 4, 822 CONNECTOR_TYPE_DISPLAY_PORT = 5, 823 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6, 824 }; 825 826 struct atom_bracket_layout_record 827 { 828 struct atom_common_record_header record_header; 829 uint8_t bracketlen; 830 uint8_t bracketwidth; 831 uint8_t conn_num; 832 uint8_t reserved; 833 struct atom_connector_layout_info conn_info[1]; 834 }; 835 836 enum atom_display_device_tag_def{ 837 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display 838 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008, 839 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080, 840 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200, 841 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400, 842 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800, 843 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040, 844 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8, 845 }; 846 847 struct atom_display_object_path_v2 848 { 849 uint16_t display_objid; //Connector Object ID or Misc Object ID 850 uint16_t disp_recordoffset; 851 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder 852 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view; 853 uint16_t encoder_recordoffset; 854 uint16_t extencoder_recordoffset; 855 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first 856 uint8_t priority_id; 857 uint8_t reserved; 858 }; 859 860 struct display_object_info_table_v1_4 861 { 862 struct atom_common_table_header table_header; 863 uint16_t supporteddevices; 864 uint8_t number_of_path; 865 uint8_t reserved; 866 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path 867 }; 868 869 870 /* 871 *************************************************************************** 872 Data Table dce_info structure 873 *************************************************************************** 874 */ 875 struct atom_display_controller_info_v4_1 876 { 877 struct atom_common_table_header table_header; 878 uint32_t display_caps; 879 uint32_t bootup_dispclk_10khz; 880 uint16_t dce_refclk_10khz; 881 uint16_t i2c_engine_refclk_10khz; 882 uint16_t dvi_ss_percentage; // in unit of 0.001% 883 uint16_t dvi_ss_rate_10hz; 884 uint16_t hdmi_ss_percentage; // in unit of 0.001% 885 uint16_t hdmi_ss_rate_10hz; 886 uint16_t dp_ss_percentage; // in unit of 0.001% 887 uint16_t dp_ss_rate_10hz; 888 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 889 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 890 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 891 uint8_t ss_reserved; 892 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available 893 uint8_t reserved1[3]; 894 uint16_t dpphy_refclk_10khz; 895 uint16_t reserved2; 896 uint8_t dceip_min_ver; 897 uint8_t dceip_max_ver; 898 uint8_t max_disp_pipe_num; 899 uint8_t max_vbios_active_disp_pipe_num; 900 uint8_t max_ppll_num; 901 uint8_t max_disp_phy_num; 902 uint8_t max_aux_pairs; 903 uint8_t remotedisplayconfig; 904 uint8_t reserved3[8]; 905 }; 906 907 908 struct atom_display_controller_info_v4_2 909 { 910 struct atom_common_table_header table_header; 911 uint32_t display_caps; 912 uint32_t bootup_dispclk_10khz; 913 uint16_t dce_refclk_10khz; 914 uint16_t i2c_engine_refclk_10khz; 915 uint16_t dvi_ss_percentage; // in unit of 0.001% 916 uint16_t dvi_ss_rate_10hz; 917 uint16_t hdmi_ss_percentage; // in unit of 0.001% 918 uint16_t hdmi_ss_rate_10hz; 919 uint16_t dp_ss_percentage; // in unit of 0.001% 920 uint16_t dp_ss_rate_10hz; 921 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode 922 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode 923 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode 924 uint8_t ss_reserved; 925 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available 926 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available 927 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 928 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable 929 uint16_t dpphy_refclk_10khz; 930 uint16_t reserved2; 931 uint8_t dcnip_min_ver; 932 uint8_t dcnip_max_ver; 933 uint8_t max_disp_pipe_num; 934 uint8_t max_vbios_active_disp_pipe_num; 935 uint8_t max_ppll_num; 936 uint8_t max_disp_phy_num; 937 uint8_t max_aux_pairs; 938 uint8_t remotedisplayconfig; 939 uint8_t reserved3[8]; 940 }; 941 942 943 enum dce_info_caps_def 944 { 945 // only for VBIOS 946 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02, 947 // only for VBIOS 948 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04, 949 // only for VBIOS 950 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08, 951 952 }; 953 954 /* 955 *************************************************************************** 956 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure 957 *************************************************************************** 958 */ 959 struct atom_ext_display_path 960 { 961 uint16_t device_tag; //A bit vector to show what devices are supported 962 uint16_t device_acpi_enum; //16bit device ACPI id. 963 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions 964 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT 965 uint8_t hpdlut_index; //An index into external HPD pin LUT 966 uint16_t ext_encoder_objid; //external encoder object id 967 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping 968 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted 969 uint16_t caps; 970 uint16_t reserved; 971 }; 972 973 //usCaps 974 enum ext_display_path_cap_def 975 { 976 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001, 977 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002, 978 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C, 979 }; 980 981 struct atom_external_display_connection_info 982 { 983 struct atom_common_table_header table_header; 984 uint8_t guid[16]; // a GUID is a 16 byte long string 985 struct atom_ext_display_path path[7]; // total of fixed 7 entries. 986 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0. 987 uint8_t stereopinid; // use for eDP panel 988 uint8_t remotedisplayconfig; 989 uint8_t edptolvdsrxid; 990 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value 991 uint8_t reserved[3]; // for potential expansion 992 }; 993 994 /* 995 *************************************************************************** 996 Data Table integratedsysteminfo structure 997 *************************************************************************** 998 */ 999 1000 struct atom_camera_dphy_timing_param 1001 { 1002 uint8_t profile_id; // SENSOR_PROFILES 1003 uint32_t param; 1004 }; 1005 1006 struct atom_camera_dphy_elec_param 1007 { 1008 uint16_t param[3]; 1009 }; 1010 1011 struct atom_camera_module_info 1012 { 1013 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user 1014 uint8_t module_name[8]; 1015 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor 1016 }; 1017 1018 struct atom_camera_flashlight_info 1019 { 1020 uint8_t flashlight_id; // 0: Rear, 1: Front 1021 uint8_t name[8]; 1022 }; 1023 1024 struct atom_camera_data 1025 { 1026 uint32_t versionCode; 1027 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max 1028 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max 1029 struct atom_camera_dphy_elec_param dphy_param; 1030 uint32_t crc_val; // CRC 1031 }; 1032 1033 1034 struct atom_14nm_dpphy_dvihdmi_tuningset 1035 { 1036 uint32_t max_symclk_in10khz; 1037 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode 1038 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1039 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1040 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1041 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1042 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms 1043 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL 1044 }; 1045 1046 struct atom_14nm_dpphy_dp_setting{ 1047 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def 1048 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom 1049 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4 1050 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset 1051 }; 1052 1053 struct atom_14nm_dpphy_dp_tuningset{ 1054 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf 1055 uint8_t version; 1056 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset 1057 uint16_t reserved; 1058 struct atom_14nm_dpphy_dp_setting dptuning[10]; 1059 }; 1060 1061 struct atom_14nm_dig_transmitter_info_header_v4_0{ 1062 struct atom_common_table_header table_header; 1063 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl 1064 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl 1065 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl 1066 }; 1067 1068 struct atom_14nm_combphy_tmds_vs_set 1069 { 1070 uint8_t sym_clk; 1071 uint8_t dig_mode; 1072 uint8_t phy_sel; 1073 uint16_t common_mar_deemph_nom__margin_deemph_val; 1074 uint8_t common_seldeemph60__deemph_6db_4_val; 1075 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ; 1076 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val; 1077 uint8_t margin_deemph_lane0__deemph_sel_val; 1078 }; 1079 1080 struct atom_i2c_reg_info { 1081 uint8_t ucI2cRegIndex; 1082 uint8_t ucI2cRegVal; 1083 }; 1084 1085 struct atom_hdmi_retimer_redriver_set { 1086 uint8_t HdmiSlvAddr; 1087 uint8_t HdmiRegNum; 1088 uint8_t Hdmi6GRegNum; 1089 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use 1090 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use. 1091 }; 1092 1093 struct atom_integrated_system_info_v1_11 1094 { 1095 struct atom_common_table_header table_header; 1096 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def 1097 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def 1098 uint32_t system_config; 1099 uint32_t cpucapinfo; 1100 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1% 1101 uint16_t gpuclk_ss_type; 1102 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1% 1103 uint16_t lvds_ss_rate_10hz; 1104 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1105 uint16_t hdmi_ss_rate_10hz; 1106 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1% 1107 uint16_t dvi_ss_rate_10hz; 1108 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def 1109 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def 1110 uint16_t backlight_pwm_hz; // pwm frequency in hz 1111 uint8_t memorytype; // enum of atom_dmi_t17_mem_type_def, APU memory type indication. 1112 uint8_t umachannelnumber; // number of memory channels 1113 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */ 1114 uint8_t pwr_on_de_to_vary_bl; 1115 uint8_t pwr_down_vary_bloff_to_de; 1116 uint8_t pwr_down_de_to_digoff; 1117 uint8_t pwr_off_delay; 1118 uint8_t pwr_on_vary_bl_to_blon; 1119 uint8_t pwr_down_bloff_to_vary_bloff; 1120 uint8_t min_allowed_bl_level; 1121 uint8_t htc_hyst_limit; 1122 uint8_t htc_tmp_limit; 1123 uint8_t reserved1; 1124 uint8_t reserved2; 1125 struct atom_external_display_connection_info extdispconninfo; 1126 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset; 1127 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset; 1128 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset; 1129 struct atom_14nm_dpphy_dp_tuningset dp_tuningset; // rbr 1.62G dp tuning set 1130 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset; // HBR3 dp tuning set 1131 struct atom_camera_data camera_info; 1132 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0 1133 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1 1134 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2 1135 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3 1136 struct atom_14nm_dpphy_dp_tuningset dp_hbr_tuningset; //hbr 2.7G dp tuning set 1137 struct atom_14nm_dpphy_dp_tuningset dp_hbr2_tuningset; //hbr2 5.4G dp turnig set 1138 struct atom_14nm_dpphy_dp_tuningset edp_tuningset; //edp tuning set 1139 uint32_t reserved[66]; 1140 }; 1141 1142 1143 // system_config 1144 enum atom_system_vbiosmisc_def{ 1145 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01, 1146 }; 1147 1148 1149 // gpucapinfo 1150 enum atom_system_gpucapinf_def{ 1151 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10, 1152 }; 1153 1154 //dpphy_override 1155 enum atom_sysinfo_dpphy_override_def{ 1156 ATOM_ENABLE_DVI_TUNINGSET = 0x01, 1157 ATOM_ENABLE_HDMI_TUNINGSET = 0x02, 1158 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04, 1159 ATOM_ENABLE_DP_TUNINGSET = 0x08, 1160 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10, 1161 }; 1162 1163 //lvds_misc 1164 enum atom_sys_info_lvds_misc_def 1165 { 1166 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01, 1167 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04, 1168 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08, 1169 }; 1170 1171 1172 //memorytype DMI Type 17 offset 12h - Memory Type 1173 enum atom_dmi_t17_mem_type_def{ 1174 OtherMemType = 0x01, ///< Assign 01 to Other 1175 UnknownMemType, ///< Assign 02 to Unknown 1176 DramMemType, ///< Assign 03 to DRAM 1177 EdramMemType, ///< Assign 04 to EDRAM 1178 VramMemType, ///< Assign 05 to VRAM 1179 SramMemType, ///< Assign 06 to SRAM 1180 RamMemType, ///< Assign 07 to RAM 1181 RomMemType, ///< Assign 08 to ROM 1182 FlashMemType, ///< Assign 09 to Flash 1183 EepromMemType, ///< Assign 10 to EEPROM 1184 FepromMemType, ///< Assign 11 to FEPROM 1185 EpromMemType, ///< Assign 12 to EPROM 1186 CdramMemType, ///< Assign 13 to CDRAM 1187 ThreeDramMemType, ///< Assign 14 to 3DRAM 1188 SdramMemType, ///< Assign 15 to SDRAM 1189 SgramMemType, ///< Assign 16 to SGRAM 1190 RdramMemType, ///< Assign 17 to RDRAM 1191 DdrMemType, ///< Assign 18 to DDR 1192 Ddr2MemType, ///< Assign 19 to DDR2 1193 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM 1194 Ddr3MemType = 0x18, ///< Assign 24 to DDR3 1195 Fbd2MemType, ///< Assign 25 to FBD2 1196 Ddr4MemType, ///< Assign 26 to DDR4 1197 LpDdrMemType, ///< Assign 27 to LPDDR 1198 LpDdr2MemType, ///< Assign 28 to LPDDR2 1199 LpDdr3MemType, ///< Assign 29 to LPDDR3 1200 LpDdr4MemType, ///< Assign 30 to LPDDR4 1201 }; 1202 1203 1204 // this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable 1205 struct atom_fusion_system_info_v4 1206 { 1207 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition 1208 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable 1209 }; 1210 1211 1212 /* 1213 *************************************************************************** 1214 Data Table gfx_info structure 1215 *************************************************************************** 1216 */ 1217 1218 struct atom_gfx_info_v2_2 1219 { 1220 struct atom_common_table_header table_header; 1221 uint8_t gfxip_min_ver; 1222 uint8_t gfxip_max_ver; 1223 uint8_t max_shader_engines; 1224 uint8_t max_tile_pipes; 1225 uint8_t max_cu_per_sh; 1226 uint8_t max_sh_per_se; 1227 uint8_t max_backends_per_se; 1228 uint8_t max_texture_channel_caches; 1229 uint32_t regaddr_cp_dma_src_addr; 1230 uint32_t regaddr_cp_dma_src_addr_hi; 1231 uint32_t regaddr_cp_dma_dst_addr; 1232 uint32_t regaddr_cp_dma_dst_addr_hi; 1233 uint32_t regaddr_cp_dma_command; 1234 uint32_t regaddr_cp_status; 1235 uint32_t regaddr_rlc_gpu_clock_32; 1236 uint32_t rlc_gpu_timer_refclk; 1237 }; 1238 1239 struct atom_gfx_info_v2_3 { 1240 struct atom_common_table_header table_header; 1241 uint8_t gfxip_min_ver; 1242 uint8_t gfxip_max_ver; 1243 uint8_t max_shader_engines; 1244 uint8_t max_tile_pipes; 1245 uint8_t max_cu_per_sh; 1246 uint8_t max_sh_per_se; 1247 uint8_t max_backends_per_se; 1248 uint8_t max_texture_channel_caches; 1249 uint32_t regaddr_cp_dma_src_addr; 1250 uint32_t regaddr_cp_dma_src_addr_hi; 1251 uint32_t regaddr_cp_dma_dst_addr; 1252 uint32_t regaddr_cp_dma_dst_addr_hi; 1253 uint32_t regaddr_cp_dma_command; 1254 uint32_t regaddr_cp_status; 1255 uint32_t regaddr_rlc_gpu_clock_32; 1256 uint32_t rlc_gpu_timer_refclk; 1257 uint8_t active_cu_per_sh; 1258 uint8_t active_rb_per_se; 1259 uint16_t gcgoldenoffset; 1260 uint32_t rm21_sram_vmin_value; 1261 }; 1262 1263 struct atom_gfx_info_v2_4 1264 { 1265 struct atom_common_table_header table_header; 1266 uint8_t gfxip_min_ver; 1267 uint8_t gfxip_max_ver; 1268 uint8_t max_shader_engines; 1269 uint8_t reserved; 1270 uint8_t max_cu_per_sh; 1271 uint8_t max_sh_per_se; 1272 uint8_t max_backends_per_se; 1273 uint8_t max_texture_channel_caches; 1274 uint32_t regaddr_cp_dma_src_addr; 1275 uint32_t regaddr_cp_dma_src_addr_hi; 1276 uint32_t regaddr_cp_dma_dst_addr; 1277 uint32_t regaddr_cp_dma_dst_addr_hi; 1278 uint32_t regaddr_cp_dma_command; 1279 uint32_t regaddr_cp_status; 1280 uint32_t regaddr_rlc_gpu_clock_32; 1281 uint32_t rlc_gpu_timer_refclk; 1282 uint8_t active_cu_per_sh; 1283 uint8_t active_rb_per_se; 1284 uint16_t gcgoldenoffset; 1285 uint16_t gc_num_gprs; 1286 uint16_t gc_gsprim_buff_depth; 1287 uint16_t gc_parameter_cache_depth; 1288 uint16_t gc_wave_size; 1289 uint16_t gc_max_waves_per_simd; 1290 uint16_t gc_lds_size; 1291 uint8_t gc_num_max_gs_thds; 1292 uint8_t gc_gs_table_depth; 1293 uint8_t gc_double_offchip_lds_buffer; 1294 uint8_t gc_max_scratch_slots_per_cu; 1295 uint32_t sram_rm_fuses_val; 1296 uint32_t sram_custom_rm_fuses_val; 1297 }; 1298 1299 /* 1300 *************************************************************************** 1301 Data Table smu_info structure 1302 *************************************************************************** 1303 */ 1304 struct atom_smu_info_v3_1 1305 { 1306 struct atom_common_table_header table_header; 1307 uint8_t smuip_min_ver; 1308 uint8_t smuip_max_ver; 1309 uint8_t smu_rsd1; 1310 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode 1311 uint16_t sclk_ss_percentage; 1312 uint16_t sclk_ss_rate_10hz; 1313 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1314 uint16_t gpuclk_ss_rate_10hz; 1315 uint32_t core_refclk_10khz; 1316 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1317 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1318 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1319 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1320 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1321 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1322 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1323 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1324 }; 1325 1326 struct atom_smu_info_v3_2 { 1327 struct atom_common_table_header table_header; 1328 uint8_t smuip_min_ver; 1329 uint8_t smuip_max_ver; 1330 uint8_t smu_rsd1; 1331 uint8_t gpuclk_ss_mode; 1332 uint16_t sclk_ss_percentage; 1333 uint16_t sclk_ss_rate_10hz; 1334 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1335 uint16_t gpuclk_ss_rate_10hz; 1336 uint32_t core_refclk_10khz; 1337 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1338 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1339 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1340 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1341 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1342 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1343 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1344 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1345 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1346 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1347 uint16_t smugoldenoffset; 1348 uint32_t gpupll_vco_freq_10khz; 1349 uint32_t bootup_smnclk_10khz; 1350 uint32_t bootup_socclk_10khz; 1351 uint32_t bootup_mp0clk_10khz; 1352 uint32_t bootup_mp1clk_10khz; 1353 uint32_t bootup_lclk_10khz; 1354 uint32_t bootup_dcefclk_10khz; 1355 uint32_t ctf_threshold_override_value; 1356 uint32_t reserved[5]; 1357 }; 1358 1359 struct atom_smu_info_v3_3 { 1360 struct atom_common_table_header table_header; 1361 uint8_t smuip_min_ver; 1362 uint8_t smuip_max_ver; 1363 uint8_t waflclk_ss_mode; 1364 uint8_t gpuclk_ss_mode; 1365 uint16_t sclk_ss_percentage; 1366 uint16_t sclk_ss_rate_10hz; 1367 uint16_t gpuclk_ss_percentage; // in unit of 0.001% 1368 uint16_t gpuclk_ss_rate_10hz; 1369 uint32_t core_refclk_10khz; 1370 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid 1371 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching 1372 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid 1373 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event 1374 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid 1375 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event 1376 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid 1377 uint8_t fw_ctf_polarity; // GPIO polarity for CTF 1378 uint8_t pcc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for PCC, =0xff means invalid 1379 uint8_t pcc_gpio_polarity; // GPIO polarity for CTF 1380 uint16_t smugoldenoffset; 1381 uint32_t gpupll_vco_freq_10khz; 1382 uint32_t bootup_smnclk_10khz; 1383 uint32_t bootup_socclk_10khz; 1384 uint32_t bootup_mp0clk_10khz; 1385 uint32_t bootup_mp1clk_10khz; 1386 uint32_t bootup_lclk_10khz; 1387 uint32_t bootup_dcefclk_10khz; 1388 uint32_t ctf_threshold_override_value; 1389 uint32_t syspll3_0_vco_freq_10khz; 1390 uint32_t syspll3_1_vco_freq_10khz; 1391 uint32_t bootup_fclk_10khz; 1392 uint32_t bootup_waflclk_10khz; 1393 uint32_t smu_info_caps; 1394 uint16_t waflclk_ss_percentage; // in unit of 0.001% 1395 uint16_t smuinitoffset; 1396 uint32_t reserved; 1397 }; 1398 1399 /* 1400 *************************************************************************** 1401 Data Table smc_dpm_info structure 1402 *************************************************************************** 1403 */ 1404 struct atom_smc_dpm_info_v4_1 1405 { 1406 struct atom_common_table_header table_header; 1407 uint8_t liquid1_i2c_address; 1408 uint8_t liquid2_i2c_address; 1409 uint8_t vr_i2c_address; 1410 uint8_t plx_i2c_address; 1411 1412 uint8_t liquid_i2c_linescl; 1413 uint8_t liquid_i2c_linesda; 1414 uint8_t vr_i2c_linescl; 1415 uint8_t vr_i2c_linesda; 1416 1417 uint8_t plx_i2c_linescl; 1418 uint8_t plx_i2c_linesda; 1419 uint8_t vrsensorpresent; 1420 uint8_t liquidsensorpresent; 1421 1422 uint16_t maxvoltagestepgfx; 1423 uint16_t maxvoltagestepsoc; 1424 1425 uint8_t vddgfxvrmapping; 1426 uint8_t vddsocvrmapping; 1427 uint8_t vddmem0vrmapping; 1428 uint8_t vddmem1vrmapping; 1429 1430 uint8_t gfxulvphasesheddingmask; 1431 uint8_t soculvphasesheddingmask; 1432 uint8_t padding8_v[2]; 1433 1434 uint16_t gfxmaxcurrent; 1435 uint8_t gfxoffset; 1436 uint8_t padding_telemetrygfx; 1437 1438 uint16_t socmaxcurrent; 1439 uint8_t socoffset; 1440 uint8_t padding_telemetrysoc; 1441 1442 uint16_t mem0maxcurrent; 1443 uint8_t mem0offset; 1444 uint8_t padding_telemetrymem0; 1445 1446 uint16_t mem1maxcurrent; 1447 uint8_t mem1offset; 1448 uint8_t padding_telemetrymem1; 1449 1450 uint8_t acdcgpio; 1451 uint8_t acdcpolarity; 1452 uint8_t vr0hotgpio; 1453 uint8_t vr0hotpolarity; 1454 1455 uint8_t vr1hotgpio; 1456 uint8_t vr1hotpolarity; 1457 uint8_t padding1; 1458 uint8_t padding2; 1459 1460 uint8_t ledpin0; 1461 uint8_t ledpin1; 1462 uint8_t ledpin2; 1463 uint8_t padding8_4; 1464 1465 uint8_t pllgfxclkspreadenabled; 1466 uint8_t pllgfxclkspreadpercent; 1467 uint16_t pllgfxclkspreadfreq; 1468 1469 uint8_t uclkspreadenabled; 1470 uint8_t uclkspreadpercent; 1471 uint16_t uclkspreadfreq; 1472 1473 uint8_t socclkspreadenabled; 1474 uint8_t socclkspreadpercent; 1475 uint16_t socclkspreadfreq; 1476 1477 uint8_t acggfxclkspreadenabled; 1478 uint8_t acggfxclkspreadpercent; 1479 uint16_t acggfxclkspreadfreq; 1480 1481 uint8_t Vr2_I2C_address; 1482 uint8_t padding_vr2[3]; 1483 1484 uint32_t boardreserved[9]; 1485 }; 1486 1487 /* 1488 *************************************************************************** 1489 Data Table smc_dpm_info structure 1490 *************************************************************************** 1491 */ 1492 struct atom_smc_dpm_info_v4_3 1493 { 1494 struct atom_common_table_header table_header; 1495 uint8_t liquid1_i2c_address; 1496 uint8_t liquid2_i2c_address; 1497 uint8_t vr_i2c_address; 1498 uint8_t plx_i2c_address; 1499 1500 uint8_t liquid_i2c_linescl; 1501 uint8_t liquid_i2c_linesda; 1502 uint8_t vr_i2c_linescl; 1503 uint8_t vr_i2c_linesda; 1504 1505 uint8_t plx_i2c_linescl; 1506 uint8_t plx_i2c_linesda; 1507 uint8_t vrsensorpresent; 1508 uint8_t liquidsensorpresent; 1509 1510 uint16_t maxvoltagestepgfx; 1511 uint16_t maxvoltagestepsoc; 1512 1513 uint8_t vddgfxvrmapping; 1514 uint8_t vddsocvrmapping; 1515 uint8_t vddmem0vrmapping; 1516 uint8_t vddmem1vrmapping; 1517 1518 uint8_t gfxulvphasesheddingmask; 1519 uint8_t soculvphasesheddingmask; 1520 uint8_t externalsensorpresent; 1521 uint8_t padding8_v; 1522 1523 uint16_t gfxmaxcurrent; 1524 uint8_t gfxoffset; 1525 uint8_t padding_telemetrygfx; 1526 1527 uint16_t socmaxcurrent; 1528 uint8_t socoffset; 1529 uint8_t padding_telemetrysoc; 1530 1531 uint16_t mem0maxcurrent; 1532 uint8_t mem0offset; 1533 uint8_t padding_telemetrymem0; 1534 1535 uint16_t mem1maxcurrent; 1536 uint8_t mem1offset; 1537 uint8_t padding_telemetrymem1; 1538 1539 uint8_t acdcgpio; 1540 uint8_t acdcpolarity; 1541 uint8_t vr0hotgpio; 1542 uint8_t vr0hotpolarity; 1543 1544 uint8_t vr1hotgpio; 1545 uint8_t vr1hotpolarity; 1546 uint8_t padding1; 1547 uint8_t padding2; 1548 1549 uint8_t ledpin0; 1550 uint8_t ledpin1; 1551 uint8_t ledpin2; 1552 uint8_t padding8_4; 1553 1554 uint8_t pllgfxclkspreadenabled; 1555 uint8_t pllgfxclkspreadpercent; 1556 uint16_t pllgfxclkspreadfreq; 1557 1558 uint8_t uclkspreadenabled; 1559 uint8_t uclkspreadpercent; 1560 uint16_t uclkspreadfreq; 1561 1562 uint8_t fclkspreadenabled; 1563 uint8_t fclkspreadpercent; 1564 uint16_t fclkspreadfreq; 1565 1566 uint8_t fllgfxclkspreadenabled; 1567 uint8_t fllgfxclkspreadpercent; 1568 uint16_t fllgfxclkspreadfreq; 1569 1570 uint32_t boardreserved[10]; 1571 }; 1572 1573 struct smudpm_i2ccontrollerconfig_t { 1574 uint32_t enabled; 1575 uint32_t slaveaddress; 1576 uint32_t controllerport; 1577 uint32_t controllername; 1578 uint32_t thermalthrottler; 1579 uint32_t i2cprotocol; 1580 uint32_t i2cspeed; 1581 }; 1582 1583 struct atom_smc_dpm_info_v4_4 1584 { 1585 struct atom_common_table_header table_header; 1586 uint32_t i2c_padding[3]; 1587 1588 uint16_t maxvoltagestepgfx; 1589 uint16_t maxvoltagestepsoc; 1590 1591 uint8_t vddgfxvrmapping; 1592 uint8_t vddsocvrmapping; 1593 uint8_t vddmem0vrmapping; 1594 uint8_t vddmem1vrmapping; 1595 1596 uint8_t gfxulvphasesheddingmask; 1597 uint8_t soculvphasesheddingmask; 1598 uint8_t externalsensorpresent; 1599 uint8_t padding8_v; 1600 1601 uint16_t gfxmaxcurrent; 1602 uint8_t gfxoffset; 1603 uint8_t padding_telemetrygfx; 1604 1605 uint16_t socmaxcurrent; 1606 uint8_t socoffset; 1607 uint8_t padding_telemetrysoc; 1608 1609 uint16_t mem0maxcurrent; 1610 uint8_t mem0offset; 1611 uint8_t padding_telemetrymem0; 1612 1613 uint16_t mem1maxcurrent; 1614 uint8_t mem1offset; 1615 uint8_t padding_telemetrymem1; 1616 1617 1618 uint8_t acdcgpio; 1619 uint8_t acdcpolarity; 1620 uint8_t vr0hotgpio; 1621 uint8_t vr0hotpolarity; 1622 1623 uint8_t vr1hotgpio; 1624 uint8_t vr1hotpolarity; 1625 uint8_t padding1; 1626 uint8_t padding2; 1627 1628 1629 uint8_t ledpin0; 1630 uint8_t ledpin1; 1631 uint8_t ledpin2; 1632 uint8_t padding8_4; 1633 1634 1635 uint8_t pllgfxclkspreadenabled; 1636 uint8_t pllgfxclkspreadpercent; 1637 uint16_t pllgfxclkspreadfreq; 1638 1639 1640 uint8_t uclkspreadenabled; 1641 uint8_t uclkspreadpercent; 1642 uint16_t uclkspreadfreq; 1643 1644 1645 uint8_t fclkspreadenabled; 1646 uint8_t fclkspreadpercent; 1647 uint16_t fclkspreadfreq; 1648 1649 1650 uint8_t fllgfxclkspreadenabled; 1651 uint8_t fllgfxclkspreadpercent; 1652 uint16_t fllgfxclkspreadfreq; 1653 1654 1655 struct smudpm_i2ccontrollerconfig_t i2ccontrollers[7]; 1656 1657 1658 uint32_t boardreserved[10]; 1659 }; 1660 1661 enum smudpm_v4_5_i2ccontrollername_e{ 1662 SMC_V4_5_I2C_CONTROLLER_NAME_VR_GFX = 0, 1663 SMC_V4_5_I2C_CONTROLLER_NAME_VR_SOC, 1664 SMC_V4_5_I2C_CONTROLLER_NAME_VR_VDDCI, 1665 SMC_V4_5_I2C_CONTROLLER_NAME_VR_MVDD, 1666 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID0, 1667 SMC_V4_5_I2C_CONTROLLER_NAME_LIQUID1, 1668 SMC_V4_5_I2C_CONTROLLER_NAME_PLX, 1669 SMC_V4_5_I2C_CONTROLLER_NAME_SPARE, 1670 SMC_V4_5_I2C_CONTROLLER_NAME_COUNT, 1671 }; 1672 1673 enum smudpm_v4_5_i2ccontrollerthrottler_e{ 1674 SMC_V4_5_I2C_CONTROLLER_THROTTLER_TYPE_NONE = 0, 1675 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_GFX, 1676 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_SOC, 1677 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_VDDCI, 1678 SMC_V4_5_I2C_CONTROLLER_THROTTLER_VR_MVDD, 1679 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID0, 1680 SMC_V4_5_I2C_CONTROLLER_THROTTLER_LIQUID1, 1681 SMC_V4_5_I2C_CONTROLLER_THROTTLER_PLX, 1682 SMC_V4_5_I2C_CONTROLLER_THROTTLER_COUNT, 1683 }; 1684 1685 enum smudpm_v4_5_i2ccontrollerprotocol_e{ 1686 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_0, 1687 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_VR_1, 1688 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_0, 1689 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_TMP_1, 1690 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_0, 1691 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_SPARE_1, 1692 SMC_V4_5_I2C_CONTROLLER_PROTOCOL_COUNT, 1693 }; 1694 1695 struct smudpm_i2c_controller_config_v2 1696 { 1697 uint8_t Enabled; 1698 uint8_t Speed; 1699 uint8_t Padding[2]; 1700 uint32_t SlaveAddress; 1701 uint8_t ControllerPort; 1702 uint8_t ControllerName; 1703 uint8_t ThermalThrotter; 1704 uint8_t I2cProtocol; 1705 }; 1706 1707 struct atom_smc_dpm_info_v4_5 1708 { 1709 struct atom_common_table_header table_header; 1710 // SECTION: BOARD PARAMETERS 1711 // I2C Control 1712 struct smudpm_i2c_controller_config_v2 I2cControllers[8]; 1713 1714 // SVI2 Board Parameters 1715 uint16_t MaxVoltageStepGfx; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1716 uint16_t MaxVoltageStepSoc; // In mV(Q2) Max voltage step that SMU will request. Multiple steps are taken if voltage change exceeds this value. 1717 1718 uint8_t VddGfxVrMapping; // Use VR_MAPPING* bitfields 1719 uint8_t VddSocVrMapping; // Use VR_MAPPING* bitfields 1720 uint8_t VddMem0VrMapping; // Use VR_MAPPING* bitfields 1721 uint8_t VddMem1VrMapping; // Use VR_MAPPING* bitfields 1722 1723 uint8_t GfxUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1724 uint8_t SocUlvPhaseSheddingMask; // set this to 1 to set PSI0/1 to 1 in ULV mode 1725 uint8_t ExternalSensorPresent; // External RDI connected to TMON (aka TEMP IN) 1726 uint8_t Padding8_V; 1727 1728 // Telemetry Settings 1729 uint16_t GfxMaxCurrent; // in Amps 1730 uint8_t GfxOffset; // in Amps 1731 uint8_t Padding_TelemetryGfx; 1732 uint16_t SocMaxCurrent; // in Amps 1733 uint8_t SocOffset; // in Amps 1734 uint8_t Padding_TelemetrySoc; 1735 1736 uint16_t Mem0MaxCurrent; // in Amps 1737 uint8_t Mem0Offset; // in Amps 1738 uint8_t Padding_TelemetryMem0; 1739 1740 uint16_t Mem1MaxCurrent; // in Amps 1741 uint8_t Mem1Offset; // in Amps 1742 uint8_t Padding_TelemetryMem1; 1743 1744 // GPIO Settings 1745 uint8_t AcDcGpio; // GPIO pin configured for AC/DC switching 1746 uint8_t AcDcPolarity; // GPIO polarity for AC/DC switching 1747 uint8_t VR0HotGpio; // GPIO pin configured for VR0 HOT event 1748 uint8_t VR0HotPolarity; // GPIO polarity for VR0 HOT event 1749 1750 uint8_t VR1HotGpio; // GPIO pin configured for VR1 HOT event 1751 uint8_t VR1HotPolarity; // GPIO polarity for VR1 HOT event 1752 uint8_t GthrGpio; // GPIO pin configured for GTHR Event 1753 uint8_t GthrPolarity; // replace GPIO polarity for GTHR 1754 1755 // LED Display Settings 1756 uint8_t LedPin0; // GPIO number for LedPin[0] 1757 uint8_t LedPin1; // GPIO number for LedPin[1] 1758 uint8_t LedPin2; // GPIO number for LedPin[2] 1759 uint8_t padding8_4; 1760 1761 // GFXCLK PLL Spread Spectrum 1762 uint8_t PllGfxclkSpreadEnabled; // on or off 1763 uint8_t PllGfxclkSpreadPercent; // Q4.4 1764 uint16_t PllGfxclkSpreadFreq; // kHz 1765 1766 // GFXCLK DFLL Spread Spectrum 1767 uint8_t DfllGfxclkSpreadEnabled; // on or off 1768 uint8_t DfllGfxclkSpreadPercent; // Q4.4 1769 uint16_t DfllGfxclkSpreadFreq; // kHz 1770 1771 // UCLK Spread Spectrum 1772 uint8_t UclkSpreadEnabled; // on or off 1773 uint8_t UclkSpreadPercent; // Q4.4 1774 uint16_t UclkSpreadFreq; // kHz 1775 1776 // SOCCLK Spread Spectrum 1777 uint8_t SoclkSpreadEnabled; // on or off 1778 uint8_t SocclkSpreadPercent; // Q4.4 1779 uint16_t SocclkSpreadFreq; // kHz 1780 1781 // Total board power 1782 uint16_t TotalBoardPower; //Only needed for TCP Estimated case, where TCP = TGP+Total Board Power 1783 uint16_t BoardPadding; 1784 1785 // Mvdd Svi2 Div Ratio Setting 1786 uint32_t MvddRatio; // This is used for MVDD Vid workaround. It has 16 fractional bits (Q16.16) 1787 1788 uint32_t BoardReserved[9]; 1789 1790 }; 1791 1792 struct atom_smc_dpm_info_v4_6 1793 { 1794 struct atom_common_table_header table_header; 1795 // section: board parameters 1796 uint32_t i2c_padding[3]; // old i2c control are moved to new area 1797 1798 uint16_t maxvoltagestepgfx; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 1799 uint16_t maxvoltagestepsoc; // in mv(q2) max voltage step that smu will request. multiple steps are taken if voltage change exceeds this value. 1800 1801 uint8_t vddgfxvrmapping; // use vr_mapping* bitfields 1802 uint8_t vddsocvrmapping; // use vr_mapping* bitfields 1803 uint8_t vddmemvrmapping; // use vr_mapping* bitfields 1804 uint8_t boardvrmapping; // use vr_mapping* bitfields 1805 1806 uint8_t gfxulvphasesheddingmask; // set this to 1 to set psi0/1 to 1 in ulv mode 1807 uint8_t externalsensorpresent; // external rdi connected to tmon (aka temp in) 1808 uint8_t padding8_v[2]; 1809 1810 // telemetry settings 1811 uint16_t gfxmaxcurrent; // in amps 1812 uint8_t gfxoffset; // in amps 1813 uint8_t padding_telemetrygfx; 1814 1815 uint16_t socmaxcurrent; // in amps 1816 uint8_t socoffset; // in amps 1817 uint8_t padding_telemetrysoc; 1818 1819 uint16_t memmaxcurrent; // in amps 1820 uint8_t memoffset; // in amps 1821 uint8_t padding_telemetrymem; 1822 1823 uint16_t boardmaxcurrent; // in amps 1824 uint8_t boardoffset; // in amps 1825 uint8_t padding_telemetryboardinput; 1826 1827 // gpio settings 1828 uint8_t vr0hotgpio; // gpio pin configured for vr0 hot event 1829 uint8_t vr0hotpolarity; // gpio polarity for vr0 hot event 1830 uint8_t vr1hotgpio; // gpio pin configured for vr1 hot event 1831 uint8_t vr1hotpolarity; // gpio polarity for vr1 hot event 1832 1833 // gfxclk pll spread spectrum 1834 uint8_t pllgfxclkspreadenabled; // on or off 1835 uint8_t pllgfxclkspreadpercent; // q4.4 1836 uint16_t pllgfxclkspreadfreq; // khz 1837 1838 // uclk spread spectrum 1839 uint8_t uclkspreadenabled; // on or off 1840 uint8_t uclkspreadpercent; // q4.4 1841 uint16_t uclkspreadfreq; // khz 1842 1843 // fclk spread spectrum 1844 uint8_t fclkspreadenabled; // on or off 1845 uint8_t fclkspreadpercent; // q4.4 1846 uint16_t fclkspreadfreq; // khz 1847 1848 1849 // gfxclk fll spread spectrum 1850 uint8_t fllgfxclkspreadenabled; // on or off 1851 uint8_t fllgfxclkspreadpercent; // q4.4 1852 uint16_t fllgfxclkspreadfreq; // khz 1853 1854 // i2c controller structure 1855 struct smudpm_i2c_controller_config_v2 i2ccontrollers[8]; 1856 1857 // memory section 1858 uint32_t memorychannelenabled; // for dram use only, max 32 channels enabled bit mask. 1859 1860 uint8_t drambitwidth; // for dram use only. see dram bit width type defines 1861 uint8_t paddingmem[3]; 1862 1863 // total board power 1864 uint16_t totalboardpower; //only needed for tcp estimated case, where tcp = tgp+total board power 1865 uint16_t boardpadding; 1866 1867 // section: xgmi training 1868 uint8_t xgmilinkspeed[4]; 1869 uint8_t xgmilinkwidth[4]; 1870 1871 uint16_t xgmifclkfreq[4]; 1872 uint16_t xgmisocvoltage[4]; 1873 1874 // reserved 1875 uint32_t boardreserved[10]; 1876 }; 1877 1878 /* 1879 *************************************************************************** 1880 Data Table asic_profiling_info structure 1881 *************************************************************************** 1882 */ 1883 struct atom_asic_profiling_info_v4_1 1884 { 1885 struct atom_common_table_header table_header; 1886 uint32_t maxvddc; 1887 uint32_t minvddc; 1888 uint32_t avfs_meannsigma_acontant0; 1889 uint32_t avfs_meannsigma_acontant1; 1890 uint32_t avfs_meannsigma_acontant2; 1891 uint16_t avfs_meannsigma_dc_tol_sigma; 1892 uint16_t avfs_meannsigma_platform_mean; 1893 uint16_t avfs_meannsigma_platform_sigma; 1894 uint32_t gb_vdroop_table_cksoff_a0; 1895 uint32_t gb_vdroop_table_cksoff_a1; 1896 uint32_t gb_vdroop_table_cksoff_a2; 1897 uint32_t gb_vdroop_table_ckson_a0; 1898 uint32_t gb_vdroop_table_ckson_a1; 1899 uint32_t gb_vdroop_table_ckson_a2; 1900 uint32_t avfsgb_fuse_table_cksoff_m1; 1901 uint32_t avfsgb_fuse_table_cksoff_m2; 1902 uint32_t avfsgb_fuse_table_cksoff_b; 1903 uint32_t avfsgb_fuse_table_ckson_m1; 1904 uint32_t avfsgb_fuse_table_ckson_m2; 1905 uint32_t avfsgb_fuse_table_ckson_b; 1906 uint16_t max_voltage_0_25mv; 1907 uint8_t enable_gb_vdroop_table_cksoff; 1908 uint8_t enable_gb_vdroop_table_ckson; 1909 uint8_t enable_gb_fuse_table_cksoff; 1910 uint8_t enable_gb_fuse_table_ckson; 1911 uint16_t psm_age_comfactor; 1912 uint8_t enable_apply_avfs_cksoff_voltage; 1913 uint8_t reserved; 1914 uint32_t dispclk2gfxclk_a; 1915 uint32_t dispclk2gfxclk_b; 1916 uint32_t dispclk2gfxclk_c; 1917 uint32_t pixclk2gfxclk_a; 1918 uint32_t pixclk2gfxclk_b; 1919 uint32_t pixclk2gfxclk_c; 1920 uint32_t dcefclk2gfxclk_a; 1921 uint32_t dcefclk2gfxclk_b; 1922 uint32_t dcefclk2gfxclk_c; 1923 uint32_t phyclk2gfxclk_a; 1924 uint32_t phyclk2gfxclk_b; 1925 uint32_t phyclk2gfxclk_c; 1926 }; 1927 1928 struct atom_asic_profiling_info_v4_2 { 1929 struct atom_common_table_header table_header; 1930 uint32_t maxvddc; 1931 uint32_t minvddc; 1932 uint32_t avfs_meannsigma_acontant0; 1933 uint32_t avfs_meannsigma_acontant1; 1934 uint32_t avfs_meannsigma_acontant2; 1935 uint16_t avfs_meannsigma_dc_tol_sigma; 1936 uint16_t avfs_meannsigma_platform_mean; 1937 uint16_t avfs_meannsigma_platform_sigma; 1938 uint32_t gb_vdroop_table_cksoff_a0; 1939 uint32_t gb_vdroop_table_cksoff_a1; 1940 uint32_t gb_vdroop_table_cksoff_a2; 1941 uint32_t gb_vdroop_table_ckson_a0; 1942 uint32_t gb_vdroop_table_ckson_a1; 1943 uint32_t gb_vdroop_table_ckson_a2; 1944 uint32_t avfsgb_fuse_table_cksoff_m1; 1945 uint32_t avfsgb_fuse_table_cksoff_m2; 1946 uint32_t avfsgb_fuse_table_cksoff_b; 1947 uint32_t avfsgb_fuse_table_ckson_m1; 1948 uint32_t avfsgb_fuse_table_ckson_m2; 1949 uint32_t avfsgb_fuse_table_ckson_b; 1950 uint16_t max_voltage_0_25mv; 1951 uint8_t enable_gb_vdroop_table_cksoff; 1952 uint8_t enable_gb_vdroop_table_ckson; 1953 uint8_t enable_gb_fuse_table_cksoff; 1954 uint8_t enable_gb_fuse_table_ckson; 1955 uint16_t psm_age_comfactor; 1956 uint8_t enable_apply_avfs_cksoff_voltage; 1957 uint8_t reserved; 1958 uint32_t dispclk2gfxclk_a; 1959 uint32_t dispclk2gfxclk_b; 1960 uint32_t dispclk2gfxclk_c; 1961 uint32_t pixclk2gfxclk_a; 1962 uint32_t pixclk2gfxclk_b; 1963 uint32_t pixclk2gfxclk_c; 1964 uint32_t dcefclk2gfxclk_a; 1965 uint32_t dcefclk2gfxclk_b; 1966 uint32_t dcefclk2gfxclk_c; 1967 uint32_t phyclk2gfxclk_a; 1968 uint32_t phyclk2gfxclk_b; 1969 uint32_t phyclk2gfxclk_c; 1970 uint32_t acg_gb_vdroop_table_a0; 1971 uint32_t acg_gb_vdroop_table_a1; 1972 uint32_t acg_gb_vdroop_table_a2; 1973 uint32_t acg_avfsgb_fuse_table_m1; 1974 uint32_t acg_avfsgb_fuse_table_m2; 1975 uint32_t acg_avfsgb_fuse_table_b; 1976 uint8_t enable_acg_gb_vdroop_table; 1977 uint8_t enable_acg_gb_fuse_table; 1978 uint32_t acg_dispclk2gfxclk_a; 1979 uint32_t acg_dispclk2gfxclk_b; 1980 uint32_t acg_dispclk2gfxclk_c; 1981 uint32_t acg_pixclk2gfxclk_a; 1982 uint32_t acg_pixclk2gfxclk_b; 1983 uint32_t acg_pixclk2gfxclk_c; 1984 uint32_t acg_dcefclk2gfxclk_a; 1985 uint32_t acg_dcefclk2gfxclk_b; 1986 uint32_t acg_dcefclk2gfxclk_c; 1987 uint32_t acg_phyclk2gfxclk_a; 1988 uint32_t acg_phyclk2gfxclk_b; 1989 uint32_t acg_phyclk2gfxclk_c; 1990 }; 1991 1992 /* 1993 *************************************************************************** 1994 Data Table multimedia_info structure 1995 *************************************************************************** 1996 */ 1997 struct atom_multimedia_info_v2_1 1998 { 1999 struct atom_common_table_header table_header; 2000 uint8_t uvdip_min_ver; 2001 uint8_t uvdip_max_ver; 2002 uint8_t vceip_min_ver; 2003 uint8_t vceip_max_ver; 2004 uint16_t uvd_enc_max_input_width_pixels; 2005 uint16_t uvd_enc_max_input_height_pixels; 2006 uint16_t vce_enc_max_input_width_pixels; 2007 uint16_t vce_enc_max_input_height_pixels; 2008 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2009 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent 2010 }; 2011 2012 2013 /* 2014 *************************************************************************** 2015 Data Table umc_info structure 2016 *************************************************************************** 2017 */ 2018 struct atom_umc_info_v3_1 2019 { 2020 struct atom_common_table_header table_header; 2021 uint32_t ucode_version; 2022 uint32_t ucode_rom_startaddr; 2023 uint32_t ucode_length; 2024 uint16_t umc_reg_init_offset; 2025 uint16_t customer_ucode_name_offset; 2026 uint16_t mclk_ss_percentage; 2027 uint16_t mclk_ss_rate_10hz; 2028 uint8_t umcip_min_ver; 2029 uint8_t umcip_max_ver; 2030 uint8_t vram_type; //enum of atom_dgpu_vram_type 2031 uint8_t umc_config; 2032 uint32_t mem_refclk_10khz; 2033 }; 2034 2035 // umc_info.umc_config 2036 enum atom_umc_config_def { 2037 UMC_CONFIG__ENABLE_1KB_INTERLEAVE_MODE = 0x00000001, 2038 UMC_CONFIG__DEFAULT_MEM_ECC_ENABLE = 0x00000002, 2039 UMC_CONFIG__ENABLE_HBM_LANE_REPAIR = 0x00000004, 2040 UMC_CONFIG__ENABLE_BANK_HARVESTING = 0x00000008, 2041 UMC_CONFIG__ENABLE_PHY_REINIT = 0x00000010, 2042 UMC_CONFIG__DISABLE_UCODE_CHKSTATUS = 0x00000020, 2043 }; 2044 2045 struct atom_umc_info_v3_2 2046 { 2047 struct atom_common_table_header table_header; 2048 uint32_t ucode_version; 2049 uint32_t ucode_rom_startaddr; 2050 uint32_t ucode_length; 2051 uint16_t umc_reg_init_offset; 2052 uint16_t customer_ucode_name_offset; 2053 uint16_t mclk_ss_percentage; 2054 uint16_t mclk_ss_rate_10hz; 2055 uint8_t umcip_min_ver; 2056 uint8_t umcip_max_ver; 2057 uint8_t vram_type; //enum of atom_dgpu_vram_type 2058 uint8_t umc_config; 2059 uint32_t mem_refclk_10khz; 2060 uint32_t pstate_uclk_10khz[4]; 2061 uint16_t umcgoldenoffset; 2062 uint16_t densitygoldenoffset; 2063 }; 2064 2065 struct atom_umc_info_v3_3 2066 { 2067 struct atom_common_table_header table_header; 2068 uint32_t ucode_reserved; 2069 uint32_t ucode_rom_startaddr; 2070 uint32_t ucode_length; 2071 uint16_t umc_reg_init_offset; 2072 uint16_t customer_ucode_name_offset; 2073 uint16_t mclk_ss_percentage; 2074 uint16_t mclk_ss_rate_10hz; 2075 uint8_t umcip_min_ver; 2076 uint8_t umcip_max_ver; 2077 uint8_t vram_type; //enum of atom_dgpu_vram_type 2078 uint8_t umc_config; 2079 uint32_t mem_refclk_10khz; 2080 uint32_t pstate_uclk_10khz[4]; 2081 uint16_t umcgoldenoffset; 2082 uint16_t densitygoldenoffset; 2083 uint32_t reserved[4]; 2084 }; 2085 2086 /* 2087 *************************************************************************** 2088 Data Table vram_info structure 2089 *************************************************************************** 2090 */ 2091 struct atom_vram_module_v9 { 2092 // Design Specific Values 2093 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2094 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2095 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2096 uint16_t reserved[3]; 2097 uint16_t mem_voltage; // mem_voltage 2098 uint16_t vram_module_size; // Size of atom_vram_module_v9 2099 uint8_t ext_memory_id; // Current memory module ID 2100 uint8_t memory_type; // enum of atom_dgpu_vram_type 2101 uint8_t channel_num; // Number of mem. channels supported in this module 2102 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2103 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2104 uint8_t tunningset_id; // MC phy registers set per. 2105 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2106 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2107 uint8_t hbm_ven_rev_id; // hbm_ven_rev_id 2108 uint8_t vram_rsd2; // reserved 2109 char dram_pnstring[20]; // part number end with '0'. 2110 }; 2111 2112 struct atom_vram_info_header_v2_3 { 2113 struct atom_common_table_header table_header; 2114 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2115 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2116 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2117 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2118 uint16_t dram_data_remap_tbloffset; // reserved for now 2119 uint16_t tmrs_seq_offset; // offset of HBM tmrs 2120 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2121 uint16_t vram_rsd2; 2122 uint8_t vram_module_num; // indicate number of VRAM module 2123 uint8_t umcip_min_ver; 2124 uint8_t umcip_max_ver; 2125 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2126 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2127 }; 2128 2129 struct atom_umc_register_addr_info{ 2130 uint32_t umc_register_addr:24; 2131 uint32_t umc_reg_type_ind:1; 2132 uint32_t umc_reg_rsvd:7; 2133 }; 2134 2135 //atom_umc_register_addr_info. 2136 enum atom_umc_register_addr_info_flag{ 2137 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01, 2138 }; 2139 2140 union atom_umc_register_addr_info_access 2141 { 2142 struct atom_umc_register_addr_info umc_reg_addr; 2143 uint32_t u32umc_reg_addr; 2144 }; 2145 2146 struct atom_umc_reg_setting_id_config{ 2147 uint32_t memclockrange:24; 2148 uint32_t mem_blk_id:8; 2149 }; 2150 2151 union atom_umc_reg_setting_id_config_access 2152 { 2153 struct atom_umc_reg_setting_id_config umc_id_access; 2154 uint32_t u32umc_id_access; 2155 }; 2156 2157 struct atom_umc_reg_setting_data_block{ 2158 union atom_umc_reg_setting_id_config_access block_id; 2159 uint32_t u32umc_reg_data[1]; 2160 }; 2161 2162 struct atom_umc_init_reg_block{ 2163 uint16_t umc_reg_num; 2164 uint16_t reserved; 2165 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num; 2166 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1]; 2167 }; 2168 2169 struct atom_vram_module_v10 { 2170 // Design Specific Values 2171 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros 2172 uint32_t channel_enable; // bit vector, each bit indicate specific channel enable or not 2173 uint32_t max_mem_clk; // max memory clock of this memory in unit of 10kHz, =0 means it is not defined 2174 uint16_t reserved[3]; 2175 uint16_t mem_voltage; // mem_voltage 2176 uint16_t vram_module_size; // Size of atom_vram_module_v9 2177 uint8_t ext_memory_id; // Current memory module ID 2178 uint8_t memory_type; // enum of atom_dgpu_vram_type 2179 uint8_t channel_num; // Number of mem. channels supported in this module 2180 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT 2181 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16 2182 uint8_t tunningset_id; // MC phy registers set per 2183 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code 2184 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms) 2185 uint8_t vram_flags; // bit0= bankgroup enable 2186 uint8_t vram_rsd2; // reserved 2187 uint16_t gddr6_mr10; // gddr6 mode register10 value 2188 uint16_t gddr6_mr1; // gddr6 mode register1 value 2189 uint16_t gddr6_mr2; // gddr6 mode register2 value 2190 uint16_t gddr6_mr7; // gddr6 mode register7 value 2191 char dram_pnstring[20]; // part number end with '0' 2192 }; 2193 2194 struct atom_vram_info_header_v2_4 { 2195 struct atom_common_table_header table_header; 2196 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting 2197 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting 2198 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings 2199 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set 2200 uint16_t dram_data_remap_tbloffset; // reserved for now 2201 uint16_t reserved; // offset of reserved 2202 uint16_t post_ucode_init_offset; // offset of atom_umc_init_reg_block structure for MC phy init after MC uCode complete umc init 2203 uint16_t vram_rsd2; 2204 uint8_t vram_module_num; // indicate number of VRAM module 2205 uint8_t umcip_min_ver; 2206 uint8_t umcip_max_ver; 2207 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset 2208 struct atom_vram_module_v10 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule; 2209 }; 2210 2211 /* 2212 *************************************************************************** 2213 Data Table voltageobject_info structure 2214 *************************************************************************** 2215 */ 2216 struct atom_i2c_data_entry 2217 { 2218 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit 2219 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit 2220 }; 2221 2222 struct atom_voltage_object_header_v4{ 2223 uint8_t voltage_type; //enum atom_voltage_type 2224 uint8_t voltage_mode; //enum atom_voltage_object_mode 2225 uint16_t object_size; //Size of Object 2226 }; 2227 2228 // atom_voltage_object_header_v4.voltage_mode 2229 enum atom_voltage_object_mode 2230 { 2231 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4 2232 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4 2233 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4 2234 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4 2235 VOLTAGE_OBJ_EVV = 8, 2236 VOLTAGE_OBJ_MERGED_POWER = 9, 2237 }; 2238 2239 struct atom_i2c_voltage_object_v4 2240 { 2241 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ 2242 uint8_t regulator_id; //Indicate Voltage Regulator Id 2243 uint8_t i2c_id; 2244 uint8_t i2c_slave_addr; 2245 uint8_t i2c_control_offset; 2246 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data 2247 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz. 2248 uint8_t reserved[2]; 2249 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff 2250 }; 2251 2252 // ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag 2253 enum atom_i2c_voltage_control_flag 2254 { 2255 VOLTAGE_DATA_ONE_BYTE = 0, 2256 VOLTAGE_DATA_TWO_BYTE = 1, 2257 }; 2258 2259 2260 struct atom_voltage_gpio_map_lut 2261 { 2262 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register 2263 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV 2264 }; 2265 2266 struct atom_gpio_voltage_object_v4 2267 { 2268 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT 2269 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode 2270 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table 2271 uint8_t phase_delay_us; // phase delay in unit of micro second 2272 uint8_t reserved; 2273 uint32_t gpio_mask_val; // GPIO Mask value 2274 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1]; 2275 }; 2276 2277 struct atom_svid2_voltage_object_v4 2278 { 2279 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2 2280 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable 2281 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold 2282 uint8_t psi0_enable; // 2283 uint8_t maxvstep; 2284 uint8_t telemetry_offset; 2285 uint8_t telemetry_gain; 2286 uint16_t reserved1; 2287 }; 2288 2289 struct atom_merged_voltage_object_v4 2290 { 2291 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER 2292 uint8_t merged_powerrail_type; //enum atom_voltage_type 2293 uint8_t reserved[3]; 2294 }; 2295 2296 union atom_voltage_object_v4{ 2297 struct atom_gpio_voltage_object_v4 gpio_voltage_obj; 2298 struct atom_i2c_voltage_object_v4 i2c_voltage_obj; 2299 struct atom_svid2_voltage_object_v4 svid2_voltage_obj; 2300 struct atom_merged_voltage_object_v4 merged_voltage_obj; 2301 }; 2302 2303 struct atom_voltage_objects_info_v4_1 2304 { 2305 struct atom_common_table_header table_header; 2306 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control 2307 }; 2308 2309 2310 /* 2311 *************************************************************************** 2312 All Command Function structure definition 2313 *************************************************************************** 2314 */ 2315 2316 /* 2317 *************************************************************************** 2318 Structures used by asic_init 2319 *************************************************************************** 2320 */ 2321 2322 struct asic_init_engine_parameters 2323 { 2324 uint32_t sclkfreqin10khz:24; 2325 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */ 2326 }; 2327 2328 struct asic_init_mem_parameters 2329 { 2330 uint32_t mclkfreqin10khz:24; 2331 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */ 2332 }; 2333 2334 struct asic_init_parameters_v2_1 2335 { 2336 struct asic_init_engine_parameters engineparam; 2337 struct asic_init_mem_parameters memparam; 2338 }; 2339 2340 struct asic_init_ps_allocation_v2_1 2341 { 2342 struct asic_init_parameters_v2_1 param; 2343 uint32_t reserved[16]; 2344 }; 2345 2346 2347 enum atom_asic_init_engine_flag 2348 { 2349 b3NORMAL_ENGINE_INIT = 0, 2350 b3SRIOV_SKIP_ASIC_INIT = 0x02, 2351 b3SRIOV_LOAD_UCODE = 0x40, 2352 }; 2353 2354 enum atom_asic_init_mem_flag 2355 { 2356 b3NORMAL_MEM_INIT = 0, 2357 b3DRAM_SELF_REFRESH_EXIT =0x20, 2358 }; 2359 2360 /* 2361 *************************************************************************** 2362 Structures used by setengineclock 2363 *************************************************************************** 2364 */ 2365 2366 struct set_engine_clock_parameters_v2_1 2367 { 2368 uint32_t sclkfreqin10khz:24; 2369 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2370 uint32_t reserved[10]; 2371 }; 2372 2373 struct set_engine_clock_ps_allocation_v2_1 2374 { 2375 struct set_engine_clock_parameters_v2_1 clockinfo; 2376 uint32_t reserved[10]; 2377 }; 2378 2379 2380 enum atom_set_engine_mem_clock_flag 2381 { 2382 b3NORMAL_CHANGE_CLOCK = 0, 2383 b3FIRST_TIME_CHANGE_CLOCK = 0x08, 2384 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result 2385 }; 2386 2387 /* 2388 *************************************************************************** 2389 Structures used by getengineclock 2390 *************************************************************************** 2391 */ 2392 struct get_engine_clock_parameter 2393 { 2394 uint32_t sclk_10khz; // current engine speed in 10KHz unit 2395 uint32_t reserved; 2396 }; 2397 2398 /* 2399 *************************************************************************** 2400 Structures used by setmemoryclock 2401 *************************************************************************** 2402 */ 2403 struct set_memory_clock_parameters_v2_1 2404 { 2405 uint32_t mclkfreqin10khz:24; 2406 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */ 2407 uint32_t reserved[10]; 2408 }; 2409 2410 struct set_memory_clock_ps_allocation_v2_1 2411 { 2412 struct set_memory_clock_parameters_v2_1 clockinfo; 2413 uint32_t reserved[10]; 2414 }; 2415 2416 2417 /* 2418 *************************************************************************** 2419 Structures used by getmemoryclock 2420 *************************************************************************** 2421 */ 2422 struct get_memory_clock_parameter 2423 { 2424 uint32_t mclk_10khz; // current engine speed in 10KHz unit 2425 uint32_t reserved; 2426 }; 2427 2428 2429 2430 /* 2431 *************************************************************************** 2432 Structures used by setvoltage 2433 *************************************************************************** 2434 */ 2435 2436 struct set_voltage_parameters_v1_4 2437 { 2438 uint8_t voltagetype; /* enum atom_voltage_type */ 2439 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */ 2440 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */ 2441 }; 2442 2443 //set_voltage_parameters_v2_1.voltagemode 2444 enum atom_set_voltage_command{ 2445 ATOM_SET_VOLTAGE = 0, 2446 ATOM_INIT_VOLTAGE_REGULATOR = 3, 2447 ATOM_SET_VOLTAGE_PHASE = 4, 2448 ATOM_GET_LEAKAGE_ID = 8, 2449 }; 2450 2451 struct set_voltage_ps_allocation_v1_4 2452 { 2453 struct set_voltage_parameters_v1_4 setvoltageparam; 2454 uint32_t reserved[10]; 2455 }; 2456 2457 2458 /* 2459 *************************************************************************** 2460 Structures used by computegpuclockparam 2461 *************************************************************************** 2462 */ 2463 2464 //ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag 2465 enum atom_gpu_clock_type 2466 { 2467 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00, 2468 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01, 2469 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02, 2470 }; 2471 2472 struct compute_gpu_clock_input_parameter_v1_8 2473 { 2474 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2475 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type 2476 uint32_t reserved[5]; 2477 }; 2478 2479 2480 struct compute_gpu_clock_output_parameter_v1_8 2481 { 2482 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock 2483 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly 2484 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac 2485 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac 2486 uint16_t pll_ss_slew_frac; 2487 uint8_t pll_ss_enable; 2488 uint8_t reserved; 2489 uint32_t reserved1[2]; 2490 }; 2491 2492 2493 2494 /* 2495 *************************************************************************** 2496 Structures used by ReadEfuseValue 2497 *************************************************************************** 2498 */ 2499 2500 struct read_efuse_input_parameters_v3_1 2501 { 2502 uint16_t efuse_start_index; 2503 uint8_t reserved; 2504 uint8_t bitslen; 2505 }; 2506 2507 // ReadEfuseValue input/output parameter 2508 union read_efuse_value_parameters_v3_1 2509 { 2510 struct read_efuse_input_parameters_v3_1 efuse_info; 2511 uint32_t efusevalue; 2512 }; 2513 2514 2515 /* 2516 *************************************************************************** 2517 Structures used by getsmuclockinfo 2518 *************************************************************************** 2519 */ 2520 struct atom_get_smu_clock_info_parameters_v3_1 2521 { 2522 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2 2523 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2524 uint8_t command; // enum of atom_get_smu_clock_info_command 2525 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ ) 2526 }; 2527 2528 enum atom_get_smu_clock_info_command 2529 { 2530 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0, 2531 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1, 2532 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2, 2533 }; 2534 2535 enum atom_smu9_syspll0_clock_id 2536 { 2537 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK 2538 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK) 2539 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 2540 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK 2541 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK 2542 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK 2543 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK 2544 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK 2545 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK 2546 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK 2547 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK 2548 }; 2549 2550 enum atom_smu11_syspll_id { 2551 SMU11_SYSPLL0_ID = 0, 2552 SMU11_SYSPLL1_0_ID = 1, 2553 SMU11_SYSPLL1_1_ID = 2, 2554 SMU11_SYSPLL1_2_ID = 3, 2555 SMU11_SYSPLL2_ID = 4, 2556 SMU11_SYSPLL3_0_ID = 5, 2557 SMU11_SYSPLL3_1_ID = 6, 2558 }; 2559 2560 enum atom_smu11_syspll0_clock_id { 2561 SMU11_SYSPLL0_ECLK_ID = 0, // ECLK 2562 SMU11_SYSPLL0_SOCCLK_ID = 1, // SOCCLK 2563 SMU11_SYSPLL0_MP0CLK_ID = 2, // MP0CLK 2564 SMU11_SYSPLL0_DCLK_ID = 3, // DCLK 2565 SMU11_SYSPLL0_VCLK_ID = 4, // VCLK 2566 SMU11_SYSPLL0_DCEFCLK_ID = 5, // DCEFCLK 2567 }; 2568 2569 enum atom_smu11_syspll1_0_clock_id { 2570 SMU11_SYSPLL1_0_UCLKA_ID = 0, // UCLK_a 2571 }; 2572 2573 enum atom_smu11_syspll1_1_clock_id { 2574 SMU11_SYSPLL1_0_UCLKB_ID = 0, // UCLK_b 2575 }; 2576 2577 enum atom_smu11_syspll1_2_clock_id { 2578 SMU11_SYSPLL1_0_FCLK_ID = 0, // FCLK 2579 }; 2580 2581 enum atom_smu11_syspll2_clock_id { 2582 SMU11_SYSPLL2_GFXCLK_ID = 0, // GFXCLK 2583 }; 2584 2585 enum atom_smu11_syspll3_0_clock_id { 2586 SMU11_SYSPLL3_0_WAFCLK_ID = 0, // WAFCLK 2587 SMU11_SYSPLL3_0_DISPCLK_ID = 1, // DISPCLK 2588 SMU11_SYSPLL3_0_DPREFCLK_ID = 2, // DPREFCLK 2589 }; 2590 2591 enum atom_smu11_syspll3_1_clock_id { 2592 SMU11_SYSPLL3_1_MP1CLK_ID = 0, // MP1CLK 2593 SMU11_SYSPLL3_1_SMNCLK_ID = 1, // SMNCLK 2594 SMU11_SYSPLL3_1_LCLK_ID = 2, // LCLK 2595 }; 2596 2597 struct atom_get_smu_clock_info_output_parameters_v3_1 2598 { 2599 union { 2600 uint32_t smu_clock_freq_hz; 2601 uint32_t syspllvcofreq_10khz; 2602 uint32_t sysspllrefclk_10khz; 2603 }atom_smu_outputclkfreq; 2604 }; 2605 2606 2607 2608 /* 2609 *************************************************************************** 2610 Structures used by dynamicmemorysettings 2611 *************************************************************************** 2612 */ 2613 2614 enum atom_dynamic_memory_setting_command 2615 { 2616 COMPUTE_MEMORY_PLL_PARAM = 1, 2617 COMPUTE_ENGINE_PLL_PARAM = 2, 2618 ADJUST_MC_SETTING_PARAM = 3, 2619 }; 2620 2621 /* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */ 2622 struct dynamic_mclk_settings_parameters_v2_1 2623 { 2624 uint32_t mclk_10khz:24; //Input= target mclk 2625 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 2626 uint32_t reserved; 2627 }; 2628 2629 /* when command = COMPUTE_ENGINE_PLL_PARAM */ 2630 struct dynamic_sclk_settings_parameters_v2_1 2631 { 2632 uint32_t sclk_10khz:24; //Input= target mclk 2633 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command 2634 uint32_t mclk_10khz; 2635 uint32_t reserved; 2636 }; 2637 2638 union dynamic_memory_settings_parameters_v2_1 2639 { 2640 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting; 2641 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting; 2642 }; 2643 2644 2645 2646 /* 2647 *************************************************************************** 2648 Structures used by memorytraining 2649 *************************************************************************** 2650 */ 2651 2652 enum atom_umc6_0_ucode_function_call_enum_id 2653 { 2654 UMC60_UCODE_FUNC_ID_REINIT = 0, 2655 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1, 2656 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2, 2657 }; 2658 2659 2660 struct memory_training_parameters_v2_1 2661 { 2662 uint8_t ucode_func_id; 2663 uint8_t ucode_reserved[3]; 2664 uint32_t reserved[5]; 2665 }; 2666 2667 2668 /* 2669 *************************************************************************** 2670 Structures used by setpixelclock 2671 *************************************************************************** 2672 */ 2673 2674 struct set_pixel_clock_parameter_v1_7 2675 { 2676 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz. 2677 2678 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0 2679 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h, 2680 // indicate which graphic encoder will be used. 2681 uint8_t encoder_mode; // Encoder mode: 2682 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info 2683 uint8_t crtc_id; // enum of atom_crtc_def 2684 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio 2685 uint8_t reserved1[2]; 2686 uint32_t reserved2; 2687 }; 2688 2689 //ucMiscInfo 2690 enum atom_set_pixel_clock_v1_7_misc_info 2691 { 2692 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01, 2693 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02, 2694 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04, 2695 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08, 2696 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30, 2697 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00, 2698 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10, 2699 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20, 2700 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30, 2701 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40, 2702 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80, 2703 }; 2704 2705 /* deep_color_ratio */ 2706 enum atom_set_pixel_clock_v1_7_deepcolor_ratio 2707 { 2708 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2709 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2710 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2711 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2712 }; 2713 2714 /* 2715 *************************************************************************** 2716 Structures used by setdceclock 2717 *************************************************************************** 2718 */ 2719 2720 // SetDCEClock input parameter for DCE11.2( ELM and BF ) and above 2721 struct set_dce_clock_parameters_v2_1 2722 { 2723 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. 2724 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK 2725 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx 2726 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 ) 2727 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK 2728 }; 2729 2730 //ucDCEClkType 2731 enum atom_set_dce_clock_clock_type 2732 { 2733 DCE_CLOCK_TYPE_DISPCLK = 0, 2734 DCE_CLOCK_TYPE_DPREFCLK = 1, 2735 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock 2736 }; 2737 2738 //ucDCEClkFlag when ucDCEClkType == DPREFCLK 2739 enum atom_set_dce_clock_dprefclk_flag 2740 { 2741 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03, 2742 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00, 2743 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01, 2744 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02, 2745 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03, 2746 }; 2747 2748 //ucDCEClkFlag when ucDCEClkType == PIXCLK 2749 enum atom_set_dce_clock_pixclk_flag 2750 { 2751 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03, 2752 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO 2753 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4 2754 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2 2755 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1 2756 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04, 2757 }; 2758 2759 struct set_dce_clock_ps_allocation_v2_1 2760 { 2761 struct set_dce_clock_parameters_v2_1 param; 2762 uint32_t ulReserved[2]; 2763 }; 2764 2765 2766 /****************************************************************************/ 2767 // Structures used by BlankCRTC 2768 /****************************************************************************/ 2769 struct blank_crtc_parameters 2770 { 2771 uint8_t crtc_id; // enum atom_crtc_def 2772 uint8_t blanking; // enum atom_blank_crtc_command 2773 uint16_t reserved; 2774 uint32_t reserved1; 2775 }; 2776 2777 enum atom_blank_crtc_command 2778 { 2779 ATOM_BLANKING = 1, 2780 ATOM_BLANKING_OFF = 0, 2781 }; 2782 2783 /****************************************************************************/ 2784 // Structures used by enablecrtc 2785 /****************************************************************************/ 2786 struct enable_crtc_parameters 2787 { 2788 uint8_t crtc_id; // enum atom_crtc_def 2789 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 2790 uint8_t padding[2]; 2791 }; 2792 2793 2794 /****************************************************************************/ 2795 // Structure used by EnableDispPowerGating 2796 /****************************************************************************/ 2797 struct enable_disp_power_gating_parameters_v2_1 2798 { 2799 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ... 2800 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE 2801 uint8_t padding[2]; 2802 }; 2803 2804 struct enable_disp_power_gating_ps_allocation 2805 { 2806 struct enable_disp_power_gating_parameters_v2_1 param; 2807 uint32_t ulReserved[4]; 2808 }; 2809 2810 /****************************************************************************/ 2811 // Structure used in setcrtc_usingdtdtiming 2812 /****************************************************************************/ 2813 struct set_crtc_using_dtd_timing_parameters 2814 { 2815 uint16_t h_size; 2816 uint16_t h_blanking_time; 2817 uint16_t v_size; 2818 uint16_t v_blanking_time; 2819 uint16_t h_syncoffset; 2820 uint16_t h_syncwidth; 2821 uint16_t v_syncoffset; 2822 uint16_t v_syncwidth; 2823 uint16_t modemiscinfo; 2824 uint8_t h_border; 2825 uint8_t v_border; 2826 uint8_t crtc_id; // enum atom_crtc_def 2827 uint8_t encoder_mode; // atom_encode_mode_def 2828 uint8_t padding[2]; 2829 }; 2830 2831 2832 /****************************************************************************/ 2833 // Structures used by processi2cchanneltransaction 2834 /****************************************************************************/ 2835 struct process_i2c_channel_transaction_parameters 2836 { 2837 uint8_t i2cspeed_khz; 2838 union { 2839 uint8_t regindex; 2840 uint8_t status; /* enum atom_process_i2c_flag */ 2841 } regind_status; 2842 uint16_t i2c_data_out; 2843 uint8_t flag; /* enum atom_process_i2c_status */ 2844 uint8_t trans_bytes; 2845 uint8_t slave_addr; 2846 uint8_t i2c_id; 2847 }; 2848 2849 //ucFlag 2850 enum atom_process_i2c_flag 2851 { 2852 HW_I2C_WRITE = 1, 2853 HW_I2C_READ = 0, 2854 I2C_2BYTE_ADDR = 0x02, 2855 HW_I2C_SMBUS_BYTE_WR = 0x04, 2856 }; 2857 2858 //status 2859 enum atom_process_i2c_status 2860 { 2861 HW_ASSISTED_I2C_STATUS_FAILURE =2, 2862 HW_ASSISTED_I2C_STATUS_SUCCESS =1, 2863 }; 2864 2865 2866 /****************************************************************************/ 2867 // Structures used by processauxchanneltransaction 2868 /****************************************************************************/ 2869 2870 struct process_aux_channel_transaction_parameters_v1_2 2871 { 2872 uint16_t aux_request; 2873 uint16_t dataout; 2874 uint8_t channelid; 2875 union { 2876 uint8_t reply_status; 2877 uint8_t aux_delay; 2878 } aux_status_delay; 2879 uint8_t dataout_len; 2880 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6 2881 }; 2882 2883 2884 /****************************************************************************/ 2885 // Structures used by selectcrtc_source 2886 /****************************************************************************/ 2887 2888 struct select_crtc_source_parameters_v2_3 2889 { 2890 uint8_t crtc_id; // enum atom_crtc_def 2891 uint8_t encoder_id; // enum atom_dig_def 2892 uint8_t encode_mode; // enum atom_encode_mode_def 2893 uint8_t dst_bpc; // enum atom_panel_bit_per_color 2894 }; 2895 2896 2897 /****************************************************************************/ 2898 // Structures used by digxencodercontrol 2899 /****************************************************************************/ 2900 2901 // ucAction: 2902 enum atom_dig_encoder_control_action 2903 { 2904 ATOM_ENCODER_CMD_DISABLE_DIG = 0, 2905 ATOM_ENCODER_CMD_ENABLE_DIG = 1, 2906 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08, 2907 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09, 2908 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a, 2909 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13, 2910 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b, 2911 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c, 2912 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d, 2913 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10, 2914 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14, 2915 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F, 2916 ATOM_ENCODER_CMD_LINK_SETUP = 0x11, 2917 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12, 2918 }; 2919 2920 //define ucPanelMode 2921 enum atom_dig_encoder_control_panelmode 2922 { 2923 DP_PANEL_MODE_DISABLE = 0x00, 2924 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01, 2925 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11, 2926 }; 2927 2928 //ucDigId 2929 enum atom_dig_encoder_control_v5_digid 2930 { 2931 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00, 2932 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01, 2933 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02, 2934 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03, 2935 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04, 2936 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05, 2937 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06, 2938 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07, 2939 }; 2940 2941 struct dig_encoder_stream_setup_parameters_v1_5 2942 { 2943 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2944 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP 2945 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2946 uint8_t lanenum; // Lane number 2947 uint32_t pclk_10khz; // Pixel Clock in 10Khz 2948 uint8_t bitpercolor; 2949 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc 2950 uint8_t reserved[2]; 2951 }; 2952 2953 struct dig_encoder_link_setup_parameters_v1_5 2954 { 2955 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2956 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP 2957 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI 2958 uint8_t lanenum; // Lane number 2959 uint8_t symclk_10khz; // Symbol Clock in 10Khz 2960 uint8_t hpd_sel; 2961 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 2962 uint8_t reserved[2]; 2963 }; 2964 2965 struct dp_panel_mode_set_parameters_v1_5 2966 { 2967 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2968 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP 2969 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode 2970 uint8_t reserved1; 2971 uint32_t reserved2[2]; 2972 }; 2973 2974 struct dig_encoder_generic_cmd_parameters_v1_5 2975 { 2976 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid 2977 uint8_t action; // = rest of generic encoder command which does not carry any parameters 2978 uint8_t reserved1[2]; 2979 uint32_t reserved2[2]; 2980 }; 2981 2982 union dig_encoder_control_parameters_v1_5 2983 { 2984 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param; 2985 struct dig_encoder_stream_setup_parameters_v1_5 stream_param; 2986 struct dig_encoder_link_setup_parameters_v1_5 link_param; 2987 struct dp_panel_mode_set_parameters_v1_5 dppanel_param; 2988 }; 2989 2990 /* 2991 *************************************************************************** 2992 Structures used by dig1transmittercontrol 2993 *************************************************************************** 2994 */ 2995 struct dig_transmitter_control_parameters_v1_6 2996 { 2997 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF 2998 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx 2999 union { 3000 uint8_t digmode; // enum atom_encode_mode_def 3001 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV" 3002 } mode_laneset; 3003 uint8_t lanenum; // Lane number 1, 2, 4, 8 3004 uint32_t symclk_10khz; // Symbol Clock in 10Khz 3005 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned 3006 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable, 3007 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h 3008 uint8_t reserved; 3009 uint32_t reserved1; 3010 }; 3011 3012 struct dig_transmitter_control_ps_allocation_v1_6 3013 { 3014 struct dig_transmitter_control_parameters_v1_6 param; 3015 uint32_t reserved[4]; 3016 }; 3017 3018 //ucAction 3019 enum atom_dig_transmitter_control_action 3020 { 3021 ATOM_TRANSMITTER_ACTION_DISABLE = 0, 3022 ATOM_TRANSMITTER_ACTION_ENABLE = 1, 3023 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2, 3024 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3, 3025 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4, 3026 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5, 3027 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6, 3028 ATOM_TRANSMITTER_ACTION_INIT = 7, 3029 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8, 3030 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9, 3031 ATOM_TRANSMITTER_ACTION_SETUP = 10, 3032 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11, 3033 ATOM_TRANSMITTER_ACTION_POWER_ON = 12, 3034 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13, 3035 }; 3036 3037 // digfe_sel 3038 enum atom_dig_transmitter_control_digfe_sel 3039 { 3040 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01, 3041 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02, 3042 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04, 3043 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08, 3044 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10, 3045 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20, 3046 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40, 3047 }; 3048 3049 3050 //ucHPDSel 3051 enum atom_dig_transmitter_control_hpd_sel 3052 { 3053 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00, 3054 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01, 3055 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02, 3056 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03, 3057 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04, 3058 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05, 3059 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06, 3060 }; 3061 3062 // ucDPLaneSet 3063 enum atom_dig_transmitter_control_dplaneset 3064 { 3065 DP_LANE_SET__0DB_0_4V = 0x00, 3066 DP_LANE_SET__0DB_0_6V = 0x01, 3067 DP_LANE_SET__0DB_0_8V = 0x02, 3068 DP_LANE_SET__0DB_1_2V = 0x03, 3069 DP_LANE_SET__3_5DB_0_4V = 0x08, 3070 DP_LANE_SET__3_5DB_0_6V = 0x09, 3071 DP_LANE_SET__3_5DB_0_8V = 0x0a, 3072 DP_LANE_SET__6DB_0_4V = 0x10, 3073 DP_LANE_SET__6DB_0_6V = 0x11, 3074 DP_LANE_SET__9_5DB_0_4V = 0x18, 3075 }; 3076 3077 3078 3079 /****************************************************************************/ 3080 // Structures used by ExternalEncoderControl V2.4 3081 /****************************************************************************/ 3082 3083 struct external_encoder_control_parameters_v2_4 3084 { 3085 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT 3086 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT 3087 uint8_t action; // 3088 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT 3089 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT 3090 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP 3091 uint8_t hpd_id; 3092 }; 3093 3094 3095 // ucAction 3096 enum external_encoder_control_action_def 3097 { 3098 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00, 3099 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01, 3100 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07, 3101 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f, 3102 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10, 3103 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11, 3104 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12, 3105 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14, 3106 }; 3107 3108 // ucConfig 3109 enum external_encoder_control_v2_4_config_def 3110 { 3111 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03, 3112 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00, 3113 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01, 3114 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02, 3115 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03, 3116 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70, 3117 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00, 3118 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10, 3119 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20, 3120 }; 3121 3122 struct external_encoder_control_ps_allocation_v2_4 3123 { 3124 struct external_encoder_control_parameters_v2_4 sExtEncoder; 3125 uint32_t reserved[2]; 3126 }; 3127 3128 3129 /* 3130 *************************************************************************** 3131 AMD ACPI Table 3132 3133 *************************************************************************** 3134 */ 3135 3136 struct amd_acpi_description_header{ 3137 uint32_t signature; 3138 uint32_t tableLength; //Length 3139 uint8_t revision; 3140 uint8_t checksum; 3141 uint8_t oemId[6]; 3142 uint8_t oemTableId[8]; //UINT64 OemTableId; 3143 uint32_t oemRevision; 3144 uint32_t creatorId; 3145 uint32_t creatorRevision; 3146 }; 3147 3148 struct uefi_acpi_vfct{ 3149 struct amd_acpi_description_header sheader; 3150 uint8_t tableUUID[16]; //0x24 3151 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture. 3152 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture. 3153 uint32_t reserved[4]; //0x3C 3154 }; 3155 3156 struct vfct_image_header{ 3157 uint32_t pcibus; //0x4C 3158 uint32_t pcidevice; //0x50 3159 uint32_t pcifunction; //0x54 3160 uint16_t vendorid; //0x58 3161 uint16_t deviceid; //0x5A 3162 uint16_t ssvid; //0x5C 3163 uint16_t ssid; //0x5E 3164 uint32_t revision; //0x60 3165 uint32_t imagelength; //0x64 3166 }; 3167 3168 3169 struct gop_vbios_content { 3170 struct vfct_image_header vbiosheader; 3171 uint8_t vbioscontent[1]; 3172 }; 3173 3174 struct gop_lib1_content { 3175 struct vfct_image_header lib1header; 3176 uint8_t lib1content[1]; 3177 }; 3178 3179 3180 3181 /* 3182 *************************************************************************** 3183 Scratch Register definitions 3184 Each number below indicates which scratch regiser request, Active and 3185 Connect all share the same definitions as display_device_tag defines 3186 *************************************************************************** 3187 */ 3188 3189 enum scratch_register_def{ 3190 ATOM_DEVICE_CONNECT_INFO_DEF = 0, 3191 ATOM_BL_BRI_LEVEL_INFO_DEF = 2, 3192 ATOM_ACTIVE_INFO_DEF = 3, 3193 ATOM_LCD_INFO_DEF = 4, 3194 ATOM_DEVICE_REQ_INFO_DEF = 5, 3195 ATOM_ACC_CHANGE_INFO_DEF = 6, 3196 ATOM_PRE_OS_MODE_INFO_DEF = 7, 3197 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers. 3198 ATOM_INTERNAL_TIMER_INFO_DEF = 10, 3199 }; 3200 3201 enum scratch_device_connect_info_bit_def{ 3202 ATOM_DISPLAY_LCD1_CONNECT =0x0002, 3203 ATOM_DISPLAY_DFP1_CONNECT =0x0008, 3204 ATOM_DISPLAY_DFP2_CONNECT =0x0080, 3205 ATOM_DISPLAY_DFP3_CONNECT =0x0200, 3206 ATOM_DISPLAY_DFP4_CONNECT =0x0400, 3207 ATOM_DISPLAY_DFP5_CONNECT =0x0800, 3208 ATOM_DISPLAY_DFP6_CONNECT =0x0040, 3209 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8, 3210 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff, 3211 }; 3212 3213 enum scratch_bl_bri_level_info_bit_def{ 3214 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8, 3215 #ifndef _H2INC 3216 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00, 3217 ATOM_DEVICE_DPMS_STATE =0x00010000, 3218 #endif 3219 }; 3220 3221 enum scratch_active_info_bits_def{ 3222 ATOM_DISPLAY_LCD1_ACTIVE =0x0002, 3223 ATOM_DISPLAY_DFP1_ACTIVE =0x0008, 3224 ATOM_DISPLAY_DFP2_ACTIVE =0x0080, 3225 ATOM_DISPLAY_DFP3_ACTIVE =0x0200, 3226 ATOM_DISPLAY_DFP4_ACTIVE =0x0400, 3227 ATOM_DISPLAY_DFP5_ACTIVE =0x0800, 3228 ATOM_DISPLAY_DFP6_ACTIVE =0x0040, 3229 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff, 3230 }; 3231 3232 enum scratch_device_req_info_bits_def{ 3233 ATOM_DISPLAY_LCD1_REQ =0x0002, 3234 ATOM_DISPLAY_DFP1_REQ =0x0008, 3235 ATOM_DISPLAY_DFP2_REQ =0x0080, 3236 ATOM_DISPLAY_DFP3_REQ =0x0200, 3237 ATOM_DISPLAY_DFP4_REQ =0x0400, 3238 ATOM_DISPLAY_DFP5_REQ =0x0800, 3239 ATOM_DISPLAY_DFP6_REQ =0x0040, 3240 ATOM_REQ_INFO_DEVICE_MASK =0x0fff, 3241 }; 3242 3243 enum scratch_acc_change_info_bitshift_def{ 3244 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4, 3245 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6, 3246 }; 3247 3248 enum scratch_acc_change_info_bits_def{ 3249 ATOM_ACC_CHANGE_ACC_MODE =0x00000010, 3250 ATOM_ACC_CHANGE_LID_STATUS =0x00000040, 3251 }; 3252 3253 enum scratch_pre_os_mode_info_bits_def{ 3254 ATOM_PRE_OS_MODE_MASK =0x00000003, 3255 ATOM_PRE_OS_MODE_VGA =0x00000000, 3256 ATOM_PRE_OS_MODE_VESA =0x00000001, 3257 ATOM_PRE_OS_MODE_GOP =0x00000002, 3258 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C, 3259 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0, 3260 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100, 3261 ATOM_ASIC_INIT_COMPLETE =0x00000200, 3262 #ifndef _H2INC 3263 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000, 3264 #endif 3265 }; 3266 3267 3268 3269 /* 3270 *************************************************************************** 3271 ATOM firmware ID header file 3272 !! Please keep it at end of the atomfirmware.h !! 3273 *************************************************************************** 3274 */ 3275 #include "atomfirmwareid.h" 3276 #pragma pack() 3277 3278 #endif 3279 3280
