1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #ifndef ATH12K_CORE_H
8 #define ATH12K_CORE_H
9
10 #include <linux/types.h>
11 #include <linux/interrupt.h>
12 #include <linux/irq.h>
13 #include <linux/bitfield.h>
14 #include "qmi.h"
15 #include "htc.h"
16 #include "wmi.h"
17 #include "hal.h"
18 #include "dp.h"
19 #include "ce.h"
20 #include "mac.h"
21 #include "hw.h"
22 #include "hal_rx.h"
23 #include "reg.h"
24 #include "dbring.h"
25
26 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
27
28 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512
29
30 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
31
32 /* Pending management packets threshold for dropping probe responses */
33 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
34
35 #define ATH12K_INVALID_HW_MAC_ID 0xFF
36 #define ATH12K_RX_RATE_TABLE_NUM 320
37 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576
38
39 #define ATH12K_MON_TIMER_INTERVAL 10
40 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ)
41 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3
42 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5
43 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ)
44 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ)
45 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ)
46
47 enum wme_ac {
48 WME_AC_BE,
49 WME_AC_BK,
50 WME_AC_VI,
51 WME_AC_VO,
52 WME_NUM_AC
53 };
54
55 #define ATH12K_HT_MCS_MAX 7
56 #define ATH12K_VHT_MCS_MAX 9
57 #define ATH12K_HE_MCS_MAX 11
58
59 enum ath12k_crypt_mode {
60 /* Only use hardware crypto engine */
61 ATH12K_CRYPT_MODE_HW,
62 /* Only use software crypto */
63 ATH12K_CRYPT_MODE_SW,
64 };
65
ath12k_tid_to_ac(u32 tid)66 static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
67 {
68 return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
69 ((tid == 1) || (tid == 2)) ? WME_AC_BK :
70 ((tid == 4) || (tid == 5)) ? WME_AC_VI :
71 WME_AC_VO);
72 }
73
74 enum ath12k_skb_flags {
75 ATH12K_SKB_HW_80211_ENCAP = BIT(0),
76 ATH12K_SKB_CIPHER_SET = BIT(1),
77 };
78
79 struct ath12k_skb_cb {
80 dma_addr_t paddr;
81 struct ath12k *ar;
82 struct ieee80211_vif *vif;
83 dma_addr_t paddr_ext_desc;
84 u32 cipher;
85 u8 flags;
86 };
87
88 struct ath12k_skb_rxcb {
89 dma_addr_t paddr;
90 bool is_first_msdu;
91 bool is_last_msdu;
92 bool is_continuation;
93 bool is_mcbc;
94 bool is_eapol;
95 struct hal_rx_desc *rx_desc;
96 u8 err_rel_src;
97 u8 err_code;
98 u8 mac_id;
99 u8 unmapped;
100 u8 is_frag;
101 u8 tid;
102 u16 peer_id;
103 };
104
105 enum ath12k_hw_rev {
106 ATH12K_HW_QCN9274_HW10,
107 ATH12K_HW_QCN9274_HW20,
108 ATH12K_HW_WCN7850_HW20
109 };
110
111 enum ath12k_firmware_mode {
112 /* the default mode, standard 802.11 functionality */
113 ATH12K_FIRMWARE_MODE_NORMAL,
114
115 /* factory tests etc */
116 ATH12K_FIRMWARE_MODE_FTM,
117 };
118
119 #define ATH12K_IRQ_NUM_MAX 57
120 #define ATH12K_EXT_IRQ_NUM_MAX 16
121
122 struct ath12k_ext_irq_grp {
123 struct ath12k_base *ab;
124 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
125 u32 num_irq;
126 u32 grp_id;
127 u64 timestamp;
128 struct napi_struct napi;
129 struct net_device napi_ndev;
130 };
131
132 #define HEHANDLE_CAP_PHYINFO_SIZE 3
133 #define HECAP_PHYINFO_SIZE 9
134 #define HECAP_MACINFO_SIZE 5
135 #define HECAP_TXRX_MCS_NSS_SIZE 2
136 #define HECAP_PPET16_PPET8_MAX_SIZE 25
137
138 #define HE_PPET16_PPET8_SIZE 8
139
140 /* 802.11ax PPE (PPDU packet Extension) threshold */
141 struct he_ppe_threshold {
142 u32 numss_m1;
143 u32 ru_mask;
144 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
145 };
146
147 struct ath12k_he {
148 u8 hecap_macinfo[HECAP_MACINFO_SIZE];
149 u32 hecap_rxmcsnssmap;
150 u32 hecap_txmcsnssmap;
151 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
152 struct he_ppe_threshold hecap_ppet;
153 u32 heop_param;
154 };
155
156 #define MAX_RADIOS 3
157
158 enum {
159 WMI_HOST_TP_SCALE_MAX = 0,
160 WMI_HOST_TP_SCALE_50 = 1,
161 WMI_HOST_TP_SCALE_25 = 2,
162 WMI_HOST_TP_SCALE_12 = 3,
163 WMI_HOST_TP_SCALE_MIN = 4,
164 WMI_HOST_TP_SCALE_SIZE = 5,
165 };
166
167 enum ath12k_scan_state {
168 ATH12K_SCAN_IDLE,
169 ATH12K_SCAN_STARTING,
170 ATH12K_SCAN_RUNNING,
171 ATH12K_SCAN_ABORTING,
172 };
173
174 enum ath12k_dev_flags {
175 ATH12K_CAC_RUNNING,
176 ATH12K_FLAG_CRASH_FLUSH,
177 ATH12K_FLAG_RAW_MODE,
178 ATH12K_FLAG_HW_CRYPTO_DISABLED,
179 ATH12K_FLAG_RECOVERY,
180 ATH12K_FLAG_UNREGISTERING,
181 ATH12K_FLAG_REGISTERED,
182 ATH12K_FLAG_QMI_FAIL,
183 ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
184 };
185
186 enum ath12k_monitor_flags {
187 ATH12K_FLAG_MONITOR_ENABLED,
188 };
189
190 struct ath12k_vif {
191 u32 vdev_id;
192 enum wmi_vdev_type vdev_type;
193 enum wmi_vdev_subtype vdev_subtype;
194 u32 beacon_interval;
195 u32 dtim_period;
196 u16 ast_hash;
197 u16 ast_idx;
198 u16 tcl_metadata;
199 u8 hal_addr_search_flags;
200 u8 search_type;
201
202 struct ath12k *ar;
203 struct ieee80211_vif *vif;
204
205 int bank_id;
206 u8 vdev_id_check_en;
207
208 struct wmi_wmm_params_all_arg wmm_params;
209 struct list_head list;
210 union {
211 struct {
212 u32 uapsd;
213 } sta;
214 struct {
215 /* 127 stations; wmi limit */
216 u8 tim_bitmap[16];
217 u8 tim_len;
218 u32 ssid_len;
219 u8 ssid[IEEE80211_MAX_SSID_LEN];
220 bool hidden_ssid;
221 /* P2P_IE with NoA attribute for P2P_GO case */
222 u32 noa_len;
223 u8 *noa_data;
224 } ap;
225 } u;
226
227 bool is_started;
228 bool is_up;
229 u32 aid;
230 u8 bssid[ETH_ALEN];
231 struct cfg80211_bitrate_mask bitrate_mask;
232 int num_legacy_stations;
233 int rtscts_prot_mode;
234 int txpower;
235 bool rsnie_present;
236 bool wpaie_present;
237 struct ieee80211_chanctx_conf chanctx;
238 u32 key_cipher;
239 u8 tx_encap_type;
240 u8 vdev_stats_id;
241 u32 punct_bitmap;
242 };
243
244 struct ath12k_vif_iter {
245 u32 vdev_id;
246 struct ath12k_vif *arvif;
247 };
248
249 #define HAL_AST_IDX_INVALID 0xFFFF
250 #define HAL_RX_MAX_MCS 12
251 #define HAL_RX_MAX_MCS_HT 31
252 #define HAL_RX_MAX_MCS_VHT 9
253 #define HAL_RX_MAX_MCS_HE 11
254 #define HAL_RX_MAX_NSS 8
255 #define HAL_RX_MAX_NUM_LEGACY_RATES 12
256 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576
257 #define ATH12K_RX_RATE_TABLE_NUM 320
258
259 struct ath12k_rx_peer_rate_stats {
260 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
261 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
262 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
263 u64 nss_count[HAL_RX_MAX_NSS];
264 u64 bw_count[HAL_RX_BW_MAX];
265 u64 gi_count[HAL_RX_GI_MAX];
266 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
267 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM];
268 };
269
270 struct ath12k_rx_peer_stats {
271 u64 num_msdu;
272 u64 num_mpdu_fcs_ok;
273 u64 num_mpdu_fcs_err;
274 u64 tcp_msdu_count;
275 u64 udp_msdu_count;
276 u64 other_msdu_count;
277 u64 ampdu_msdu_count;
278 u64 non_ampdu_msdu_count;
279 u64 stbc_count;
280 u64 beamformed_count;
281 u64 mcs_count[HAL_RX_MAX_MCS + 1];
282 u64 nss_count[HAL_RX_MAX_NSS];
283 u64 bw_count[HAL_RX_BW_MAX];
284 u64 gi_count[HAL_RX_GI_MAX];
285 u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
286 u64 tid_count[IEEE80211_NUM_TIDS + 1];
287 u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
288 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
289 u64 rx_duration;
290 u64 dcm_count;
291 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
292 struct ath12k_rx_peer_rate_stats pkt_stats;
293 struct ath12k_rx_peer_rate_stats byte_stats;
294 };
295
296 #define ATH12K_HE_MCS_NUM 12
297 #define ATH12K_VHT_MCS_NUM 10
298 #define ATH12K_BW_NUM 5
299 #define ATH12K_NSS_NUM 4
300 #define ATH12K_LEGACY_NUM 12
301 #define ATH12K_GI_NUM 4
302 #define ATH12K_HT_MCS_NUM 32
303
304 enum ath12k_pkt_rx_err {
305 ATH12K_PKT_RX_ERR_FCS,
306 ATH12K_PKT_RX_ERR_TKIP,
307 ATH12K_PKT_RX_ERR_CRYPT,
308 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
309 ATH12K_PKT_RX_ERR_MAX,
310 };
311
312 enum ath12k_ampdu_subfrm_num {
313 ATH12K_AMPDU_SUBFRM_NUM_10,
314 ATH12K_AMPDU_SUBFRM_NUM_20,
315 ATH12K_AMPDU_SUBFRM_NUM_30,
316 ATH12K_AMPDU_SUBFRM_NUM_40,
317 ATH12K_AMPDU_SUBFRM_NUM_50,
318 ATH12K_AMPDU_SUBFRM_NUM_60,
319 ATH12K_AMPDU_SUBFRM_NUM_MORE,
320 ATH12K_AMPDU_SUBFRM_NUM_MAX,
321 };
322
323 enum ath12k_amsdu_subfrm_num {
324 ATH12K_AMSDU_SUBFRM_NUM_1,
325 ATH12K_AMSDU_SUBFRM_NUM_2,
326 ATH12K_AMSDU_SUBFRM_NUM_3,
327 ATH12K_AMSDU_SUBFRM_NUM_4,
328 ATH12K_AMSDU_SUBFRM_NUM_MORE,
329 ATH12K_AMSDU_SUBFRM_NUM_MAX,
330 };
331
332 enum ath12k_counter_type {
333 ATH12K_COUNTER_TYPE_BYTES,
334 ATH12K_COUNTER_TYPE_PKTS,
335 ATH12K_COUNTER_TYPE_MAX,
336 };
337
338 enum ath12k_stats_type {
339 ATH12K_STATS_TYPE_SUCC,
340 ATH12K_STATS_TYPE_FAIL,
341 ATH12K_STATS_TYPE_RETRY,
342 ATH12K_STATS_TYPE_AMPDU,
343 ATH12K_STATS_TYPE_MAX,
344 };
345
346 struct ath12k_htt_data_stats {
347 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
348 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
349 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
350 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
351 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
352 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
353 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
354 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
355 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
356 };
357
358 struct ath12k_htt_tx_stats {
359 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
360 u64 tx_duration;
361 u64 ba_fails;
362 u64 ack_fails;
363 u16 ru_start;
364 u16 ru_tones;
365 u32 mu_group[MAX_MU_GROUP_ID];
366 };
367
368 struct ath12k_per_ppdu_tx_stats {
369 u16 succ_pkts;
370 u16 failed_pkts;
371 u16 retry_pkts;
372 u32 succ_bytes;
373 u32 failed_bytes;
374 u32 retry_bytes;
375 };
376
377 struct ath12k_wbm_tx_stats {
378 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
379 };
380
381 struct ath12k_sta {
382 struct ath12k_vif *arvif;
383
384 /* the following are protected by ar->data_lock */
385 u32 changed; /* IEEE80211_RC_* */
386 u32 bw;
387 u32 nss;
388 u32 smps;
389 enum hal_pn_type pn_type;
390
391 struct work_struct update_wk;
392 struct rate_info txrate;
393 struct rate_info last_txrate;
394 u64 rx_duration;
395 u64 tx_duration;
396 u8 rssi_comb;
397 struct ath12k_rx_peer_stats *rx_stats;
398 struct ath12k_wbm_tx_stats *wbm_tx_stats;
399 u32 bw_prev;
400 };
401
402 #define ATH12K_MIN_5G_FREQ 4150
403 #define ATH12K_MIN_6G_FREQ 5945
404 #define ATH12K_MAX_6G_FREQ 7115
405 #define ATH12K_NUM_CHANS 100
406 #define ATH12K_MAX_5G_CHAN 173
407
408 enum ath12k_state {
409 ATH12K_STATE_OFF,
410 ATH12K_STATE_ON,
411 ATH12K_STATE_RESTARTING,
412 ATH12K_STATE_RESTARTED,
413 ATH12K_STATE_WEDGED,
414 /* Add other states as required */
415 };
416
417 /* Antenna noise floor */
418 #define ATH12K_DEFAULT_NOISE_FLOOR -95
419
420 struct ath12k_fw_stats {
421 u32 pdev_id;
422 u32 stats_id;
423 struct list_head pdevs;
424 struct list_head vdevs;
425 struct list_head bcn;
426 };
427
428 struct ath12k_per_peer_tx_stats {
429 u32 succ_bytes;
430 u32 retry_bytes;
431 u32 failed_bytes;
432 u32 duration;
433 u16 succ_pkts;
434 u16 retry_pkts;
435 u16 failed_pkts;
436 u16 ru_start;
437 u16 ru_tones;
438 u8 ba_fails;
439 u8 ppdu_type;
440 u32 mu_grpid;
441 u32 mu_pos;
442 bool is_ampdu;
443 };
444
445 #define ATH12K_FLUSH_TIMEOUT (5 * HZ)
446 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
447
448 struct ath12k {
449 struct ath12k_base *ab;
450 struct ath12k_pdev *pdev;
451 struct ieee80211_hw *hw;
452 struct ieee80211_ops *ops;
453 struct ath12k_wmi_pdev *wmi;
454 struct ath12k_pdev_dp dp;
455 u8 mac_addr[ETH_ALEN];
456 u32 ht_cap_info;
457 u32 vht_cap_info;
458 struct ath12k_he ar_he;
459 enum ath12k_state state;
460 bool supports_6ghz;
461 struct {
462 struct completion started;
463 struct completion completed;
464 struct completion on_channel;
465 struct delayed_work timeout;
466 enum ath12k_scan_state state;
467 bool is_roc;
468 int vdev_id;
469 int roc_freq;
470 bool roc_notify;
471 } scan;
472
473 struct {
474 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
475 struct ieee80211_sband_iftype_data
476 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
477 } mac;
478
479 unsigned long dev_flags;
480 unsigned int filter_flags;
481 unsigned long monitor_flags;
482 u32 min_tx_power;
483 u32 max_tx_power;
484 u32 txpower_limit_2g;
485 u32 txpower_limit_5g;
486 u32 txpower_scale;
487 u32 power_scale;
488 u32 chan_tx_pwr;
489 u32 num_stations;
490 u32 max_num_stations;
491 bool monitor_present;
492 /* To synchronize concurrent synchronous mac80211 callback operations,
493 * concurrent debugfs configuration and concurrent FW statistics events.
494 */
495 struct mutex conf_mutex;
496 /* protects the radio specific data like debug stats, ppdu_stats_info stats,
497 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info,
498 * channel context data, survey info, test mode data.
499 */
500 spinlock_t data_lock;
501
502 struct list_head arvifs;
503 /* should never be NULL; needed for regular htt rx */
504 struct ieee80211_channel *rx_channel;
505
506 /* valid during scan; needed for mgmt rx during scan */
507 struct ieee80211_channel *scan_channel;
508
509 u8 cfg_tx_chainmask;
510 u8 cfg_rx_chainmask;
511 u8 num_rx_chains;
512 u8 num_tx_chains;
513 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
514 u8 pdev_idx;
515 u8 lmac_id;
516
517 struct completion peer_assoc_done;
518 struct completion peer_delete_done;
519
520 int install_key_status;
521 struct completion install_key_done;
522
523 int last_wmi_vdev_start_status;
524 struct completion vdev_setup_done;
525 struct completion vdev_delete_done;
526
527 int num_peers;
528 int max_num_peers;
529 u32 num_started_vdevs;
530 u32 num_created_vdevs;
531 unsigned long long allocated_vdev_map;
532
533 struct idr txmgmt_idr;
534 /* protects txmgmt_idr data */
535 spinlock_t txmgmt_idr_lock;
536 atomic_t num_pending_mgmt_tx;
537 wait_queue_head_t txmgmt_empty_waitq;
538
539 /* cycle count is reported twice for each visited channel during scan.
540 * access protected by data_lock
541 */
542 u32 survey_last_rx_clear_count;
543 u32 survey_last_cycle_count;
544
545 /* Channel info events are expected to come in pairs without and with
546 * COMPLETE flag set respectively for each channel visit during scan.
547 *
548 * However there are deviations from this rule. This flag is used to
549 * avoid reporting garbage data.
550 */
551 bool ch_info_can_report_survey;
552 struct survey_info survey[ATH12K_NUM_CHANS];
553 struct completion bss_survey_done;
554
555 struct work_struct regd_update_work;
556
557 struct work_struct wmi_mgmt_tx_work;
558 struct sk_buff_head wmi_mgmt_tx_queue;
559
560 struct ath12k_per_peer_tx_stats peer_tx_stats;
561 struct list_head ppdu_stats_info;
562 u32 ppdu_stat_list_depth;
563
564 struct ath12k_per_peer_tx_stats cached_stats;
565 u32 last_ppdu_id;
566 u32 cached_ppdu_id;
567
568 bool dfs_block_radar_events;
569 bool monitor_conf_enabled;
570 bool monitor_vdev_created;
571 bool monitor_started;
572 int monitor_vdev_id;
573 };
574
575 struct ath12k_band_cap {
576 u32 phy_id;
577 u32 max_bw_supported;
578 u32 ht_cap_info;
579 u32 he_cap_info[2];
580 u32 he_mcs;
581 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
582 struct ath12k_wmi_ppe_threshold_arg he_ppet;
583 u16 he_6ghz_capa;
584 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
585 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
586 u32 eht_mcs_20_only;
587 u32 eht_mcs_80;
588 u32 eht_mcs_160;
589 u32 eht_mcs_320;
590 struct ath12k_wmi_ppe_threshold_arg eht_ppet;
591 u32 eht_cap_info_internal;
592 };
593
594 struct ath12k_pdev_cap {
595 u32 supported_bands;
596 u32 ampdu_density;
597 u32 vht_cap;
598 u32 vht_mcs;
599 u32 he_mcs;
600 u32 tx_chain_mask;
601 u32 rx_chain_mask;
602 u32 tx_chain_mask_shift;
603 u32 rx_chain_mask_shift;
604 struct ath12k_band_cap band[NUM_NL80211_BANDS];
605 };
606
607 struct mlo_timestamp {
608 u32 info;
609 u32 sync_timestamp_lo_us;
610 u32 sync_timestamp_hi_us;
611 u32 mlo_offset_lo;
612 u32 mlo_offset_hi;
613 u32 mlo_offset_clks;
614 u32 mlo_comp_clks;
615 u32 mlo_comp_timer;
616 };
617
618 struct ath12k_pdev {
619 struct ath12k *ar;
620 u32 pdev_id;
621 struct ath12k_pdev_cap cap;
622 u8 mac_addr[ETH_ALEN];
623 struct mlo_timestamp timestamp;
624 };
625
626 struct ath12k_fw_pdev {
627 u32 pdev_id;
628 u32 phy_id;
629 u32 supported_bands;
630 };
631
632 struct ath12k_board_data {
633 const struct firmware *fw;
634 const void *data;
635 size_t len;
636 };
637
638 struct ath12k_soc_dp_tx_err_stats {
639 /* TCL Ring Descriptor unavailable */
640 u32 desc_na[DP_TCL_NUM_RING_MAX];
641 /* Other failures during dp_tx due to mem allocation failure
642 * idr unavailable etc.
643 */
644 atomic_t misc_fail;
645 };
646
647 struct ath12k_soc_dp_stats {
648 u32 err_ring_pkts;
649 u32 invalid_rbm;
650 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
651 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
652 u32 hal_reo_error[DP_REO_DST_RING_MAX];
653 struct ath12k_soc_dp_tx_err_stats tx_err;
654 };
655
656 /* Master structure to hold the hw data which may be used in core module */
657 struct ath12k_base {
658 enum ath12k_hw_rev hw_rev;
659 struct platform_device *pdev;
660 struct device *dev;
661 struct ath12k_qmi qmi;
662 struct ath12k_wmi_base wmi_ab;
663 struct completion fw_ready;
664 int num_radios;
665 /* HW channel counters frequency value in hertz common to all MACs */
666 u32 cc_freq_hz;
667
668 struct ath12k_htc htc;
669
670 struct ath12k_dp dp;
671
672 void __iomem *mem;
673 unsigned long mem_len;
674
675 struct {
676 enum ath12k_bus bus;
677 const struct ath12k_hif_ops *ops;
678 } hif;
679
680 struct ath12k_ce ce;
681 struct timer_list rx_replenish_retry;
682 struct ath12k_hal hal;
683 /* To synchronize core_start/core_stop */
684 struct mutex core_lock;
685 /* Protects data like peers */
686 spinlock_t base_lock;
687
688 /* Single pdev device (struct ath12k_hw_params::single_pdev_only):
689 *
690 * Firmware maintains data for all bands but advertises a single
691 * phy to the host which is stored as a single element in this
692 * array.
693 *
694 * Other devices:
695 *
696 * This array will contain as many elements as the number of
697 * radios.
698 */
699 struct ath12k_pdev pdevs[MAX_RADIOS];
700
701 /* struct ath12k_hw_params::single_pdev_only devices use this to
702 * store phy specific data
703 */
704 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
705 u8 fw_pdev_count;
706
707 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
708 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
709 unsigned long long free_vdev_map;
710 unsigned long long free_vdev_stats_id_map;
711 struct list_head peers;
712 wait_queue_head_t peer_mapping_wq;
713 u8 mac_addr[ETH_ALEN];
714 bool wmi_ready;
715 u32 wlan_init_status;
716 int irq_num[ATH12K_IRQ_NUM_MAX];
717 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
718 struct napi_struct *napi;
719 struct ath12k_wmi_target_cap_arg target_caps;
720 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
721 bool pdevs_macaddr_valid;
722 int bd_api;
723
724 const struct ath12k_hw_params *hw_params;
725
726 const struct firmware *cal_file;
727
728 /* Below regd's are protected by ab->data_lock */
729 /* This is the regd set for every radio
730 * by the firmware during initialization
731 */
732 struct ieee80211_regdomain *default_regd[MAX_RADIOS];
733 /* This regd is set during dynamic country setting
734 * This may or may not be used during the runtime
735 */
736 struct ieee80211_regdomain *new_regd[MAX_RADIOS];
737
738 /* Current DFS Regulatory */
739 enum ath12k_dfs_region dfs_region;
740 struct ath12k_soc_dp_stats soc_stats;
741
742 unsigned long dev_flags;
743 struct completion driver_recovery;
744 struct workqueue_struct *workqueue;
745 struct work_struct restart_work;
746 struct workqueue_struct *workqueue_aux;
747 struct work_struct reset_work;
748 atomic_t reset_count;
749 atomic_t recovery_count;
750 atomic_t recovery_start_count;
751 bool is_reset;
752 struct completion reset_complete;
753 struct completion reconfigure_complete;
754 struct completion recovery_start;
755 /* continuous recovery fail count */
756 atomic_t fail_cont_count;
757 unsigned long reset_fail_timeout;
758 struct {
759 /* protected by data_lock */
760 u32 fw_crash_counter;
761 } stats;
762 u32 pktlog_defs_checksum;
763
764 struct ath12k_dbring_cap *db_caps;
765 u32 num_db_cap;
766
767 struct timer_list mon_reap_timer;
768
769 struct completion htc_suspend;
770
771 u64 fw_soc_drop_count;
772 bool static_window_map;
773
774 /* must be last */
775 u8 drv_priv[] __aligned(sizeof(void *));
776 };
777
778 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
779 int ath12k_core_pre_init(struct ath12k_base *ab);
780 int ath12k_core_init(struct ath12k_base *ath12k);
781 void ath12k_core_deinit(struct ath12k_base *ath12k);
782 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
783 enum ath12k_bus bus);
784 void ath12k_core_free(struct ath12k_base *ath12k);
785 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
786 struct ath12k_board_data *bd,
787 char *filename);
788 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
789 struct ath12k_board_data *bd);
790 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
791
792 void ath12k_core_halt(struct ath12k *ar);
793 int ath12k_core_resume(struct ath12k_base *ab);
794 int ath12k_core_suspend(struct ath12k_base *ab);
795
796 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
797 const char *filename);
798
ath12k_scan_state_str(enum ath12k_scan_state state)799 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
800 {
801 switch (state) {
802 case ATH12K_SCAN_IDLE:
803 return "idle";
804 case ATH12K_SCAN_STARTING:
805 return "starting";
806 case ATH12K_SCAN_RUNNING:
807 return "running";
808 case ATH12K_SCAN_ABORTING:
809 return "aborting";
810 }
811
812 return "unknown";
813 }
814
ATH12K_SKB_CB(struct sk_buff * skb)815 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
816 {
817 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
818 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
819 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
820 }
821
ATH12K_SKB_RXCB(struct sk_buff * skb)822 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
823 {
824 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
825 return (struct ath12k_skb_rxcb *)skb->cb;
826 }
827
ath12k_vif_to_arvif(struct ieee80211_vif * vif)828 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif)
829 {
830 return (struct ath12k_vif *)vif->drv_priv;
831 }
832
ath12k_ab_to_ar(struct ath12k_base * ab,int mac_id)833 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
834 int mac_id)
835 {
836 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
837 }
838
ath12k_core_create_firmware_path(struct ath12k_base * ab,const char * filename,void * buf,size_t buf_len)839 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
840 const char *filename,
841 void *buf, size_t buf_len)
842 {
843 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
844 ab->hw_params->fw.dir, filename);
845 }
846
ath12k_bus_str(enum ath12k_bus bus)847 static inline const char *ath12k_bus_str(enum ath12k_bus bus)
848 {
849 switch (bus) {
850 case ATH12K_BUS_PCI:
851 return "pci";
852 }
853
854 return "unknown";
855 }
856
857 #endif /* _CORE_H_ */
858
