1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * IOMMU API for ARM architected SMMU implementations.
4 *
5 * Copyright (C) 2013 ARM Limited
6 *
7 * Author: Will Deacon <will.deacon@arm.com>
8 */
9
10 #ifndef _ARM_SMMU_H
11 #define _ARM_SMMU_H
12
13 #include <linux/atomic.h>
14 #include <linux/bits.h>
15 #include <linux/clk.h>
16 #include <linux/device.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
20 #include <linux/mutex.h>
21 #include <linux/spinlock.h>
22 #include <linux/types.h>
23
24 /* Configuration registers */
25 #define ARM_SMMU_GR0_sCR0 0x0
26 #define sCR0_VMID16EN BIT(31)
27 #define sCR0_BSU GENMASK(15, 14)
28 #define sCR0_FB BIT(13)
29 #define sCR0_PTM BIT(12)
30 #define sCR0_VMIDPNE BIT(11)
31 #define sCR0_USFCFG BIT(10)
32 #define sCR0_GCFGFIE BIT(5)
33 #define sCR0_GCFGFRE BIT(4)
34 #define sCR0_EXIDENABLE BIT(3)
35 #define sCR0_GFIE BIT(2)
36 #define sCR0_GFRE BIT(1)
37 #define sCR0_CLIENTPD BIT(0)
38
39 /* Auxiliary Configuration register */
40 #define ARM_SMMU_GR0_sACR 0x10
41
42 /* Identification registers */
43 #define ARM_SMMU_GR0_ID0 0x20
44 #define ID0_S1TS BIT(30)
45 #define ID0_S2TS BIT(29)
46 #define ID0_NTS BIT(28)
47 #define ID0_SMS BIT(27)
48 #define ID0_ATOSNS BIT(26)
49 #define ID0_PTFS_NO_AARCH32 BIT(25)
50 #define ID0_PTFS_NO_AARCH32S BIT(24)
51 #define ID0_NUMIRPT GENMASK(23, 16)
52 #define ID0_CTTW BIT(14)
53 #define ID0_NUMSIDB GENMASK(12, 9)
54 #define ID0_EXIDS BIT(8)
55 #define ID0_NUMSMRG GENMASK(7, 0)
56
57 #define ARM_SMMU_GR0_ID1 0x24
58 #define ID1_PAGESIZE BIT(31)
59 #define ID1_NUMPAGENDXB GENMASK(30, 28)
60 #define ID1_NUMS2CB GENMASK(23, 16)
61 #define ID1_NUMCB GENMASK(7, 0)
62
63 #define ARM_SMMU_GR0_ID2 0x28
64 #define ID2_VMID16 BIT(15)
65 #define ID2_PTFS_64K BIT(14)
66 #define ID2_PTFS_16K BIT(13)
67 #define ID2_PTFS_4K BIT(12)
68 #define ID2_UBS GENMASK(11, 8)
69 #define ID2_OAS GENMASK(7, 4)
70 #define ID2_IAS GENMASK(3, 0)
71
72 #define ARM_SMMU_GR0_ID3 0x2c
73 #define ARM_SMMU_GR0_ID4 0x30
74 #define ARM_SMMU_GR0_ID5 0x34
75 #define ARM_SMMU_GR0_ID6 0x38
76
77 #define ARM_SMMU_GR0_ID7 0x3c
78 #define ID7_MAJOR GENMASK(7, 4)
79 #define ID7_MINOR GENMASK(3, 0)
80
81 #define ARM_SMMU_GR0_sGFSR 0x48
82 #define ARM_SMMU_GR0_sGFSYNR0 0x50
83 #define ARM_SMMU_GR0_sGFSYNR1 0x54
84 #define ARM_SMMU_GR0_sGFSYNR2 0x58
85
86 /* Global TLB invalidation */
87 #define ARM_SMMU_GR0_TLBIVMID 0x64
88 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
89 #define ARM_SMMU_GR0_TLBIALLH 0x6c
90 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
91
92 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
93 #define sTLBGSTATUS_GSACTIVE BIT(0)
94
95 /* Stream mapping registers */
96 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
97 #define SMR_VALID BIT(31)
98 #define SMR_MASK GENMASK(31, 16)
99 #define SMR_ID GENMASK(15, 0)
100
101 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
102 #define S2CR_PRIVCFG GENMASK(25, 24)
103 enum arm_smmu_s2cr_privcfg {
104 S2CR_PRIVCFG_DEFAULT,
105 S2CR_PRIVCFG_DIPAN,
106 S2CR_PRIVCFG_UNPRIV,
107 S2CR_PRIVCFG_PRIV,
108 };
109 #define S2CR_TYPE GENMASK(17, 16)
110 enum arm_smmu_s2cr_type {
111 S2CR_TYPE_TRANS,
112 S2CR_TYPE_BYPASS,
113 S2CR_TYPE_FAULT,
114 };
115 #define S2CR_EXIDVALID BIT(10)
116 #define S2CR_CBNDX GENMASK(7, 0)
117
118 /* Context bank attribute registers */
119 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
120 #define CBAR_IRPTNDX GENMASK(31, 24)
121 #define CBAR_TYPE GENMASK(17, 16)
122 enum arm_smmu_cbar_type {
123 CBAR_TYPE_S2_TRANS,
124 CBAR_TYPE_S1_TRANS_S2_BYPASS,
125 CBAR_TYPE_S1_TRANS_S2_FAULT,
126 CBAR_TYPE_S1_TRANS_S2_TRANS,
127 };
128 #define CBAR_S1_MEMATTR GENMASK(15, 12)
129 #define CBAR_S1_MEMATTR_WB 0xf
130 #define CBAR_S1_BPSHCFG GENMASK(9, 8)
131 #define CBAR_S1_BPSHCFG_NSH 3
132 #define CBAR_VMID GENMASK(7, 0)
133
134 #define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2))
135
136 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
137 #define CBA2R_VMID16 GENMASK(31, 16)
138 #define CBA2R_VA64 BIT(0)
139
140 #define ARM_SMMU_CB_SCTLR 0x0
141 #define SCTLR_S1_ASIDPNE BIT(12)
142 #define SCTLR_CFCFG BIT(7)
143 #define SCTLR_CFIE BIT(6)
144 #define SCTLR_CFRE BIT(5)
145 #define SCTLR_E BIT(4)
146 #define SCTLR_AFE BIT(2)
147 #define SCTLR_TRE BIT(1)
148 #define SCTLR_M BIT(0)
149
150 #define ARM_SMMU_CB_ACTLR 0x4
151
152 #define ARM_SMMU_CB_RESUME 0x8
153 #define RESUME_TERMINATE BIT(0)
154
155 #define ARM_SMMU_CB_TCR2 0x10
156 #define TCR2_SEP GENMASK(17, 15)
157 #define TCR2_SEP_UPSTREAM 0x7
158 #define TCR2_AS BIT(4)
159
160 #define ARM_SMMU_CB_TTBR0 0x20
161 #define ARM_SMMU_CB_TTBR1 0x28
162 #define TTBRn_ASID GENMASK_ULL(63, 48)
163
164 #define ARM_SMMU_CB_TCR 0x30
165 #define ARM_SMMU_CB_CONTEXTIDR 0x34
166 #define ARM_SMMU_CB_S1_MAIR0 0x38
167 #define ARM_SMMU_CB_S1_MAIR1 0x3c
168
169 #define ARM_SMMU_CB_PAR 0x50
170 #define CB_PAR_F BIT(0)
171
172 #define ARM_SMMU_CB_FSR 0x58
173 #define FSR_MULTI BIT(31)
174 #define FSR_SS BIT(30)
175 #define FSR_UUT BIT(8)
176 #define FSR_ASF BIT(7)
177 #define FSR_TLBLKF BIT(6)
178 #define FSR_TLBMCF BIT(5)
179 #define FSR_EF BIT(4)
180 #define FSR_PF BIT(3)
181 #define FSR_AFF BIT(2)
182 #define FSR_TF BIT(1)
183
184 #define FSR_IGN (FSR_AFF | FSR_ASF | \
185 FSR_TLBMCF | FSR_TLBLKF)
186 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
187 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
188
189 #define ARM_SMMU_CB_FAR 0x60
190
191 #define ARM_SMMU_CB_FSYNR0 0x68
192 #define FSYNR0_WNR BIT(4)
193
194 #define ARM_SMMU_CB_S1_TLBIVA 0x600
195 #define ARM_SMMU_CB_S1_TLBIASID 0x610
196 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
197 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
198 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
199 #define ARM_SMMU_CB_TLBSYNC 0x7f0
200 #define ARM_SMMU_CB_TLBSTATUS 0x7f4
201 #define ARM_SMMU_CB_ATS1PR 0x800
202
203 #define ARM_SMMU_CB_ATSR 0x8f0
204 #define ATSR_ACTIVE BIT(0)
205
206
207 /* Maximum number of context banks per SMMU */
208 #define ARM_SMMU_MAX_CBS 128
209
210
211 /* Shared driver definitions */
212 enum arm_smmu_arch_version {
213 ARM_SMMU_V1,
214 ARM_SMMU_V1_64K,
215 ARM_SMMU_V2,
216 };
217
218 enum arm_smmu_implementation {
219 GENERIC_SMMU,
220 ARM_MMU500,
221 CAVIUM_SMMUV2,
222 QCOM_SMMUV2,
223 };
224
225 struct arm_smmu_device {
226 struct device *dev;
227
228 void __iomem *base;
229 unsigned int numpage;
230 unsigned int pgshift;
231
232 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
233 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
234 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
235 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
236 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
237 #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
238 #define ARM_SMMU_FEAT_VMID16 (1 << 6)
239 #define ARM_SMMU_FEAT_FMT_AARCH64_4K (1 << 7)
240 #define ARM_SMMU_FEAT_FMT_AARCH64_16K (1 << 8)
241 #define ARM_SMMU_FEAT_FMT_AARCH64_64K (1 << 9)
242 #define ARM_SMMU_FEAT_FMT_AARCH32_L (1 << 10)
243 #define ARM_SMMU_FEAT_FMT_AARCH32_S (1 << 11)
244 #define ARM_SMMU_FEAT_EXIDS (1 << 12)
245 u32 features;
246
247 enum arm_smmu_arch_version version;
248 enum arm_smmu_implementation model;
249 const struct arm_smmu_impl *impl;
250
251 u32 num_context_banks;
252 u32 num_s2_context_banks;
253 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
254 struct arm_smmu_cb *cbs;
255 atomic_t irptndx;
256
257 u32 num_mapping_groups;
258 u16 streamid_mask;
259 u16 smr_mask_mask;
260 struct arm_smmu_smr *smrs;
261 struct arm_smmu_s2cr *s2crs;
262 struct mutex stream_map_mutex;
263
264 unsigned long va_size;
265 unsigned long ipa_size;
266 unsigned long pa_size;
267 unsigned long pgsize_bitmap;
268
269 u32 num_global_irqs;
270 u32 num_context_irqs;
271 unsigned int *irqs;
272 struct clk_bulk_data *clks;
273 int num_clks;
274
275 spinlock_t global_sync_lock;
276
277 /* IOMMU core code handle */
278 struct iommu_device iommu;
279 };
280
281 enum arm_smmu_context_fmt {
282 ARM_SMMU_CTX_FMT_NONE,
283 ARM_SMMU_CTX_FMT_AARCH64,
284 ARM_SMMU_CTX_FMT_AARCH32_L,
285 ARM_SMMU_CTX_FMT_AARCH32_S,
286 };
287
288 struct arm_smmu_cfg {
289 u8 cbndx;
290 u8 irptndx;
291 union {
292 u16 asid;
293 u16 vmid;
294 };
295 enum arm_smmu_cbar_type cbar;
296 enum arm_smmu_context_fmt fmt;
297 };
298 #define INVALID_IRPTNDX 0xff
299
300 enum arm_smmu_domain_stage {
301 ARM_SMMU_DOMAIN_S1 = 0,
302 ARM_SMMU_DOMAIN_S2,
303 ARM_SMMU_DOMAIN_NESTED,
304 ARM_SMMU_DOMAIN_BYPASS,
305 };
306
307 struct arm_smmu_flush_ops {
308 struct iommu_flush_ops tlb;
309 void (*tlb_inv_range)(unsigned long iova, size_t size, size_t granule,
310 bool leaf, void *cookie);
311 void (*tlb_sync)(void *cookie);
312 };
313
314 struct arm_smmu_domain {
315 struct arm_smmu_device *smmu;
316 struct io_pgtable_ops *pgtbl_ops;
317 const struct arm_smmu_flush_ops *flush_ops;
318 struct arm_smmu_cfg cfg;
319 enum arm_smmu_domain_stage stage;
320 bool non_strict;
321 struct mutex init_mutex; /* Protects smmu pointer */
322 spinlock_t cb_lock; /* Serialises ATS1* ops and TLB syncs */
323 struct iommu_domain domain;
324 };
325
326
327 /* Implementation details, yay! */
328 struct arm_smmu_impl {
329 u32 (*read_reg)(struct arm_smmu_device *smmu, int page, int offset);
330 void (*write_reg)(struct arm_smmu_device *smmu, int page, int offset,
331 u32 val);
332 u64 (*read_reg64)(struct arm_smmu_device *smmu, int page, int offset);
333 void (*write_reg64)(struct arm_smmu_device *smmu, int page, int offset,
334 u64 val);
335 int (*cfg_probe)(struct arm_smmu_device *smmu);
336 int (*reset)(struct arm_smmu_device *smmu);
337 int (*init_context)(struct arm_smmu_domain *smmu_domain);
338 };
339
arm_smmu_page(struct arm_smmu_device * smmu,int n)340 static inline void __iomem *arm_smmu_page(struct arm_smmu_device *smmu, int n)
341 {
342 return smmu->base + (n << smmu->pgshift);
343 }
344
arm_smmu_readl(struct arm_smmu_device * smmu,int page,int offset)345 static inline u32 arm_smmu_readl(struct arm_smmu_device *smmu, int page, int offset)
346 {
347 if (smmu->impl && unlikely(smmu->impl->read_reg))
348 return smmu->impl->read_reg(smmu, page, offset);
349 return readl_relaxed(arm_smmu_page(smmu, page) + offset);
350 }
351
arm_smmu_writel(struct arm_smmu_device * smmu,int page,int offset,u32 val)352 static inline void arm_smmu_writel(struct arm_smmu_device *smmu, int page,
353 int offset, u32 val)
354 {
355 if (smmu->impl && unlikely(smmu->impl->write_reg))
356 smmu->impl->write_reg(smmu, page, offset, val);
357 else
358 writel_relaxed(val, arm_smmu_page(smmu, page) + offset);
359 }
360
arm_smmu_readq(struct arm_smmu_device * smmu,int page,int offset)361 static inline u64 arm_smmu_readq(struct arm_smmu_device *smmu, int page, int offset)
362 {
363 if (smmu->impl && unlikely(smmu->impl->read_reg64))
364 return smmu->impl->read_reg64(smmu, page, offset);
365 return readq_relaxed(arm_smmu_page(smmu, page) + offset);
366 }
367
arm_smmu_writeq(struct arm_smmu_device * smmu,int page,int offset,u64 val)368 static inline void arm_smmu_writeq(struct arm_smmu_device *smmu, int page,
369 int offset, u64 val)
370 {
371 if (smmu->impl && unlikely(smmu->impl->write_reg64))
372 smmu->impl->write_reg64(smmu, page, offset, val);
373 else
374 writeq_relaxed(val, arm_smmu_page(smmu, page) + offset);
375 }
376
377 #define ARM_SMMU_GR0 0
378 #define ARM_SMMU_GR1 1
379 #define ARM_SMMU_CB(s, n) ((s)->numpage + (n))
380
381 #define arm_smmu_gr0_read(s, o) \
382 arm_smmu_readl((s), ARM_SMMU_GR0, (o))
383 #define arm_smmu_gr0_write(s, o, v) \
384 arm_smmu_writel((s), ARM_SMMU_GR0, (o), (v))
385
386 #define arm_smmu_gr1_read(s, o) \
387 arm_smmu_readl((s), ARM_SMMU_GR1, (o))
388 #define arm_smmu_gr1_write(s, o, v) \
389 arm_smmu_writel((s), ARM_SMMU_GR1, (o), (v))
390
391 #define arm_smmu_cb_read(s, n, o) \
392 arm_smmu_readl((s), ARM_SMMU_CB((s), (n)), (o))
393 #define arm_smmu_cb_write(s, n, o, v) \
394 arm_smmu_writel((s), ARM_SMMU_CB((s), (n)), (o), (v))
395 #define arm_smmu_cb_readq(s, n, o) \
396 arm_smmu_readq((s), ARM_SMMU_CB((s), (n)), (o))
397 #define arm_smmu_cb_writeq(s, n, o, v) \
398 arm_smmu_writeq((s), ARM_SMMU_CB((s), (n)), (o), (v))
399
400 struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu);
401
402 #endif /* _ARM_SMMU_H */
403
