1 /* SPDX-License-Identifier: GPL-2.0-only */
2 #ifndef _ASM_X86_APIC_H
3 #define _ASM_X86_APIC_H
4
5 #include <linux/cpumask.h>
6
7 #include <asm/alternative.h>
8 #include <asm/cpufeature.h>
9 #include <asm/apicdef.h>
10 #include <linux/atomic.h>
11 #include <asm/fixmap.h>
12 #include <asm/mpspec.h>
13 #include <asm/msr.h>
14 #include <asm/hardirq.h>
15
16 #define ARCH_APICTIMER_STOPS_ON_C3 1
17
18 /*
19 * Debugging macros
20 */
21 #define APIC_QUIET 0
22 #define APIC_VERBOSE 1
23 #define APIC_DEBUG 2
24
25 /* Macros for apic_extnmi which controls external NMI masking */
26 #define APIC_EXTNMI_BSP 0 /* Default */
27 #define APIC_EXTNMI_ALL 1
28 #define APIC_EXTNMI_NONE 2
29
30 /*
31 * Define the default level of output to be very little
32 * This can be turned up by using apic=verbose for more
33 * information and apic=debug for _lots_ of information.
34 * apic_verbosity is defined in apic.c
35 */
36 #define apic_printk(v, s, a...) do { \
37 if ((v) <= apic_verbosity) \
38 printk(s, ##a); \
39 } while (0)
40
41
42 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_X86_32)
43 extern void generic_apic_probe(void);
44 #else
generic_apic_probe(void)45 static inline void generic_apic_probe(void)
46 {
47 }
48 #endif
49
50 #ifdef CONFIG_X86_LOCAL_APIC
51
52 extern int apic_verbosity;
53 extern int local_apic_timer_c2_ok;
54
55 extern int disable_apic;
56 extern unsigned int lapic_timer_period;
57
58 extern enum apic_intr_mode_id apic_intr_mode;
59 enum apic_intr_mode_id {
60 APIC_PIC,
61 APIC_VIRTUAL_WIRE,
62 APIC_VIRTUAL_WIRE_NO_CONFIG,
63 APIC_SYMMETRIC_IO,
64 APIC_SYMMETRIC_IO_NO_ROUTING
65 };
66
67 #ifdef CONFIG_SMP
68 extern void __inquire_remote_apic(int apicid);
69 #else /* CONFIG_SMP */
__inquire_remote_apic(int apicid)70 static inline void __inquire_remote_apic(int apicid)
71 {
72 }
73 #endif /* CONFIG_SMP */
74
default_inquire_remote_apic(int apicid)75 static inline void default_inquire_remote_apic(int apicid)
76 {
77 if (apic_verbosity >= APIC_DEBUG)
78 __inquire_remote_apic(apicid);
79 }
80
81 /*
82 * With 82489DX we can't rely on apic feature bit
83 * retrieved via cpuid but still have to deal with
84 * such an apic chip so we assume that SMP configuration
85 * is found from MP table (64bit case uses ACPI mostly
86 * which set smp presence flag as well so we are safe
87 * to use this helper too).
88 */
apic_from_smp_config(void)89 static inline bool apic_from_smp_config(void)
90 {
91 return smp_found_config && !disable_apic;
92 }
93
94 /*
95 * Basic functions accessing APICs.
96 */
97 #ifdef CONFIG_PARAVIRT
98 #include <asm/paravirt.h>
99 #endif
100
101 extern int setup_profiling_timer(unsigned int);
102
native_apic_mem_write(u32 reg,u32 v)103 static inline void native_apic_mem_write(u32 reg, u32 v)
104 {
105 volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
106
107 alternative_io("movl %0, %P1", "xchgl %0, %P1", X86_BUG_11AP,
108 ASM_OUTPUT2("=r" (v), "=m" (*addr)),
109 ASM_OUTPUT2("0" (v), "m" (*addr)));
110 }
111
native_apic_mem_read(u32 reg)112 static inline u32 native_apic_mem_read(u32 reg)
113 {
114 return *((volatile u32 *)(APIC_BASE + reg));
115 }
116
117 extern void native_apic_wait_icr_idle(void);
118 extern u32 native_safe_apic_wait_icr_idle(void);
119 extern void native_apic_icr_write(u32 low, u32 id);
120 extern u64 native_apic_icr_read(void);
121
apic_is_x2apic_enabled(void)122 static inline bool apic_is_x2apic_enabled(void)
123 {
124 u64 msr;
125
126 if (rdmsrl_safe(MSR_IA32_APICBASE, &msr))
127 return false;
128 return msr & X2APIC_ENABLE;
129 }
130
131 extern void enable_IR_x2apic(void);
132
133 extern int get_physical_broadcast(void);
134
135 extern int lapic_get_maxlvt(void);
136 extern void clear_local_APIC(void);
137 extern void disconnect_bsp_APIC(int virt_wire_setup);
138 extern void disable_local_APIC(void);
139 extern void apic_soft_disable(void);
140 extern void lapic_shutdown(void);
141 extern void sync_Arb_IDs(void);
142 extern void init_bsp_APIC(void);
143 extern void apic_intr_mode_select(void);
144 extern void apic_intr_mode_init(void);
145 extern void init_apic_mappings(void);
146 void register_lapic_address(unsigned long address);
147 extern void setup_boot_APIC_clock(void);
148 extern void setup_secondary_APIC_clock(void);
149 extern void lapic_update_tsc_freq(void);
150
151 #ifdef CONFIG_X86_64
apic_force_enable(unsigned long addr)152 static inline int apic_force_enable(unsigned long addr)
153 {
154 return -1;
155 }
156 #else
157 extern int apic_force_enable(unsigned long addr);
158 #endif
159
160 extern void apic_ap_setup(void);
161
162 /*
163 * On 32bit this is mach-xxx local
164 */
165 #ifdef CONFIG_X86_64
166 extern int apic_is_clustered_box(void);
167 #else
apic_is_clustered_box(void)168 static inline int apic_is_clustered_box(void)
169 {
170 return 0;
171 }
172 #endif
173
174 extern int setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask);
175 extern void lapic_assign_system_vectors(void);
176 extern void lapic_assign_legacy_vector(unsigned int isairq, bool replace);
177 extern void lapic_online(void);
178 extern void lapic_offline(void);
179 extern bool apic_needs_pit(void);
180
181 extern void apic_send_IPI_allbutself(unsigned int vector);
182
183 #else /* !CONFIG_X86_LOCAL_APIC */
lapic_shutdown(void)184 static inline void lapic_shutdown(void) { }
185 #define local_apic_timer_c2_ok 1
init_apic_mappings(void)186 static inline void init_apic_mappings(void) { }
disable_local_APIC(void)187 static inline void disable_local_APIC(void) { }
188 # define setup_boot_APIC_clock x86_init_noop
189 # define setup_secondary_APIC_clock x86_init_noop
lapic_update_tsc_freq(void)190 static inline void lapic_update_tsc_freq(void) { }
init_bsp_APIC(void)191 static inline void init_bsp_APIC(void) { }
apic_intr_mode_select(void)192 static inline void apic_intr_mode_select(void) { }
apic_intr_mode_init(void)193 static inline void apic_intr_mode_init(void) { }
lapic_assign_system_vectors(void)194 static inline void lapic_assign_system_vectors(void) { }
lapic_assign_legacy_vector(unsigned int i,bool r)195 static inline void lapic_assign_legacy_vector(unsigned int i, bool r) { }
apic_needs_pit(void)196 static inline bool apic_needs_pit(void) { return true; }
197 #endif /* !CONFIG_X86_LOCAL_APIC */
198
199 #ifdef CONFIG_X86_X2APIC
200 /*
201 * Make previous memory operations globally visible before
202 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
203 * mfence for this.
204 */
x2apic_wrmsr_fence(void)205 static inline void x2apic_wrmsr_fence(void)
206 {
207 asm volatile("mfence" : : : "memory");
208 }
209
native_apic_msr_write(u32 reg,u32 v)210 static inline void native_apic_msr_write(u32 reg, u32 v)
211 {
212 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
213 reg == APIC_LVR)
214 return;
215
216 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
217 }
218
native_apic_msr_eoi_write(u32 reg,u32 v)219 static inline void native_apic_msr_eoi_write(u32 reg, u32 v)
220 {
221 __wrmsr(APIC_BASE_MSR + (APIC_EOI >> 4), APIC_EOI_ACK, 0);
222 }
223
native_apic_msr_read(u32 reg)224 static inline u32 native_apic_msr_read(u32 reg)
225 {
226 u64 msr;
227
228 if (reg == APIC_DFR)
229 return -1;
230
231 rdmsrl(APIC_BASE_MSR + (reg >> 4), msr);
232 return (u32)msr;
233 }
234
native_x2apic_wait_icr_idle(void)235 static inline void native_x2apic_wait_icr_idle(void)
236 {
237 /* no need to wait for icr idle in x2apic */
238 return;
239 }
240
native_safe_x2apic_wait_icr_idle(void)241 static inline u32 native_safe_x2apic_wait_icr_idle(void)
242 {
243 /* no need to wait for icr idle in x2apic */
244 return 0;
245 }
246
native_x2apic_icr_write(u32 low,u32 id)247 static inline void native_x2apic_icr_write(u32 low, u32 id)
248 {
249 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
250 }
251
native_x2apic_icr_read(void)252 static inline u64 native_x2apic_icr_read(void)
253 {
254 unsigned long val;
255
256 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
257 return val;
258 }
259
260 extern int x2apic_mode;
261 extern int x2apic_phys;
262 extern void __init check_x2apic(void);
263 extern void x2apic_setup(void);
x2apic_enabled(void)264 static inline int x2apic_enabled(void)
265 {
266 return boot_cpu_has(X86_FEATURE_X2APIC) && apic_is_x2apic_enabled();
267 }
268
269 #define x2apic_supported() (boot_cpu_has(X86_FEATURE_X2APIC))
270 #else /* !CONFIG_X86_X2APIC */
check_x2apic(void)271 static inline void check_x2apic(void) { }
x2apic_setup(void)272 static inline void x2apic_setup(void) { }
x2apic_enabled(void)273 static inline int x2apic_enabled(void) { return 0; }
274
275 #define x2apic_mode (0)
276 #define x2apic_supported() (0)
277 #endif /* !CONFIG_X86_X2APIC */
278
279 struct irq_data;
280
281 /*
282 * Copyright 2004 James Cleverdon, IBM.
283 *
284 * Generic APIC sub-arch data struct.
285 *
286 * Hacked for x86-64 by James Cleverdon from i386 architecture code by
287 * Martin Bligh, Andi Kleen, James Bottomley, John Stultz, and
288 * James Cleverdon.
289 */
290 struct apic {
291 /* Hotpath functions first */
292 void (*eoi_write)(u32 reg, u32 v);
293 void (*native_eoi_write)(u32 reg, u32 v);
294 void (*write)(u32 reg, u32 v);
295 u32 (*read)(u32 reg);
296
297 /* IPI related functions */
298 void (*wait_icr_idle)(void);
299 u32 (*safe_wait_icr_idle)(void);
300
301 void (*send_IPI)(int cpu, int vector);
302 void (*send_IPI_mask)(const struct cpumask *mask, int vector);
303 void (*send_IPI_mask_allbutself)(const struct cpumask *msk, int vec);
304 void (*send_IPI_allbutself)(int vector);
305 void (*send_IPI_all)(int vector);
306 void (*send_IPI_self)(int vector);
307
308 /* dest_logical is used by the IPI functions */
309 u32 dest_logical;
310 u32 disable_esr;
311 u32 irq_delivery_mode;
312 u32 irq_dest_mode;
313
314 u32 (*calc_dest_apicid)(unsigned int cpu);
315
316 /* ICR related functions */
317 u64 (*icr_read)(void);
318 void (*icr_write)(u32 low, u32 high);
319
320 /* Probe, setup and smpboot functions */
321 int (*probe)(void);
322 int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
323 int (*apic_id_valid)(u32 apicid);
324 int (*apic_id_registered)(void);
325
326 bool (*check_apicid_used)(physid_mask_t *map, int apicid);
327 void (*init_apic_ldr)(void);
328 void (*ioapic_phys_id_map)(physid_mask_t *phys_map, physid_mask_t *retmap);
329 void (*setup_apic_routing)(void);
330 int (*cpu_present_to_apicid)(int mps_cpu);
331 void (*apicid_to_cpu_present)(int phys_apicid, physid_mask_t *retmap);
332 int (*check_phys_apicid_present)(int phys_apicid);
333 int (*phys_pkg_id)(int cpuid_apic, int index_msb);
334
335 u32 (*get_apic_id)(unsigned long x);
336 u32 (*set_apic_id)(unsigned int id);
337
338 /* wakeup_secondary_cpu */
339 int (*wakeup_secondary_cpu)(int apicid, unsigned long start_eip);
340
341 void (*inquire_remote_apic)(int apicid);
342
343 #ifdef CONFIG_X86_32
344 /*
345 * Called very early during boot from get_smp_config(). It should
346 * return the logical apicid. x86_[bios]_cpu_to_apicid is
347 * initialized before this function is called.
348 *
349 * If logical apicid can't be determined that early, the function
350 * may return BAD_APICID. Logical apicid will be configured after
351 * init_apic_ldr() while bringing up CPUs. Note that NUMA affinity
352 * won't be applied properly during early boot in this case.
353 */
354 int (*x86_32_early_logical_apicid)(int cpu);
355 #endif
356 char *name;
357 };
358
359 /*
360 * Pointer to the local APIC driver in use on this system (there's
361 * always just one such driver in use - the kernel decides via an
362 * early probing process which one it picks - and then sticks to it):
363 */
364 extern struct apic *apic;
365
366 /*
367 * APIC drivers are probed based on how they are listed in the .apicdrivers
368 * section. So the order is important and enforced by the ordering
369 * of different apic driver files in the Makefile.
370 *
371 * For the files having two apic drivers, we use apic_drivers()
372 * to enforce the order with in them.
373 */
374 #define apic_driver(sym) \
375 static const struct apic *__apicdrivers_##sym __used \
376 __aligned(sizeof(struct apic *)) \
377 __section(".apicdrivers") = { &sym }
378
379 #define apic_drivers(sym1, sym2) \
380 static struct apic *__apicdrivers_##sym1##sym2[2] __used \
381 __aligned(sizeof(struct apic *)) \
382 __section(".apicdrivers") = { &sym1, &sym2 }
383
384 extern struct apic *__apicdrivers[], *__apicdrivers_end[];
385
386 /*
387 * APIC functionality to boot other CPUs - only used on SMP:
388 */
389 #ifdef CONFIG_SMP
390 extern int wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip);
391 extern int lapic_can_unplug_cpu(void);
392 #endif
393
394 #ifdef CONFIG_X86_LOCAL_APIC
395
apic_read(u32 reg)396 static inline u32 apic_read(u32 reg)
397 {
398 return apic->read(reg);
399 }
400
apic_write(u32 reg,u32 val)401 static inline void apic_write(u32 reg, u32 val)
402 {
403 apic->write(reg, val);
404 }
405
apic_eoi(void)406 static inline void apic_eoi(void)
407 {
408 apic->eoi_write(APIC_EOI, APIC_EOI_ACK);
409 }
410
apic_icr_read(void)411 static inline u64 apic_icr_read(void)
412 {
413 return apic->icr_read();
414 }
415
apic_icr_write(u32 low,u32 high)416 static inline void apic_icr_write(u32 low, u32 high)
417 {
418 apic->icr_write(low, high);
419 }
420
apic_wait_icr_idle(void)421 static inline void apic_wait_icr_idle(void)
422 {
423 apic->wait_icr_idle();
424 }
425
safe_apic_wait_icr_idle(void)426 static inline u32 safe_apic_wait_icr_idle(void)
427 {
428 return apic->safe_wait_icr_idle();
429 }
430
431 extern void __init apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v));
432
433 #else /* CONFIG_X86_LOCAL_APIC */
434
apic_read(u32 reg)435 static inline u32 apic_read(u32 reg) { return 0; }
apic_write(u32 reg,u32 val)436 static inline void apic_write(u32 reg, u32 val) { }
apic_eoi(void)437 static inline void apic_eoi(void) { }
apic_icr_read(void)438 static inline u64 apic_icr_read(void) { return 0; }
apic_icr_write(u32 low,u32 high)439 static inline void apic_icr_write(u32 low, u32 high) { }
apic_wait_icr_idle(void)440 static inline void apic_wait_icr_idle(void) { }
safe_apic_wait_icr_idle(void)441 static inline u32 safe_apic_wait_icr_idle(void) { return 0; }
apic_set_eoi_write(void (* eoi_write)(u32 reg,u32 v))442 static inline void apic_set_eoi_write(void (*eoi_write)(u32 reg, u32 v)) {}
443
444 #endif /* CONFIG_X86_LOCAL_APIC */
445
446 extern void apic_ack_irq(struct irq_data *data);
447
ack_APIC_irq(void)448 static inline void ack_APIC_irq(void)
449 {
450 /*
451 * ack_APIC_irq() actually gets compiled as a single instruction
452 * ... yummie.
453 */
454 apic_eoi();
455 }
456
457
lapic_vector_set_in_irr(unsigned int vector)458 static inline bool lapic_vector_set_in_irr(unsigned int vector)
459 {
460 u32 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
461
462 return !!(irr & (1U << (vector % 32)));
463 }
464
default_get_apic_id(unsigned long x)465 static inline unsigned default_get_apic_id(unsigned long x)
466 {
467 unsigned int ver = GET_APIC_VERSION(apic_read(APIC_LVR));
468
469 if (APIC_XAPIC(ver) || boot_cpu_has(X86_FEATURE_EXTD_APICID))
470 return (x >> 24) & 0xFF;
471 else
472 return (x >> 24) & 0x0F;
473 }
474
475 /*
476 * Warm reset vector position:
477 */
478 #define TRAMPOLINE_PHYS_LOW 0x467
479 #define TRAMPOLINE_PHYS_HIGH 0x469
480
481 extern void generic_bigsmp_probe(void);
482
483 #ifdef CONFIG_X86_LOCAL_APIC
484
485 #include <asm/smp.h>
486
487 #define APIC_DFR_VALUE (APIC_DFR_FLAT)
488
489 DECLARE_EARLY_PER_CPU_READ_MOSTLY(u16, x86_bios_cpu_apicid);
490
491 extern struct apic apic_noop;
492
read_apic_id(void)493 static inline unsigned int read_apic_id(void)
494 {
495 unsigned int reg = apic_read(APIC_ID);
496
497 return apic->get_apic_id(reg);
498 }
499
500 extern int default_apic_id_valid(u32 apicid);
501 extern int default_acpi_madt_oem_check(char *, char *);
502 extern void default_setup_apic_routing(void);
503
504 extern u32 apic_default_calc_apicid(unsigned int cpu);
505 extern u32 apic_flat_calc_apicid(unsigned int cpu);
506
507 extern bool default_check_apicid_used(physid_mask_t *map, int apicid);
508 extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap);
509 extern int default_cpu_present_to_apicid(int mps_cpu);
510 extern int default_check_phys_apicid_present(int phys_apicid);
511
512 #endif /* CONFIG_X86_LOCAL_APIC */
513
514 #ifdef CONFIG_SMP
515 bool apic_id_is_primary_thread(unsigned int id);
516 void apic_smt_update(void);
517 #else
apic_id_is_primary_thread(unsigned int id)518 static inline bool apic_id_is_primary_thread(unsigned int id) { return false; }
apic_smt_update(void)519 static inline void apic_smt_update(void) { }
520 #endif
521
522 struct msi_msg;
523
524 #ifdef CONFIG_PCI_MSI
525 void x86_vector_msi_compose_msg(struct irq_data *data, struct msi_msg *msg);
526 #else
527 # define x86_vector_msi_compose_msg NULL
528 #endif
529
530 extern void ioapic_zap_locks(void);
531
532 #endif /* _ASM_X86_APIC_H */
533
