1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __KGD_PP_INTERFACE_H__
25 #define __KGD_PP_INTERFACE_H__
26 
27 extern const struct amdgpu_ip_block_version pp_smu_ip_block;
28 
29 struct amd_vce_state {
30 	/* vce clocks */
31 	u32 evclk;
32 	u32 ecclk;
33 	/* gpu clocks */
34 	u32 sclk;
35 	u32 mclk;
36 	u8 clk_idx;
37 	u8 pstate;
38 };
39 
40 
41 enum amd_dpm_forced_level {
42 	AMD_DPM_FORCED_LEVEL_AUTO = 0x1,
43 	AMD_DPM_FORCED_LEVEL_MANUAL = 0x2,
44 	AMD_DPM_FORCED_LEVEL_LOW = 0x4,
45 	AMD_DPM_FORCED_LEVEL_HIGH = 0x8,
46 	AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD = 0x10,
47 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK = 0x20,
48 	AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK = 0x40,
49 	AMD_DPM_FORCED_LEVEL_PROFILE_PEAK = 0x80,
50 	AMD_DPM_FORCED_LEVEL_PROFILE_EXIT = 0x100,
51 };
52 
53 enum amd_pm_state_type {
54 	/* not used for dpm */
55 	POWER_STATE_TYPE_DEFAULT,
56 	POWER_STATE_TYPE_POWERSAVE,
57 	/* user selectable states */
58 	POWER_STATE_TYPE_BATTERY,
59 	POWER_STATE_TYPE_BALANCED,
60 	POWER_STATE_TYPE_PERFORMANCE,
61 	/* internal states */
62 	POWER_STATE_TYPE_INTERNAL_UVD,
63 	POWER_STATE_TYPE_INTERNAL_UVD_SD,
64 	POWER_STATE_TYPE_INTERNAL_UVD_HD,
65 	POWER_STATE_TYPE_INTERNAL_UVD_HD2,
66 	POWER_STATE_TYPE_INTERNAL_UVD_MVC,
67 	POWER_STATE_TYPE_INTERNAL_BOOT,
68 	POWER_STATE_TYPE_INTERNAL_THERMAL,
69 	POWER_STATE_TYPE_INTERNAL_ACPI,
70 	POWER_STATE_TYPE_INTERNAL_ULV,
71 	POWER_STATE_TYPE_INTERNAL_3DPERF,
72 };
73 
74 #define AMD_MAX_VCE_LEVELS 6
75 
76 enum amd_vce_level {
77 	AMD_VCE_LEVEL_AC_ALL = 0,     /* AC, All cases */
78 	AMD_VCE_LEVEL_DC_EE = 1,      /* DC, entropy encoding */
79 	AMD_VCE_LEVEL_DC_LL_LOW = 2,  /* DC, low latency queue, res <= 720 */
80 	AMD_VCE_LEVEL_DC_LL_HIGH = 3, /* DC, low latency queue, 1080 >= res > 720 */
81 	AMD_VCE_LEVEL_DC_GP_LOW = 4,  /* DC, general purpose queue, res <= 720 */
82 	AMD_VCE_LEVEL_DC_GP_HIGH = 5, /* DC, general purpose queue, 1080 >= res > 720 */
83 };
84 
85 enum amd_fan_ctrl_mode {
86 	AMD_FAN_CTRL_NONE = 0,
87 	AMD_FAN_CTRL_MANUAL = 1,
88 	AMD_FAN_CTRL_AUTO = 2,
89 };
90 
91 enum pp_clock_type {
92 	PP_SCLK,
93 	PP_MCLK,
94 	PP_PCIE,
95 	PP_SOCCLK,
96 	PP_FCLK,
97 	PP_DCEFCLK,
98 	OD_SCLK,
99 	OD_MCLK,
100 	OD_VDDC_CURVE,
101 	OD_RANGE,
102 };
103 
104 enum amd_pp_sensors {
105 	AMDGPU_PP_SENSOR_GFX_SCLK = 0,
106 	AMDGPU_PP_SENSOR_VDDNB,
107 	AMDGPU_PP_SENSOR_VDDGFX,
108 	AMDGPU_PP_SENSOR_UVD_VCLK,
109 	AMDGPU_PP_SENSOR_UVD_DCLK,
110 	AMDGPU_PP_SENSOR_VCE_ECCLK,
111 	AMDGPU_PP_SENSOR_GPU_LOAD,
112 	AMDGPU_PP_SENSOR_MEM_LOAD,
113 	AMDGPU_PP_SENSOR_GFX_MCLK,
114 	AMDGPU_PP_SENSOR_GPU_TEMP,
115 	AMDGPU_PP_SENSOR_EDGE_TEMP = AMDGPU_PP_SENSOR_GPU_TEMP,
116 	AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
117 	AMDGPU_PP_SENSOR_MEM_TEMP,
118 	AMDGPU_PP_SENSOR_VCE_POWER,
119 	AMDGPU_PP_SENSOR_UVD_POWER,
120 	AMDGPU_PP_SENSOR_GPU_POWER,
121 	AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
122 	AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
123 	AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK,
124 	AMDGPU_PP_SENSOR_MIN_FAN_RPM,
125 	AMDGPU_PP_SENSOR_MAX_FAN_RPM,
126 	AMDGPU_PP_SENSOR_VCN_POWER_STATE,
127 };
128 
129 enum amd_pp_task {
130 	AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
131 	AMD_PP_TASK_ENABLE_USER_STATE,
132 	AMD_PP_TASK_READJUST_POWER_STATE,
133 	AMD_PP_TASK_COMPLETE_INIT,
134 	AMD_PP_TASK_MAX
135 };
136 
137 enum PP_SMC_POWER_PROFILE {
138 	PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT = 0x0,
139 	PP_SMC_POWER_PROFILE_FULLSCREEN3D = 0x1,
140 	PP_SMC_POWER_PROFILE_POWERSAVING  = 0x2,
141 	PP_SMC_POWER_PROFILE_VIDEO        = 0x3,
142 	PP_SMC_POWER_PROFILE_VR           = 0x4,
143 	PP_SMC_POWER_PROFILE_COMPUTE      = 0x5,
144 	PP_SMC_POWER_PROFILE_CUSTOM       = 0x6,
145 	PP_SMC_POWER_PROFILE_COUNT,
146 };
147 
148 enum {
149 	PP_GROUP_UNKNOWN = 0,
150 	PP_GROUP_GFX = 1,
151 	PP_GROUP_SYS,
152 	PP_GROUP_MAX
153 };
154 
155 enum PP_OD_DPM_TABLE_COMMAND {
156 	PP_OD_EDIT_SCLK_VDDC_TABLE,
157 	PP_OD_EDIT_MCLK_VDDC_TABLE,
158 	PP_OD_EDIT_VDDC_CURVE,
159 	PP_OD_RESTORE_DEFAULT_TABLE,
160 	PP_OD_COMMIT_DPM_TABLE
161 };
162 
163 struct pp_states_info {
164 	uint32_t nums;
165 	uint32_t states[16];
166 };
167 
168 enum PP_HWMON_TEMP {
169 	PP_TEMP_EDGE = 0,
170 	PP_TEMP_JUNCTION,
171 	PP_TEMP_MEM,
172 	PP_TEMP_MAX
173 };
174 
175 enum pp_mp1_state {
176 	PP_MP1_STATE_NONE,
177 	PP_MP1_STATE_SHUTDOWN,
178 	PP_MP1_STATE_UNLOAD,
179 	PP_MP1_STATE_RESET,
180 };
181 
182 enum pp_df_cstate {
183 	DF_CSTATE_DISALLOW = 0,
184 	DF_CSTATE_ALLOW,
185 };
186 
187 #define PP_GROUP_MASK        0xF0000000
188 #define PP_GROUP_SHIFT       28
189 
190 #define PP_BLOCK_MASK        0x0FFFFF00
191 #define PP_BLOCK_SHIFT       8
192 
193 #define PP_BLOCK_GFX_CG         0x01
194 #define PP_BLOCK_GFX_MG         0x02
195 #define PP_BLOCK_GFX_3D         0x04
196 #define PP_BLOCK_GFX_RLC        0x08
197 #define PP_BLOCK_GFX_CP         0x10
198 #define PP_BLOCK_SYS_BIF        0x01
199 #define PP_BLOCK_SYS_MC         0x02
200 #define PP_BLOCK_SYS_ROM        0x04
201 #define PP_BLOCK_SYS_DRM        0x08
202 #define PP_BLOCK_SYS_HDP        0x10
203 #define PP_BLOCK_SYS_SDMA       0x20
204 
205 #define PP_STATE_MASK           0x0000000F
206 #define PP_STATE_SHIFT          0
207 #define PP_STATE_SUPPORT_MASK   0x000000F0
208 #define PP_STATE_SUPPORT_SHIFT  0
209 
210 #define PP_STATE_CG             0x01
211 #define PP_STATE_LS             0x02
212 #define PP_STATE_DS             0x04
213 #define PP_STATE_SD             0x08
214 #define PP_STATE_SUPPORT_CG     0x10
215 #define PP_STATE_SUPPORT_LS     0x20
216 #define PP_STATE_SUPPORT_DS     0x40
217 #define PP_STATE_SUPPORT_SD     0x80
218 
219 #define PP_CG_MSG_ID(group, block, support, state) \
220 		((group) << PP_GROUP_SHIFT | (block) << PP_BLOCK_SHIFT | \
221 		(support) << PP_STATE_SUPPORT_SHIFT | (state) << PP_STATE_SHIFT)
222 
223 #define XGMI_MODE_PSTATE_D3 0
224 #define XGMI_MODE_PSTATE_D0 1
225 
226 struct seq_file;
227 enum amd_pp_clock_type;
228 struct amd_pp_simple_clock_info;
229 struct amd_pp_display_configuration;
230 struct amd_pp_clock_info;
231 struct pp_display_clock_request;
232 struct pp_clock_levels_with_voltage;
233 struct pp_clock_levels_with_latency;
234 struct amd_pp_clocks;
235 
236 struct amd_pm_funcs {
237 /* export for dpm on ci and si */
238 	int (*pre_set_power_state)(void *handle);
239 	int (*set_power_state)(void *handle);
240 	void (*post_set_power_state)(void *handle);
241 	void (*display_configuration_changed)(void *handle);
242 	void (*print_power_state)(void *handle, void *ps);
243 	bool (*vblank_too_short)(void *handle);
244 	void (*enable_bapm)(void *handle, bool enable);
245 	int (*check_state_equal)(void *handle,
246 				void  *cps,
247 				void  *rps,
248 				bool  *equal);
249 /* export for sysfs */
250 	void (*set_fan_control_mode)(void *handle, u32 mode);
251 	u32 (*get_fan_control_mode)(void *handle);
252 	int (*set_fan_speed_percent)(void *handle, u32 speed);
253 	int (*get_fan_speed_percent)(void *handle, u32 *speed);
254 	int (*force_clock_level)(void *handle, enum pp_clock_type type, uint32_t mask);
255 	int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
256 	int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
257 	int (*get_sclk_od)(void *handle);
258 	int (*set_sclk_od)(void *handle, uint32_t value);
259 	int (*get_mclk_od)(void *handle);
260 	int (*set_mclk_od)(void *handle, uint32_t value);
261 	int (*read_sensor)(void *handle, int idx, void *value, int *size);
262 	enum amd_dpm_forced_level (*get_performance_level)(void *handle);
263 	enum amd_pm_state_type (*get_current_power_state)(void *handle);
264 	int (*get_fan_speed_rpm)(void *handle, uint32_t *rpm);
265 	int (*set_fan_speed_rpm)(void *handle, uint32_t rpm);
266 	int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
267 	int (*get_pp_table)(void *handle, char **table);
268 	int (*set_pp_table)(void *handle, const char *buf, size_t size);
269 	void (*debugfs_print_current_performance_level)(void *handle, struct seq_file *m);
270 	int (*switch_power_profile)(void *handle, enum PP_SMC_POWER_PROFILE type, bool en);
271 /* export to amdgpu */
272 	struct amd_vce_state *(*get_vce_clock_state)(void *handle, u32 idx);
273 	int (*dispatch_tasks)(void *handle, enum amd_pp_task task_id,
274 			enum amd_pm_state_type *user_state);
275 	int (*load_firmware)(void *handle);
276 	int (*wait_for_fw_loading_complete)(void *handle);
277 	int (*set_powergating_by_smu)(void *handle,
278 				uint32_t block_type, bool gate);
279 	int (*set_clockgating_by_smu)(void *handle, uint32_t msg_id);
280 	int (*set_power_limit)(void *handle, uint32_t n);
281 	int (*get_power_limit)(void *handle, uint32_t *limit, bool default_limit);
282 	int (*get_power_profile_mode)(void *handle, char *buf);
283 	int (*set_power_profile_mode)(void *handle, long *input, uint32_t size);
284 	int (*set_fine_grain_clk_vol)(void *handle, uint32_t type, long *input, uint32_t size);
285 	int (*odn_edit_dpm_table)(void *handle, uint32_t type, long *input, uint32_t size);
286 	int (*set_mp1_state)(void *handle, enum pp_mp1_state mp1_state);
287 	int (*smu_i2c_bus_access)(void *handle, bool acquire);
288 /* export to DC */
289 	u32 (*get_sclk)(void *handle, bool low);
290 	u32 (*get_mclk)(void *handle, bool low);
291 	int (*display_configuration_change)(void *handle,
292 		const struct amd_pp_display_configuration *input);
293 	int (*get_display_power_level)(void *handle,
294 		struct amd_pp_simple_clock_info *output);
295 	int (*get_current_clocks)(void *handle,
296 		struct amd_pp_clock_info *clocks);
297 	int (*get_clock_by_type)(void *handle,
298 		enum amd_pp_clock_type type,
299 		struct amd_pp_clocks *clocks);
300 	int (*get_clock_by_type_with_latency)(void *handle,
301 		enum amd_pp_clock_type type,
302 		struct pp_clock_levels_with_latency *clocks);
303 	int (*get_clock_by_type_with_voltage)(void *handle,
304 		enum amd_pp_clock_type type,
305 		struct pp_clock_levels_with_voltage *clocks);
306 	int (*set_watermarks_for_clocks_ranges)(void *handle,
307 						void *clock_ranges);
308 	int (*display_clock_voltage_request)(void *handle,
309 				struct pp_display_clock_request *clock);
310 	int (*get_display_mode_validation_clocks)(void *handle,
311 		struct amd_pp_simple_clock_info *clocks);
312 	int (*notify_smu_enable_pwe)(void *handle);
313 	int (*enable_mgpu_fan_boost)(void *handle);
314 	int (*set_active_display_count)(void *handle, uint32_t count);
315 	int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
316 	int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
317 	int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
318 	int (*get_asic_baco_capability)(void *handle, bool *cap);
319 	int (*get_asic_baco_state)(void *handle, int *state);
320 	int (*set_asic_baco_state)(void *handle, int state);
321 	int (*get_ppfeature_status)(void *handle, char *buf);
322 	int (*set_ppfeature_status)(void *handle, uint64_t ppfeature_masks);
323 	int (*asic_reset_mode_2)(void *handle);
324 	int (*set_df_cstate)(void *handle, enum pp_df_cstate state);
325 	int (*set_xgmi_pstate)(void *handle, uint32_t pstate);
326 	ssize_t (*get_gpu_metrics)(void *handle, void **table);
327 };
328 
329 struct metrics_table_header {
330 	uint16_t			structure_size;
331 	uint8_t				format_revision;
332 	uint8_t				content_revision;
333 };
334 
335 struct gpu_metrics_v1_0 {
336 	struct metrics_table_header	common_header;
337 
338 	/* Driver attached timestamp (in ns) */
339 	uint64_t			system_clock_counter;
340 
341 	/* Temperature */
342 	uint16_t			temperature_edge;
343 	uint16_t			temperature_hotspot;
344 	uint16_t			temperature_mem;
345 	uint16_t			temperature_vrgfx;
346 	uint16_t			temperature_vrsoc;
347 	uint16_t			temperature_vrmem;
348 
349 	/* Utilization */
350 	uint16_t			average_gfx_activity;
351 	uint16_t			average_umc_activity; // memory controller
352 	uint16_t			average_mm_activity; // UVD or VCN
353 
354 	/* Power/Energy */
355 	uint16_t			average_socket_power;
356 	uint32_t			energy_accumulator;
357 
358 	/* Average clocks */
359 	uint16_t			average_gfxclk_frequency;
360 	uint16_t			average_socclk_frequency;
361 	uint16_t			average_uclk_frequency;
362 	uint16_t			average_vclk0_frequency;
363 	uint16_t			average_dclk0_frequency;
364 	uint16_t			average_vclk1_frequency;
365 	uint16_t			average_dclk1_frequency;
366 
367 	/* Current clocks */
368 	uint16_t			current_gfxclk;
369 	uint16_t			current_socclk;
370 	uint16_t			current_uclk;
371 	uint16_t			current_vclk0;
372 	uint16_t			current_dclk0;
373 	uint16_t			current_vclk1;
374 	uint16_t			current_dclk1;
375 
376 	/* Throttle status */
377 	uint32_t			throttle_status;
378 
379 	/* Fans */
380 	uint16_t			current_fan_speed;
381 
382 	/* Link width/speed */
383 	uint8_t				pcie_link_width;
384 	uint8_t				pcie_link_speed; // in 0.1 GT/s
385 };
386 
387 struct gpu_metrics_v2_0 {
388 	struct metrics_table_header	common_header;
389 
390 	/* Driver attached timestamp (in ns) */
391 	uint64_t			system_clock_counter;
392 
393 	/* Temperature */
394 	uint16_t			temperature_gfx; // gfx temperature on APUs
395 	uint16_t			temperature_soc; // soc temperature on APUs
396 	uint16_t			temperature_core[8]; // CPU core temperature on APUs
397 	uint16_t			temperature_l3[2];
398 
399 	/* Utilization */
400 	uint16_t			average_gfx_activity;
401 	uint16_t			average_mm_activity; // UVD or VCN
402 
403 	/* Power/Energy */
404 	uint16_t			average_socket_power; // dGPU + APU power on A + A platform
405 	uint16_t			average_cpu_power;
406 	uint16_t			average_soc_power;
407 	uint16_t			average_gfx_power;
408 	uint16_t			average_core_power[8]; // CPU core power on APUs
409 
410 	/* Average clocks */
411 	uint16_t			average_gfxclk_frequency;
412 	uint16_t			average_socclk_frequency;
413 	uint16_t			average_uclk_frequency;
414 	uint16_t			average_fclk_frequency;
415 	uint16_t			average_vclk_frequency;
416 	uint16_t			average_dclk_frequency;
417 
418 	/* Current clocks */
419 	uint16_t			current_gfxclk;
420 	uint16_t			current_socclk;
421 	uint16_t			current_uclk;
422 	uint16_t			current_fclk;
423 	uint16_t			current_vclk;
424 	uint16_t			current_dclk;
425 	uint16_t			current_coreclk[8]; // CPU core clocks
426 	uint16_t			current_l3clk[2];
427 
428 	/* Throttle status */
429 	uint32_t			throttle_status;
430 
431 	/* Fans */
432 	uint16_t			fan_pwm;
433 
434 	uint16_t			padding;
435 };
436 
437 #endif
438